JP2007141992A - Display device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a gate insulating film of a thin film transistor formed on a TFT substrate as a thick film using a high dielectric material, and dope enough ion thereinto. <P>SOLUTION: An n<SP>+</SP>region 7 is formed by ion doping after a contact hole 7a is formed in the gate insulating film 3 consisting of a thick film high dielectric material. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a flat panel display device and a method for manufacturing the same, and in particular, an active device in which a gate insulating film of a thin film transistor formed on an active matrix substrate is thickened to improve a breakdown voltage between a silicon semiconductor layer and a gate electrode. -It is effective for a display device having a matrix substrate.

  Display devices capable of high-definition and color display for notebook computers and display monitors, liquid crystal display devices using liquid crystal panels as display panels for mobile phones, and electroluminescence (especially organic electroluminescence) elements Various types of flat panel display devices such as an organic electroluminescence display device (organic EL display device) or a field emission display device (FED) using a field emission element are already in practical use or practical application research stage.

  A flat panel display device includes a display area in which a large number of pixels composed of thin film transistor circuits are arranged in a matrix, horizontal and vertical drive circuits for driving the pixels around the display area, and other peripheral circuit semiconductor chips. And an insulating substrate such as glass. In addition, what is called a system-in-glass (SIG) in which each of these drive circuits and the like are directly formed on an insulating substrate has been developed. Such an insulating substrate in which various thin film transistor circuits are built is also called a thin film transistor (TFT) substrate or an active matrix substrate. In the following description, it is also expressed as a TFT substrate or simply a substrate.

In low-temperature polysilicon (LTPS), silicon oxide SiO ₂ is used as a gate insulating film. Since the thickness of the gate insulating film of this silicon oxide SiO ₂ is as thin as about 100 nm, the breakdown voltage between the active silicon semiconductor layer, that is, the polysilicon (p-Si) layer and the gate electrode is low, and defects due to electrostatic breakdown occur. May occur.

As a countermeasure, it is conceivable to increase the breakdown voltage without deteriorating the mobility by using a high dielectric material (high-k material) for the gate insulating film. However, if the gate insulating film is thick, it becomes difficult to ion-dope the p-Si layer over the insulating film. Patent Document 1 discloses a conventional technique for increasing the breakdown voltage between a p-Si layer and a gate electrode by using a high dielectric material for a gate insulating film to increase the thickness and performing ion doping before forming the gate insulating film. There is a disclosure. Patent Document 2 discloses that a coating type insulating material is used for a gate insulating film of a bottom gate type thin film transistor.
JP-A-5-82740 JP 2003-68757 A

However, in the method disclosed in Patent Document 1 in which ion doping is performed before the formation of the gate insulating film, a photolithography process (hereinafter simply referred to as a “photo process”) is required for doping, and the process constant increases. Note that the gate insulating material of Patent Document 2 is SiO ₂ and has a dielectric constant of 3.9, which is not so high. Therefore, considering the mobility, it is difficult to obtain sufficient withstand voltage because it is not a thick film.

An object of the present invention is to provide a display device having a p-Si layer in which a gate insulating film of a thin film transistor formed on a TFT substrate is a thick film using a high-k material and is doped with sufficient ions. .

  The present invention is characterized in that ion doping is performed after patterning a gate insulating film made of a high-k material. Many high-k materials are difficult to etch. Therefore, the patterning of the gate insulating film in the present invention is performed in the order of resist patterning, insulating film coating, and resist removal.

The characteristic configuration of the present invention is as follows. First, the characteristics of the display device of the present invention are as follows.
(1) having an active matrix substrate on which a thin film transistor circuit formed in a semiconductor film patterned on the substrate is formed;
The edge of the gate insulating film on the patterned silicon semiconductor film is aligned with the edge of the n ⁺ region of the silicon semiconductor.

(2) A silicon oxide layer is provided on the silicon semiconductor.

In addition, the characteristics of the display device manufacturing method of the present invention are
(3) The contact hole between the silicon semiconductor film and the gate insulating film on the substrate is patterned in one photo process.

(4) forming a polycrystalline silicon layer on the main surface of the insulating substrate;
Patterning the polycrystalline silicon layer to form a high dielectric constant gate insulating film;
Patterning the gate insulating film;
Covering the patterned gate insulating film, forming a gate electrode film, and patterning to form a gate electrode;
Doping ions into the n ⁺ region 7 from the opening of the patterned gate insulating film, that is, the contact hole;
Implanting phosphorus ions using the gate electrode as a mask to form an n ⁻ region;
Forming and processing an interlayer insulating film; forming a source / drain electrode layer; and processing to form a source / drain electrode;
After forming the source / drain electrodes, forming an insulating layer and patterning,
Forming a pixel electrode 12;

(5) The present invention also includes a step of forming a silicon oxide film on the polycrystalline silicon layer.

  Since ions are directly doped into the p-Si layer after patterning the gate insulating film, ion doping is easy even if the gate insulating film is thick. In addition, since there is no need to process a high-k material, various insulating materials can be used.

  In particular, regarding the display device of the present invention, (1) by increasing the thickness of the gate insulating film, the breakdown voltage between the p-Si layer and the gate electrode is improved. In addition, (2) by forming a thick gate insulating film using a high-k material, the mobility of the thin film transistor is improved and the leakage current can be reduced, so that low frequency driving is possible. Furthermore, (3) since the area of the thin film transistor can be reduced, the aperture ratio is improved.

  In addition, regarding the method for manufacturing a display device of the present invention, (4) the p-Si layer and the contact hole are patterned in one photo process, so the number of photo processes can be reduced. (5) Since the p-Si layer and the contact hole are patterned in one photo process, misalignment does not occur. As a result, as described in (3) above, the area of the thin film transistor can be reduced and the aperture ratio can be improved.

  Hereinafter, the display device of the present invention will be described by a manufacturing method. In the following description, an insulating substrate on which a semiconductor layer serving as an active layer of a thin film transistor to be formed on a thin film transistor substrate of a liquid crystal display device is described as a glass substrate.

  1 to 12 are schematic cross-sectional views sequentially showing manufacturing steps of a thin film transistor substrate which constitutes a first embodiment of a display device according to the present invention.

FIG. 1: A base film (not shown) of silicon nitride (SiN) and silicon oxide (SiO ₂ ) is formed on the main surface of the glass substrate 1. A polycrystalline silicon (p-Si) layer 2 is formed on the main surface of the glass substrate 1. The polycrystalline silicon layer 2 is patterned to form a high dielectric constant (high-k) gate insulating film 3 with a thickness of about 200 to 300 nm. The gate insulating film 3 is made of one or more of silicon oxide, silicon nitride, tantalum oxide and the like, and spins a solution using a CVD method or a metal alkoxide such as Si (C ₂ H ₅ O) ₄ as a raw material. A film is formed by coating, sol-gel reaction, and baking.

Since the gate insulating film 3 is a high dielectric constant material, the breakdown voltage can be improved without increasing the mobility by increasing the thickness. Further, since the mobility can be improved and the leakage current can be reduced, low-frequency driving is possible.

  FIG. 2: The gate insulating film 3 is patterned. If the gate insulating film 3 is a coating type insulating film and is a photosensitive material, it is patterned in a photo process. When the gate insulation 3 is a non-photosensitive material, patterning is performed by a photo process and an etching process using a hydrofluoric acid aqueous solution.

  FIG. 3: Covering the patterned gate insulating film 3, a gate electrode film 4 preferably made of an alloy of molybdenum (Mo) and tungsten (W) is formed.

  FIG. 4: A resist 5 is applied, pattern-exposed and developed to remove the resist 5 except for the gate electrode portion, and the gate electrode film 4 is etched to form a gate electrode 6. FIG. 4 shows the state after etching. The pattern of the resist 5 is left.

FIG. 5: Phosphorus is doped from the opening of the patterned gate insulating film 3, that is, the contact hole 7a to form an n ⁺ region. This ion doping is performed by a plasma doping method or the like. Since the p-Si layer is directly doped, the required ion doping is easy even if the gate insulating film 3 is thick.

FIG. 6: Using the resist 5 as a mask, phosphorus is implanted (hereinafter simply referred to as “implant”) to form the n ⁻ region 8. n ^- implantation, because the dose amount is about 1.0 × 10 ¹³ cm ^-2, it is possible to implant in a thick film. The width 8a of an LDD (Lightly Doped Drain) region 8 by this implantation is about 1 μm, and the area of the thin film transistor can be reduced as will be described later.

  FIG. 7: Next, the resist 5 is removed, and an interlayer insulating film 9 is formed. The interlayer insulating film 9 has a relative dielectric constant of 2.6 to 2 as polysiloxane having an organic functional group such as a methyl group by spin-coating and baking a solution of silicon oxide by CVD or siloxane or polysilazane. .9, a low dielectric constant coating type insulating film.

  FIG. 8: The interlayer insulating film 9 is processed. If the interlayer insulating film 9 is a photosensitive material, it is patterned in a photo process. In the case where the interlayer insulating film 9 is a non-photosensitive material, patterning is performed by a photo process by resist application and patterning and an etching process by a hydrofluoric acid aqueous solution or the like.

  FIG. 9: The source / drain electrode 10 is formed. The source / drain electrode 10 is a three-layer structure film in which an aluminum (Al) alloy is sandwiched between titanium (Ti) or molybdenum (Mo) alloy, and film formation by sputtering, patterning by resist coating / exposure / development, etc. Process by etching.

  FIG. 10: After forming the source / drain electrode 10, an insulating layer 11 is formed. This insulating layer 11 is a polylayer having an organic functional group such as a methyl group by spin-coating and baking a two-layer film of a silicon nitride film and a photosensitive acrylic resin by a CVD method, or a solution of siloxane or polysilazane. It is a low dielectric constant coating type insulating film made of siloxane.

  FIG. 11: The insulating layer 11 is patterned. When the insulating layer 11 is a two-layer film of a silicon nitride film and a photosensitive acrylic resin, the photosensitive acrylic resin is patterned by photolithography, and the silicon nitride film is etched using the patterned acrylic resin as a mask. In the case of a low dielectric constant coating type insulating film made of polysiloxane, if it is a photosensitive material, it is patterned by photolithography.

  In the case of a non-photosensitive material, patterning is performed by a photo process by resist coating / exposure / development and an etching process by hydrofluoric acid aqueous solution. When a polysiloxane low-dielectric-constant coating type insulating film is used for the insulating layer 11, the semiconductor chip can be repaired because it is stronger than an acrylic resin. Thus, when the thin film transistor substrate or the semiconductor chip is defective, the yield can be improved by removing or reattaching the semiconductor chip.

  FIG. 12: Next, the pixel electrode 12 is formed. The pixel electrode 12 is made of an In—Sn—O compound, an In—Zn—O compound, or the like. Patterning is performed by film formation by sputtering, resist coating / exposure / development, and etching by oxalic acid. In the case where the insulating layer 11 is a low dielectric constant coating type insulating film, the capacitance between the pixel electrode and the source / drain electrodes is reduced, and the power consumption can be reduced.

  FIG. 13 is a top view of the main part of the thin film transistor in the thin film transistor substrate of the display device manufactured by the manufacturing method of the first embodiment. 14 is a top view of a main part corresponding to FIG. 13 of a thin film transistor in a thin film transistor substrate of a conventional display device shown for comparison, and FIG. 15 is a cross-sectional view of the thin film transistor of FIG. The size of the LDD region 8a of the thin film transistor of Example 1 and the conventional thin film transistor is about 1 μm.

In FIG. 13, the contact hole 7a and the end of the n ⁺ region 7 are aligned, and there is no misalignment. On the other hand, in the conventional thin film transistor shown in FIGS. 14 and 15, there is no matching relationship between the contact hole 7a and the end of the n ⁺ region 7.

  16 to 21 are schematic cross-sectional views sequentially showing the manufacturing process of the thin film transistor substrate constituting the second embodiment of the display device according to the present invention. FIG. 22 is a top view for explaining the halftone mask used in the patterning step of FIG.

FIG. 16: A base film (not shown) of silicon nitride (SiN) and silicon oxide (SiO ₂ ) is formed on the main surface of the glass substrate 1. A polycrystalline silicon (p-Si) layer 2 is formed on the main surface of the glass substrate 1.

FIG. 17: Using the halftone mask 16 shown in FIG. 22, a contact hole pattern resist 18 is formed in the resist non-exposed portion, and a silicon (p-Si) island pattern resist 19 is formed in the half exposed portion. The halftone mask 16 includes a non-transmissive portion 21 that forms the contact hole pattern resist 18, a semi-transmissive portion 22 that forms the silicon island pattern resist 19, and a total transmissive portion 23. The semi-transmissive portion 22 is a line and space pattern with a width outside the resolution limit of exposure.

FIG. 18: The silicon (p-Si) layer 2 where there is no resist is removed by dry etching, and a silicon island 15 is formed.

FIG. 19: The silicon island pattern resist 19 which is a half exposure part is removed by ashing.

FIG. 20: A solution using a metal alkoxide as a raw material is applied by spin coating to form an insulating film 3. The metal alkoxide raw materials are Si (C ₂ H ₅ O) ₄ , Al (C ₂ H ₅ CH (CH ₃ ) O) ₃ , Mg (C ₂ H ₅ O) ₂ , Ti (C ₂ H ₅ O) ₄ , One or a mixture of two or more of Zr (O (CH ₂ ) ₃ CH ₃ ) ₄ , Ta (OC ₂ H ₅ ) ₅ and the like. As the solvent for the metal alkoxide solution, water that does not dissolve the resist is used. If necessary, an acid such as hydrochloric acid is added as a catalyst. After application of this solution, drying, baking, and aging are performed as necessary.

FIG. 21: The resist 18 is removed by ashing or an alkali stripping solution such as monoethanolamine (MEA). Thereby, the contact hole 7A is obtained. Thereafter, the insulating film 3 is baked. This firing is performed by lamp annealing, pressure annealing with nitrogen, hydrogen, or the like. Thereby, the gate insulating film 3 having a high dielectric constant is formed. Since a processing step such as etching is not required for patterning the gate insulating film 3, a material such as Al ₂ O ₃ that is difficult to process can be used.

  Thereafter, the same thin film transistor as that shown in FIG. 12 is formed through steps similar to those in FIGS.

  FIG. 23 is a top view of a silicon island in the second embodiment. In the second embodiment, since there is no misalignment between the silicon island and the contact hole, the widths 24 and 25 in one direction and two directions of the silicon island can be reduced. Accordingly, since the size of the thin film transistor can be reduced, the aperture ratio can be improved.

  FIG. 24 is another top view of the silicon island in the second embodiment. According to the second embodiment, since the unidirectional width 24 of the silicon island can be reduced, the width 24 of the silicon island can be made equal to the channel width of the thin film transistor, and the thin film transistor can be made smaller. Further, the aperture ratio can be improved.

FIG. 25 is a schematic cross-sectional view illustrating a method for forming a gate insulating film corresponding to FIG. 20 for explaining the third embodiment of the present invention. Here, a slurry in which metal oxide particles 28 such as Al ₂ O ₃ are dispersed in a solution 27 of a metal alkoxide such as Si (C ₂ H ₅ O) ₄ after the steps of FIGS. Is applied and baked to form a coating-type gate insulating film similar to that shown in FIG.

FIG. 26 and FIG. 27 are main part process diagrams for explaining Example 4 of the present invention. FIG. 26 is a schematic sectional view corresponding to FIG. 16, and FIG. 27 is a schematic sectional view of a thin film transistor manufactured in Example 4. is there. Here, as shown in FIG. 26, an underlying film (not shown) of silicon nitride (SiN) and silicon oxide (SiO ₂ ) is formed on the main surface of the glass substrate 1, and a polycrystalline film is formed thereon. A silicon layer (p-Si) 2 is formed, and the surface of the polycrystalline silicon layer 2 is oxidized by ozone oxidation, ashing or the like to form a silicon oxide film 2A.

  After the process of FIG. 26, the polycrystalline silicon layer 2 and the silicon oxide film 2A are processed as shown in FIG. 27, and the thin film transistor shown in FIG. 27 is obtained through the same processes as in FIGS. In this thin film transistor, since the silicon oxide film 2A is interposed between the high dielectric constant insulating film 20 and the polycrystalline silicon layer, the number of trap sites is small and the mobility loss is small.

  28 to 30 are main part process diagrams for explaining the fifth embodiment of the present invention. FIG. 28 is a resist patterning process chart in which contact holes are formed, FIG. 29 is a resist removal process chart, and FIG. 30 is an interlayer process chart. It is a formation process figure of an insulating film.

In Example 5, a positive resist 32 is used for forming contact holes. When a positive resist is used, the patterned resist may have a forward tapered shape (conical shape) as shown in FIG. Then, when this resist is removed to form the contact hole 33, the inner wall of the contact hole 33 becomes a reverse taper shape as shown in FIG. As a result, the coverage of the source / drain electrodes formed in the upper layer is deteriorated. Therefore, in this embodiment, as shown in FIG. 30, the diameter 34 of the interlayer insulating film 9 is made smaller than the diameter 35 of the gate insulating film 3A. As a result, the problem of coverage deterioration of the source / drain electrodes can be solved. In this case, the outer end of contact hole 34 does not coincide with the end of n ⁺ region 7.

  31 to 38 are main part process diagrams for explaining the sixth embodiment of the present invention, and FIG. 39 is a cross-sectional view of the thin film transistor manufactured in the process of the sixth embodiment of the present invention.

FIG. 31: A base film (not shown) of silicon nitride (SiN) and silicon oxide (SiO ₂ ) is formed on the main surface of the glass substrate 1, and a polycrystalline silicon layer (p-Si) 2 is formed thereon. And patterning.

FIG. 32: A resist 48 is applied and patterned so that the channel portion 38 of the thin film transistor becomes a space.

FIG. 33: Si (C ₂ H ₅ O) ₄ , Al (C ₂ H ₅ CH (CH ₃ ) O) ₃ , Mg (C ₂ H ₅ O) ₂ , Ti (C ₂ H ₅ O) ₄ , Zr ( A solution 390 using one or a mixture of two or more metal alkoxides such as O (CH ₂ ) ₃ CH ₃ ) ₄ and Ta (OC ₂ H ₅ ) ₅ as a raw material is applied to the channel portion 38 by a method such as inkjet. Note that water or the like that does not dissolve the resist 48 is used as the solvent of the metal alkoxide solution. If necessary, an acid such as hydrochloric acid is added as a catalyst. After application, drying, baking and aging are performed as necessary.

In this embodiment, since the area for applying the metal alkoxide solution to be a high dielectric constant gate insulating film is small, the material can be saved. It should be noted that such a coating type gate insulating film is formed by replacing particles of a metal oxide such as Al ₂ O ₃ with a metal alkoxide such as Si (C ₂ H ₅ O) ₄ instead of applying the above metal alkoxide solution. A slurry dispersed in a solution may be applied.

  FIG. 34: The resist 48 is removed by ashing or an alkaline stripping solution such as monoethanolamine (MEA). Thereafter, the gate insulating film 390 is baked to form the gate insulating film 39. This firing is performed by a method such as lamp annealing, pressure annealing with nitrogen, hydrogen, or the like. Even in a material that easily cracks due to shrinkage due to drying, since the area of the gate insulating film 39 is small, the amount of shrinkage is small and cracks are difficult to crack. Therefore, it is applicable also to the material which a crack tends to enter.

Since a processing step such as etching is not required for patterning the gate insulating film 39, a material such as Al ₂ O ₃ that is difficult to process can be used.

  FIG. 35: A conductive film for forming a gate electrode is formed, and a resist is applied thereon and patterned to form a resist pattern 40 of the gate electrode. The gate electrode 41 is patterned by etching using the resist pattern 40 as a mask.

Using the gate insulating film 39 as a mask, an n ⁺ region 42 is formed by a plasma doping method or the like. Since the silicon layer 2 is directly doped, the gate insulating film 39 can be easily doped even if it is thick.

FIG. 36: An n ⁻ region 43 is formed by an implantation method or the like using the resist pattern 40 and the gate electrode 41 as a mask. The end of the n ⁻ region 43 coincides with the end of the gate electrode 41 and the end of the gate insulating film 39.

  FIG. 37: The resist 40 is removed, and an interlayer insulating film 44 is formed. The interlayer insulating film 44 is a low dielectric constant coating type insulating film obtained by spin-coating silicon oxide by a CVD method or a solution such as siloxane or polysilazane and baking it to form polysiloxane.

  FIG. 38: The interlayer insulating film 44 is processed. When the interlayer insulating film 44 is made of a photosensitive material, it is patterned by a photo process, and when it is made of a non-photosensitive material, it is patterned by a photo process by resist coating or an etching process by a hydrofluoric acid aqueous solution. Thereafter, a thin film transistor is manufactured through steps similar to those shown in FIGS.

  FIG. 39 is a cross-sectional view of the thin film transistor manufactured in the process of this example. The same reference numerals as those in FIG. 27 correspond to the same functional parts. FIG. 40 is a top view of the main part of the thin film transistor of this example. As shown in FIG. 40, the width 45 of the portion of the gate insulating film 39 that is not covered by the gate electrode 41 is about 1 μm. Reference numeral 37 indicates a silicon island.

  41 and 42 are enlarged views of a portion A in FIG. 40, showing a configuration example of the width 47 of the gate insulating film 39 and the width 46 of the channel portion of the silicon island 37. FIG. 41 shows that the width 47 of the gate insulating film 39 is equal to the width 46 of the channel portion of the silicon island 37. FIG. 42 shows that the width 47 of the gate insulating film 39 is longer than the width 46 of the channel portion of the silicon island 37. Shows what In this embodiment, one of the configurations shown in FIGS. 41 and 42 is employed.

  FIG. 43 is a schematic plan view for explaining an example of a thin film transistor substrate constituting the display device of the present invention. In this thin film transistor substrate, a pixel region 402, a signal processing circuit 403, a horizontal scanning circuit 404, a vertical scanning circuit 405, a peripheral circuit 406 such as a booster circuit, and an input pad 407 are arranged on a glass substrate 1.

  The present invention described above can be similarly applied to various active matrix type display devices such as a liquid crystal display device and an organic EL display device.

It is a schematic cross section which shows the manufacturing process of the thin-film transistor substrate which comprises Example 1 of the display apparatus by this invention. It is a schematic cross section following FIG. 1 which shows the manufacturing process of the thin-film transistor substrate which comprises Example 1 of the display apparatus by this invention. FIG. 3 is a schematic cross-sectional view subsequent to FIG. 2 showing a manufacturing process of a thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 4 is a schematic cross-sectional view subsequent to FIG. 3, showing a manufacturing process of a thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 5 is a cross-sectional view subsequent to FIG. 4 showing a manufacturing process of a thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 6 is a schematic cross-sectional view subsequent to FIG. 5 showing a manufacturing process of the thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 7 is a schematic cross-sectional view continuing from FIG. 6, showing a manufacturing process of the thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 8 is a schematic cross-sectional view subsequent to FIG. 7 showing the manufacturing process of the thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 9 is a schematic cross-sectional view subsequent to FIG. 8 showing the manufacturing process of the thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 10 is a schematic cross-sectional view subsequent to FIG. 9 showing the manufacturing process of the thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 11 is a schematic cross-sectional view subsequent to FIG. 10 showing a manufacturing process of the thin film transistor substrate constituting Example 1 of the display device according to the present invention. FIG. 12 is a schematic cross-sectional view subsequent to FIG. 11, showing a manufacturing process of a thin film transistor substrate constituting Example 1 of the display device according to the present invention. 4 is a top view of a main part of a thin film transistor in a thin film transistor substrate of a display device manufactured by the manufacturing method of Example 1. FIG. It is a principal part top view corresponding to FIG. 13 of the thin-film transistor in the thin-film transistor substrate of the conventional display apparatus shown for a comparison. It is sectional drawing of the thin-film transistor of FIG. It is a schematic cross section which shows the manufacturing process of the thin-film transistor substrate which comprises Example 2 of the display apparatus by this invention. FIG. 17 is a schematic cross-sectional view subsequent to FIG. 16, showing a manufacturing process of a thin film transistor substrate constituting Example 2 of the display device according to the present invention. FIG. 18 is a schematic cross-sectional view subsequent to FIG. 17, showing a manufacturing process of a thin film transistor substrate constituting Example 2 of the display device according to the present invention. FIG. 19 is a schematic cross-sectional view subsequent to FIG. 18 showing a manufacturing process of a thin film transistor substrate constituting Example 2 of the display device according to the present invention. FIG. 20 is a schematic cross-sectional view subsequent to FIG. 19, showing a manufacturing process of a thin film transistor substrate constituting Example 2 of the display device according to the present invention. FIG. 21 is a schematic cross-sectional view subsequent to FIG. 20 showing a manufacturing process of a thin film transistor substrate which constitutes Example 2 of the display device according to the present invention. FIG. 18 is a top view illustrating a halftone mask used in the patterning process of FIG. 17. 6 is a top view of a silicon island in Example 2. FIG. 6 is another top view of the silicon island in Example 2. FIG. FIG. 21 is a schematic cross-sectional view illustrating a method for forming a gate insulating film corresponding to FIG. 20 for explaining Example 3 of the present invention. It is principal part process drawing corresponding to FIG. 1 explaining Example 4 of this invention. 6 is a schematic cross-sectional view of a thin film transistor manufactured in Example 4. FIG. It is process drawing of the resist patterning which forms the contact hole explaining Example 5 of this invention. It is the resist removal process figure explaining Example 5 of this invention. It is a formation process figure of the interlayer insulation film explaining Example 5 of this invention. It is principal part process drawing explaining Example 6 of this invention. It is principal part process drawing following FIG. 31 explaining Example 6 of this invention. FIG. 33 is a main part process diagram following FIG. 32, illustrating Example 6 of the present invention. It is principal part process drawing following FIG. 33 explaining Example 6 of this invention. It is principal part process drawing following FIG. 34 explaining Example 6 of this invention. It is principal part process drawing following FIG. 35 explaining Example 6 of this invention. FIG. 37 is a main part process diagram following FIG. 36, illustrating Example 6 of the present invention. FIG. 38 is a main part process diagram illustrating FIG. 37 for explaining an example 6 of the present invention; It is sectional drawing of the thin-film transistor manufactured at the process of Example 6 of this invention. It is a principal part top view of the thin-film transistor of Example 6 of this invention. FIG. 41 is an enlarged view of a portion A in FIG. 40 showing a configuration example in which the width 47 of the gate insulating film 39 and the width 46 of the channel portion of the silicon island 37 are made equal. 41 is an enlarged view of a portion A in FIG. 40 showing a configuration example in which the width 47 of the gate insulating film 39 is longer than the width 46 of the channel portion of the silicon island 37. FIG. . It is a schematic plan view illustrating an example of a thin film transistor substrate that constitutes the display device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Silicon film, 3 ... Gate insulating film, 4 ... Gate electrode film, 5 ... Resist, 6 ... Gate electrode, 7 ... n ⁺ area ^| region, 8 ... n ^- region, 8a ... LDD region, 9 ... interlayer insulating film, 10 ... source / drain electrodes, 11 ... insulating layer, 12 ... pixel electrodes.

Claims (5)

A display device having an active matrix substrate in which a thin film transistor circuit formed in a semiconductor film patterned on a substrate is formed,
A gate insulating film on the patterned silicon semiconductor film;
A display device, wherein an edge of the gate insulating film and an edge of an n ⁺ region of the silicon semiconductor are aligned.   The display device according to claim 1, further comprising a silicon oxide layer on an upper layer of the silicon semiconductor. A method of manufacturing a display device including an active matrix substrate having a thin film transistor circuit formed in a semiconductor film patterned on a substrate,
A method of manufacturing a display device, comprising: forming a gate insulating film on a patterned silicon semiconductor film on the substrate; and patterning the silicon semiconductor film and the contact hole in one photo step. A method of manufacturing a display device including an active matrix substrate having a thin film transistor circuit formed in a semiconductor film patterned on a substrate,
Forming a polycrystalline silicon layer on the main surface of the substrate;
Patterning the polycrystalline silicon layer to form a high dielectric constant gate insulating film;
Patterning the gate insulating film;
Covering the patterned gate insulating film, forming a gate electrode film, and patterning to form a gate electrode;
Doping ions into the n ⁺ region 7 from the opening of the patterned gate insulating film, that is, the contact hole;
Implanting phosphorus ions using the gate electrode as a mask to form an n ⁻ region;
A step of forming and processing an interlayer insulating film 9, a step of forming a source / drain electrode film and processing to form a source / drain electrode;
After forming the source / drain electrodes, forming an insulating layer and patterning,
And a step of forming the pixel electrode 12. The method for manufacturing a display device according to claim 4, further comprising a step of forming a silicon oxide film on the polycrystalline silicon layer.

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