JP2007027532A - Ferroelectric memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory device having an excellent electrical characteristic and a high performance. <P>SOLUTION: A first insulating film 30 and a hydrogen barrier film 60 covering a ferroelectric capacitor structure 40 are formed, a second insulating film 70 is formed on the hydrogen barrier film, a first opening 72 is formed to be passed through the second insulating film and to reach a surface 60a of the hydrogen barrier film, a second opening 62 is formed to be passed through the hydrogen barrier film, a recess communicating with the second opening is formed within the thickness of an etching stopper layer 47, the bottom of the recess is cut to form a third opening 52 to expose an upper electrode 46 therefrom, and a contact hole 90 is formed to be extended from the surface of the second insulating film and to reach the upper electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory device having a memory cell for storing binarized data as a polarization state of a ferroelectric layer, and a manufacturing method thereof.

  As a so-called ferroelectric memory, an FeRAM (Ferroelectric Random Access Memory) is known.

The ferroelectric layer included in the FeRAM is formed of an oxygen compound material such as so-called SBT (SrBi ₂ Ta ₂ O ₉ ) or PZT (Pb (Zr, Ti) O ₃ ). This ferroelectric layer is formed in the periphery, for example, moisture (H ₂ O) inevitably mixed in the CVD film, hydrogen (H ₂ ) derived from this moisture, or a buried contact (plug). The reduction reaction is caused by the hydrogen generated when forming. This reduction reaction deteriorates the polarization characteristics of the ferroelectric layer.

  For example, in order to protect a ferroelectric layer made of PZT (lead zirconate titanate) from internally diffusing hydrogen, a configuration in which the ferroelectric layer is covered with a conductive diffusion barrier TiAlN (titanium aluminum nitride) is known. (See Patent Document 1).

  Further, for the purpose of suppressing and preventing deterioration of the characteristics of the memory cell capacitor due to hydrogen or a reducing atmosphere, the upper side of the memory cell capacitor is covered with an interlayer film for level difference made of TEOS or the like, and this interlayer film is further covered. A semiconductor memory device provided with a second hydrogen barrier film and a first hydrogen barrier film covering the lower side of the memory cell capacitor and a manufacturing method thereof are known (see Patent Document 2).

Furthermore, in order to prevent deterioration of the ferroelectric characteristics of the ferroelectric capacitor due to hydrogen diffusion caused by an interlayer dielectric film, an Al ₂ O ₃ film and a TiO ₂ film formed by the ALD method are laminated. A configuration in which the membrane is an encapsulating barrier layer is disclosed (see Non-Patent Document 1).
JP 2000-133633 A Japanese Patent Laid-Open No. 2003-068987 Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 394-395

  As disclosed in Patent Document 1, if a continuity with a contact is made through a TiAlN film provided as a hydrogen barrier film covering the ferroelectric layer, so-called contact resistance increases, The electrical characteristics of the device may be adversely affected.

  Further, as disclosed in Patent Document 2, if the periphery of the memory cell capacitor including the ferroelectric layer is covered with a silicon oxide film or the like for reducing the step, the step for reducing the step is performed in the etching process of the hydrogen barrier film. It is considered that the film functions as an etching stopper layer. However, in such a configuration, there is a possibility that the memory cell capacitor is deteriorated by hydrogen generated by the step-relief film.

Further, a hydrogen barrier film (encapsulated barrier film) having a configuration disclosed in Non-Patent Document 1 is opened, and a chlorine-based gas such as CF ₄ + CHF ₃ gas or Cl ₂ plasma, or a chlorine-based gas is used to establish conduction with the upper electrode. When an etching gas such as a mixed gas of fluorine gas is used, the etching rate of the upper electrode of the capacitor and the etching rate of the hydrogen barrier film are almost equal. Then, the upper electrode is unintentionally scraped off during the etching process of the hydrogen barrier film, and as a result, conduction failure in the upper electrode may occur, and contact resistance may become unstable.

  The present invention has been made in view of the above-described problems of the prior art. That is, an object of the present invention is to strongly prevent conduction failure in the upper electrode of the ferroelectric capacitor and instability of contact resistance effectively while preventing hydrogen or moisture penetration by the hydrogen barrier film. A dielectric memory device and a method for manufacturing the same are provided.

  In order to achieve these objects, the ferroelectric memory device of the present invention has the following configuration.

  That is, the ferroelectric memory device has a semiconductor substrate having a memory cell array region in which a plurality of memory cell elements are provided.

  The ferroelectric memory device also has a first insulating film provided so as to cover the memory cell array region of the semiconductor substrate.

  Furthermore, the ferroelectric memory device has a plurality of plugs that penetrate the first insulating film and are connected to the memory cell elements in the memory cell array region.

  Furthermore, the ferroelectric memory device is a ferroelectric capacitor structure provided on the first insulating film, and is provided with a part of the surface of the first insulating film exposed and connected to the plug. And a ferroelectric capacitor structure having a laminate including a conductive anti-oxidation film, a lower electrode, a ferroelectric layer, an upper electrode, and an etching stopper layer in this order.

  Further, the ferroelectric memory device includes a hydrogen barrier film that covers the exposed first insulating film and the ferroelectric capacitor structure. A second insulating film is provided on the hydrogen barrier film.

  Further, the ferroelectric memory device includes a contact hole that penetrates the second insulating film, the hydrogen barrier film, and the etching stopper layer and extends from the surface of the second insulating film to the upper electrode.

  The manufacturing method of the ferroelectric memory device according to the present invention includes the following steps.

  That is, a semiconductor substrate including a plurality of chip regions having a memory cell array region in which a plurality of memory cell elements are provided in a matrix is prepared.

  A first insulating film is formed on the semiconductor substrate on which the memory cell element is provided.

  A step of forming a ferroelectric capacitor structure on the first insulating film, wherein a lower electrode, a ferroelectric layer, an upper electrode, and an etching stopper layer exposing a part of the surface of the first insulating film are arranged in this order. The ferroelectric capacitor structure having the included laminate is formed.

  A hydrogen barrier film that covers the first insulating film and the ferroelectric capacitor structure is formed, and a second insulating film is formed on the hydrogen barrier film.

  A first opening that penetrates the second insulating film and reaches the surface of the hydrogen barrier film is formed.

  A second opening that penetrates the hydrogen barrier film and communicates with the first opening is formed in the hydrogen barrier film, and a recess that communicates with the second opening and reaches the thickness of the etching stopper layer is formed.

  The bottom of the concave portion of the etching stopper layer is scraped to form a third opening that exposes the upper electrode, and the first opening, the second opening, and the third opening communicate with each other and the surface of the second insulating film A contact hole extending from the upper electrode to the upper electrode is formed.

  The ferroelectric memory device according to the present invention has high operation reliability and excellent electrical characteristics, in particular, since the reliability of conduction of the contact connected to the upper electrode is high.

  Further, according to the method for manufacturing a ferroelectric memory device of the present invention, the upper electrode is not etched more than necessary in the etching process of the hydrogen barrier film, so that the reliability with so-called contact resistance is stabilized. High ferroelectric memory device can be manufactured efficiently and with high yield.

  In other words, the contact between the upper electrode and the contact can be made directly without any other film while preventing the upper electrode from deteriorating, so that the contact resistance is further reduced as compared with the above-described conventional configuration. can do. In addition, since the ferroelectric layer is covered with a hydrogen barrier film, it is possible to effectively prevent deterioration due to hydrogen due to the surrounding insulating film.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, it is to be understood that each component is only schematically shown to such an extent that the present invention can be understood, and the numerical conditions and the like listed below are merely examples.

<Configuration example of ferroelectric memory device>
A configuration example of the ferroelectric memory device of the present invention will be described with reference to FIG.

  FIG. 1 is a schematic view showing a cut end of a memory cell array region obtained by cutting the ferroelectric memory device of the present invention.

  The ferroelectric memory device 100 of the present invention is characterized by the structure of an etching stopper layer described later. As for other components, any suitable components of a conventionally known ferroelectric memory device can be appropriately selected and applied.

  As shown in FIG. 1, the ferroelectric memory device 100 includes a semiconductor substrate 11. A memory cell array region 1 is defined on the semiconductor substrate 11. In addition to the memory cell array region 1, the semiconductor substrate 11 has other regions such as a so-called logic circuit region including a configuration having a function of electrically controlling a structure provided in the memory cell array region 1 described later. It may be (not shown).

  As used herein, “region” means a three-dimensional region including components provided on the semiconductor substrate 11.

  A plurality of memory cell elements 10 are provided in the memory cell array region 1. These memory cell elements 10 are isolated from each other by an element isolation structure 5 formed by a conventionally known element isolation process, for example, STI (Shallow Trench Isolation) in this example.

  In the memory cell array region 1, a plurality of memory cells (ferroelectric capacitor structures) including a ferroelectric layer, which will be described later, are arranged in a matrix, but the region including two ferroelectric capacitor structures is illustrated. Shown and explained.

  The memory cell element 10 is a switch transistor, for example, and has a conventionally known configuration. For example, as a component of the transistor, in the illustrated example, a plurality of memory cell element diffusion regions 12, a memory cell element gate electrode 14, and the like are provided.

  The memory cell element diffusion region 12 is, for example, an ion diffusion region into which any suitable ions are implanted. The memory cell element gate electrode 14 is combined with the memory cell element diffusion region 12 to form the memory cell element 10. The memory cell element diffusion region 12 and the memory cell element gate electrode 14 can be combined in any conventionally known suitable structure.

  A first insulating film 30 is provided on the memory cell array region 1 in which the memory cell element 10 is formed, that is, on the entire upper surface of the semiconductor substrate 11 on which the memory cell element 10 is provided. The first insulating film 30 is preferably a silicon oxide film (hereinafter also simply referred to as a TEOS film) formed by a plasma CVD method using TEOS as a material, for example.

  A first contact hole 32 provided in the memory cell array region 1 is provided in the first insulating film 30. The first contact hole 32 extends from the surface 30a of the first insulating film 30 to the memory cell element 10 (memory cell element diffusion region 12). The inner surface of the first contact hole is covered with the first barrier layer 34. The first barrier layer 34 is preferably a titanium nitride (TiN) film.

  The first contact hole 32 covered with the first barrier layer 34 is filled with, for example, tungsten (W) to form a plug 36.

  A ferroelectric capacitor structure 40 is provided on the first insulating film 30. The ferroelectric capacitor structure 40 has a conventionally known configuration. That is, the ferroelectric capacitor structure 40 is formed of a multilayer structure including at least the lower electrode 44, the ferroelectric layer 45, and the upper electrode 46.

  In the illustrated example, the ferroelectric capacitor structure 40 includes a conductive antioxidant layer 41, a first adhesion layer 42, a second adhesion layer 43, a lower electrode 44, a ferroelectric layer 45, an upper electrode 46, and an etching stopper layer. 47 is formed as a laminated structure.

  The antioxidant layer 41 is preferably a titanium aluminum nitride (TiAlN) film.

  The antioxidant layer 41 is patterned by exposing a part of the surface 30 a of the first insulating film 30. The pattern shape of the antioxidant layer 41 may be any suitable planar shape and area that are necessary and sufficient to exhibit the function of the entire ferroelectric capacitor structure 40.

  The antioxidant layer 41 individually covers the top surfaces 36 a of the plurality of plugs 36 and is electrically connected to the plugs 36.

  This anti-oxidation layer 41 prevents conduction failure due to oxidation of the top surface 36a of the plug 36 by a plasma CVD process in the manufacturing process or a heat treatment called so-called recovery annealing. Further, the antioxidant film 41 prevents moisture or hydrogen from penetrating.

  A conductive first adhesion layer 42 is provided on the antioxidant layer 41. The first adhesion layer 42 is preferably an iridium (Ir) film. The pattern shape of the first adhesion layer 42 may be the same shape as the planar shape of the antioxidant layer 41.

A conductive second adhesion layer 43 is provided on the first adhesion layer 42. The second adhesion layer 43 is preferably a film of iridium oxide (IrO ₂ ). The pattern shape of the second adhesion layer 43 may be the same shape as the planar shape of the first adhesion layer 42.

  The laminated structure of the antioxidant film 41 and the first and second adhesion layers 42 and 43 is a structure for preventing moisture or hydrogen from penetrating upward from the laminated structure.

  On the second adhesion layer 43, a lower electrode 44 having the same planar shape as that of the second adhesion layer 43 is provided. The lower electrode 44 is preferably formed of platinum (Pt), for example.

A ferroelectric layer 45 having a planar shape similar to that of the lower electrode 44 is laminated on the lower electrode 44. The ferroelectric layer 45 is preferably an SBT (SrBi ₂ Ta ₂ O ₉ ) film, for example.

  On the ferroelectric layer 45, an upper electrode 46 having the same planar shape as that of the ferroelectric layer 45 is provided. The upper electrode 46 is preferably a platinum film, for example.

  An etching stopper layer 47 is provided on the upper electrode 46. The etching stopper layer 47 has the same planar shape as that of the upper electrode 46. The material of the etching stopper layer 47 may be determined in consideration of a selection ratio in an etching process with respect to a hydrogen barrier film described later, but is preferably a silicon oxide film.

  The etching stopper layer 47 has an opening (third opening 52) from the upper surface 47a to the upper surface 46a of the upper electrode 46.

  The hydrogen barrier film 60 is provided so as to integrally cover a plurality of ferroelectric capacitor structures 40 provided in a matrix in the memory cell region 1. That is, the hydrogen barrier film 60 is provided on the entire memory cell region 1.

  The hydrogen barrier film 60 includes the exposed surface of the ferroelectric capacitor structure 40 in the memory cell region 1, that is, the side surface of the antioxidant layer 41, the side surface of the first adhesion layer 42, the side surface of the second adhesion layer 43, and the lower electrode. 44, the side surface of the ferroelectric layer 45, the side surface of the upper electrode 46, the upper surface 47a of the etching stopper film 47 and the exposed surface which is the side surface, and is provided on the surface 30a of the remaining first insulating film 30. It has been.

  In the illustrated example, only the memory cell region 1 is shown. However, the hydrogen barrier film 60 is a film that covers another region (not shown) adjacent to the memory cell region 1, that is, a logic circuit region, for example. It is provided as.

  As a result, the ferroelectric layer 45 is sealed and surrounded by the hydrogen barrier film 60 that is impermeable to hydrogen or moisture, and the antioxidant layer 41, the first adhesion layer 42, and the second adhesion layer 43 that have already been described. In particular, the oxide film formed by the CVD method is protected from hydrogen generated.

Examples of the hydrogen barrier film 60 include tantalum oxide (TaOx), titanium oxide (TiOx), and aluminum oxide (alumina: Al ₂ O ₃ ). It is better to use a membrane.

  The hydrogen barrier film 60 is provided with an opening (second opening 62) extending from the surface 60a to the upper surface 47a of the etching stopper film 47. The second opening 62 communicates with the already described third opening 52 to expose a part of the upper surface 46a of the upper electrode 46.

  A second insulating film 70 is provided on the hydrogen barrier film 60. The second insulating film 70 is preferably a silicon oxide film formed by a conventionally known CVD method, for example.

  The second insulating film 70 is provided from the memory cell array region 1 on the hydrogen barrier film 60 to another region adjacent thereto.

  The second insulating film 70 is provided with an opening from the surface 70 a to the surface 60 a of the hydrogen barrier film 60, that is, a first opening 72. The first opening 72 is provided in communication with the second opening 62.

  That is, the ferroelectric memory device 100 has a contact hole (second contact hole 90) extending from the surface 70a of the second insulating film 70 to the upper surface 46a of the upper electrode 46.

  A second barrier layer 91 is provided on a part of the inner surface (side wall and bottom surface) of the second contact hole 90 and a surface 70a of the second insulating film 70 on which a first wiring layer (92) described later is formed. That is, the second barrier layer 91 covers a region where the first wiring layer (92) extends.

  The second barrier layer 91 is preferably a titanium nitride film, for example. As will be described in detail later, the second barrier layer 91 is a layer for improving the adhesion between the first wiring layer 92 and the first insulating film 30, and the first wiring layer 92 is embedded in the second contact hole 90. Can be improved. At the same time, the second barrier layer 91 also functions as a barrier film that prevents hydrogen penetration. The second barrier layer 91 is provided so as to be connected to the hydrogen barrier film 60 exposed from the contact hole 90. That is, the second barrier layer 91, together with the hydrogen barrier film 60, seals the ferroelectric capacitor structure 40 from above, and blocks hydrogen that permeates through the wiring layer.

  The first wiring layer 92 is provided on the second barrier layer 91. The first wiring layer 92 fills the second contact hole 90 covered with the second barrier layer 91 and is electrically connected to the upper electrode 46, that is, the ferroelectric capacitor structure 40.

  The first wiring layer 92 is preferably a metal wiring such as aluminum (Al) or copper (Cu).

  Further, if the second barrier layer 91 is provided, particularly when the first wiring layer 92 is an aluminum wiring layer, there is a problem caused by the reaction between the aluminum wiring and platinum which is the material of the upper electrode 46. It can be effectively prevented.

  With the first wiring layer 92 as a first layer, the second and third layers electrically connected to the first wiring layer 92 above the first wiring layer 92 through further interlayer insulating films and vias. A multilayer wiring structure including these wiring layers may be further provided (not shown).

<Manufacturing Method of Ferroelectric Memory Device>
Next, an example of a method for manufacturing the ferroelectric memory device of the present invention will be described with reference to FIGS.

  In the manufacturing method of the present invention, the contact hole (plug) forming step connected to the upper electrode of the ferroelectric capacitor structure including the ferroelectric layer, that is, the ferroelectric capacitor structure is arranged in a matrix. The manufacturing process in the memory cell array region is characterized. For example, the configuration of the logic circuit region and the like for controlling the operation of the memory cell adjacent to the memory cell array region and the manufacturing process thereof are not different from the conventional one.

  Therefore, in order to avoid complication of the explanatory diagram, only a part of the memory cell array region of one ferroelectric memory is illustrated and described among many ferroelectric memory devices formed simultaneously on one wafer. To do.

  2A, 2B, and 2C are schematic manufacturing process diagrams showing a cut end of a ferroelectric memory device that is being manufactured at the wafer level.

  3A and 3B are manufacturing process diagrams following FIG. 2C.

  4 (A) and 4 (B) are manufacturing process diagrams following FIG. 3 (B).

  As shown in FIG. 2A, first, a plurality of chip regions including the memory cell array region 1 are partitioned in a matrix on a semiconductor substrate (wafer) 11.

  A memory cell element 10 is formed in the memory cell array region 1 of the semiconductor substrate 11 by a conventionally known wafer process.

  Specifically, for example, a field oxide film by a LOCOS method, an element isolation structure 5 such as a so-called STI is formed.

  Next, the memory cell element 10 including the memory cell element diffusion region 12 and the memory cell element gate electrode 14 which are components such as transistors is formed in the memory cell array region 1.

  Next, a first insulating film 30 is formed on the entire upper surface of the semiconductor substrate 11 including the memory cell array region 1 in which the memory cell element 10 is formed.

  Specifically, the film forming process of the first insulating film 30 is preferably a silicon oxide film forming process performed by a conventionally known plasma CVD method using TEOS as a material. The film thickness of the first insulating film 30 may be about 700 nm.

  Next, a first contact hole 32 extending from the surface 30 a of the first insulating film 30 to the memory cell element 10 is formed in the first insulating film 30. The first contact hole 32 may be formed by a conventionally known photolithography process and etching process.

  Next, a first barrier film, which is a so-called barrier metal, is formed on the entire exposed surface of the first contact hole 32. As the first barrier film, for example, titanium nitride may be formed according to a conventional method.

  Next, using a conductive material such as tungsten (W), the first contact hole 32 provided with the first barrier film is filled according to a conventional method, and an etch back process is performed. A plug 36 exposed from the surface 30a of the insulating film 30 is formed. By this step, the first barrier film becomes the first barrier layer 34 that covers the inner surface (side surface and bottom surface) of the first contact hole 32 with a substantially uniform film thickness.

  As shown in FIG. 2B, an antioxidant film 41X covering the top surface 36a of the first plug 36 is formed on the first insulating film 30 according to a conventional method. This film forming process can be a film forming process such as any suitable conventionally known sputtering method or CVD method according to a desired material.

  In the same film forming process, for example, the first adhesion film 42X is formed on the antioxidant film 41X, the second adhesion film 43X is formed on the first adhesion film 42X, and the second film is formed using any suitable film formation material described above. A lower electrode film 44X is formed on the adhesion film 43X, a ferroelectric film 45X is formed on the lower electrode film 44X, an upper electrode film 46X is formed on the ferroelectric film 45X, and an etching stopper film 47X is formed on the upper electrode film 46X. The film is formed.

  Specifically, the antioxidant film 41X, the first adhesion film 42X, the second adhesion film 43X, the lower electrode film 44X, and the upper electrode film 46X may be formed by a sputtering process under any suitable conditions.

As the anti-oxidation film 41X, Ti / Al (composition ratio 1: 1) is used as a target material, and a TiAlN film is formed under an Ar / N ₂ atmosphere with an applied power of 100 watts and a substrate temperature of 200 ° C. Good.

  As described above, the first adhesion film 42X is formed using iridium as a target material and using, for example, argon (Ar) gas under an applied power of 1000 watts and a substrate temperature of 400 ° C. The film thickness may be about 50 nm.

  As described above, the second adhesion film 43X is formed by using iridium as a target material and using, for example, an argon / oxygen mixed gas under conditions of an applied power of 500 watts and a substrate temperature of 350 ° C. The film thickness may be about 50 nm.

  As described above, the lower electrode film 44X and the upper electrode film 46X are formed using platinum as a target material and using argon gas under an applied power of 1000 watts and a substrate temperature of 200 ° C. Each film thickness may be about 200 nm.

  The ferroelectric film 45X may be formed by a conventionally known sol-gel method according to a conventional method.

  Specifically, the SBT solution is applied on the lower electrode film 44X by a spin-on process. Next, crystallization annealing is performed at 700 ° C. Further, an SBT solution is applied in layers, and a second crystallization annealing is performed at 700 ° C. Furthermore, the SBT solution may be applied repeatedly, and this time, the third crystallization annealing may be performed at 800 ° C.

  An etching stopper film 47X is formed on the upper electrode film 46X. As the etching stopper film 47X, for example, a silicon oxide film, for example, may be formed by any conventionally known suitable process.

  As shown in FIG. 2C, the antioxidant film 41X, the first adhesion film 42X, the second adhesion film 43X, the lower electrode film 44X, the ferroelectric film 45X, the upper electrode film 46X, and the etching stopper film 47X are formed. Using a mask pattern (not shown) as a mask, a ferroelectric capacitor structure 40 that is placed on the plug 36 and electrically connected to the plug 36 is formed by a dry etching process according to a conventional method.

  In the ferroelectric capacitor structure 40, an antioxidant layer 41, a first adhesion layer 42, a second adhesion layer 43, a lower electrode 44, a ferroelectric layer 45, an upper electrode 46, and an etching stopper layer 47 are laminated. That is, the ferroelectric capacitor structure 40 has an etching stopper layer 47 that covers only the upper surface 46a of the upper electrode 46 as the uppermost layer.

  Here, a so-called recovery annealing process for recovering the deterioration of the ferroelectric layer 45 is performed. Specifically, this step is preferably performed by heat treatment in an oxygen atmosphere in the range of 550 ° C. to 850 ° C. for 30 minutes to 90 minutes, particularly preferably 600 ° C. for about 60 minutes.

  In the manufacturing process of the present invention, when this recovery annealing process is performed, the top surface 36a of the plug 36 connected to the memory cell element 10 is not exposed, but is covered and protected by the antioxidant layer 41. Accordingly, it is possible to effectively prevent conduction failure due to oxidation of the plug 36 due to the recovery annealing step, and consequently, oxidation of the plug 36.

  As shown in FIG. 3A, a hydrogen barrier film 60 is formed. The hydrogen barrier film 60 covers the exposed surface of the ferroelectric capacitor structure 40 in the memory cell region 1 and reaches the surface 30 a of the first insulating film 30 around the ferroelectric capacitor structure 40. Form up to.

  When the hydrogen barrier film 60 is an aluminum oxide film, the film formation process of the hydrogen barrier film 60 can be performed by, for example, an atomic layer film forming method. Specifically, aluminum oxide having a desired film thickness can be obtained by repeating a deposition process in which triethylaluminum gas and ozone gas are alternately introduced into the chamber. Preferably, the thickness of the hydrogen barrier film 60 may be about 50 nm.

  As a result, the ferroelectric layer 45 of the ferroelectric capacitor structure 40, as a result, includes a hydrogen barrier film 60 located on the upper side, a second barrier film 91 (described later), an antioxidant layer 41 located on the lower side, and The whole is covered with the first and second adhesion layers 42 and 43, and is sealed without gaps therebetween. As described above, the antioxidant layer 41, the first adhesion layer 42, and the second adhesion layer 43 also have a function of preventing hydrogen permeation, that is, entry of hydrogen from the lower side of the ferroelectric capacitor structure 40. That is, the ferroelectric layer 45 is completely shielded from hydrogen existing in the external environment.

  Next, a second insulating film 70 is formed. The second insulating film 70 is formed over the entire surface of the memory cell array region 1. That is, the second insulating film 70 is formed so as to cover the hydrogen barrier film 60 that covers the ferroelectric capacitor structure 40.

  For example, a silicon oxide film may be deposited on the second insulating film 70 by a conventional CVD method.

  Next, a resist film 80 for forming contact holes is formed on the entire surface 70a of the second insulating film 70 using any suitable resist material.

  An opening pattern 82 extending from the surface 80a of the resist film 80 to the surface 70a of the second insulating film 70 is formed by a photolithography process according to a conventional method. The opening pattern 82 is located immediately above the ferroelectric capacitor structure 40.

  Next, a second contact hole 90 (see FIG. 1) is formed. The second contact hole 90 is a contact hole extending from the surface 70 a of the second insulating film 70 to the upper surface 46 a of the upper electrode 46. The formation process of the second contact hole 90 includes a three-stage etching process (hereinafter referred to as a first etching process, a second etching process, and a third etching process).

  As shown in FIG. 3B, as the first etching step, a first opening 72 that penetrates the second insulating film 70 and reaches the surface 60 a of the hydrogen barrier film 60 is formed. This step is performed as an etching step using a hydrogen barrier film 60 made of, for example, aluminum oxide as an etching stopper film according to a conventional method.

  As shown in FIG. 4A, the second etching step is subsequently performed. This second etching step is performed from the surface 60 a of the hydrogen barrier film 60 to within the thickness of the etching stopper layer 47.

  Specifically, the second etching step forms a second opening 62 that communicates with the first opening 72 and penetrates the hydrogen barrier film 60, and communicates with the second opening 62 to form an upper portion. This is a step of forming the recess 52X that reaches the thickness of the etching stopper layer 47 provided on the electrode 46.

  At this time, if the selection ratio of the etching stopper layer to the hydrogen barrier film is less than 0.7, the etching is excessively etched up to the upper electrode 46 through the etching stopper layer 47, and the upper electrode 46 is lost, resulting in contact resistance. May become unstable. Therefore, this second etching step is performed so that the selection ratio of the etching stopper layer 47 to the hydrogen barrier film 60 is at least about 0.7.

  The larger the selection ratio, the better. However, considering the realistic film thickness, productivity, cost, etc. of the etching stopper layer, a sufficient effect can be obtained if the selection ratio is at least about 0.7. .

Specifically, it may be performed as a dry etching process using a mixed gas of chlorine gas such as BCl ₃ and Cl ₂ .

  Hereinafter, specific etching conditions will be described as examples with reference to Table 1. In this example, the etching stopper layer 47 is a silicon oxide film, and the hydrogen barrier film 60 is an aluminum oxide film.

  Table 1 is a table showing the etching conditions when etching the aluminum oxide film and the selection ratio with respect to the silicon oxide film.

Thus, the selection ratio can be optimized by making the applied power smaller and lowering the flow rate ratio of BCl ₃ compared to the conventional etching conditions.

Specifically, the BCl ₃ gas flow rate is preferably 50 SCCM, provided that the electrode applied power is 70 watts (W) and the sum of the BCl ₃ gas flow rate (SCCM) and the Cl ₂ gas flow rate (SCCM) is 100 SCCM. If the Cl ₂ gas flow rate is in the range of 50 SCCM to 30 SCCM, the Al ₂ O ₃ / SiO ₂ selection ratio can be about 0.8 to 0.9.

That is, the Al ₂ O ₃ / SiO ₂ selection ratio can be further reduced as compared with the case where a conventional chlorine gas or a mixed gas of chlorine gas and F (fluorine) gas is used. It becomes easy to control the etching amount in the etching process so as to be within the thickness of the etching stopper layer 47.

  Accordingly, the thickness of the etching stopper layer 47 can be set to any suitable thickness on the condition that the etching does not reach the upper electrode during the etching process of the hydrogen diffusion barrier film.

  As a result, according to such an etching process, the progress of etching (reaction) can be temporarily stopped within the thickness of the etching stopper layer 47. Therefore, for example, in the etching process of the hydrogen barrier film 60 that is an aluminum oxide film, a phenomenon in which the upper electrode 46 is excessively shaved due to excessive etching can be prevented.

  As shown in FIG. 4B, a third etching step is subsequently performed. The third etching step is a step of etching the bottom 52Xa of the recess 52X existing within the thickness of the etching stopper layer 47. By this third etching step, a third opening 52 that exposes the upper surface 46 a of the upper electrode 46 and communicates with the second opening 62 is formed. As a result, the first opening 72, the second opening 62, and the third opening 52 communicate with each other to complete the second contact hole 90 from the surface 70a of the second insulating film 70 to the upper surface 46a of the upper electrode 46. To do.

The third etching step may be performed using, for example, a mixed gas of C ₄ F ₈ / Ar / O ₂ . Specifically, the flow rate ratio of C ₄ F ₈ / Ar / O ₂ may be 20 SCCM / 500 SCCM / 10 SCCM, the applied power may be 1500 watts, and the pressure may be 5.33 Pa (40 mTorr).

  4B, after removing the resist film 80, the second barrier film 91X is formed on the entire inner surface (side wall and bottom surface) of the second contact hole 90 and the entire surface 70a of the second insulating film 70. Form.

  As the second barrier film 91X, a TiN film is preferably formed under any suitable conditions by a conventionally known method.

  Next, as shown in FIG. 1, a first wiring layer 92 is formed. The first wiring layer 92 is formed by filling the second contact hole 90 covered with the second barrier film 91X and connecting to the upper electrode 46.

  The first wiring layer 92 is preferably formed using a metal material such as aluminum (Al) or copper (Cu), for example.

  The first wiring layer 92 may be patterned into a desired wiring pattern by a conventionally known film forming process, photolithography process, and etching process. At this time, the second barrier film 91X is patterned as the second barrier layer 91 in the same shape as the wiring pattern of the first wiring layer 92 in plan view.

  Although not shown, the first wiring layer 92 is used as a first layer, an interlayer insulating film covering the wiring layer, a via hole formed in the interlayer insulating film, a via hole is buried, and a plug connected to a lower layer wiring, plug A desired multilayer wiring structure can be formed by repeating the step of forming a further wiring layer connected to the.

  Thereafter, by dicing along a scribe line (not shown) using a conventionally known dicing apparatus, a plurality of chip areas set in advance on the substrate 11 are cut out and separated into individual pieces.

  In this way, a plurality of ferroelectric memory devices 100 having a so-called semiconductor chip configuration and the same structure can be manufactured from one wafer 11.

1 is a schematic diagram showing a partial cut surface obtained by cutting a part of a ferroelectric memory device according to the present invention; FIG. (A), (B), and (C) are schematic manufacturing process diagrams showing a cut surface of a ferroelectric memory device being manufactured at the wafer level. FIGS. 2A and 2B are manufacturing process diagrams subsequent to FIG. FIGS. 3A and 3B are manufacturing process diagrams subsequent to FIG.

Explanation of symbols

1: memory cell array region 5: element isolation structure 10: memory cell element 11: semiconductor substrate 12: memory cell element diffusion region 14: memory cell element gate electrode 30: first insulating film 30a: surface 32: first contact hole 34: First barrier layer 36: Plug 36a: Top surface 40: Ferroelectric capacitor structure 41: Antioxidation layer 41X: Antioxidation film 42: First adhesion layer 42X: First adhesion film 43: Second adhesion layer 43X: First 2 Adhesive film 44: Lower electrode 44X: Lower electrode film 45: Ferroelectric layer 45X: Ferroelectric film 46: Upper electrode 46a: Upper surface 46X: Upper electrode film 47: Etching stopper layer 47a: Upper surface 47X: Etching stopper film 52 : Third opening 52X: recess 52Xa: bottom 60: hydrogen barrier film 60a: surface 62: second opening 70: second insulating film 70a: surface 72: first opening Part 80: resist film 80a: surface 82: aperture pattern 90: second contact hole 91: second barrier layer 91X: second barrier film 92: first wiring layer 100: a ferroelectric memory device

Claims (9)

A semiconductor substrate having a memory cell array region provided with a plurality of memory cell elements;
A first insulating film provided to cover the memory cell array region of the semiconductor substrate;
A plurality of plugs provided in the memory cell array region through the first insulating film and connected to the memory cell element;
A ferroelectric capacitor structure provided on the first insulating film, wherein the conductive antioxidant film is provided by exposing a part of the surface of the first insulating film and connected to the plug The ferroelectric capacitor structure having a laminate including a lower electrode, a ferroelectric layer, an upper electrode, and an etching stopper layer in this order;
A hydrogen barrier film covering the exposed first insulating film and the ferroelectric capacitor structure;
A second insulating film provided on the hydrogen barrier film;
A ferroelectric memory comprising a contact hole penetrating through the second insulating film, the hydrogen barrier film and the etching stopper layer and extending from the surface of the second insulating film to the upper electrode. apparatus.   2. The ferroelectric memory device according to claim 1, wherein the etching stopper layer is a silicon oxide film, and the hydrogen barrier film is an aluminum oxide film.   The barrier layer which covers the inner surface of the said contact hole, is connected with the said hydrogen barrier film | membrane, and seals the said ferroelectric capacitor structure from the upper side is further provided. 2. A ferroelectric memory device according to 1. Preparing a semiconductor substrate including a plurality of chip regions having a memory cell array region in which a plurality of memory cell elements are provided in a matrix;
Forming a first insulating film on the semiconductor substrate provided with the memory cell element;
Forming a ferroelectric capacitor structure on the first insulating film, wherein a lower electrode, a ferroelectric layer, an upper electrode, and an etching stopper layer exposing a part of the surface of the first insulating film; Forming the ferroelectric capacitor structure having the multilayer body included in this order;
Forming a hydrogen barrier film covering the first insulating film and the ferroelectric capacitor structure;
Forming a second insulating film on the hydrogen barrier film;
Forming a first opening that penetrates the second insulating film and reaches the surface of the hydrogen barrier film;
A recess that penetrates through the hydrogen barrier film, forms a second opening in the hydrogen barrier film and communicates with the first opening, and communicates with the second opening and reaches the thickness of the etching stopper layer. Forming a step;
The bottom of the recess of the etching stopper layer is scraped to form a third opening that exposes the upper electrode, and the first opening, the second opening, and the third opening communicate with each other. Forming a contact hole from the surface of the second insulating film to the upper electrode. The method of manufacturing a ferroelectric memory device according to claim 1, further comprising: Preparing a semiconductor substrate including a plurality of chip regions having a memory cell array region in which a plurality of memory cell elements are provided in a matrix;
Forming a first insulating film on the semiconductor substrate provided with the memory cell element;
Forming a plurality of plugs connected to the memory cell element through the first insulating film in the memory cell array region;
An antioxidant film covering the top surface of the plug and the first insulating film; a first adhesion film; a second adhesion film provided on the first adhesion film; a lower electrode film provided on the second adhesion film; Sequentially forming a ferroelectric film provided on the lower electrode film, an upper electrode film provided on the ferroelectric film, and an etching stopper film provided on the upper electrode film;
Patterning the first adhesion film, the second adhesion film, the lower electrode film, the ferroelectric film, the upper electrode film, and the etching stopper film to expose a portion of the surface of the first insulating film; A ferroelectric capacitor structure in which an antioxidant layer, a first adhesion layer, a second adhesion layer, a lower electrode, a ferroelectric layer, an upper electrode, and an etching stopper layer connected to the plug are sequentially laminated; Forming a step;
Forming a hydrogen barrier film covering the exposed first insulating film and the ferroelectric capacitor structure;
Forming a second insulating film on the hydrogen barrier film;
Forming a first opening that penetrates the second insulating film and reaches the surface of the hydrogen barrier film;
A recess that penetrates the hydrogen barrier film, forms a second opening in the hydrogen barrier film and communicates with the first opening, and communicates with the second opening and reaches the thickness of the etching stopper layer. Forming a step;
The bottom of the recess of the etching stopper layer is scraped to form a third opening that exposes the upper electrode, and the first opening, the second opening, and the third opening communicate with each other. Forming a contact hole from the surface of the second insulating film to the upper electrode. A method for manufacturing a ferroelectric memory device, comprising:   After the step of forming the contact hole, a step of forming a barrier layer that covers the inner surface of the contact hole and is connected to the hydrogen barrier film to seal the ferroelectric capacitor structure from above. 6. The ferroelectric memory device according to claim 4, further comprising a ferroelectric memory device. The step of forming the etching stopper film is a step of forming a silicon oxide film,
The step of forming the hydrogen barrier film is a step of forming an aluminum oxide film,
7. The step of forming the second opening and the recess is an etching step in which a selection ratio of the etching stopper film to the hydrogen barrier film is 0.7 at a minimum. A method for manufacturing a ferroelectric memory device according to claim 1. 8. The method of manufacturing a ferroelectric memory device according to claim 7, wherein the etching process is a dry etching process using a mixed gas containing BCl ₃ gas and Cl ₂ gas. In the etching step, the flow rate of the BCl ₃ gas is set to a range of 50 SCCM to 70 SCCM on the condition that the sum of the flow rate of the BCl ₃ gas and the flow rate of the Cl ₂ gas is 100 SCCM, and the flow rate of the Cl ₂ gas 9. The method of manufacturing a ferroelectric memory device according to claim 8, wherein the dry etching process is performed in a range of 50 SCCM to 30 SCCM.

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