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JP2007027261A - Power module - Google Patents

Power module Download PDF

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Publication number
JP2007027261A
JP2007027261A JP2005204463A JP2005204463A JP2007027261A JP 2007027261 A JP2007027261 A JP 2007027261A JP 2005204463 A JP2005204463 A JP 2005204463A JP 2005204463 A JP2005204463 A JP 2005204463A JP 2007027261 A JP2007027261 A JP 2007027261A
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Prior art keywords
ceramic substrate
wiring
power module
semiconductor element
power semiconductor
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Inventor
Kazuhiro Tada
和弘 多田
Tetsushi Tanda
哲史 反田
Kei Yamamoto
圭 山本
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2005204463A priority Critical patent/JP2007027261A/en
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/181—Encapsulation

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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a transfer molded power module exhibiting excellent heat dissipation properties in which cracking and detachment are prevented. <P>SOLUTION: In the transfer molded power module where one power semiconductor element 2 is mounted on each of a plurality of wiring ceramic substrates 1, the wiring ceramic substrate 1 is obtained by forming a wiring layer 1b on a ceramic substrate 1a. A bonding member 3a is bonded to the ceramic substrate 1a of the wiring ceramic substrate 1, a bonding member 3b is bonded to the wiring layer 1b, and a bonding member 3c is bonded to the wiring layer 1b and other wiring ceramic substrate 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、放熱特性に優れたパワーモジュール、特にトランスファーモールド型のパワーモジュールに関するものである。   The present invention relates to a power module excellent in heat dissipation characteristics, particularly to a transfer mold type power module.

パワーモジュールにおいては、電気的な絶縁を確保しながら、パワー半導体素子から発生する熱をいかに放熱するかが重要である。
従来のパワーモジュールとしては、導電体板を設けたセラミック基板を放熱板上に取り付け、上記導電体板に半導体チップ（パワー半導体素子）を搭載し、上記セラミック基板における導電体板の周囲端部に、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂等の固体絶縁物を配置し、上記セラミック基板を囲うように上記放熱板上にケースを設け、このケース内にシリコーンゲルを封止樹脂として充填したものがある（例えば、特許文献１参照）。 In a power module, it is important how to dissipate heat generated from a power semiconductor element while ensuring electrical insulation.
As a conventional power module, a ceramic substrate provided with a conductor plate is mounted on a heat radiating plate, a semiconductor chip (power semiconductor element) is mounted on the conductor plate, and the periphery of the conductor plate in the ceramic substrate is mounted. There is a case in which a solid insulator such as an epoxy resin, a phenol resin, or a polyimide resin is disposed, a case is provided on the heat sink so as to surround the ceramic substrate, and silicone gel is filled as a sealing resin in the case (For example, refer to Patent Document 1).

特開２００２−７６１９７号公報（第１頁）JP 2002-76197 A (first page)

上記従来のパワーモジュールは、放熱特性に優れているがコストが高く、封止樹脂として用いたシリコーンゲルは柔軟性があるが、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂等の硬い絶縁物を封止樹脂として用いたものに比べて破壊電圧が低い。
一方、上記硬い絶縁物を封止樹脂とし、セラミック基板を用いて、量産性に優れたトランスファーモールドによりパワーモジュールを製造する方法が用いられるが、この方法では、上記封止樹脂と配線セラミック基板とでは線膨張係数が大きく異なるため、製造工程中または使用中において、封止樹脂とセラミック基板の間に応力が発生し、上記封止樹脂の配線セラミック基板との界面における剥離やセラミック基板の割れが発生するという課題がある。 The above conventional power module is excellent in heat dissipation characteristics but high in cost, and the silicone gel used as a sealing resin is flexible, but a hard insulator such as an epoxy resin, a phenol resin, or a polyimide resin is used as the sealing resin. The breakdown voltage is lower than that used in the above.
On the other hand, a method of manufacturing a power module by transfer molding excellent in mass productivity using a hard insulating material as a sealing resin and a ceramic substrate is used. In this method, the sealing resin and a wiring ceramic substrate are used. Since the linear expansion coefficient differs greatly, stress is generated between the sealing resin and the ceramic substrate during the manufacturing process or during use, and peeling at the interface between the sealing resin and the wiring ceramic substrate or cracking of the ceramic substrate occurs. There is a problem that occurs.

本発明は、かかる課題を解決するためになされたものであり、放熱性に優れ、クラックや剥離が防止された、トランスファーモールド型のパワーモジュールを得ることを目的とする。   The present invention has been made to solve such a problem, and an object of the present invention is to obtain a transfer mold type power module that has excellent heat dissipation and prevents cracking and peeling.

本発明に係るパワーモジュールは、セラミック基板に配線層が形成されてなる複数の配線セラミック基板と、少なくとも一つの上記配線層に搭載されたパワー半導体素子と、上記複数の配線セラミック基板および上記パワー半導体素子をモールドする封止樹脂と、上記複数の配線セラミック基板に接合された接合部材とを備えたものである。   A power module according to the present invention includes a plurality of wiring ceramic substrates each having a wiring layer formed on a ceramic substrate, a power semiconductor element mounted on at least one of the wiring layers, the plurality of wiring ceramic substrates, and the power semiconductor. A sealing resin for molding the element and a bonding member bonded to the plurality of wiring ceramic substrates are provided.

本発明によれば、配線セラミック基板を複数個用いることにより、セラミック基板のクラックや封止樹脂の剥離が防止された、トランスファーモールド型のパワーモジュールを得ることができるという効果がある。   According to the present invention, by using a plurality of wiring ceramic substrates, there is an effect that a transfer mold type power module in which cracking of the ceramic substrate and peeling of the sealing resin are prevented can be obtained.

実施の形態１．
図１は、本発明の実施の形態１おける、トランスファーモールド用の封止樹脂６を透視したパワーモジュールの概略構成を示す上面図であり、図２（ａ）、（ｂ）は、各々図１のａ−ａ線における断面図と、ｂ−ｂ線における断面図である。
本実施の形態のパワーモジュールは、４個の配線セラミック基板１にそれぞれ各１個のパワー半導体素子２が搭載されたもので、上記配線セラミック基板１はセラミック基板１ａに配線層１ｂが形成されたものからなり、上記配線セラミック基板１の配線層１ｂに各１個のパワー半導体素子２がダイボンド剤４により搭載されている。また、接合部材３ａが上記配線セラミック基板１のセラミック基板１ａに、接合部材３ｂが配線層１ｂに接合され、接合部材３ｃが配線層１ｂに接合されるとともに別の配線セラミック基板１に架設されている。また、パワー半導体素子２の上面とリード３ｘ間およびパワー半導体素子２の上面と接合部材３ｂ間は、ワイヤ５により接続され、封止樹脂６で封止されたトランスファーモールド型のものである。なお、本実施の形態に係わる上記接合部材３ａ〜３ｃは、製造工程において有効となるもので、詳細は下記に示す。
また、図１に示すように、本実施の形態のパワーモジュールは、上記配線セラミック基板１における、パワー半導体素子２の搭載面の反対面を露出させてモールドされているので高い放熱性を維持することができる。 Embodiment 1 FIG.
FIG. 1 is a top view showing a schematic configuration of a power module seen through a transfer molding sealing resin 6 in Embodiment 1 of the present invention, and FIGS. They are sectional drawing in the aa line, and sectional drawing in the bb line.
In the power module of the present embodiment, one power semiconductor element 2 is mounted on each of four wiring ceramic substrates 1, and the wiring ceramic substrate 1 has a wiring layer 1b formed on a ceramic substrate 1a. Each power semiconductor element 2 is mounted on the wiring layer 1 b of the wiring ceramic substrate 1 by a die bond agent 4. Further, the bonding member 3a is bonded to the ceramic substrate 1a of the wiring ceramic substrate 1, the bonding member 3b is bonded to the wiring layer 1b, and the bonding member 3c is bonded to the wiring layer 1b and is installed on another wiring ceramic substrate 1. Yes. The upper surface of the power semiconductor element 2 and the leads 3x and the upper surface of the power semiconductor element 2 and the bonding member 3b are connected by a wire 5 and are of a transfer mold type sealed with a sealing resin 6. In addition, the said joining members 3a-3c concerning this Embodiment become effective in a manufacturing process, and a detail is shown below.
Further, as shown in FIG. 1, the power module of the present embodiment is molded by exposing the surface opposite to the mounting surface of the power semiconductor element 2 in the wiring ceramic substrate 1, so that high heat dissipation is maintained. be able to.

図３（ａ）〜（ｅ）は、本実施の形態における、トランスファーモールドによるパワーモジュールの製造方法の概略を示す工程図である。
まず、図３（ａ）に示すように、半田をダイボンド剤４として、パワー半導体素子２を配線セラミック基板１の配線層１ｂの所定位置に固定する。上記のように、ダイボンド剤４として半田を用いる場合は、上記配線層１ｂの表面にニッケルメッキが施されているのが好ましいが、ダイボンド剤４として導電性樹脂を用いたり、ダイボンド剤４として半田を用いて還元雰囲気下で固定する場合は必ずしも必要ではない。
また、図３（ｂ）に示すリードフレーム３を用意する。つまり、リードフレーム３は、トランスファーモールドにおいて固定部材となるフレーム３０と、一方が上記フレーム３０に接合したリード３ａ、３ｂ、３ｃ、３ｘとからなる。また、上記リード３ａ、３ｂ、３ｃは各々配線セラミック基板１に接合するように設けられ、本実施の形態に係わる接合部材となるものである。
なお、リードフレーム３の材質は特に限定されるものではないが、導電性に優れるとともに安価であることから、銅およびその合金が好ましく、半田とのぬれ性改善や酸化防止の面から、表面にニッケル等によるメッキを施していてもよい。 3A to 3E are process diagrams showing an outline of a method of manufacturing a power module by transfer molding in the present embodiment.
First, as shown in FIG. 3A, the power semiconductor element 2 is fixed at a predetermined position on the wiring layer 1 b of the wiring ceramic substrate 1 by using solder as the die bond agent 4. As described above, when solder is used as the die bond agent 4, it is preferable that the surface of the wiring layer 1 b is nickel-plated, but a conductive resin is used as the die bond agent 4, or solder is used as the die bond agent 4. It is not always necessary to fix in a reducing atmosphere using
Also, a lead frame 3 shown in FIG. 3B is prepared. That is, the lead frame 3 includes a frame 30 that is a fixing member in the transfer mold, and leads 3 a, 3 b, 3 c, and 3 x that are joined to the frame 30. The leads 3a, 3b, and 3c are provided so as to be joined to the wiring ceramic substrate 1 and serve as joining members according to the present embodiment.
The material of the lead frame 3 is not particularly limited, but copper and its alloys are preferable because they are excellent in conductivity and are inexpensive, and on the surface from the viewpoint of improving wettability with solder and preventing oxidation. It may be plated with nickel or the like.

次に、図３（ｃ）に示すように、上記リードフレーム３の接合部材（リード）３ａ、３ｂ、３ｃの先端部に、パワー半導体素子２を搭載した複数の配線セラミック基板１を載置し、接合部材３ａ、３ｂ、３ｃを各配線セラミック基板１に接合することにより、配線セラミック基板１をフレーム３０に固定する。接合部材３ｃは配線セラミック基板１間に架設され、複数の配線セラミック基板１を効率良くフレーム３０に安定に固定することができる。
なお、上記接合部材３ａ、３ｂ、３ｃと配線セラミック基板１の配線層１ｂとの接合は、半田接合、溶接または超音波接合などにより行われ、配線セラミック基板１のセラミック基板１ａとの接合は接着剤により行う。
また、パワー半導体素子の上面とリード３ｘ間は、通常アルミワイヤ５を用いてワイヤボンドで接続するが、電流量を多く流す必要があれば金属板を用いることができる。 Next, as shown in FIG. 3 (c), a plurality of wiring ceramic substrates 1 on which the power semiconductor elements 2 are mounted are placed on the distal ends of the joining members (leads) 3a, 3b, 3c of the lead frame 3. The wiring ceramic substrate 1 is fixed to the frame 30 by bonding the bonding members 3 a, 3 b, 3 c to the respective wiring ceramic substrates 1. The joining member 3c is installed between the wiring ceramic substrates 1 and can fix the plurality of wiring ceramic substrates 1 to the frame 30 efficiently and stably.
The bonding members 3a, 3b, and 3c and the wiring layer 1b of the wiring ceramic substrate 1 are bonded by solder bonding, welding, or ultrasonic bonding, and the bonding of the wiring ceramic substrate 1 to the ceramic substrate 1a is bonded. This is done with the agent.
Further, the upper surface of the power semiconductor element and the lead 3x are usually connected by wire bonding using an aluminum wire 5, but a metal plate can be used if it is necessary to flow a large amount of current.

次に、図３（ｄ）に示すように、図では金型を省略しているが、複数の配線セラミック基板１を固定したリードフレーム３を、約１８０℃に設定した金型内に設置し、例えばエポキシ樹脂に無機フィラーを充填した封止樹脂６を注入して硬化させ、量産性に優れているトランスファーモールドにより成型する。
その後、図３（ｅ）に示すように、フレーム３０を切断除去して本実施の形態のパワーモジュールを得る。
上記のように、本実施の形態においては、接合部材３ａ、３ｂ、３ｃにより、複数の配線セラミック基板１がフレーム３０に安定に固定されるので、量産性に優れたトランスファモールドにより信頼性よくパワーモジュールを製造することができる。 Next, as shown in FIG. 3 (d), although the mold is omitted in the figure, the lead frame 3 to which a plurality of wiring ceramic substrates 1 are fixed is placed in a mold set at about 180 ° C. For example, the sealing resin 6 filled with an inorganic filler in an epoxy resin is injected and cured, and then molded by a transfer mold having excellent mass productivity.
Thereafter, as shown in FIG. 3 (e), the frame 30 is cut and removed to obtain the power module of the present embodiment.
As described above, in the present embodiment, since the plurality of wiring ceramic substrates 1 are stably fixed to the frame 30 by the joining members 3a, 3b, and 3c, power can be reliably supplied by a transfer mold having excellent mass productivity. Modules can be manufactured.

なお、上記パワーモジュールの製造工程中や使用中における、封止樹脂６の配線セラミック基板１との界面における剥離やセラミック基板１ａの割れは、配線セラミック基板１が小さい程、より正確にはセラミック基板１ａ面の最長の対角線長さが短い程発生し難くなる。
つまり、上記封止樹脂６と配線セラミック基板１との界面においては、トランスファーモールド時に封止樹脂６が反応によって収縮するために発生する硬化収縮応力と、封止樹脂６と配線セラミック基板１の線膨張率の違いにより、成形時の温度と使用時の温度の差に基づいて発生する熱応力との合算の応力（合算応力）が発生する。
上記合算応力は配線セラミック基板１の中央部からの距離が長くなる程大きくなり、上記剥離または割れが生じやすくなるので、本実施の形態のパワーモジュールでは、配線セラミック基板１を複数個として一個当たりの配線セラミック基板１を小さくし、上記各配線セラミック基板１の中央部からの距離を短く、つまり、セラミック基板１ａ面の最長の対角線長さを短くすることにより、相対的に上記合算応力を小さくして、上記剥離または割れを防止しようとするものである。 Note that peeling of the sealing resin 6 at the interface with the wiring ceramic substrate 1 and cracking of the ceramic substrate 1a during the manufacturing process and use of the power module described above are more accurate as the wiring ceramic substrate 1 is smaller. As the longest diagonal length of the 1a surface is shorter, it is less likely to occur.
That is, at the interface between the sealing resin 6 and the wiring ceramic substrate 1, the curing shrinkage stress generated because the sealing resin 6 contracts by reaction during transfer molding, and the line between the sealing resin 6 and the wiring ceramic substrate 1. Due to the difference in expansion coefficient, a combined stress (summed stress) of the thermal stress generated based on the difference between the temperature during molding and the temperature during use is generated.
The total stress increases as the distance from the center of the wiring ceramic substrate 1 increases, and the peeling or cracking is likely to occur. Therefore, in the power module of the present embodiment, a plurality of wiring ceramic substrates 1 are used per one. By reducing the wiring ceramic substrate 1 and reducing the distance from the central portion of each wiring ceramic substrate 1, that is, by shortening the longest diagonal length of the ceramic substrate 1a surface, the total stress is relatively reduced. Thus, the above peeling or cracking is to be prevented.

表１は、実施の形態１−１〜３および比較例１、２のパワーモジュールにおける、四角形のセラミック基板１ａの二辺のサイズと最長の対角線長さ、パワー半導体素子２の個数、並びに評価結果を示したものである。
なお、パワーモジュールの評価は、上記パワーモジュールの製造工程終了直後、並びに上記パワーモジュールに、「−４０℃での３０分間保持と１２５℃での３０分間保持」を１サイクルとして、３００サイクルおよび１０００サイクルのヒートサイクル試験を実施し、封止樹脂６の配線セラミック基板１との界面における剥離（表中に剥離と記載）またはセラミック基板１ａのクラック（表中、割れと記載）が生じたパワーモジュールの割合を不良率として示すことにより行った。
また、３００サイクルは民生用や一般産業用などで要求される信頼性レベル、１０００サイクルは自動車用などで要求される高信頼性レベルである。 Table 1 shows the sizes of the two sides of the rectangular ceramic substrate 1a, the longest diagonal length, the number of power semiconductor elements 2, and the evaluation results in the power modules of Embodiments 1-1 to 1-3 and Comparative Examples 1 and 2. Is shown.
The power module is evaluated immediately after the manufacturing process of the power module is completed, and in the power module, 300 cycles and 1000 cycles with “holding at −40 ° C. for 30 minutes and holding at 125 ° C. for 30 minutes” as one cycle. A power module in which a heat cycle test of the cycle was performed and peeling (described as peeling in the table) or cracking (described as cracking) in the ceramic substrate 1a occurred at the interface between the sealing resin 6 and the wiring ceramic substrate 1 This was done by showing the ratio of as a defective rate.
Further, 300 cycles is a reliability level required for consumer use and general industrial use, and 1000 cycles is a high reliability level required for automobile use.

つまり、封止樹脂６として、線膨張係数が１０×１０−６／℃、曲げ弾性率が２０ＧＰａ、ガラス転移温度が１６０℃、硬化収縮率が約０．２％の樹脂を用い、配線セラミック基板１として、アルミナ（Ａｌ２Ｏ３）からなり厚さが０．６３５ｍｍで表１に示す各大きさの四角形のセラミック基板１ａに、０．２ｍｍ厚の銅層を設けたものを用い、パワー半導体素子として、表１に示す個数のＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）またはダイオードを搭載して製造したパワーモジュールの上記不良率を検出した。
表１に示すように、配線セラミック基板１として、１６×４８（ｍｍ）のセラミック基板１ａを用い、１２個のパワー半導体素子を搭載したパワーモジュール（比較例１）では製造直後で不良率が１００％であったのに対して、上記比較例１で用いたセラミック基板１ａを３分割した大きさに相当するセラミック基板１ａを３個用い、上記各配線セラミック基板１に各４個のパワー半導体素子を搭載したパワーモジュール（実施の形態１−１）、および２分割した大きさに相当するセラミック基板１ａを２個用い、上記各配線セラミック基板１に各６個のパワー半導体素子を搭載したパワーモジュール（実施の形態１−２）では、上記１０００サイクルのヒートサイクル試験においても割れは生じていない。また、配線セラミック基板１として、３８×３８（ｍｍ）の大きさのセラミック基板１ａを用い、４個のパワー半導体素子を搭載したパワーモジュール（比較例２）では３００サイクル後の不良率が１００％であったのに対して、上記比較例２で用いたセラミック基板１ａを４分割した大きさに相当するセラミック基板１ａを４個用い、上記各配線セラミック基板１に各１個のパワー半導体素子を搭載したパワーモジュール（実施の形態１−３）では１０００サイクルのヒートサイクル試験においても割れは生じていない。
以上のことから、配線セラミック基板１を複数個用いることにより、配線セラミック基板１と封止樹脂６との界面に発生する応力を低減することで、配線セラミック基板１の割れや界面での剥離を防止でき、ヒートサイクル信頼性が向上することが示される。
なお、上記のように、本実施の形態における配線セラミック基板１は、セラミック基板１ａに配線層１ｂとして０．２〜０．３ｍｍの銅層を直接接合したものが用いられるが、上記セラミック基板１ａと配線層１ｂとは強固に接合されて１つのバイメタルとして作用し、また、セラミック基板１ａが配線層１ｂより厚く、配線セラミック基板１の端部はセラミック基板１ａが露出し、上記端部で剥離が発生して界面全域に広がり易いことから、封止樹脂６と配線セラミック基板１との線膨張率の違いによる熱応力に対しては、セラミック基板１ａの大きさ、つまりセラミック基板１ａ面の対角線長さが大きく影響する。 That is, as the sealing resin 6, a resin having a linear expansion coefficient of 10 × 10 −6 / ° C., a flexural modulus of 20 GPa, a glass transition temperature of 160 ° C., and a curing shrinkage of about 0.2% is used. 1, a power semiconductor using a ceramic substrate 1a made of alumina (Al 2 O 3 ) and having a thickness of 0.635 mm and a square ceramic substrate 1a of each size shown in Table 1 provided with a 0.2 mm thick copper layer. The defective rate of the power module manufactured by mounting the number of IGBTs (Insulated Gate Bipolar Transistors) or diodes shown in Table 1 as elements was detected.
As shown in Table 1, in the power module (Comparative Example 1) in which a ceramic substrate 1a of 16 × 48 (mm) is used as the wiring ceramic substrate 1 and 12 power semiconductor elements are mounted, the defect rate is 100 immediately after manufacture. %, The three ceramic substrates 1a corresponding to the size obtained by dividing the ceramic substrate 1a used in the comparative example 1 into three parts are used, and four power semiconductor elements are provided on each wiring ceramic substrate 1. The power module (Embodiment 1-1) on which the power is mounted, and the power module in which the two ceramic substrates 1a corresponding to the size divided into two are used and each of the power ceramic elements 1 is mounted on each wiring ceramic substrate 1 In (Embodiment 1-2), no cracks have occurred even in the 1000-cycle heat cycle test. In addition, in the power module (Comparative Example 2) in which a ceramic substrate 1a having a size of 38 × 38 (mm) is used as the wiring ceramic substrate 1 and four power semiconductor elements are mounted, the defect rate after 300 cycles is 100%. On the other hand, four ceramic substrates 1a corresponding to the size obtained by dividing the ceramic substrate 1a used in the comparative example 2 into four parts are used, and one power semiconductor element is provided on each wiring ceramic substrate 1. In the mounted power module (Embodiment 1-3), no cracks occurred even in the 1000-cycle heat cycle test.
From the above, by using a plurality of wiring ceramic substrates 1, the stress generated at the interface between the wiring ceramic substrate 1 and the sealing resin 6 is reduced, so that the wiring ceramic substrate 1 can be cracked or peeled off at the interface. It can be prevented and the heat cycle reliability is improved.
As described above, the wiring ceramic substrate 1 in the present embodiment is obtained by directly bonding a 0.2 to 0.3 mm copper layer as the wiring layer 1b to the ceramic substrate 1a. And the wiring layer 1b are firmly bonded and act as one bimetal, and the ceramic substrate 1a is thicker than the wiring layer 1b, and the ceramic substrate 1a is exposed at the end of the wiring ceramic substrate 1 and peeled off at the end. Is generated and easily spreads over the entire interface. Therefore, the size of the ceramic substrate 1a, that is, the diagonal line of the surface of the ceramic substrate 1a is against the thermal stress due to the difference in the linear expansion coefficient between the sealing resin 6 and the wiring ceramic substrate 1. Length greatly affects.

Figure 2007027261
Figure 2007027261

表２は、実施の形態１−４〜８と比較例３〜５のパワーモジュールにおける、四角形のセラミック基板１ａの二辺のサイズと最長の対角線長さ、パワー半導体素子２の個数、並びに評価結果を示す。また、不良率は、上記と同様にしてパワーモジュールを製造して得たものである。   Table 2 shows the size and the longest diagonal length of the square ceramic substrate 1a, the number of power semiconductor elements 2, and the evaluation results in the power modules of Embodiments 1-4 to 8 and Comparative Examples 3 to 5. Indicates. The defect rate is obtained by manufacturing a power module in the same manner as described above.

Figure 2007027261
Figure 2007027261

表１、表２に示すように、比較例１〜比較例５では製造工程後にすでに不良が発生しているのに対して、実施の形態１−１〜８（セラミック基板１ａ面の最長の対角線長さが４１ｍｍ以下）では、上記３００サイクルのヒートサイクル試験においても不良が見られず、実施の形態１−１〜６（セラミック基板１ａ面の最長の対角線長さが３４ｍｍ以下）では、上記１０００サイクルのヒートサイクル試験においても不良が見られないことから、セラミック基板１ａ面の最長の対角線長さは４１ｍｍ以下が好ましく、３４ｍｍ以下が特に好ましいことがわかる。なお、本実施の形態に係わるセラミック基板１ａは、搭載されるパワー半導体素子を越える大きさであるのが好ましいが、上記接合部材との接合安定のためには上記パワー半導体素子の大きさの１．２倍以上であるのがより好ましい。   As shown in Tables 1 and 2, in Comparative Examples 1 to 5, defects were already generated after the manufacturing process, whereas Embodiments 1-1 to 8 (the longest diagonal line of the ceramic substrate 1a surface) When the length is 41 mm or less, no defect is observed in the 300-cycle heat cycle test. In Embodiments 1-1 to 6 (the longest diagonal length of the ceramic substrate 1a surface is 34 mm or less), 1000 Since no defect is observed in the heat cycle test of the cycle, it can be seen that the longest diagonal length of the surface of the ceramic substrate 1a is preferably 41 mm or less, and particularly preferably 34 mm or less. The ceramic substrate 1a according to the present embodiment preferably has a size that exceeds the power semiconductor element to be mounted. However, in order to stabilize the bonding with the bonding member, the ceramic substrate 1a has a size 1 of the power semiconductor element. More preferably, it is 2 times or more.

本実施の形態に係わる配線セラミック基板１におけるセラミック基板１ａとしては、絶縁性で熱伝導性が良好なアルミナ（Ａｌ２Ｏ３）（熱伝導率：２０〜４０Ｗ／ｍＫ,線膨張係数：約７×１０−６／℃）、信頼性やコストの面から好ましい窒化アルミ(ＡｌＮ)（熱伝導率７０〜２００Ｗ／ｍＫ,線膨張係数：約４×１０−６／℃）、強度が強い窒化ケイ素（Ｓｉ３Ｎ４）（熱伝導率３０〜８０Ｗ／ｍＫ,線膨張係数：約３×１０−６／℃）のセラミック基板用いられ、封止樹脂６としてはエポキシ樹脂に溶融シリカを８０重量％以上充填したもので、線膨張係数が８〜１２×１０−６／℃のものが用いられる。
また、本実施の形態に係わるセラミック基板１ａの厚さは０．２〜１．０ｍｍであるのが好ましく、セラミック基板１ａの厚さが０．２ｍｍ未満では絶縁性や強度が低下する可能性があり、１．０ｍｍを越えると放熱性が悪くなる。
なお、本実施の形態に係わる配線セラミック基板１におけるセラミック基板１ａとして、０．２〜１．０ｍｍ厚のアルミナ（Ａｌ２Ｏ３）、窒化アルミ(ＡｌＮ)または窒化ケイ素（Ｓｉ３Ｎ４）のセラミック基板を用いた場合も、本実施の形態と同様の結果が得られた。 As the ceramic substrate 1a in the wiring ceramic substrate 1 according to the present embodiment, alumina (Al 2 O 3 ) having good insulation and thermal conductivity (thermal conductivity: 20 to 40 W / mK, linear expansion coefficient: about 7 × 10 −6 / ° C.) Aluminum nitride (AlN) preferred from the viewpoint of reliability and cost (thermal conductivity 70 to 200 W / mK, linear expansion coefficient: about 4 × 10 −6 / ° C.), strong silicon nitride A ceramic substrate of (Si 3 N 4 ) (thermal conductivity 30 to 80 W / mK, linear expansion coefficient: about 3 × 10 −6 / ° C.) is used. As the sealing resin 6, 80 wt% of fused silica is used as an epoxy resin. What is filled above and has a linear expansion coefficient of 8 to 12 × 10 −6 / ° C. is used.
Moreover, it is preferable that the thickness of the ceramic substrate 1a according to the present embodiment is 0.2 to 1.0 mm, and if the thickness of the ceramic substrate 1a is less than 0.2 mm, there is a possibility that the insulation and the strength are lowered. Yes, if it exceeds 1.0 mm, the heat dissipation becomes worse.
The ceramic substrate 1a in the wiring ceramic substrate 1 according to the present embodiment is made of alumina (Al 2 O 3 ), aluminum nitride (AlN), or silicon nitride (Si 3 N 4 ) having a thickness of 0.2 to 1.0 mm. Even when a ceramic substrate was used, the same result as in the present embodiment was obtained.

実施の形態２．
図４は、本発明の実施の形態２における、封止樹脂６を透視したパワーモジュールの概略構成を示す上面図、図５は図４のＢ−Ｂ線における断面図、図６は本実施の形態における、配線セラミック基板１のパワー半導体素子２の搭載面の反対面から見たパワーモジュールの概略構成を示す下面図である。
本実施の形態のパワーモジュールは、２個の配線セラミック基板１に各々２個のパワー半導体素子２が搭載され、接合部材３ｄ、３ｅ、３ｆと接合され、配線セラミック基板１のパワー半導体素子２の搭載面の反対面に銅層等の金属層１ｃが設けられ、また、図５に示すように、配線セラミック基板１のパワー半導体素子２の搭載面の反対面に、外周端領域１ｄを除いて内側に銅層等の金属層１ｃが設けられ、封止樹脂６が上記金属層１ｃが設けられていない外周端領域１ｄに連続して設けられている他は実施の形態１と同様である。本実施の形態のパワーモジュールは、配線セラミック基板１のパワー半導体素子の搭載面の反対面に金属層１ｃと封止樹脂６を設けることにより、高い放熱性を維持するとともに、セラミック基板１ａを保護することができる。 Embodiment 2. FIG.
4 is a top view showing a schematic configuration of the power module seen through the sealing resin 6 in Embodiment 2 of the present invention, FIG. 5 is a sectional view taken along line BB in FIG. 4, and FIG. It is a bottom view which shows schematic structure of the power module seen from the surface opposite to the mounting surface of the power semiconductor element 2 of the wiring ceramic substrate 1 in a form.
In the power module of the present embodiment, two power semiconductor elements 2 are mounted on two wiring ceramic substrates 1 and bonded to bonding members 3d, 3e, and 3f. A metal layer 1c such as a copper layer is provided on the opposite surface of the mounting surface, and as shown in FIG. 5, except for the outer peripheral end region 1d on the surface opposite to the mounting surface of the power semiconductor element 2 of the wiring ceramic substrate 1. A metal layer 1c such as a copper layer is provided on the inner side, and the sealing resin 6 is provided continuously to the outer peripheral end region 1d where the metal layer 1c is not provided, and is the same as in the first embodiment. The power module according to the present embodiment maintains high heat dissipation and protects the ceramic substrate 1a by providing the metal layer 1c and the sealing resin 6 on the opposite surface of the wiring ceramic substrate 1 to the power semiconductor element mounting surface. can do.

実施の形態３．
図７は、本発明の実施の形態３における、封止樹脂６を透視したパワーモジュールの概略構成を示す上面図、図８は図７のＣ−Ｃ線における断面図である。
本実施の形態のパワーモジュールは、実施の形態１において、パワー半導体素子２が搭載された部分以外の配線セラミック基板１上に、応力緩和層７を設けている他は実施の形態１と同様である。本実施の形態において、エポキシ樹脂を封止樹脂６として用いると、上記応力緩和層７として、シリコーン樹脂やポリイミド樹脂等を用いることにより、セラミック基板１ａと封止樹脂６との間に発生する応力を緩和することができる。なお、上記応力緩和層７は、パワー半導体素子２の上面を被覆せず、配線セラミック基板１の全面を被覆することが好ましく、厚さが０．０３〜０．２０ｍｍであると効果的に応力を緩和することができる。 Embodiment 3 FIG.
7 is a top view showing a schematic configuration of a power module seen through the sealing resin 6 in Embodiment 3 of the present invention, and FIG. 8 is a cross-sectional view taken along the line CC in FIG.
The power module of the present embodiment is the same as that of the first embodiment except that the stress relaxation layer 7 is provided on the wiring ceramic substrate 1 other than the portion where the power semiconductor element 2 is mounted in the first embodiment. is there. In the present embodiment, when an epoxy resin is used as the sealing resin 6, a stress generated between the ceramic substrate 1 a and the sealing resin 6 by using a silicone resin or a polyimide resin as the stress relaxation layer 7. Can be relaxed. The stress relaxation layer 7 preferably covers the entire surface of the wiring ceramic substrate 1 without covering the upper surface of the power semiconductor element 2, and effectively has a thickness of 0.03 to 0.20 mm. Can be relaxed.

なお、上記実施の形態１〜実施の形態３においては、配線セラミック基板１に搭載された半導体素子が全てパワー半導体素子２である場合を示したが、パワー半導体素子２の一部が駆動半導体素子等、他の半導体素子で置換されていても、上記実施の形態と同様の効果を得ることができる。   In the first to third embodiments, the case where all the semiconductor elements mounted on the wiring ceramic substrate 1 are the power semiconductor elements 2 is shown. However, a part of the power semiconductor elements 2 is a driving semiconductor element. Even if it is replaced with another semiconductor element, the same effect as the above embodiment can be obtained.

本発明の実施の形態１における、パワーモジュールの概略構成を示す上面図と断面図である。It is the upper side figure and sectional drawing which show schematic structure of the power module in Embodiment 1 of this invention. 図１のａ−ａ線における断面図と、ｂ−ｂ線における断面図である。It is sectional drawing in the aa line of FIG. 1, and sectional drawing in the bb line. 本発明の実施の形態１における、パワーモジュールの製造方法の概略を示す工程図である。It is process drawing which shows the outline of the manufacturing method of the power module in Embodiment 1 of this invention. 本発明の実施の形態２における、パワーモジュールの概略構成を示す上面図である。It is a top view which shows schematic structure of the power module in Embodiment 2 of this invention. 図４のＢ−Ｂ線における断面図である。It is sectional drawing in the BB line of FIG. 本発明の実施の形態２における、パワーモジュールの概略構成を示す下面図である。It is a bottom view which shows schematic structure of the power module in Embodiment 2 of this invention. 本発明の実施の形態３における、パワーモジュールの概略構成を示す上面図である。It is a top view which shows schematic structure of the power module in Embodiment 3 of this invention. 図７のＣ−Ｃ線における断面図である。It is sectional drawing in the CC line of FIG.

符号の説明Explanation of symbols

１ 配線セラミック基板１、１ａ セラミック基板、１ｂ 配線層、１ｃ 金属層、１ｄ 外周端領域、２ パワー半導体素子、３ａ、３ｂ、３ｃ、３ｄ、３ｅ、３ｆ 接合部材（リード）、３ｘ リード、６ 封止樹脂。



1 Wiring ceramic substrate 1, 1a Ceramic substrate, 1b Wiring layer, 1c Metal layer, 1d Outer edge region, 2 Power semiconductor element, 3a, 3b, 3c, 3d, 3e, 3f Bonding member (lead), 3x lead, 6 sealed Stop resin.



Claims (5)

セラミック基板に配線層が形成されてなる複数の配線セラミック基板と、少なくとも一つの上記配線層に搭載されたパワー半導体素子と、上記複数の配線セラミック基板および上記パワー半導体素子をモールドする封止樹脂と、上記複数の配線セラミック基板に接合された接合部材とを備えたことを特徴とするパワーモジュール。 A plurality of wiring ceramic substrates in which a wiring layer is formed on a ceramic substrate; a power semiconductor element mounted on at least one of the wiring layers; a sealing resin for molding the plurality of wiring ceramic substrates and the power semiconductor element; A power module comprising: a joining member joined to the plurality of wiring ceramic substrates. 接合部材がリードであることを特徴とする請求項１に記載のパワーモジュール。 The power module according to claim 1, wherein the joining member is a lead. 接合部材が配線セラミック基板間に架設されていることを特徴とする請求項１に記載のパワーモジュール。 The power module according to claim 1, wherein the joining member is provided between the wiring ceramic substrates. セラミック基板のパワー半導体素子搭載面の大きさが、上記パワー半導体素子の大きさを越え、セラミック基板面の最長の対角線長さが４１ｍｍ以下であることを特徴とする請求項１〜請求項３のいずれかに記載のパワーモジュール。 4. The size of the power semiconductor element mounting surface of the ceramic substrate exceeds the size of the power semiconductor element, and the longest diagonal length of the ceramic substrate surface is 41 mm or less. A power module according to any one of the above. 配線セラミック基板には半導体素子が搭載され、上記半導体素子の少なくとも一つがパワー半導体素子であり、上記半導体素子の搭載面の反対面に、外周端領域の少なくとも一部を除いて金属層が設けられ、封止樹脂は、上記反対面の金属層が設けられていない領域に連続して設けられていることを特徴とする請求項１に記載のパワーモジュール。





A semiconductor element is mounted on the wiring ceramic substrate, at least one of the semiconductor elements is a power semiconductor element, and a metal layer is provided on a surface opposite to the mounting surface of the semiconductor element except for at least a part of the outer peripheral end region. The power module according to claim 1, wherein the sealing resin is continuously provided in a region where the metal layer on the opposite surface is not provided.





JP2005204463A 2005-07-13 2005-07-13 Power module Pending JP2007027261A (en)

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JP2008288564A (en) * 2007-03-28 2008-11-27 Ixys Semiconductor Gmbh Power semiconductor module and arrangement of printed circuit board, and power semiconductor module
JP2013042135A (en) * 2011-08-16 2013-02-28 General Electric Co <Ge> Power overlay structure with leadframe connections
JP2014090136A (en) * 2012-10-31 2014-05-15 Sanken Electric Co Ltd Semiconductor device and manufacturing method of the same
KR20170026557A (en) 2014-07-04 2017-03-08 미쓰비시 마테리알 가부시키가이샤 Substrate unit for power modules, and power module

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JP2004111560A (en) * 2002-09-17 2004-04-08 Toshiba Corp Semiconductor device and method of manufacturing the same

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JPH04179152A (en) * 1990-11-08 1992-06-25 Fujitsu Ltd Integrated circuit device
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JP2003031765A (en) * 2001-07-17 2003-01-31 Hitachi Ltd Power module and inverter
JP2004111560A (en) * 2002-09-17 2004-04-08 Toshiba Corp Semiconductor device and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
JP2008288564A (en) * 2007-03-28 2008-11-27 Ixys Semiconductor Gmbh Power semiconductor module and arrangement of printed circuit board, and power semiconductor module
JP2013042135A (en) * 2011-08-16 2013-02-28 General Electric Co <Ge> Power overlay structure with leadframe connections
JP2014090136A (en) * 2012-10-31 2014-05-15 Sanken Electric Co Ltd Semiconductor device and manufacturing method of the same
KR20170026557A (en) 2014-07-04 2017-03-08 미쓰비시 마테리알 가부시키가이샤 Substrate unit for power modules, and power module
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