JP2007019992A - Electronic equipment and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide electronic equipment and an image forming apparatus by which rewrite and confirmation after the rewrite of a programmable logic circuit are easily and conveniently performed. <P>SOLUTION: The electronic equipment has one or more programmable logic circuits (FPGA 201-203), storage means (a configuration memory 16, a server 170 and an external memory 180) for storing one or more pieces of circuit information for defining a logic circuit of the programmable logic circuit and management information for managing each piece of circuit information by associating them with one another, an acquisition means for acquiring the management information and a display means (display part 13) for displaying the acquired management information. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic apparatus and an image forming apparatus, and more particularly to an electronic apparatus and an image forming apparatus provided with a programmable logic circuit such as a PLD.

  An image processing function of an image forming apparatus such as a copying machine is composed of a plurality of complicated algorithms, and is usually composed of a logic circuit such as an ASIC (Application Specific Integrated Circuit) in order to reach a desired execution speed. Yes. Since this ASIC is a non-rewritable (masked) circuit integrated on one chip, it cannot cope with a circuit change. In order to solve this problem, a logic circuit called PLD (Programmable Logic Device) such as FPGA (Field Programmable Gate Array) may be used.

  An FPGA can be reconfigured (rewritten) even after it has been hardwareized, by providing another type of circuit information (hereinafter referred to as configuration data) from the outside. For this reason, the FPGA is used as a device for hardwareizing a plurality of complicated algorithms such as image processing. In addition, with the development of the Internet and the like, it is possible to download FPGA rewrite configuration data from a server or the like connected to the network, so that the latest data can be supplied to the device even after product shipment. ing.

  As the case where the FPGA is rewritten, there may be reasons such as upgrade such as addition of functions, correction of defects such as bug fixes found after shipment of machine production, and the like. In addition, depending on the externally connected model such as a print controller or a scanner, it may be considered that a part of the image processing function is changed (for example, when a desired image processing function cannot be performed only by changing parameters). In the initial stage of device development, configuration data is updated as needed to evaluate debugging work and specific functions.

Conventionally, there has been proposed a technique for confirming that a desired circuit has been correctly rewritten to an FPGA when the FPGA is rewritten. For example, when setting circuit information that constitutes an electronic circuit in which a plurality of FPGAs are combined, configuration special information (FPGA version) for each combination, effective configuration information (FPGA group combination identification information), and a board on which the FPGA is mounted A technique has been proposed in which FPGA identification information is stored in the FPGA, and the FPGA itself determines whether or not a circuit combination based on the combination is operable by comparing these pieces of information for each combination (for example, patents). Reference 1). In addition, as a technology for identifying PLD data that has been mounted on a device or board, a display device is provided on the surface of the PLD, and the checksum value of the written configuration data is saved to save the configuration data. A technique for displaying version information, checksum value, etc. has been proposed (see, for example, Patent Document 2).
JP 2004-88625 A JP 2004-252855 A

  However, in the technique described in Patent Document 1, it is possible to recognize version information only with hardware and determine whether or not to operate the FPGA logic circuit, but the circuit becomes complicated and the circuit scale increases. In addition, there is a problem that since there is no control means such as a CPU for controlling each FPGA, it is difficult to deal with when a new combination occurs, and lacks versatility. In addition, the technique described in Patent Document 2 is limited to the version confirmation of a single FPGA, and when applied to a plurality of FPGAs, a display device is required for each device, which increases the cost. In addition, there is a problem that it is only used at the time of development and is not suitable after product shipment.

  An object of the present invention is to provide an electronic apparatus and an image forming apparatus capable of easily and simply performing writing of a programmable logic circuit and confirmation after writing.

In order to solve the above-mentioned problem, the invention described in claim 1
One or more programmable logic circuits;
Storage means for storing one or more circuit information defining the logic circuit of the programmable logic circuit and management information for managing the circuit information in association with each other;
Obtaining means for obtaining the management information;
Display means for displaying the acquired management information;
It is characterized by having.

Furthermore, the invention according to claim 2 is the invention according to claim 1,
Circuit information designating means capable of designating specific circuit information based on the management information,
The acquisition unit acquires the circuit information specified by the circuit information specifying unit from the storage unit.

Furthermore, the invention according to claim 3 is the invention according to claim 2,
Writing means for writing the acquired circuit information into the programmable logic circuit is provided.

Furthermore, the invention according to claim 4 is the invention according to claim 3,
A determination means for determining whether or not the acquired circuit information and the circuit information written in the programmable logic circuit match;
The display means displays a determination result by the determination means.

Furthermore, the invention according to claim 5 is the invention according to claim 1,
Comprising a logic circuit designating means capable of designating a specific programmable logic circuit;
The acquisition means acquires management information of circuit information related to the programmable logic circuit designated by the logic circuit designation means from the storage means.

Furthermore, the invention according to claim 6 is the invention according to any one of claims 1 to 5,
The management information includes version information indicating that a version of a logic circuit defined by the circuit information can be identified.

Furthermore, according to the invention described in claim 7, in the invention described in any one of claims 1 to 6,
The management information includes circuit information group information that is identifiable as a unit of a combination of a plurality of circuit information.

Furthermore, according to the invention described in claim 8, in the invention described in claim 1,
The storage means is a server device connected via a communication line.

Moreover, in order to solve the said subject, invention of Claim 9 is the following.
An image forming apparatus comprising: an image processing unit that performs predetermined image processing on image data; and an image forming unit that records an image of the image data processed by the image processing unit on a predetermined recording medium.
Storage means for storing one or more circuit information defining logic circuits of one or more programmable logic circuits included in the image processing means and management information for managing the circuit information in association with each other;
Obtaining means for obtaining the management information;
Display means for displaying the acquired management information;
It is characterized by having.

Furthermore, the invention of claim 10 is the invention of claim 9,
Circuit information designating means capable of designating specific circuit information based on the management information,
The acquisition unit acquires the circuit information specified by the circuit information specifying unit from the storage unit.

Furthermore, the invention of claim 11 is the invention of claim 10,
Write control means for writing the acquired circuit information into the programmable logic circuit is provided.

Furthermore, the invention of claim 12 is the invention of claim 11,
A determination means for determining whether or not the acquired circuit information and the circuit information written in the programmable logic circuit match;
The display means displays a determination result by the determination means.

Furthermore, the invention of claim 13 is the invention of claim 11 or 12,
The writing control means writes the circuit information into the program logic circuit and then controls the image forming means to record an operation verification image of the image processing means on the recording medium. .

Furthermore, the invention of claim 14 is the invention of claim 9,
Comprising a logic circuit designating means capable of designating a specific programmable logic circuit;
The acquisition means acquires management information of circuit information related to the programmable logic circuit designated by the logic circuit designation means from the storage means.

Furthermore, the invention described in claim 15 is the invention described in any one of claims 9 to 14,
The management information includes version information indicating that a version of a logic circuit defined by the circuit information can be identified.

Furthermore, the invention described in claim 16 is the invention described in any one of claims 9 to 15,
The management information includes circuit information group information that is identifiable as a unit of a combination of a plurality of circuit information.

Furthermore, the invention of claim 17 is the invention of claim 9,
The storage means is a server device connected via a communication line.

  According to the first aspect of the present invention, circuit information relating to the programmable logic circuit can be confirmed easily and simply.

  According to the second aspect of the present invention, it is possible to easily and simply acquire the specific circuit information specified via the specifying means.

  According to the third aspect of the present invention, the programmable logic circuit can be written easily and simply.

  According to the fourth aspect of the present invention, it is possible to easily and simply determine whether or not the programmable logic circuit has been normally written.

  According to the fifth aspect of the present invention, it is possible to easily and easily confirm circuit information related to a specific programmable logic circuit.

  According to the sixth aspect of the present invention, the version of the circuit information can be confirmed easily and simply.

  According to the seventh aspect of the invention, a combination of a plurality of pieces of circuit information can be confirmed easily and simply.

  According to the invention described in claim 8, circuit information and management information can be acquired from a server device connected via a communication line.

  According to the ninth aspect of the present invention, it is possible to easily and easily confirm circuit information relating to the programmable logic circuit included in the image processing means.

  According to the invention described in claim 10, the specific circuit information designated via the designation means can be acquired easily and simply.

  According to the eleventh aspect of the present invention, the programmable logic circuit included in the pre-image processing means can be written easily and simply.

  According to the twelfth aspect of the present invention, it is possible to easily and easily determine whether or not the writing of the programmable logic circuit included in the image processing means has been normally performed.

  According to the thirteenth aspect of the present invention, it is possible to easily and simply confirm the operation after writing circuit information.

  According to the fourteenth aspect of the present invention, it is possible to easily and easily confirm circuit information relating to a specific programmable logic circuit.

  According to the invention described in claim 15, the version of the circuit information can be confirmed easily and simply.

  According to the sixteenth aspect of the present invention, a combination of a plurality of pieces of circuit information can be confirmed easily and simply.

  According to the seventeenth aspect of the present invention, circuit information and management information can be acquired from a server device connected via a communication line.

  The best mode for carrying out the present invention will be described below in detail with reference to the drawings. However, the scope of the invention is not limited to the illustrated examples.

  FIG. 1 is a block diagram illustrating a configuration of the image forming apparatus 100. 1, the image forming apparatus 100 includes a CPU 11, an operation unit 12, a display unit 13, a ROM 14, a RAM 15, a configuration memory 16, a communication control unit 17, an I / F 18, a scanner unit 19, an image processing unit 20, and a printer unit 21. Etc., and each part is connected via the bus 22.

  The CPU 11 reads out various programs such as a system program stored in the ROM 14, develops and executes them in a work area formed in the RAM 15, and controls the respective units of the image forming apparatus 100 according to the programs. Further, the CPU 11 reads out various programs such as a system program stored in the ROM 14, develops and executes them in a work area formed in the RAM 15, and displays the processing result on the display unit 13.

  Further, the CPU 11 configures the logic circuits of the FPGAs 201 to 203 by writing the configuration data stored in the configuration memory 16 into the FPGAs 201 to 203 described later. In this writing, version information included in management information described later is written at the same time.

  Further, the CPU 11 compares the configuration data stored in the configuration memory 16 with the configuration data written in the FPGAs 201 to 203 and displays the result on the display unit 13.

  The operation unit 12 includes input keys and the like, receives information input by a user as an operation signal, and outputs the operation signal to the CPU 11.

  Specifically, when an FPGA rewrite mode for rewriting the logic circuits of FPGAs 201 to 203 (see FIG. 2) to be described later is instructed via the operation unit 12, the CPU 11 performs FPGA rewrite processing (see FIG. 3) to be described later. Execute. When an FPGA confirmation mode for confirming the state of the FPGAs 201 to 203 is instructed via the operation unit 12, the CPU 11 executes an FPGA confirmation process (see FIG. 6) described later.

  The display unit 13 is configured by an LCD (Liquid Crystal Display) or the like, and displays various information based on a display signal from the CPU 11. The display unit 13 may be configured as a touch panel integrally with the operation unit 12.

  The ROM 14 stores various programs such as a system program necessary for the operation of the image forming apparatus 100. The RAM 15 expands various programs executed by the CPU 11 in a program storage area. Further, the RAM 15 temporarily stores data such as processing results generated when various programs are executed in the work area.

  The configuration memory 16 includes a nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory), and includes three pieces of configuration data for setting logic circuits of FPGAs 201 to 203 (see FIG. 2) described later. The management information for managing the configuration data is stored in association with each other.

  Here, the management information includes version information indicating that the version of the logic circuit defined by each configuration data can be identified, upgrade number information indicating that a combination of a plurality of configuration data can be identified as a unit, and the upgrade number Date and time information on the validity of the information is included.

  The communication control unit 17 includes a LAN adapter, a router, and the like. Various types of data are exchanged between the CPU 11 and a server 170 connected via a communication line such as a LAN (Local Area Network) or a WAN (Wide Area Network). Send and receive.

  The server 170 is a Web server, an FTP server, or the like, and provides various data stored in a storage unit (not shown) to an external device connected to the server 170. It is assumed that the storage seed means stores configuration data related to each of the FPGAs 201 to 203 serving as rewrite candidates and management information of the configuration data in association with each other.

  The CPU 11 acquires configuration data and management information of the configuration data from the server 170 via the communication control unit 17, and associates the acquired configuration data with the management information to configure the configuration memory 16. Remember me.

  The I / F 18 is an interface conforming to standards such as USB (Universal Serial Bus), IEEE 1394, PCMCIA (Personal Computer Memory Card International Association), and the like, between the CPU 11 and the external memory 180 connected to the I / F 18. Send and receive various data.

  The external memory 180 is portable external storage means such as CompactFlash (registered trademark) and smart media (registered trademark) that can be rewritten, and the external memory 180 includes FPGAs 201 to 203 that are candidates for rewriting. Assume that each configuration data and management information of the configuration data are stored in association with each other.

  The CPU 11 acquires configuration data related to the FPGAs 201 to 203 and information related to the configuration data from the external memory 180 via the I / F 18, and associates the acquired configuration data with management information. It is stored in the configuration memory 16.

  The scanner unit 19 is composed of a light source, a CCD (Charge Coupled Device), a contact glass on which a document is placed, and the like. An image of the document is formed by forming an image of reflected light of the light scanned from the light source to the document and performing photoelectric conversion. , And the read image is converted into digital image data and output to the image processing unit 20.

  The image processing unit 20 applies spatial filter processing, enlargement / reduction processing, rotation processing, tone correction processing to image data input via the communication control unit 17 or the I / F 18 or image data read by the scanner unit 19. The image processing such as the above is performed and output to the printer unit 21.

FIG. 2 shows an example of the internal configuration of the image processing unit 20.
As shown in FIG. 2, the image processing unit 20 includes an FPGA 201, an FPGA 202, an FPGA 203, an image memory 204, a bus 205, and the like.

  The FPGA 201, the FPGA 202, and the FPGA 203 are programmable logic circuits that can electrically rewrite the logic circuit. The configuration data input via the bus 205 such as a JTAG (Joint Test Action Group) under the control of the CPU 11 is used as the configuration data. Based on this, the above-described logic circuit for image processing is configured. 2 illustrates the case where the image processing unit 20 includes the FPGAs 201 to 203. However, the number of FPGAs is not limited to this, and may be configured with other numbers.

  Further, the FPGAs 201 to 203 perform the above-described image processing on the image data input to the image processing unit 20 using the image memory 204 as a temporary under the control of the CPU 11, and the image data after the image processing is transferred to the printer unit. To 21.

  The image memory 204 is a large-capacity DRAM (Dynamic Random Access Memory), HDD (Hard Disk Drive), or the like, and temporarily stores image data subjected to various image processing by the FPGAs 201 to 203. In the image processing unit 20, the location where the image memory 204 is connected is not limited to the illustrated example.

  The printer unit 21 includes a photosensitive drum, toner, a discharge unit, a paper feed unit, and the like. In accordance with a print instruction from the CPU 11, the printer unit 21 conveys a sheet of the size and orientation input from the operation unit 12 from the paper supply unit, and statically prints the image input from the image processing unit 20 on the surface of the photosensitive drum. An electrostatic latent image is formed. Further, the printer unit 21 attaches toner to an area including an electrostatic latent image on the surface of the photosensitive drum, transfers the toner onto the printing paper conveyed from the paper feeding unit, fixes it, and then discharges it from the discharge unit.

Next, the operation of the image forming apparatus 100 in this embodiment will be described.
First, the FPGA rewriting process executed when the configuration data of the FPGAs 201 to 203 is rewritten will be described with reference to the flowchart of FIG. Each process in FIG. 3 shows a process executed under the control of the CPU 11 and in cooperation with a predetermined program stored in the ROM 14.

  Also, as a premise of this processing, the server storage means connected via the communication control unit 17 and the external storage means connected via the I / F 18 include the configuration data related to the FPGAs 201 to 203 and the configuration concerned. It is assumed that data management information is stored.

  First, when the FPGA rewrite mode is designated via the operation unit 12 and the operation signal is input (step S11; Yes), a screen for selecting a storage device in which configuration data to be rewritten is stored is displayed on the display unit. 13 (step S12). Here, the user can selectively designate either the server 170 connected via the communication control unit 17 or the external memory 180 connected via the I / F 18 via the operation unit 12. Yes.

  Next, when it is determined that the server 170 has been designated based on the display screen displayed in step S12 (step S13; server), the server 170 is connected via the communication control unit 17 to the server 170. The management information of the stored configuration data is acquired (step S14), and this management information is displayed on the display unit 13 (step S16). Here, the connection to the server 170 may be based on destination information such as a predetermined URL or IP address, or may be based on destination information input via the operation unit 12. It is good.

  When the external memory 180 is specified in step S13 (step S13; external memory), configuration data management information related to the FPGAs 201 to 203 stored in the external memory 180 is acquired via the I / F 18. The management information is displayed on the display unit 13 (step S16).

  FIG. 4 is a diagram illustrating an example of the screen displayed on the display unit 13 in step S16. As shown in the figure, the information included in the management information includes “Upgrade_No” indicating upgrade number information, “Date” indicating the date and time when the validity of the upgrade number information was confirmed, and the FPGA 201 included in the upgrade information. The version information of each configuration data corresponding to .about.203 is displayed in a list in units of upgrade numbers. A specific upgrade number can be selectively designated via the operation unit 12 based on the screen displayed on the display unit 13 so that the designated operation signal is output to the CPU 11. It has become.

  Returning to FIG. 3, when it is determined that a specific upgrade number has been designated based on the display screen displayed in step S <b> 16 (step S <b> 17; Yes), this designated upgrade number (for example, “3. Each configuration data corresponding to the version information included in SP-00123 ") is acquired from the server 170 or the external memory 180 (step S18) and stored in the configuration memory 16. When the storage of the configuration data is completed, a screen for notifying that the acquisition of the configuration data has been completed is displayed on the display unit 13 (step S19). The acquired configuration data is stored in association with the management information of the configuration data.

  Next, when an operation signal instructing rewriting of the logic circuits of the FPGAs 201 to 203 is input via the operation unit 12 (step S20), each configuration data stored in the configuration memory 16 is read, and each The logic circuit is rewritten by being transmitted to the FPGAs 201 to 203 corresponding to the configuration data (step S21). When the rewriting of the FPGAs 201 to 203 is completed, the process proceeds to a rewriting inspection process in step S22. The configuration data may be transmitted directly to the FPGA to be rewritten, or may be transmitted to the FPGA to be rewritten by a daisy chain method via another FPGA.

Hereinafter, the writing check process in step S22 will be described with reference to FIG.
First, the version information of the configuration data written to the FPGAs 201 to 203 in step S22 is read from the management information of the configuration memory 16 (step S221), and the version information of the configuration data written to the FPGAs 201 to 203 is , Read from the FPGAs 201 to 203 (step S222).

  Next, the acquired version information is compared (step S223), and it is determined whether or not they match (step S224). Here, if it is determined that the versions of the configuration data do not match (step S224; No), a screen for notifying that the writing of the configuration data has not been normally completed is displayed on the display unit 13. (Step S225), this process ends.

  On the other hand, if it is determined in step S224 that the version information of both circuit information matches (step S224; Yes), a screen informing that the writing of the configuration data has been normally completed is displayed on the display unit 13. (Step S226), the process proceeds to Step S23 in FIG. The screen displayed in step S225 or step S226 includes configuration data version information corresponding to each FPGA stored in the configuration memory 16, and configuration data version information written in the FPGAs 201 to 203. Are preferably displayed in a comparable manner.

  In this writing check process, the version information of the configuration data stored in the configuration memory 16 is compared with the version information of the configuration data written in the FPGA. The checksum of the configuration data stored in the configuration memory 16 may be compared with the checksum of the configuration data written in the FPGA.

  Returning to FIG. 3, a screen for confirming whether or not to perform a test print for verifying the operation of the rewritten FPGAs 201 to 203 is displayed on the display unit 13 (step S23). Here, when an operation signal indicating that the test print is not performed is input via the operation unit 12 (step S24; No), this process ends.

  On the other hand, when an operation signal for performing a test print is input via the operation unit 12 in step S24 (step S24; Yes), predetermined test image data stored in the ROM 14 or the like is stored in the image processing unit. The image of the test image data is recorded on a predetermined recording medium by the printer unit 21 (step S25), and the process ends. In this process, a mode in which the user confirms whether or not test printing has been performed is used. However, the present invention is not limited thereto, and a mode in which test printing is performed immediately after step S22 may be employed.

  Here, the test image data is not particularly limited as long as it is printable image data. For example, the test image data may be image data such as a test chart or a photograph, or may be text data such as characters and symbols. . Further, version information, information related to configuration data, and the like related to circuit information written in the FPGAs 201 to 203 may be recorded on a recording medium.

  As described above, according to the present FPGA rewriting process, it is possible to easily and easily check the circuit information related to the FPGAs 201 to 203 stored in the server 170 or the external memory 180 in which configuration data to be rewritten is stored. Can do. Further, the configuration data designated via the operation unit 12 is acquired from the server 170 or the external memory 180 and stored in the configuration memory 16 in association with the management information of the configuration data. Can be carried out easily and simply. Further, it is possible to easily determine whether or not the writing of the FPGAs 201 to 203 has been normally performed, and it is possible to easily and easily check the operation after writing the configuration data.

  Next, with reference to the flowchart of FIG. 6, an FPGA confirmation process executed when confirming the configuration data currently written in the FPGAs 201 to 203 will be described. Each process in FIG. 6 represents a process executed under the control of the CPU 11 and in cooperation with a predetermined program stored in the ROM 14.

  First, when the FPGA confirmation mode is designated via the operation unit 12 and the operation signal is input (step S31; Yes), a screen for selecting the FPGA to be confirmed is displayed on the display unit 13 (step S32). ). Here, the user can designate any or all of the FPGAs 201 to 203 via the operation unit 12.

  Next, if it is determined that the FPGA to be confirmed is designated based on the display screen displayed in step S32 (step S33; Yes), the version information of the configuration data related to the designated FPGA is changed to the configuration. The information is read from the management information in the configuration memory 16 or the corresponding FPGA (step S34), the version information is displayed on the display unit 13 (step S35), and the process ends.

  As described above, according to the FPGA confirmation process, the configuration data related to the FPGAs 201 to 203 stored in the configuration memory 16 can be easily and easily confirmed. The configuration data related to the specified FPGA can be easily and simply confirmed. For example, before performing the above-described FPGA rewriting process (see FIG. 3), by performing this FPGA confirmation process in advance, the configuration data can be rewritten more safely and efficiently.

  In this process, the version information of the configuration data related to the FPGA to be checked is acquired from the management information of the configuration memory 16 or the corresponding FPGA itself, and displayed. However, the version information acquired from both is displayed. It is good also as displaying in the aspect which can be compared, and it is good also as performing the write-in test process (refer FIG. 5) mentioned above in this case.

  In this process, the read version information is displayed on the display unit 13. However, the present invention is not limited to this, and may be recorded on a recording medium via the printer unit 21.

  The detailed configuration and detailed operation of the image forming apparatus in the above embodiment can be changed as appropriate without departing from the spirit of the present invention.

  For example, in the above embodiment, configuration data that is a rewrite candidate is acquired from the server 170 or the external memory 180. However, configuration data that is a rewrite candidate is stored in advance in a predetermined storage area of the configuration memory 16. It is good to keep it.

  In the above-described embodiment, the FPGAs 201 to 203 provided in the image processing unit 20 have been described as an example. However, when an FPGA is provided in a part used for other purposes, the present invention is applied to that part. It is good.

  In the above-described embodiment, the FPGA is described as an electrically rewritable programmable logic circuit. However, the present invention is not limited to this, and an SPLD (Simple PLD), CPLD (Complex PLD), or the like may be used. Good.

  The image forming apparatus according to the above-described embodiment may be a multifunction peripheral device (MFP) having a printing function such as a printer, a digital copying machine, or a facsimile machine. Moreover, the electronic device with which it uses for another use may be sufficient.

1 is a block diagram illustrating a configuration of an image forming apparatus. It is a block diagram which shows the structure of an image process part. It is a flowchart which shows the procedure of FPGA rewriting process. It is a figure which shows an example in the management information displayed on the display part. It is a flowchart which shows the procedure of a writing test | inspection process. It is a flowchart which shows the procedure of FPGA confirmation processing.

Explanation of symbols

100 Image forming apparatus 11 CPU
12 Operation unit 13 Display unit 14 ROM
15 RAM
16 Configuration memory 17 Communication control unit 18 I / F
19 Scanner unit 20 Image processing unit 201 FPGA
202 FPGA
203 FPGA
204 Image memory 205 Bus 21 Printer unit 22 Bus 170 Server 180 External memory

Claims (17)

One or more programmable logic circuits;
Storage means for storing one or more circuit information defining the logic circuit of the programmable logic circuit and management information for managing the circuit information in association with each other;
Obtaining means for obtaining the management information;
Display means for displaying the acquired management information;
An electronic device characterized by comprising: Circuit information designating means capable of designating specific circuit information based on the management information,
The electronic apparatus according to claim 1, wherein the acquisition unit acquires the circuit information specified by the circuit information specifying unit from the storage unit.   The electronic apparatus according to claim 2, further comprising a writing unit that writes the acquired circuit information into the programmable logic circuit. A determination means for determining whether or not the acquired circuit information and the circuit information written in the programmable logic circuit match;
The electronic device according to claim 3, wherein the display unit displays a determination result by the determination unit. Comprising a logic circuit designating means capable of designating a specific programmable logic circuit;
The electronic device according to claim 1, wherein the acquisition unit acquires management information of circuit information related to the programmable logic circuit designated by the logic circuit designation unit from the storage unit.   The electronic apparatus according to claim 1, wherein the management information includes version information indicating that a version of a logic circuit defined by the circuit information can be identified.   The electronic apparatus according to claim 1, wherein the management information includes circuit information group information that can be identified as a unit of a combination of a plurality of circuit information.   The electronic device according to claim 1, wherein the storage unit is a server device connected via a communication line. An image forming apparatus comprising: an image processing unit that performs predetermined image processing on image data; and an image forming unit that records an image of the image data processed by the image processing unit on a predetermined recording medium.
Storage means for storing one or more circuit information defining logic circuits of one or more programmable logic circuits included in the image processing means and management information for managing the circuit information in association with each other;
Obtaining means for obtaining the management information;
Display means for displaying the acquired management information;
An image forming apparatus comprising: Circuit information designating means capable of designating specific circuit information based on the management information,
The image forming apparatus according to claim 9, wherein the acquisition unit acquires the circuit information designated by the circuit information designation unit from the storage unit.   The image forming apparatus according to claim 10, further comprising a writing control unit that writes the acquired circuit information into the programmable logic circuit. A determination means for determining whether or not the acquired circuit information and the circuit information written in the programmable logic circuit match;
The image forming apparatus according to claim 11, wherein the display unit displays a determination result by the determination unit.   The writing control means writes the circuit information into the program logic circuit, and then controls the image forming means to record an operation verification image of the image processing means on the recording medium. The image forming apparatus according to claim 11. Comprising a logic circuit designating means capable of designating a specific programmable logic circuit;
The image forming apparatus according to claim 9, wherein the acquisition unit acquires management information of circuit information related to the programmable logic circuit designated by the logic circuit designation unit from the storage unit.   The image forming apparatus according to claim 9, wherein the management information includes version information that indicates a version of a logic circuit defined by the circuit information so as to be identifiable.   The image forming apparatus according to claim 9, wherein the management information includes circuit information group information that can be identified as a unit of a combination of a plurality of circuit information.   The image forming apparatus according to claim 9, wherein the storage unit is a server apparatus connected via a communication line.

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