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JP2007005833A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP2007005833A
JP2007005833A JP2006275710A JP2006275710A JP2007005833A JP 2007005833 A JP2007005833 A JP 2007005833A JP 2006275710 A JP2006275710 A JP 2006275710A JP 2006275710 A JP2006275710 A JP 2006275710A JP 2007005833 A JP2007005833 A JP 2007005833A
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insulating material
semiconductor
semiconductor device
manufacturing
insulating film
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JP4341663B2 (en
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Hiroyasu Sadabetto
裕康 定別当
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To easily polish using an inexpensive and low precise polishing device even if a polishing process is required at the time of manufacturing a semiconductor device called as BGA, for example. <P>SOLUTION: Semiconductor constructions 3 called as CSP are arranged in a plurality of places on a bonding layer 2 on a base plate 1 in a size corresponding to a plurality of semiconductor devices. An insulating material 13A formed of semi-cured thermosetting resin comprising glass fiber is arranged between the semiconductor construction 3. Heating and pressurization are preformed by using a pair of heating pressuring plates. Thus, an insulating material whose upper face becomes almost flush as an upper face of the semiconductor construction 3 is formed. Even if resin in the insulating material 13A flows out onto the semiconductor construction 3, it can easily be polished and removed by using an inexpensive and low precise buff or endless polishing belt. An upper layer insulating film, an upper layer rewiring and solder balls are formed on it. When a part between the adjacent semiconductor constructions 3 is cut, a plurality of semiconductor devices having the solder balls can be obtained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

近年、携帯電話に代表されるような携帯型電子機器の小型化に相俟ってＣＳＰ(chip size package)と呼ばれる半導体装置が開発されている。このＣＳＰは、複数の外部接続用の接続パッドが形成されたベアーの半導体装置の上面にパッシベーション膜（中間絶縁膜）を設け、このパッシベーション膜の各接続パッドの対応部に開口部を形成し、該開口部を介して各接続パッドに接続される再配線を形成し、各再配線の他端部側に柱状の外部接続用電極を形成するとともに、各外部接続用電極間に封止材を充填したものである。このような、ＣＳＰによれば、各柱状の外部接続用電極上に半田ボールを形成しておくことにより、接続端子を有する回路基板にフェースダウン方式でボンディングすることができ、実装面積をほぼベアーの半導体装置と同一のサイズとすることが可能となるので、従来のワイヤーボンディング等を用いたフェースアップ方式のボンディング方法に比し、電子機器を大幅に小型化することが可能である。このような、ＣＳＰにおいて、生産性を高めるために、ウエハ状態の半導体基板にパッシベーション膜、再配線、外部接続用電極、および封止材を形成し、さらに、封止材で覆われずに露出された外部接続用電極の上面に半田ボールを設けた後、ダイシングラインで切断するようにしたものがある（例えば、特許文献１参照）。   In recent years, a semiconductor device called a CSP (chip size package) has been developed in conjunction with downsizing of a portable electronic device represented by a mobile phone. This CSP is provided with a passivation film (intermediate insulating film) on the upper surface of a bare semiconductor device in which a plurality of connection pads for external connection are formed, and an opening is formed in a corresponding portion of each connection pad of the passivation film. A rewiring connected to each connection pad is formed through the opening, a columnar external connection electrode is formed on the other end of each rewiring, and a sealing material is provided between the external connection electrodes. Filled. According to such CSP, by forming solder balls on each columnar external connection electrode, it is possible to bond to a circuit board having connection terminals by a face-down method, and the mounting area is almost bare. Therefore, the electronic device can be significantly reduced in size as compared with a conventional face-up bonding method using wire bonding or the like. In such a CSP, in order to increase productivity, a passivation film, a rewiring, an external connection electrode, and a sealing material are formed on a semiconductor substrate in a wafer state, and further exposed without being covered with the sealing material. There is one in which a solder ball is provided on the upper surface of the external connection electrode and then cut by a dicing line (see, for example, Patent Document 1).

特開２００１−１６８１２８号公報JP 2001-168128 A

ところで、上記従来の半導体装置では、集積化が進むに従って、外部接続用電極の数が増加すると、次のような問題があった。すなわち、上述した如く、ＣＳＰは、ベアーの半導体装置の上面に外部接続用電極を配列するので、通常は、マトリクス状に配列するのであるが、そのために、外部接続用電極数の多い半導体装置の場合には、外部接続用電極のサイズおよびピッチが極端に小さくなってしまう欠点を有しており、このため、ベアーの半導体装置のサイズの割に外部接続用電極が多いものには適用できないものであった。すなわち、外部接続用電極のサイズおよびピッチが極端に小さくなれば、回路基板との位置合わせが困難であるばかりでなく、接合強度が不足する、ボンディング時に電極間の短絡が発生する、通常はシリコン基板からなる半導体基板と回路基板の線膨張係数の差に起因して発生する応力により外部接続用電極が破壊される等の致命的な問題が発生するのである。   By the way, the conventional semiconductor device has the following problems when the number of external connection electrodes increases as integration increases. That is, as described above, the CSP arranges the external connection electrodes on the upper surface of the bare semiconductor device. Therefore, the CSP is usually arranged in a matrix. For this reason, the CSP has a large number of external connection electrodes. In some cases, the size and pitch of the external connection electrodes become extremely small, and therefore, this is not applicable to the case where the number of external connection electrodes is large for the size of the bare semiconductor device. Met. That is, if the size and pitch of the electrodes for external connection become extremely small, not only alignment with the circuit board is difficult, but also the bonding strength is insufficient, and a short circuit between the electrodes occurs during bonding, usually silicon A fatal problem such as destruction of the external connection electrode occurs due to the stress generated due to the difference between the linear expansion coefficients of the semiconductor substrate and the circuit board.

そこで、この発明は、外部接続用電極の数が増加しても、そのサイズおよびピッチを必要な大きさにすることが可能となる新規な半導体装置の製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel method for manufacturing a semiconductor device that allows the size and pitch to be increased as required even when the number of external connection electrodes increases.

請求項１に記載の発明は、ベース板上に、各々が上面に複数の外部接続部を有する複数の半導体構成体および隣接する前記半導体構成体間に絶縁材を配置し、少なくともいずれかの前記外部接続部に接続される接続パッド部を前記絶縁材上に設け、前記半導体構成体間における前記絶縁材を切断して少なくともいずれかの前記接続パッド部が前記半導体構成体の側方に設けられた前記絶縁材上に配置された半導体装置を複数個得る半導体装置の製造方法であって、前記半導体構成体間における前記絶縁材を切断する前に前記ベース板上に配置された前記絶縁材を加熱または加圧して平坦化を行う処理を含むことを特徴とするものである。
請求項２に記載の発明は、ベース板上に、各々が、半導体基板の上面に設けられた複数の再配線、前記各再配線の一端部上に形成された柱状電極および前記半田謡基板上において前記柱状電極間に設けられ、その上面が前記柱状電極の上面と同一平面に位置する封止膜を有する複数の半導体構成体および隣接する前記半導体構成体間に絶縁材を配置する工程と、前記半導体構成体の外部接続部を除く上面および前記絶縁材の上面に絶縁膜を形成する工程と、前記絶縁膜上に、接続パッド部を有し且ついずれかの前記半導体構成体の対応する前記外部接続部に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッド部が前記絶縁材上に配置されるように形成する工程と、前記半導体構成体間における前記絶縁材を切断して少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体の側方に設けられた前記絶縁材上に配置された半導体装置を複数個得る工程とを有し、前記絶縁材配置工程と前記絶縁膜形成工程とのうちの少なくともいずれかの工程で加熱処理または加圧処理を行なうことを特徴とするものである。
請求項３に係る発明は、請求項１または２に記載の発明において、前記絶縁材切断工程は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項４に記載された発明は、請求項１または２に記載の発明において、前記絶縁材は補強材を含む樹脂からなることを特徴とするものである。
請求項５に記載された発明は、請求項１または２に記載の発明において、前記絶縁材は樹脂からなることを特徴とするものである。
請求項６に記載された発明は、請求項１または２に記載の発明において、前記絶縁材配置工程において、前記ベース板上において前記半導体構成体間に配置された絶縁材材料を加熱加圧処理して、上面が前記半導体構成体の上面とほぼ面一となる前記絶縁材を形成することを特徴とするものである。
請求項７に記載された発明は、請求項１または２に記載の発明において、前記絶縁材配置工程において、前記ベース板上に配置された前記複数の半導体構成体上に配置されたシート状の絶縁材材料を加熱加圧処理して、上面が前記半導体構成体の上面とほぼ面一となる前記絶縁材を形成することを特徴とするものである。
請求項８に記載された発明は、請求項６または７に記載の発明において、前記加熱加圧処理は、前記半導体構成体の上面を加圧制限面として行なうことを特徴とするものである。
請求項９に記載された発明は、請求項７に記載の発明において、前記加熱加圧処理後に、前記半導体構成体の上面側および前記絶縁材の上面側をバフまたはエンドレス研磨ベルトを用いて研磨することを特徴とするものである。
請求項１０に記載された発明は、請求項１または２に記載の発明において、前記接続パッド部上に半田ボールを形成する工程を有することを特徴とするものである。
請求項１１に記載された発明は、請求項１または２に記載の発明において、前記絶縁材切断工程は前記絶縁材を切断するとともに前記ベース板を切断し、前記半導体装置としてベース板を備えたものを得ることを特徴とするものである。
請求項１２に記載された発明は、請求項１１に記載の発明において、切断前の前記ベース板下に別のベース板を配置し、前記ベース板を切断した後に、前記別のベース板を取り除く工程を有することを特徴とするものである。
請求項１３に係る発明は、請求項２に記載の発明において、前記絶縁材配置工程および前記絶縁膜形成工程において、前記ベース板上において前記半導体構成体間に配置された絶縁材材料およびその上に配置されたシート状の絶縁膜材料を加熱加圧処理して、上面が前記半導体構成体の上面とほぼ面一となる前記絶縁材を形成するとともに、その上に前記絶縁膜を形成することを特徴とするものである。
請求項１４に記載された発明は、請求項１３に記載の発明において、前記シート状の絶縁膜材料は樹脂からなることを特徴とするものである。
請求項１５に記載された発明は、請求項１４に記載の発明において、前記シート状の絶縁膜材料を配置した後に、該シート状の絶縁膜材料を仮硬化させることを特徴とするものである。
請求項１６に記載された発明は、請求項１４に記載の発明において、前記加熱加圧処理は、形成すべき前記絶縁膜の上面を加圧制限面として行なうことを特徴とするものである。
請求項１７に記載された発明は、請求項２に記載の発明において、前記絶縁膜形成工程において、前記ベース板上において前記半導体構成体間に隙間をおいて配置された前記絶縁材上に配置されたシート状の絶縁膜材料を加熱加圧処理して、前記絶縁膜を形成するとともに、前記絶縁膜材料の一部によって前記隙間に絶縁膜を形成することを特徴とするものである。
請求項１８に記載された発明は、請求項１７に記載の発明において、前記絶縁材の厚さは前記半導体構成体の厚さよりもやや薄くなっており、前記絶縁材の上面を前記半導体構成体の上面よりもやや低い位置に配置することを特徴とするものである。
請求項１９に記載された発明は、請求項１８に記載の発明において、前記シート状の絶縁膜材料は補強材を含む樹脂からなることを特徴とするものである。
請求項２０に記載された発明は、請求項２に記載の発明において、前記加熱加圧処理は、前記半導体構成体の上面よりも前記補強材の直径だけ高い仮想面を加圧制限面として行なうことを特徴とするものである。
請求項２１に記載された発明は、請求項２に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の外部接続部とそれに対応する前記上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とするものである。
請求項２２に記載された発明は、請求項２に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線の接続パッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とするものである。 According to the first aspect of the present invention, on the base plate, an insulating material is disposed between a plurality of semiconductor structures each having a plurality of external connection portions on the upper surface and the adjacent semiconductor structures, and at least one of the above A connection pad portion connected to an external connection portion is provided on the insulating material, and at least one of the connection pad portions is provided on a side of the semiconductor structure by cutting the insulating material between the semiconductor structures. A semiconductor device manufacturing method for obtaining a plurality of semiconductor devices arranged on the insulating material, wherein the insulating material arranged on the base plate is cut before the insulating material between the semiconductor components is cut. It includes a process of performing planarization by heating or pressurizing.
According to a second aspect of the present invention, on the base plate, each of the plurality of rewirings provided on the upper surface of the semiconductor substrate, the columnar electrode formed on one end of each rewiring, and the solder iron substrate A step of disposing an insulating material between a plurality of semiconductor structures having a sealing film provided between the columnar electrodes and having an upper surface positioned in the same plane as the upper surface of the columnar electrode; and A step of forming an insulating film on an upper surface of the semiconductor structure excluding an external connection portion and an upper surface of the insulating material; and a connection pad portion on the insulating film and corresponding to the semiconductor structure Forming the upper layer rewiring connected to the external connection portion so that at least any one of the connection pads of the upper layer rewiring is disposed on the insulating material; and the insulating material between the semiconductor structures. Cut off A step of obtaining a plurality of semiconductor devices in which at least one of the upper layer rewiring connection pad portions is arranged on the insulating material provided on the side of the semiconductor structure, and the insulating material arranging step Heat treatment or pressure treatment is performed in at least one of the insulating film forming step and the insulating film forming step.
According to a third aspect of the present invention, in the first or second aspect of the present invention, the insulating material cutting step is performed so that a plurality of the semiconductor structural bodies are included.
The invention described in claim 4 is the invention described in claim 1 or 2, characterized in that the insulating material is made of a resin containing a reinforcing material.
The invention described in claim 5 is characterized in that, in the invention described in claim 1 or 2, the insulating material is made of a resin.
According to a sixth aspect of the present invention, in the first or second aspect of the present invention, in the insulating material disposing step, the insulating material disposed between the semiconductor structural bodies on the base plate is heated and pressurized. Then, the insulating material whose upper surface is substantially flush with the upper surface of the semiconductor structure is formed.
The invention described in claim 7 is a sheet-like material arranged on the plurality of semiconductor structures arranged on the base plate in the insulating material arranging step in the invention described in claim 1 or 2. The insulating material is heated and pressurized to form the insulating material whose upper surface is substantially flush with the upper surface of the semiconductor structure.
The invention described in claim 8 is characterized in that, in the invention described in claim 6 or 7, the heating and pressurizing treatment is performed using the upper surface of the semiconductor structure as a pressure limiting surface.
The invention described in claim 9 is the invention according to claim 7, wherein after the heat and pressure treatment, the upper surface side of the semiconductor structure and the upper surface side of the insulating material are polished using a buff or an endless polishing belt. It is characterized by doing.
The invention described in claim 10 is characterized in that, in the invention described in claim 1 or 2, the method further comprises a step of forming a solder ball on the connection pad portion.
According to an eleventh aspect of the present invention, in the invention according to the first or second aspect, the insulating material cutting step includes cutting the insulating material and cutting the base plate, and providing the base plate as the semiconductor device. It is characterized by obtaining things.
The invention described in claim 12 is the invention according to claim 11, wherein another base plate is arranged under the base plate before cutting, and after the base plate is cut, the another base plate is removed. It has the process, It is characterized by the above-mentioned.
According to a thirteenth aspect of the present invention, in the invention according to the second aspect, in the insulating material arranging step and the insulating film forming step, the insulating material material disposed between the semiconductor structural bodies on the base plate and the top thereof The sheet-like insulating film material disposed on the substrate is heated and pressurized to form the insulating material whose upper surface is substantially flush with the upper surface of the semiconductor structure, and the insulating film is formed thereon It is characterized by.
The invention described in claim 14 is the invention according to claim 13, wherein the sheet-like insulating film material is made of a resin.
The invention described in claim 15 is characterized in that, in the invention described in claim 14, after the sheet-like insulating film material is disposed, the sheet-like insulating film material is temporarily cured. .
A sixteenth aspect of the invention is characterized in that, in the invention of the fourteenth aspect, the heat and pressure treatment is performed using the upper surface of the insulating film to be formed as a pressure limiting surface.
According to a seventeenth aspect of the present invention, in the invention according to the second aspect, the insulating film forming step is arranged on the insulating material arranged with a gap between the semiconductor structural bodies on the base plate. The sheet-like insulating film material is heated and pressurized to form the insulating film, and the insulating film is formed in the gap by a part of the insulating film material.
According to an eighteenth aspect of the present invention, in the invention of the seventeenth aspect, the thickness of the insulating material is slightly smaller than the thickness of the semiconductor structure, and the upper surface of the insulating material is placed on the semiconductor structure. It arrange | positions in a position a little lower than the upper surface of this.
The invention described in claim 19 is characterized in that, in the invention described in claim 18, the sheet-like insulating film material is made of a resin containing a reinforcing material.
According to a twentieth aspect of the present invention, in the invention of the second aspect, the heat and pressure treatment is performed using a virtual surface that is higher in diameter than the upper surface of the semiconductor structure by the diameter of the reinforcing material as a pressure limiting surface. It is characterized by this.
The invention described in claim 21 is the invention described in claim 2, wherein the insulating film is formed of a plurality of layers, and an external connection portion of each semiconductor structure and the corresponding upper layer rewiring between the layers are provided between the insulating films. The method includes a step of forming a plurality of sets of inter-layer rewirings that connect each other.
According to a twenty-second aspect of the present invention, in the second aspect of the invention, an uppermost layer insulating film is formed on a portion of the upper surface of the insulating film including the upper layer rewiring except a connection pad portion of the upper layer rewiring. It has the process, It is characterized by the above-mentioned.

そして、この発明によれば、半導体構成体の側方に設けられた絶縁材上に最上層の上層再配線の少なくとも一部の接続パッド部を配置しているので、最上層の上層再配線の接続パッド部の数が増加しても、そのサイズおよびピッチを必要な大きさにすることが可能となる。   According to the present invention, since the connection pad portion of at least a part of the uppermost upper layer rewiring is disposed on the insulating material provided on the side of the semiconductor structure, the uppermost upper layer rewiring Even if the number of connection pad portions increases, the size and pitch can be made as large as necessary.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示したものである。この半導体装置は、シリコン、ガラス、セラミックス等からなる平面矩形形状のベース板１を備えている。ベース板１の上面には、接着剤、粘着シート、両面接着テープ等からなる接着層２が設けられている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. The semiconductor device includes a flat rectangular base plate 1 made of silicon, glass, ceramics, or the like. On the upper surface of the base plate 1, an adhesive layer 2 made of an adhesive, a pressure-sensitive adhesive sheet, a double-sided adhesive tape or the like is provided.

接着層２の上面中央部には、ベース板１のサイズよりもやや小さいサイズの平面矩形形状の半導体構成体３の下面が接着されている。この場合、半導体構成体３は、ＣＳＰと呼ばれるものであり、接着層２の上面中央部に接着されたシリコン基板（半導体基板）４を備えている。   The lower surface of the planar rectangular semiconductor structure 3 having a size slightly smaller than the size of the base plate 1 is bonded to the center of the upper surface of the adhesive layer 2. In this case, the semiconductor structure 3 is called CSP, and includes a silicon substrate (semiconductor substrate) 4 bonded to the center of the upper surface of the adhesive layer 2.

シリコン基板４の上面中央部には集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド５が集積回路に接続されて設けられている。接続パッド５の中央部を除くシリコン基板４の上面には酸化シリコン等からなる絶縁膜６が設けられ、接続パッド５の中央部は絶縁膜６に設けられた開口部７を介して露出されている。   An integrated circuit (not shown) is provided at the center of the upper surface of the silicon substrate 4, and a plurality of connection pads 5 made of aluminum-based metal or the like are provided connected to the integrated circuit at the periphery of the upper surface. An insulating film 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the central portion of the connection pad 5, and the central portion of the connection pad 5 is exposed through an opening 7 provided in the insulating film 6. Yes.

ここで、シリコン基板４上に接続パッド５および絶縁膜６を設けてなるものは、通常、ウエハ状態のシリコン基板４をダイシングして個々のチップとなした場合に得られるものである。しかしながら、この実施形態では、ウエハ状態のシリコン基板４上に接続パッド５および絶縁膜６が形成された状態では、ダイシングを行わず、以下に説明するように、再配線１０および柱状電極１１を有する半導体構成体３が得られる状態でウエハ状態のシリコン基板４をダイシングする。   Here, the connection pad 5 and the insulating film 6 provided on the silicon substrate 4 are usually obtained when the silicon substrate 4 in a wafer state is diced into individual chips. However, in this embodiment, in the state where the connection pad 5 and the insulating film 6 are formed on the silicon substrate 4 in the wafer state, dicing is not performed and the rewiring 10 and the columnar electrode 11 are provided as described below. The silicon substrate 4 in the wafer state is diced in a state where the semiconductor structure 3 is obtained.

次に、ＣＳＰと呼ばれる半導体構成体３の構成について説明する。シリコン基板４上に設けられた絶縁膜６の上面にはエポキシ系樹脂やポリイミド等からなる保護膜（絶縁膜）８が設けられている。この場合、絶縁膜６の開口部７に対応する部分における保護膜８には開口部９が設けられている。両開口部７、９を介して露出された接続パッド５の上面から保護膜８の上面の所定の箇所にかけて下地金属層１０ａおよび該下地金属層１０ａ上に設けられた上層金属層１０ｂからなる再配線１０が設けられている。   Next, the configuration of the semiconductor structure 3 called CSP will be described. A protective film (insulating film) 8 made of epoxy resin, polyimide, or the like is provided on the upper surface of the insulating film 6 provided on the silicon substrate 4. In this case, an opening 9 is provided in the protective film 8 at a portion corresponding to the opening 7 of the insulating film 6. From the upper surface of the connection pad 5 exposed through both the openings 7 and 9 to a predetermined position on the upper surface of the protective film 8, a re-layer consisting of a base metal layer 10a and an upper metal layer 10b provided on the base metal layer 10a. A wiring 10 is provided.

再配線１０の接続パッド部上面には銅からなる柱状電極１１が設けられている。再配線１０を含む保護膜８の上面にはエポキシ系樹脂やポリイミド等からなる封止膜（絶縁膜）１２がその上面が柱状電極１１の上面と面一となるように設けられている。このように、ＣＳＰと呼ばれる半導体構成体３は、シリコン基板４、接続パッド５、絶縁膜６を含み、さらに、保護膜８、再配線１０、柱状電極１１、封止膜１２を含んで構成されている。   A columnar electrode 11 made of copper is provided on the upper surface of the connection pad portion of the rewiring 10. A sealing film (insulating film) 12 made of epoxy resin, polyimide, or the like is provided on the upper surface of the protective film 8 including the rewiring 10 so that the upper surface is flush with the upper surface of the columnar electrode 11. As described above, the semiconductor structure 3 called CSP includes the silicon substrate 4, the connection pad 5, and the insulating film 6, and further includes the protective film 8, the rewiring 10, the columnar electrode 11, and the sealing film 12. ing.

半導体構成体３の周囲における接着層２の上面には矩形枠状の絶縁材１３が設けられている。絶縁材１３は、エポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂中に繊維やフィラー等の補強材を含有させたものからなっている。繊維は、ガラス繊維やアラミド繊維等である。フィラーは、シリカフィラーやセラミックス系フィラー等である。絶縁材１３の厚さは、半導体構成体３の厚さとほぼ同じとなっている。   A rectangular frame-shaped insulating material 13 is provided on the upper surface of the adhesive layer 2 around the semiconductor structure 3. The insulating material 13 is made of a thermosetting resin such as an epoxy resin or a BT resin containing a reinforcing material such as a fiber or a filler. The fiber is glass fiber or aramid fiber. The filler is a silica filler or a ceramic filler. The thickness of the insulating material 13 is substantially the same as the thickness of the semiconductor structure 3.

半導体構成体３および絶縁材１３の上面にはエポキシ系樹脂やポリイミド等からなる第１の上層絶縁膜１４が設けられている。柱状電極１１の上面中央部に対応する部分における第１の上層絶縁膜１４には開口部１５が設けられている。開口部１５を介して露出された柱状電極１１の上面から第１の上層絶縁膜１４の上面の所定の箇所にかけて第１の下地金属層１６ａおよび該第１の下地金属層１６ａ上に設けられた第１の上層金属層１６ｂからなる第１の上層再配線１６が設けられている。   A first upper insulating film 14 made of epoxy resin, polyimide, or the like is provided on the upper surfaces of the semiconductor structure 3 and the insulating material 13. An opening 15 is provided in the first upper insulating film 14 in a portion corresponding to the center of the upper surface of the columnar electrode 11. Provided on the first base metal layer 16a and the first base metal layer 16a from the upper surface of the columnar electrode 11 exposed through the opening 15 to a predetermined location on the upper surface of the first upper insulating film 14 A first upper layer rewiring 16 made of the first upper metal layer 16b is provided.

第１の上層再配線１６を含む第１の上層絶縁膜１４の上面にはエポキシ系樹脂やポリイミド等からなる第２の上層絶縁膜１７が設けられている。第１の上層再配線１６の接続パッド部に対応する部分における第２の上層絶縁膜１７には開口部１８が設けられている。開口部１８を介して露出された第１の上層再配線１６の接続パッド部上面から第２の上層絶縁膜１７の上面の所定の箇所にかけて第２の下地金属層１９ａおよび該第２の下地金属層１９ａ上に設けられた第２の上層金属層１９ｂからなる第２の上層再配線１９が設けられている。   A second upper insulating film 17 made of epoxy resin, polyimide, or the like is provided on the upper surface of the first upper insulating film 14 including the first upper rewiring 16. An opening 18 is provided in the second upper insulating film 17 at a portion corresponding to the connection pad portion of the first upper rewiring 16. From the upper surface of the connection pad portion of the first upper layer rewiring 16 exposed through the opening 18 to a predetermined position on the upper surface of the second upper layer insulating film 17, the second base metal layer 19a and the second base metal A second upper layer rewiring 19 made of the second upper metal layer 19b provided on the layer 19a is provided.

第２の上層再配線１９を含む第２の上層絶縁膜１７の上面にはエポキシ系樹脂やポリイミド等からなる第３の上層絶縁膜２０が設けられている。第２の上層再配線１９の接続パッド部に対応する部分における第３の上層絶縁膜２０には開口部２１が設けられている。開口部２１内およびその上方には半田ボール２２が第２の上層再配線１９の接続パッド部に接続されて設けられている。複数の半田ボール２２は、第３の上層絶縁膜２０上にマトリクス状に配置されている。   A third upper layer insulating film 20 made of epoxy resin, polyimide, or the like is provided on the upper surface of the second upper layer insulating film 17 including the second upper layer rewiring 19. An opening 21 is provided in the third upper-layer insulating film 20 in a portion corresponding to the connection pad portion of the second upper-layer rewiring 19. Solder balls 22 are provided in the opening 21 and above it, connected to the connection pad portion of the second upper layer rewiring 19. The plurality of solder balls 22 are arranged in a matrix on the third upper insulating film 20.

ところで、ベース板１のサイズを半導体構成体３のサイズよりもやや大きくしているのは、シリコン基板４上の接続パッド５の数の増加に応じて、半田ボール２２の配置領域を半導体構成体３のサイズよりもやや大きくし、これにより、第２の上層再配線１９の接続パッド部（第３の上層絶縁膜２０の開口部２１内の部分）のサイズおよびピッチを柱状電極１１のサイズおよびピッチよりも大きくするためである。   By the way, the size of the base plate 1 is made slightly larger than the size of the semiconductor structure 3 because the area where the solder balls 22 are arranged is increased according to the increase in the number of connection pads 5 on the silicon substrate 4. 3 so that the size and pitch of the connection pad portion of the second upper-layer rewiring 19 (the portion in the opening 21 of the third upper-layer insulating film 20) and the pitch of the columnar electrode 11 are increased. This is to make it larger than the pitch.

このため、マトリクス状に配置された第２の上層再配線１９の接続パッド部は、半導体構成体３に対応する領域のみでなく、半導体構成体３の周側面の外側に設けられた絶縁材１３に対応する領域上にも配置されている。つまり、マトリクス状に配置された半田ボール２２のうち、少なくとも最外周の半田ボール２２は半導体構成体３よりも外側に位置する周囲に配置されている。   Therefore, the connection pad portions of the second upper layer rewiring 19 arranged in a matrix form not only the region corresponding to the semiconductor structure 3 but also the insulating material 13 provided outside the peripheral side surface of the semiconductor structure 3. It is also arranged on the area corresponding to. That is, among the solder balls 22 arranged in a matrix, at least the outermost solder balls 22 are arranged around the semiconductor structure 3.

この場合、変形例として、第２の上層再配線１９の接続パッド部を全て半導体構成体３よりも外側に位置する周囲に配置するようにしてもよい。また、上層の再配線を１層として、つまり第１の上層再配線１６のみとして、少なくとも、最外周の接続パッド部を半導体構成体３よりも外側に位置する周囲に配置することもできる。   In this case, as a modification, all of the connection pad portions of the second upper layer rewiring 19 may be disposed around the semiconductor structure 3. Further, the upper layer rewiring can be arranged as one layer, that is, only the first upper layer rewiring 16, and at least the outermost connection pad portion can be disposed around the semiconductor structure 3.

このように、この半導体装置では、シリコン基板４上に、接続パッド５、絶縁膜６を有するのみでなく、保護膜８、再配線１０、柱状電極１１、封止膜１２等をも形成した半導体構成体３の周囲に絶縁材１３を設け、その上面に少なくとも第１の上層絶縁膜１４および該第１の上層絶縁膜１４に形成された開口部１５を介して柱状電極１１に接続される第１の上層再配線１６を設ける構成を特徴としている。   As described above, in this semiconductor device, not only the connection pad 5 and the insulating film 6 are formed on the silicon substrate 4, but also the protective film 8, the rewiring 10, the columnar electrode 11, the sealing film 12 and the like are formed. An insulating material 13 is provided around the structure 3, and the first upper insulating film 14 is provided on the upper surface of the insulating material 13 and the first electrode 13 is connected to the columnar electrode 11 through the opening 15 formed in the first upper insulating film 14. One upper layer rewiring 16 is provided.

この場合、半導体構成体３の周囲に配置された矩形枠状の絶縁材１３は、熱硬化性樹脂中に繊維やフィラー等の補強材を含有させたものからなっているので、熱硬化性樹脂のみからなる場合と比較して、熱硬化性樹脂の硬化時の収縮による応力を小さくすることができ、ひいてはベース基板１が反りにくいようにすることができる。また、絶縁材１３を用いることで、上面を平坦化し、後述する如く、以降の工程で形成する上層再配線１６、１９や半田ボール２２の上面の高さ位置を均一にし、ボンディング時の信頼性を向上することができる．   In this case, the rectangular frame-shaped insulating material 13 arranged around the semiconductor structure 3 is made of a thermosetting resin containing a reinforcing material such as a fiber or a filler. Compared with the case of only comprising, the stress due to the shrinkage at the time of curing of the thermosetting resin can be reduced, and as a result, the base substrate 1 can be made difficult to warp. Further, by using the insulating material 13, the upper surface is flattened, and as will be described later, the upper layer rewirings 16 and 19 and the upper surface of the solder ball 22 formed in the subsequent steps are made to have a uniform height position, and reliability during bonding. Can be improved.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体３の製造方法の一例について説明する。この場合、まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）４上にアルミニウム系金属等からなる接続パッド５、酸化シリコン等からなる絶縁膜６およびエポキシ系樹脂やポリイミド等からなる保護膜８が設けられ、接続パッド５の中央部が絶縁膜６および保護膜８に形成された開口部７、９を介して露出されたものを用意する。   Next, an example of a method for manufacturing the semiconductor device 3 will be described. In this case, first, as shown in FIG. 2, on a silicon substrate (semiconductor substrate) 4 in a wafer state, a connection pad 5 made of aluminum metal or the like, an insulating film 6 made of silicon oxide or the like, and an epoxy resin or polyimide, etc. A protective film 8 is provided, and the central portion of the connection pad 5 is exposed through the openings 7 and 9 formed in the insulating film 6 and the protective film 8.

次に、図３に示すように、両開口部７、９を介して露出された接続パッド５の上面を含む保護膜８の上面全体に下地金属層１０ａを形成する。この場合、下地金属層１０ａは、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。これは、後述する上層下地金属層１６ａ、１９ａの場合も同様である。   Next, as shown in FIG. 3, a base metal layer 10 a is formed on the entire upper surface of the protective film 8 including the upper surface of the connection pad 5 exposed through the openings 7 and 9. In this case, the base metal layer 10a may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering. The same applies to the upper base metal layers 16a and 19a described later.

次に、下地金属層１０ａの上面にメッキレジスト膜３１をパターン形成する。この場合、再配線１０形成領域に対応する部分におけるメッキレジスト膜３１には開口部３２が形成されている。次に、下地金属層１０ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜３１の開口部３２内の下地金属層１０ａの上面に上層金属層１０ｂを形成する。次に、メッキレジスト膜３１を剥離する。   Next, a plating resist film 31 is formed on the upper surface of the base metal layer 10a. In this case, an opening 32 is formed in the plating resist film 31 in a portion corresponding to the rewiring 10 formation region. Next, the upper metal layer 10 b is formed on the upper surface of the base metal layer 10 a in the opening 32 of the plating resist film 31 by performing copper electroplating using the base metal layer 10 a as a plating current path. Next, the plating resist film 31 is peeled off.

次に、図４に示すように、上層金属層１０ｂを含む下地金属層１０ａの上面にメッキレジスト膜３３をパターン形成する。この場合、柱状電極１１形成領域に対応する部分におけるメッキレジスト膜３３には開口部３４が形成されている。次に、下地金属層１０ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜３３の開口部３４内の上層金属層１０ｂの接続パッド部上面に柱状電極１１を形成する。   Next, as shown in FIG. 4, a plating resist film 33 is formed on the upper surface of the base metal layer 10a including the upper metal layer 10b. In this case, an opening 34 is formed in the plating resist film 33 in a portion corresponding to the columnar electrode 11 formation region. Next, the columnar electrode 11 is formed on the upper surface of the connection pad portion of the upper metal layer 10b in the opening 34 of the plating resist film 33 by performing copper electroplating using the base metal layer 10a as a plating current path.

次に、メッキレジスト膜３３を剥離し、次いで、柱状電極１１および上層金属層１０ｂをマスクとして下地金属層１０ａの不要な部分をエッチングして除去すると、図５に示すように、上層金属層１０ｂ下にのみ下地金属層１０ａが残存され、この残存された下地金属層１０ａおよびその上面全体に形成された上層金属層１０ｂにより再配線１０が形成される。   Next, the plating resist film 33 is peeled off, and then unnecessary portions of the base metal layer 10a are removed by etching using the columnar electrode 11 and the upper metal layer 10b as a mask, as shown in FIG. 5, the upper metal layer 10b. The underlying metal layer 10a remains only below, and the rewiring 10 is formed by the remaining underlying metal layer 10a and the upper metal layer 10b formed on the entire upper surface thereof.

次に、図６に示すように、スクリーン印刷法やスピンコーティング法等により、柱状電極１１および再配線１０を含む保護膜８の上面全体にエポキシ系樹脂やポリイミド等からなる封止膜１２をその厚さが柱状電極１１の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極１１の上面は封止膜１２によって覆われている。   Next, as shown in FIG. 6, the sealing film 12 made of epoxy resin, polyimide, or the like is applied to the entire upper surface of the protective film 8 including the columnar electrode 11 and the rewiring 10 by screen printing, spin coating, or the like. It is formed so that the thickness is greater than the height of the columnar electrode 11. Therefore, in this state, the upper surface of the columnar electrode 11 is covered with the sealing film 12.

次に、封止膜１２および柱状電極１１の上面側を適宜に研磨し、図７に示すように、柱状電極１１の上面を露出させ、且つ、この露出された柱状電極１１の上面を含む封止膜１２の上面を平坦化する。次に、図８に示すように、ダンシング工程を経ると、図１に示す半導体構成体３が複数個得られる。   Next, the upper surface side of the sealing film 12 and the columnar electrode 11 is appropriately polished to expose the upper surface of the columnar electrode 11 and to include the exposed upper surface of the columnar electrode 11 as shown in FIG. The upper surface of the stop film 12 is flattened. Next, as shown in FIG. 8, a plurality of semiconductor structures 3 shown in FIG. 1 are obtained through a dancing process.

ところで、柱状電極１１の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極１１の高さにばらつきがあるため、このばらつきを解消して、柱状電極１１の高さを均一にするためである。また、この場合、軟質の銅からなる柱状電極１１とエポキシ系樹脂等からなる封止膜１２とを同時に研磨するため、適宜な粗さの砥石を備えたグラインダーを用いている。   By the way, the reason why the upper surface side of the columnar electrode 11 is appropriately polished is that there is a variation in the height of the columnar electrode 11 formed by electrolytic plating, so this variation is eliminated and the height of the columnar electrode 11 is made uniform. It is to do. In this case, a grinder provided with a grindstone having an appropriate roughness is used to simultaneously polish the columnar electrode 11 made of soft copper and the sealing film 12 made of epoxy resin or the like.

次に、このようにして得られた半導体構成体３を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図９に示すように、図１に示すベース板１を複数枚採取することができる大きさで、限定する意味ではないが、平面形状が長方形、好ましくは、ほぼ正方形のベース板１の上面全体に接着層２を形成する。次に、接着層２の上面の所定の複数箇所にそれぞれ半導体構成体３のシリコン基板４の下面を接着する。   Next, an example of manufacturing the semiconductor device shown in FIG. 1 using the semiconductor structure 3 obtained in this manner will be described. First, as shown in FIG. 9, the size is such that a plurality of base plates 1 shown in FIG. 1 can be sampled and is not limited. However, the planar shape of the base plate 1 is preferably rectangular. The adhesive layer 2 is formed on the entire top surface. Next, the lower surface of the silicon substrate 4 of the semiconductor structure 3 is bonded to a plurality of predetermined locations on the upper surface of the adhesive layer 2.

次に、半導体構成体３間および最外周に配置された半導体構成体３の外側における接着層２の上面に、繊維やフィラー等の補強材を含む半硬化のエポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂からなる絶縁材材料１３Ａを半導体構成体３の上面よりもやや盛り上がるように配置する。   Next, heat such as semi-cured epoxy resin or BT resin including reinforcing materials such as fibers and fillers is formed on the upper surface of the adhesive layer 2 between the semiconductor structural bodies 3 and outside the semiconductor structural bodies 3 arranged at the outermost periphery. The insulating material 13 </ b> A made of a curable resin is disposed so as to rise slightly from the upper surface of the semiconductor structure 3.

次に、図１０に示すように、一対の加熱加圧板３５、３６を用いて絶縁材材料１３Ａを加熱加圧することにより、半導体構成体３間および最外周に配置された半導体構成体３の外側における接着層２の上面に、絶縁材１３をその上面が半導体構成体３の上面とほぼ面一となるように形成する。   Next, as shown in FIG. 10, the insulating material 13 </ b> A is heated and pressurized using a pair of heating and pressing plates 35 and 36, so that the outside of the semiconductor structure 3 disposed between the semiconductor structures 3 and at the outermost periphery. The insulating material 13 is formed on the upper surface of the adhesive layer 2 so that the upper surface thereof is substantially flush with the upper surface of the semiconductor structure 3.

この場合、図７に示すように、ウエハ状態において、半導体構成体３の柱状電極１１の高さは均一とされ、且つ、柱状電極１１の上面を含む封止膜１２の上面は平坦化されているため、図１０に示す状態において、複数の半導体構成体３の各厚さは同じである。   In this case, as shown in FIG. 7, in the wafer state, the height of the columnar electrode 11 of the semiconductor structure 3 is uniform, and the upper surface of the sealing film 12 including the upper surface of the columnar electrode 11 is flattened. Therefore, in the state shown in FIG. 10, each thickness of the several semiconductor structure 3 is the same.

そこで、図１０に示す状態において、半導体構成体３の上面を加圧制限面として加熱加圧を行なうと、絶縁材１３の厚さは半導体構成体３の厚さとほぼ同じとなる。また、一対の加熱加圧板３５、３６を備えたプレス装置として、オープンエンド型（開放型）の平面プレス装置を用いると、絶縁材材料１３Ａ中の余分の熱硬化性樹脂は一対の加熱加圧板３５、３６の外側に押し出される。そして、この状態で、絶縁材１３中の半硬化の熱硬化性樹脂が硬化すると、絶縁材１３の上面は半導体構成体３の上面とほぼ面一となる。なお、図１０に示す製造工程において、上面側からは加圧のみとし、加熱は半導体構成体３の下面側をヒーター等で行うというように、加熱と加圧は別々の手段で行ってもよいし、加圧と加熱とを別の工程で行うようにすることもできる。   Therefore, in the state shown in FIG. 10, when heating and pressing are performed using the upper surface of the semiconductor structure 3 as the pressure limiting surface, the thickness of the insulating material 13 becomes substantially the same as the thickness of the semiconductor structure 3. Further, when an open-end type (open type) flat pressing device is used as a press device provided with a pair of heating and pressurizing plates 35 and 36, the extra thermosetting resin in the insulating material 13A is paired with a pair of heating and pressing plates. Extruded outside of 35 and 36. In this state, when the semi-cured thermosetting resin in the insulating material 13 is cured, the upper surface of the insulating material 13 is substantially flush with the upper surface of the semiconductor structure 3. In the manufacturing process shown in FIG. 10, heating and pressurization may be performed by different means, for example, only pressure is applied from the upper surface side, and heating is performed on the lower surface side of the semiconductor structure 3 with a heater or the like. However, pressurization and heating can be performed in separate steps.

このように、加熱加圧あるいは加圧のみにより、絶縁材１３の厚さが半導体構成体３の厚さとほぼ同じとなるようにしているので、研磨工程は不要である。したがって、ベース板１のサイズが例えば５００×５００ｍｍ程度と比較的大きくても、その上に配置された複数の半導体構成体３に対して絶縁材１３の平坦化を一括して簡単に行なうことができる。   Thus, since the thickness of the insulating material 13 is made substantially the same as the thickness of the semiconductor structure 3 only by heating or pressurization, a polishing step is unnecessary. Therefore, even if the size of the base plate 1 is relatively large, for example, about 500 × 500 mm, the planarization of the insulating material 13 can be easily performed collectively on the plurality of semiconductor structures 3 arranged thereon. it can.

ここで、絶縁材材料１３Ａ中の余分の熱硬化性樹脂が半導体構成体３上にやや流出しても、この流出により形成された熱硬化性樹脂層の厚さが無視できるほど薄ければ、別に支障はない。一方、この流出により形成された熱硬化性樹脂層の厚さが無視できないほど厚い場合には、バフ研磨により除去すればよい。   Here, even if excess thermosetting resin in the insulating material 13A slightly flows out on the semiconductor structure 3, if the thickness of the thermosetting resin layer formed by this outflow is so thin that it can be ignored, There is no problem. On the other hand, when the thickness of the thermosetting resin layer formed by the outflow is so thick that it cannot be ignored, it may be removed by buffing.

すなわち、この場合の研磨は、半導体構成体３の上面側つまり銅からなる柱状電極１１の上面側を研磨するのではなく、半導体構成体３の上面および形成すべき厚さの絶縁材１３の上面を覆っている熱硬化性樹脂層を除去するものであり、且つ、この熱硬化性樹脂層中に繊維やフィラー等の補強材は含まれていないので、安価で低精度のバフ研磨装置を用いて簡単に研磨することができる。   That is, the polishing in this case does not polish the upper surface side of the semiconductor structure 3, that is, the upper surface side of the columnar electrode 11 made of copper, but the upper surface of the semiconductor structure 3 and the upper surface of the insulating material 13 having a thickness to be formed. The thermosetting resin layer covering the surface is removed, and the reinforcing material such as fiber and filler is not included in the thermosetting resin layer, so an inexpensive and low-precision buffing device is used. Can be easily polished.

研磨の他の例としては、安価で低精度のエンドレス研磨ベルトの一部をフラット化し、このフラット化した部分で半導体構成体３の上面および形成すべき厚さの絶縁材１３の上面を覆っている熱硬化性樹脂層を半導体構成体３の上面を研磨制限面として平滑化研磨するようにしてもよい。   As another example of polishing, a part of an inexpensive and low-precision endless polishing belt is flattened, and the flattened portion covers the upper surface of the semiconductor structure 3 and the insulating material 13 having a thickness to be formed. The thermosetting resin layer may be smoothened and polished using the upper surface of the semiconductor structure 3 as a polishing limiting surface.

そして、バフやエンドレス研磨ベルトを用いた研磨装置では、ベース板１のサイズが例えば５００×５００ｍｍ程度と比較的大きくても、それに容易に対応することができる上、研磨工程は１回で済み、短時間で簡単に研磨することができる。このように、この工程では、砥石等による研磨と異なり、柱状電極１１の上面側にダレが発生しないような研磨を行うようにすることが、生産性の面で望ましい。   And in a polishing apparatus using a buff or an endless polishing belt, even if the size of the base plate 1 is relatively large, for example, about 500 × 500 mm, it can be easily dealt with, and the polishing process can be performed only once. It can be easily polished in a short time. As described above, in this step, it is desirable in terms of productivity that polishing is performed so that no sagging occurs on the upper surface side of the columnar electrode 11, unlike polishing with a grindstone or the like.

ところで、半導体構成体３の周囲に配置された方形枠状の絶縁材１３は、熱硬化性樹脂中に繊維やフィラー等の補強材を含有させたものからなっているので、熱硬化性樹脂のみからなる場合と比較して、熱硬化性樹脂の硬化時の収縮による応力を小さくすることができ、ひいてはベース板１が反りにくいようにすることができる。なお、絶縁材材料１３Ａは、予め、各半導体構成体３が配置される位置に対応して、半導体構成体３のサイズとほぼ同じか、或いは少し大きめのサイズの開口部が形成されたシート状のものを用いてもよい。また、上記実施形態では、ベース板１上に複数の半導体構成体３を配置した後、絶縁材材料１３Ａを配置する場合で説明したが、ベース板１上に各半導体構成体３に対応する開口部が形成された絶縁材材料１３Ａを配置した後、半導体構成体３を配置するようにすることも可能である。   By the way, the rectangular frame-shaped insulating material 13 arranged around the semiconductor structure 3 is made of a thermosetting resin containing a reinforcing material such as a fiber or a filler, so that only the thermosetting resin is used. Compared with the case where it consists of, the stress by the shrinkage | contraction at the time of hardening of a thermosetting resin can be made small, and, as a result, the base board 1 can be made hard to warp. The insulating material 13 </ b> A is formed in advance in a sheet shape in which an opening having a size substantially the same as or slightly larger than the size of the semiconductor structure 3 is formed corresponding to the position where each semiconductor structure 3 is arranged. May be used. In the above-described embodiment, the case where the insulating material 13 </ b> A is disposed after the plurality of semiconductor structures 3 are disposed on the base plate 1 has been described. However, the openings corresponding to the respective semiconductor structures 3 are disposed on the base plate 1. It is also possible to arrange the semiconductor structure 3 after arranging the insulating material 13 </ b> A in which the portion is formed.

さて、図１０に示す工程が終了したら、次に、図１１に示すように、ほぼ面一となった半導体構成体３および絶縁材１３の上面全体に第１の上層絶縁膜１４を形成する。この場合、第１の上層絶縁膜１４の形成は、樹脂シートのラミネートであってもよく、液状樹脂の塗布であってもよい。そして、第１の上層絶縁膜１４をエポキシ系樹脂やカルド樹脂等の感光性樹脂によって形成する場合には、フォトリソグラフィ法により、柱状電極１１の上面中央部に対応する部分における第１の上層絶縁膜１４に開口部１５を形成する。   When the step shown in FIG. 10 is completed, next, as shown in FIG. 11, a first upper insulating film 14 is formed on the entire upper surface of the semiconductor structure 3 and the insulating material 13 that are substantially flush with each other. In this case, the first upper insulating film 14 may be formed by laminating a resin sheet or applying a liquid resin. When the first upper insulating film 14 is formed of a photosensitive resin such as epoxy resin or cardo resin, the first upper insulating layer in a portion corresponding to the center of the upper surface of the columnar electrode 11 is formed by photolithography. An opening 15 is formed in the film 14.

第１の上層絶縁膜１４をエポキシ系樹脂やＢＴ樹脂等の非感光性樹脂によって形成する場合には、レーザビームを照射するレーザ加工により、第１の上層絶縁膜１４に開口部１５を形成する。この場合、図１０に示す製造工程において、絶縁材材料１３Ａ中の余分の熱硬化性樹脂が半導体構成体３上にやや流出し、この流出により形成された熱硬化性樹脂層の厚さが無視できないほど厚くても、レーザ加工による開口形成が可能な程度に薄い場合には、上述の研磨工程は省略してもよい。   When the first upper insulating film 14 is formed of a non-photosensitive resin such as epoxy resin or BT resin, the opening 15 is formed in the first upper insulating film 14 by laser processing with laser beam irradiation. . In this case, in the manufacturing process shown in FIG. 10, the excess thermosetting resin in the insulating material 13A slightly flows out onto the semiconductor structure 3, and the thickness of the thermosetting resin layer formed by this outflow is ignored. If it is too thick to be able to form an opening by laser processing, the above polishing step may be omitted.

次に、図１２に示すように、開口部１５を介して露出された柱状電極１１の上面を含む第１の上層絶縁膜１４の上面全体に第１の下地金属層１６ａを形成する。次に、第１の下地金属層１６ａの上面にメッキレジスト膜３７をパターン形成する。この場合、第１の上層再配線１６形成領域に対応する部分におけるメッキレジスト膜３７には開口部３８が形成されている。次に、第１の下地金属層１６ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜３７の開口部３８内の第１の下地金属層１６ａの上面に第１の上層金属層１６ｂを形成する。   Next, as shown in FIG. 12, the first base metal layer 16 a is formed on the entire upper surface of the first upper insulating film 14 including the upper surface of the columnar electrode 11 exposed through the opening 15. Next, a plating resist film 37 is patterned on the upper surface of the first base metal layer 16a. In this case, an opening 38 is formed in the plating resist film 37 in a portion corresponding to the first upper layer rewiring 16 formation region. Next, by performing electrolytic plating of copper using the first base metal layer 16a as a plating current path, the first upper metal layer is formed on the upper surface of the first base metal layer 16a in the opening 38 of the plating resist film 37. 16b is formed.

次に、メッキレジスト膜３７を剥離し、次いで、第１の上層金属層１６ｂをマスクとして第１の下地金属層１６ａの不要な部分をエッチングして除去すると、図１３に示すように、第１の上層金属層１６ｂ下にのみ第１の下地金属層１６ａが残存され、この残存された第１の下地金属層１６ａおよびその上面全体に形成された第１の上層金属層１６ｂにより第１の上層再配線１６が形成される。   Next, the plating resist film 37 is peeled off, and then unnecessary portions of the first base metal layer 16a are removed by etching using the first upper metal layer 16b as a mask, as shown in FIG. The first base metal layer 16a is left only under the upper metal layer 16b, and the first upper metal layer 16b formed on the entire upper surface of the first base metal layer 16a and the first upper metal layer 16b is formed. A rewiring 16 is formed.

次に、図１４に示すように、スクリーン印刷法やスピンコーティング法等により、第１の上層再配線１６を含む第１の上層絶縁膜１４の上面全体にエポキシ系樹脂やポリイミド等からなる第２の上層絶縁膜１７を形成する。この場合、第１の上層再配線１６の接続パッド部に対応する部分における第２の上層絶縁膜１７には開口部１８が形成されている。次に、開口部１８を介して露出された第１の上層再配線１６の接続パッド部を含む第２の上層絶縁膜１７の上面全体に第２の下地金属層１９ａを形成する。   Next, as shown in FIG. 14, the second upper surface made of epoxy resin, polyimide, or the like is formed on the entire upper surface of the first upper layer insulating film 14 including the first upper layer rewiring 16 by screen printing, spin coating, or the like. An upper insulating film 17 is formed. In this case, an opening 18 is formed in the second upper insulating film 17 in a portion corresponding to the connection pad portion of the first upper rewiring 16. Next, a second base metal layer 19 a is formed on the entire upper surface of the second upper insulating film 17 including the connection pad portion of the first upper rewiring 16 exposed through the opening 18.

次に、第２の下地金属層１９ａの上面にメッキレジスト膜３９をパターン形成する。この場合、第２の上層再配線１９形成領域に対応する部分におけるメッキレジスト膜３９には開口部４０が形成されている。次に、第２の下地金属層１９ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜３９の開口部４０内の第２の下地金属層１９ａの上面に第２の上層金属層１９ｂを形成する。   Next, a plating resist film 39 is patterned on the upper surface of the second base metal layer 19a. In this case, an opening 40 is formed in the plating resist film 39 in a portion corresponding to the second upper layer rewiring 19 formation region. Next, by performing copper electroplating using the second base metal layer 19a as a plating current path, a second upper metal layer is formed on the upper surface of the second base metal layer 19a in the opening 40 of the plating resist film 39. 19b is formed.

次に、メッキレジスト膜３９を剥離し、次いで、第２の上層金属層１９ｂをマスクとして第２の下地金属層１９ａの不要な部分をエッチングして除去すると、図１５に示すように、第２の上層金属層１９ｂ下にのみ第２の下地金属層１９ａが残存され、この残存された第２の下地金属層１９ａおよびその上面全体に形成された第２の上層金属層１９ｂにより第２の上層再配線１９が形成される。   Next, the plating resist film 39 is peeled off, and then unnecessary portions of the second base metal layer 19a are removed by etching using the second upper metal layer 19b as a mask. As shown in FIG. The second base metal layer 19a remains only under the upper metal layer 19b, and the second upper metal layer 19b formed on the entire upper surface of the second base metal layer 19a and the second upper metal layer 19b remain. A rewiring 19 is formed.

次に、図１６に示すように、スクリーン印刷法やスピンコーティング法等により、第２の上層再配線１９を含む第２の上層絶縁膜１７の上面全体にエポキシ系樹脂やポリイミド等からなる第３の上層絶縁膜２０を形成する。この場合、第２の上層再配線１９の接続パッド部に対応する部分における第３の上層絶縁膜２０には開口部２１が形成されている。次に、開口部２１内およびその上方に半田ボール２２を第２の上層再配線１９の接続パッド部に接続させて形成する。   Next, as shown in FIG. 16, a third upper layer 17 made of epoxy resin, polyimide, or the like is formed on the entire upper surface of the second upper layer insulating film 17 including the second upper layer rewiring 19 by screen printing, spin coating, or the like. An upper insulating film 20 is formed. In this case, an opening 21 is formed in the third upper layer insulating film 20 in a portion corresponding to the connection pad portion of the second upper layer rewiring 19. Next, a solder ball 22 is formed in the opening 21 and above it by connecting it to the connection pad portion of the second upper layer rewiring 19.

次に、図１７に示すように、互いに隣接する半導体構成体３間において、３層の絶縁膜２０、１７、１４、絶縁材１３、接着層２およびベース板１を切断すると、図１に示す半導体装置が複数個得られる。   Next, as shown in FIG. 17, when the three insulating films 20, 17, 14, the insulating material 13, the adhesive layer 2, and the base plate 1 are cut between the adjacent semiconductor structures 3, the structure shown in FIG. 1 is obtained. A plurality of semiconductor devices are obtained.

このようにして得られた半導体装置では、半導体構成体３の柱状電極１１に接続される第１の下地金属層１６ａおよび第１の上層金属層１６ｂを無電解メッキ（またはスパッタ）および電解メッキにより形成し、第１の上層再配線１６の接続パッド部に接続される第２の下地金属層１９ａおよび第２の上層金属層１９ｂを無電解メッキ（またはスパッタ）および電解メッキにより形成しているので、半導体構成体３の柱状電極１１と第１の上層再配線１６との間の導電接続および第１の上層再配線１６と第２の上層再配線１９との間の導電接続を確実とすることができる。   In the semiconductor device thus obtained, the first base metal layer 16a and the first upper metal layer 16b connected to the columnar electrode 11 of the semiconductor structure 3 are formed by electroless plating (or sputtering) and electrolytic plating. The second base metal layer 19a and the second upper metal layer 19b that are formed and connected to the connection pad portion of the first upper layer rewiring 16 are formed by electroless plating (or sputtering) and electrolytic plating. The conductive connection between the columnar electrode 11 of the semiconductor structure 3 and the first upper layer rewiring 16 and the conductive connection between the first upper layer rewiring 16 and the second upper layer rewiring 19 are ensured. Can do.

また、上記製造方法では、ベース板１上の接着層２上に複数の半導体構成体３を配置し、複数の半導体構成体３に対して絶縁材１３、第１〜第３の上層絶縁膜１４、１７、２０、第１、第２の下地金属層１６ａ、１９ａ、第１、第２の上層金属層１６ｂ、１９ｂおよび半田ボール２２の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。   In the manufacturing method, a plurality of semiconductor structures 3 are arranged on the adhesive layer 2 on the base plate 1, and the insulating material 13 and the first to third upper insulating films 14 are arranged with respect to the plurality of semiconductor structures 3. , 17, 20, first and second base metal layers 16 a, 19 a, first and second upper metal layers 16 b, 19 b and solder balls 22 are formed in a lump and then divided into a plurality of Since the semiconductor device is obtained, the manufacturing process can be simplified.

また、ベース板１と共に複数の半導体構成体３を搬送することができるので、これによっても製造工程を簡略化することができる。さらに、ベース板１の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。   Moreover, since the several semiconductor structure 3 can be conveyed with the base plate 1, a manufacturing process can also be simplified by this. Furthermore, if the outer dimensions of the base plate 1 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.

さらに、上記製造方法では、図９に示すように、再配線１０および柱状電極１１を備えたＣＳＰタイプの半導体構成体３を接着層２上に接着しているので、例えば、シリコン基板４上に接続パッド５および絶縁膜６を設けてなる通常の半導体チップを接着層２上に接着して、半導体チップの周囲に設けられた封止膜上等に再配線および柱状電極を形成する場合と比較して、コストを低減することができる。   Furthermore, in the above manufacturing method, as shown in FIG. 9, the CSP type semiconductor structure 3 including the rewiring 10 and the columnar electrode 11 is bonded onto the adhesive layer 2. Compared to the case where a normal semiconductor chip provided with the connection pad 5 and the insulating film 6 is bonded on the adhesive layer 2 to form the rewiring and the columnar electrode on the sealing film provided around the semiconductor chip. Thus, the cost can be reduced.

例えば、切断前のベース板１がシリコンウエハのように一定のサイズのほぼ円形状である場合、接着層２上に接着された半導体チップの周囲に設けられた封止膜上等に再配線および柱状電極を形成すると、処理面積が増大する。換言すれば、低密度処理になるため、一回当たりの処理枚数が低減し、スループットが低下するので、コストアップとなる。   For example, when the base plate 1 before cutting has a substantially circular shape of a certain size like a silicon wafer, the rewiring and the like are performed on the sealing film provided around the semiconductor chip bonded onto the adhesive layer 2 When the columnar electrode is formed, the processing area increases. In other words, since low-density processing is performed, the number of processed sheets per process is reduced and throughput is lowered, resulting in an increase in cost.

これに対し、上記製造方法では、再配線１０および柱状電極１１を備えたＣＳＰタイプの半導体構成体３を接着層２上に接着した後に、ビルドアップしているので、プロセス数は増大するが、柱状電極１１を形成するまでは高密度処理のため、効率が良く、プロセス数の増大を考慮しても、全体の価格を低減することができる。   On the other hand, in the above manufacturing method, since the CSP type semiconductor structure 3 provided with the rewiring 10 and the columnar electrode 11 is adhered on the adhesive layer 2 and built up, the number of processes increases. Since the high-density processing is performed until the columnar electrode 11 is formed, the efficiency is high, and the overall price can be reduced even if the increase in the number of processes is taken into consideration.

なお、上記実施形態においては、半田ボール２２を、半導体構成体３上および絶縁材１３上の全面に対応してマトリクス状に配列されるよう設けているが、半田ボール２２を半導体構成体３の周囲の絶縁材１３上に対応する領域上にのみ設けるようにしてもよい。その場合、半田ボール２２を半導体構成体３の全周囲ではなく、半導体構成体３の４辺の中、１〜３辺の側方のみに設けてもよい。また、このような場合には、絶縁材１３を矩形枠状のものとする必要はなく、半田ボール２２を設ける辺の側方のみに配置されるようにしてもよい。   In the above embodiment, the solder balls 22 are provided so as to be arranged in a matrix corresponding to the entire surface of the semiconductor structure 3 and the insulating material 13. However, the solder balls 22 of the semiconductor structure 3 are provided. You may make it provide only on the area | region corresponding on the surrounding insulating material 13. FIG. In that case, the solder balls 22 may be provided not only on the entire periphery of the semiconductor structure 3 but only on the sides of 1 to 3 of the four sides of the semiconductor structure 3. In such a case, the insulating material 13 does not need to have a rectangular frame shape, and may be disposed only on the side where the solder ball 22 is provided.

（製造方法の他の第１の例）
次に、図１に示す半導体装置の製造方法の他の第１の例について説明する。まず、図１８に示すように、紫外線透過性の透明樹脂板やガラス板等からなる別のベース板４１の上面全体に紫外線硬化型の粘着シート等からなる接着層４２を接着し、接着層４２の上面に上述のベース板２１および接着層２２を接着したものを用意する。 (Another first example of the manufacturing method)
Next, another first example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, as shown in FIG. 18, an adhesive layer 42 made of an ultraviolet curable pressure sensitive adhesive sheet or the like is adhered to the entire upper surface of another base plate 41 made of an ultraviolet transparent transparent resin plate, a glass plate, or the like. Prepared by adhering the base plate 21 and the adhesive layer 22 to the upper surface.

そして、図９〜図１６にそれぞれ示す製造工程を経た後に、図１９に示すように、３層の絶縁膜２０、１７、１４、絶縁材１３、接着層２、ベース板１および接着層４２を切断し、別のベース板４１を切断しない。次に、別のベース板４１の下面側から紫外線を照射し、接着層４２を硬化させる。すると、分断されたベース板１の下面に対する接着層４２による接着性が低下する。そこで、接着層４２上に存在する個片化されたものを１つずつ剥がしてピックアップすると、図１に示す半導体装置が複数個得られる。   Then, after the manufacturing steps shown in FIGS. 9 to 16, as shown in FIG. 19, three layers of insulating films 20, 17, 14, insulating material 13, adhesive layer 2, base plate 1, and adhesive layer 42 are formed. Cut and do not cut another base plate 41. Next, the adhesive layer 42 is cured by irradiating ultraviolet rays from the lower surface side of another base plate 41. Then, the adhesiveness by the adhesive layer 42 with respect to the lower surface of the divided base plate 1 is lowered. Therefore, when the separated pieces existing on the adhesive layer 42 are peeled one by one and picked up, a plurality of semiconductor devices shown in FIG. 1 are obtained.

この製造方法では、図１９に示す状態において、接着層４２上に存在する個片化された半導体装置がバラバラとならないので、専用の半導体装置載置用トレーを用いることなく、そのまま、図示しない回路基板上への実装時に１つずつ剥がしてピックアップすることができる。また、別のベース板４１の上面に残存する接着性が低下した接着層４２を剥離すると、別のベース板４１を再利用することができる。さらに、別のベース板４１の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。   In this manufacturing method, in the state shown in FIG. 19, the separated semiconductor devices existing on the adhesive layer 42 do not fall apart, so that a circuit (not shown) is used as it is without using a dedicated semiconductor device mounting tray. When mounting on a substrate, it can be removed and picked up one by one. Further, when the adhesive layer 42 with reduced adhesion remaining on the upper surface of another base plate 41 is peeled off, the other base plate 41 can be reused. Furthermore, if the outer dimensions of the other base plate 41 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.

なおここで、別のベース板４１として、膨張させることにより半導体装置を取り外す、通常のダイシングテープ等を用いることも可能であり、その場合には、接着層は紫外線硬化型でなくてもよい。また、別のベース板４１を研磨やエッチングにより除去するようにしてもよい。   Here, as another base plate 41, it is also possible to use a normal dicing tape or the like in which the semiconductor device is removed by expansion, and in this case, the adhesive layer may not be an ultraviolet curable type. Further, another base plate 41 may be removed by polishing or etching.

（製造方法の他の第２の例）
次に、図１に示す半導体装置の製造方法の他の第２の例について説明する。この製造方法では、図１１に示す製造工程後に、図２０に示すように、開口部１５を介して露出された柱状電極１１の上面を含む第１の上層絶縁膜１４の上面全体に銅の無電解メッキにより第１の下地金属層１６ａを形成する。次に、第１の下地金属層１６ａをメッキ電流路として銅の電解メッキを行うことにより、第１の下地金属層１６ａの上面全体に第１の上層金属形成用層１６ｃを形成する。次に、第１の上層金属形成用層３９ｃの上面の第１の上層再配線形成領域に対応する部分にレジスト膜４３をパターン形成する。 (Another second example of the manufacturing method)
Next, another second example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this manufacturing method, after the manufacturing process shown in FIG. 11, as shown in FIG. 20, there is no copper on the entire upper surface of the first upper insulating film 14 including the upper surface of the columnar electrode 11 exposed through the opening 15. A first base metal layer 16a is formed by electrolytic plating. Next, the first upper metal layer 16c is formed on the entire upper surface of the first base metal layer 16a by performing copper electroplating using the first base metal layer 16a as a plating current path. Next, a resist film 43 is patterned on a portion corresponding to the first upper layer rewiring formation region on the upper surface of the first upper metal forming layer 39c.

次に、レジスト膜４３をマスクとして第１の上層金属形成用層１６ｃおよび第１の下地金属層１６ａの不要な部分をエッチングして除去すると、図２１に示すように、レジスト膜４３下にのみ第１の上層配線層１６が残存される。この後、レジスト膜４３を剥離する。なお、これと同様の形成方法により、第２の上層再配線１９を形成するようにしてもよい。   Next, when unnecessary portions of the first upper metal forming layer 16c and the first base metal layer 16a are removed by etching using the resist film 43 as a mask, only under the resist film 43, as shown in FIG. The first upper wiring layer 16 remains. Thereafter, the resist film 43 is peeled off. Note that the second upper layer rewiring 19 may be formed by the same formation method.

ところで、図９に示すベース板１あるいは図１９に示す別のベース板４１をトレイ状とすることもできる。つまり、ベース板を、半導体構成体３を配列する領域が周囲より陥没した受け皿のような形状とする。そして、このトレイ状のベース板の半導体構成体３配列領域を囲む周囲の上面にメッキ電流路用金属層を設け、このメッキ電流路用金属層とメッキ電流路用の下地金属層（１６ａ、１９ａ）とを導電部材で接続して、電解メッキを行うようにしてもよい。この場合、トレイの外形サイズを同一としておくことにより、製造する半導体装置のサイズが異なる場合でも、同一の製造装置の使用が可能となり効率的となる。   By the way, the base plate 1 shown in FIG. 9 or another base plate 41 shown in FIG. 19 can be formed in a tray shape. That is, the base plate is shaped like a saucer in which the region where the semiconductor structures 3 are arranged is recessed from the surroundings. Then, a plating current path metal layer is provided on the upper surface surrounding the array region of the semiconductor structure 3 of the tray-like base plate, and this plating current path metal layer and the plating current path base metal layer (16a, 19a). ) May be connected by a conductive member to perform electrolytic plating. In this case, by setting the same outer size of the tray, the same manufacturing apparatus can be used even when the size of the semiconductor device to be manufactured is different, which is efficient.

（製造方法の他の第３の例）
次に、図１に示す半導体装置の製造方法の他の第３の例について説明する。この製造方法では、図２２に示すように、ベース板１上の接着層２上に配置された複数の半導体構成体３上に、繊維やフィラー等の補強材を含む半硬化のエポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂からなるシート状の絶縁材材料１３Ｂを配置する。 (Other third example of manufacturing method)
Next, another third example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this manufacturing method, as shown in FIG. 22, a semi-cured epoxy resin containing a reinforcing material such as fiber or filler is formed on a plurality of semiconductor structures 3 arranged on the adhesive layer 2 on the base plate 1. A sheet-like insulating material 13B made of a thermosetting resin such as BT resin is disposed.

次に、一対の加熱加圧板３５、３６を用いて、半導体構成体３の上面を加圧制限面として加熱加圧することにより、シート状の絶縁材材料１３Ｂ中の熱硬化性樹脂が補強材と共に半導体構成体３間および最外周に配置された半導体構成体３の外側における接着層２上に押し込まれ、図１０に示す場合と同様に、上面が半導体構成体３の上面とほぼ面一となる絶縁材１３が形成される。   Next, the thermosetting resin in the sheet-like insulating material 13 </ b> B together with the reinforcing material is heated and pressed using the pair of heating and pressing plates 35 and 36 with the upper surface of the semiconductor structure 3 as the pressure limiting surface. As shown in FIG. 10, the upper surface is substantially flush with the upper surface of the semiconductor structure 3 by being pushed onto the adhesive layer 2 between the semiconductor structures 3 and outside the semiconductor structure 3 disposed on the outermost periphery. An insulating material 13 is formed.

（製造方法の他の第４の例）
次に、図１に示す半導体装置の製造方法の他の第４の例について説明する。この製造方法では、図９に示す製造工程後に、図２３に示すように、複数の半導体構成体３の上面および絶縁材材料１３Ａの上面に、エポキシ系樹脂やカルド樹脂等の感光性樹脂からなるシート状の第１の上層絶縁膜材料１４Ａをラミネータ等を用いて仮接着する。この場合、シート状の第１の上層絶縁膜材料１４Ａを形成する感光性樹脂としては、流動性の比較的低いものが好ましい。 (Other Fourth Example of Manufacturing Method)
Next, another fourth example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this manufacturing method, after the manufacturing process shown in FIG. 9, as shown in FIG. 23, the upper surface of the plurality of semiconductor structures 3 and the upper surface of the insulating material 13 </ b> A are made of a photosensitive resin such as an epoxy resin or a cardo resin. The sheet-like first upper insulating film material 14A is temporarily bonded using a laminator or the like. In this case, as the photosensitive resin for forming the sheet-like first upper insulating film material 14A, one having relatively low fluidity is preferable.

次に、光照射により、第１の上層絶縁膜材料１４Ａを仮硬化させる。この仮硬化は、次の加熱加圧工程において、絶縁材材料１３Ａ中の熱硬化性樹脂が半導体構成体３上に流出しないようにするとともに、絶縁材材料１３Ａ中の熱硬化性樹脂と第１の上層絶縁膜材料１４Ａを形成する感光性樹脂とが混ざり合わないようにするためである。   Next, the first upper insulating film material 14A is temporarily cured by light irradiation. This temporary curing prevents the thermosetting resin in the insulating material 13A from flowing out onto the semiconductor structure 3 and the first thermosetting resin in the insulating material 13A and the first heating and pressurizing step. This is to prevent mixing with the photosensitive resin forming the upper insulating film material 14A.

次に、図２４に示すように、一対の加熱加圧板３５、３６を用いて、形成すべき第１の上層絶縁膜１４の上面を加圧制限面として加熱加圧することにより、半導体構成体３間および最外周に配置された半導体構成体３の外側における接着層２の上面に、絶縁材１３をその上面が半導体構成体３の上面とほぼ面一となるように形成し、且つ、ほぼ面一となった半導体構成体３および絶縁材１３の上面全体に第１の上層絶縁膜１４を形成する。   Next, as shown in FIG. 24, by using a pair of heating and pressing plates 35 and 36, the upper surface of the first upper insulating film 14 to be formed is heated and pressed to form a pressure limiting surface, thereby forming the semiconductor structure 3. An insulating material 13 is formed on the upper surface of the adhesive layer 2 on the outer side of the semiconductor structure 3 disposed between and at the outermost periphery so that the upper surface is substantially flush with the upper surface of the semiconductor structure 3 A first upper-layer insulating film 14 is formed on the entire upper surface of the semiconductor structure 3 and the insulating material 13 that have become one.

この場合の加熱加圧処理は、感光性樹脂からなる第１の上層絶縁膜材料１４Ａを介して半導体構成３を加圧するため、半導体構成体３にかかるストレスを軽減することができる。次に、感光性樹脂からなる第１の上層絶縁膜１４には仮硬化のための光がすでに照射されているため、フォトリソグラフィ法ではなく、レーザ加工により、柱状電極１１の上面中央部に対応する部分における第１の上層絶縁膜１４に開口部１５（図１１参照）を形成する。   In this case, the heat and pressure treatment pressurizes the semiconductor structure 3 through the first upper insulating film material 14A made of a photosensitive resin, so that stress applied to the semiconductor structure 3 can be reduced. Next, the first upper-layer insulating film 14 made of a photosensitive resin has already been irradiated with light for pre-curing, so that it corresponds to the center of the upper surface of the columnar electrode 11 by laser processing rather than photolithography. An opening 15 (see FIG. 11) is formed in the first upper insulating film 14 in the portion to be formed.

（第２実施形態）
図９に示す製造工程において、接着層２を半導体構成体３のシリコン基板４の下面のそれぞれ設け、これらの接着層２をベース板１の上面の各所定の箇所に接着した場合には、図１０に示す製造工程において、絶縁材１３の下面がベース板１の上面に接合するため、図２５に示すこの発明の第２実施形態としての半導体装置が得られる。 (Second Embodiment)
In the manufacturing process shown in FIG. 9, when the adhesive layer 2 is provided on the lower surface of the silicon substrate 4 of the semiconductor structure 3 and the adhesive layer 2 is bonded to each predetermined location on the upper surface of the base plate 1, In the manufacturing process shown in FIG. 10, since the lower surface of the insulating material 13 is bonded to the upper surface of the base plate 1, the semiconductor device as the second embodiment of the present invention shown in FIG. 25 is obtained.

このようにして得られた半導体装置では、例えば、シリコン基板４の下面が接着層２を介してベース板１の上面に接着されているほかに、シリコン基板４の側面が絶縁材１３を介してベース板１の上面に接合されているので、半導体構成体３のベース板１に対する接合強度をある程度強くすることができる。   In the semiconductor device thus obtained, for example, the lower surface of the silicon substrate 4 is bonded to the upper surface of the base plate 1 via the adhesive layer 2, and the side surface of the silicon substrate 4 is interposed via the insulating material 13. Since it is bonded to the upper surface of the base plate 1, the bonding strength of the semiconductor structure 3 to the base plate 1 can be increased to some extent.

（第３、第４実施形態）
図２６はこの発明の第３実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、ベース板１および接着層２を備えていないことである。 (Third and fourth embodiments)
FIG. 26 shows a sectional view of a semiconductor device as a third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the base plate 1 and the adhesive layer 2 are not provided.

この第３実施形態の半導体装置を製造する場合には、例えば図１６に示すように、半田ボール２２を形成した後に、ベース板１および接着層２を研磨やエッチング等により除去し、次いで互いに隣接する半導体構成体３間において、３層の絶縁膜２０、１７、１４および絶縁材１３を切断すると、図２６に示す半導体装置が複数個得られる。このようにして得られた半導体装置では、ベース板１および接着層２を備えていないので、その分だけ、薄型化することができる。   When manufacturing the semiconductor device of the third embodiment, for example, as shown in FIG. 16, after forming the solder balls 22, the base plate 1 and the adhesive layer 2 are removed by polishing, etching, or the like, and then adjacent to each other. When the three insulating films 20, 17, and 14 and the insulating material 13 are cut between the semiconductor structures 3 to be manufactured, a plurality of semiconductor devices shown in FIG. 26 are obtained. Since the semiconductor device thus obtained does not include the base plate 1 and the adhesive layer 2, the thickness can be reduced accordingly.

また、ベース板１および接着層２を研磨やエッチング等により除去した後に、シリコン基板４および絶縁材１３の下面側を適宜に研磨し、次いで互いに隣接する半導体構成体３間において、３層の絶縁膜２０、１７、１４および絶縁材１３を切断すると、図２７に示すこの発明の第４実施形態としての半導体装置が複数個得られる。このようにして得られた半導体装置では、さらに薄型化することができる。   In addition, after removing the base plate 1 and the adhesive layer 2 by polishing, etching, or the like, the lower surface side of the silicon substrate 4 and the insulating material 13 is appropriately polished, and then three layers of insulation are formed between the adjacent semiconductor structures 3. When the films 20, 17, 14 and the insulating material 13 are cut, a plurality of semiconductor devices as the fourth embodiment of the present invention shown in FIG. 27 are obtained. The semiconductor device thus obtained can be further reduced in thickness.

なお、半田ボール２２を形成する前に、ベース板１および接着層２を研磨やエッチング等により除去し（必要に応じてさらにシリコン基板４および絶縁材１３の下面側を適宜に研磨し）、次いで半田ボール２２を形成し、次いで互いに隣接する半導体構成体３間において、３層の絶縁膜２０、１７、１４および絶縁材１３を切断するようにしてもよい。   Before forming the solder balls 22, the base plate 1 and the adhesive layer 2 are removed by polishing, etching, or the like (further, the lower surface side of the silicon substrate 4 and the insulating material 13 is appropriately polished if necessary), and then The solder balls 22 may be formed, and then the three layers of the insulating films 20, 17, 14 and the insulating material 13 may be cut between the semiconductor structures 3 adjacent to each other.

（第５実施形態）
図２８はこの発明の第５実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、接着層２の下面に放熱用の金属層４４が接着されていることである。金属層４４は、厚さ数十μｍの銅箔等からなっている。 (Fifth embodiment)
FIG. 28 shows a sectional view of a semiconductor device as a fifth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that a metal layer 44 for heat dissipation is bonded to the lower surface of the adhesive layer 2. The metal layer 44 is made of a copper foil having a thickness of several tens of μm.

この第５実施形態の半導体装置を製造する場合には、例えば図１６に示すように、半田ボール２２を形成した後に、ベース板１を研磨やエッチング等により除去し、次いで接着層２の下面全体に金属層４４を接着し、次いで互いに隣接する半導体構成体３間において、３層の絶縁膜２０、１７、１４、絶縁材１３、接着層２および金属層４４を切断すると、図２８に示す半導体装置が複数個得られる。   In the case of manufacturing the semiconductor device of the fifth embodiment, for example, as shown in FIG. 16, after forming the solder balls 22, the base plate 1 is removed by polishing or etching, and then the entire lower surface of the adhesive layer 2 is formed. 28, and then the three insulating films 20, 17, 14, the insulating material 13, the adhesive layer 2 and the metal layer 44 are cut between the adjacent semiconductor structures 3, and the semiconductor shown in FIG. Multiple devices are obtained.

なお、接着層２も研磨やエッチング等により除去し（必要に応じてさらにシリコン基板４および絶縁材１３の下面側を適宜に研磨し）、シリコン基板４および絶縁材１３の下面に新たな接着層を介して金属層４４を接着するようにしてもよい。   The adhesive layer 2 is also removed by polishing, etching, or the like (further, if necessary, the lower surface side of the silicon substrate 4 and the insulating material 13 is appropriately polished), and a new adhesive layer is formed on the lower surfaces of the silicon substrate 4 and the insulating material 13. You may make it adhere | attach the metal layer 44 through this.

（第６実施形態）
図２９はこの発明の第６実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と大きく異なる点は、第１の上層絶縁膜１４を絶縁材１３と同一の材料によって形成し、半導体構成体３と絶縁材１３との間に隙間２３を形成し、この隙間２３に樹脂からなる絶縁膜２４を設けたことである。 (Sixth embodiment)
FIG. 29 is a sectional view of a semiconductor device according to the sixth embodiment of the present invention. This semiconductor device is greatly different from the semiconductor device shown in FIG. 1 in that the first upper insulating film 14 is formed of the same material as the insulating material 13, and a gap 23 is formed between the semiconductor structure 3 and the insulating material 13. And an insulating film 24 made of resin is provided in the gap 23.

次に、この半導体装置の製造方法の一例について説明する。まず、図３０に示すように、ベース板１上に設けられた接着層２の上面の所定の箇所に格子状の絶縁材１３の下面を接着する。格子状の絶縁材１３は、繊維やフィラー等の補強材を含む熱硬化性樹脂からなるシート状の絶縁材材料（例えば、プリプレグ）に型抜き加工やエッチング等により複数の矩形形状の開口部２５を形成することにより得られる。開口部２５のサイズは半導体構成体３のサイズよりもやや大きくなっている。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 30, the lower surface of the lattice-shaped insulating material 13 is bonded to a predetermined location on the upper surface of the adhesive layer 2 provided on the base plate 1. The grid-like insulating material 13 is formed by a plurality of rectangular openings 25 formed by punching or etching a sheet-like insulating material (for example, prepreg) made of a thermosetting resin including a reinforcing material such as fiber or filler. Is obtained. The size of the opening 25 is slightly larger than the size of the semiconductor structure 3.

次に、格子状の絶縁材１３の各開口部２５内における接着層２の上面中央部にそれぞれ半導体構成体３のシリコン基板４の下面を接着する。ここで、格子状の絶縁材１３の厚さは半導体構成体３の厚さよりもやや薄くなっている。このため、格子状の絶縁材１３の上面は半導体構成体３の上面よりもやや下方に配置されている。また、絶縁材１３の開口部２５のサイズは半導体構成体３のサイズよりもやや大きくなっているため、絶縁材１３と半導体構成体３との間には隙間２３が形成されている。   Next, the lower surface of the silicon substrate 4 of the semiconductor structure 3 is bonded to the center of the upper surface of the adhesive layer 2 in each opening 25 of the lattice-like insulating material 13. Here, the thickness of the lattice-like insulating material 13 is slightly thinner than the thickness of the semiconductor structure 3. For this reason, the upper surface of the lattice-like insulating material 13 is disposed slightly below the upper surface of the semiconductor structure 3. In addition, since the size of the opening 25 of the insulating material 13 is slightly larger than the size of the semiconductor structure 3, a gap 23 is formed between the insulating material 13 and the semiconductor structure 3.

次に、図３１に示すように、複数の半導体構成体３の上面に、繊維やフィラー等の補強材を含む半硬化の熱硬化性樹脂からなるシート状の第１の上層絶縁膜材料（例えば、プリプレグ）１４Ｂをただ単に載置する。ここで、絶縁材１３と半導体構成体３との間の隙間２３の間隔は、第１の上層絶縁膜材料１４Ｂ中の繊維やフィラー等からなる補強材の直径よりも小さくなっている。   Next, as shown in FIG. 31, a sheet-like first upper insulating film material (for example, made of a semi-cured thermosetting resin containing a reinforcing material such as a fiber or a filler is provided on the upper surface of the plurality of semiconductor structures 3 (for example, Prepreg) 14B is simply placed. Here, the interval of the gap 23 between the insulating material 13 and the semiconductor structure 3 is smaller than the diameter of the reinforcing material made of fibers, filler, or the like in the first upper insulating film material 14B.

次に、一対の加熱加圧板３５、３６を用いて加熱加圧する。すると、第１の上層絶縁膜材料１４Ｂ中の繊維やフィラー等からなる補強材の直径は絶縁材１３と半導体構成体３との間の隙間２３の間隔よりも大きくなっているため、図３２に示すように、第１の上層絶縁膜材料１４Ｂ中の熱硬化性樹脂のみが絶縁材１３と半導体構成体３との間の隙間２３に押し込まれて絶縁膜２４が形成されるとともに、この絶縁膜２４、絶縁材１３および半導体構成体３の上面に、補強材を含む熱硬化性樹脂からなる第１の上層絶縁膜材料１４が形成される。   Next, heat and pressure are applied using a pair of heat and pressure plates 35 and 36. Then, since the diameter of the reinforcing material made of fibers, fillers, etc. in the first upper insulating film material 14B is larger than the gap 23 between the insulating material 13 and the semiconductor structure 3, FIG. As shown, only the thermosetting resin in the first upper insulating film material 14B is pushed into the gap 23 between the insulating material 13 and the semiconductor structure 3 to form an insulating film 24, and this insulating film 24, a first upper insulating film material 14 made of a thermosetting resin including a reinforcing material is formed on the top surfaces of the insulating material 13 and the semiconductor structure 3.

この場合、半導体構成体３の上面よりも第１の上層絶縁膜材料１４中の補強材の直径だけ高い仮想面を加圧制限面とすると、半導体構成体３上における第１の上層絶縁膜１４の厚さはその中の補強材の直径と同じとなる。ここで、絶縁材１３の上面を半導体構成体３の上面よりもやや下方に配置するのは、絶縁材１３の上面よりも第１の上層絶縁膜材料１４中の補強材の直径だけ高い仮想面が加圧制限面とならないようにするためである。また、第１の上層絶縁膜材料１４の上面は、上側の加熱加圧板３６の下面によって押さえ付けられるため、平坦面となる。したがって、第１の上層絶縁膜材料１４の上面を平坦化するための研磨工程は不要である。   In this case, if a virtual surface that is higher than the upper surface of the semiconductor structure 3 by the diameter of the reinforcing material in the first upper insulating film material 14 is a pressure limiting surface, the first upper insulating film 14 on the semiconductor structure 3 is used. The thickness of is the same as the diameter of the reinforcing material therein. Here, the reason why the upper surface of the insulating material 13 is disposed slightly below the upper surface of the semiconductor structure 3 is that the virtual surface is higher than the upper surface of the insulating material 13 by the diameter of the reinforcing material in the first upper insulating film material 14. This is to prevent the pressure from becoming a pressure limiting surface. Further, the upper surface of the first upper-layer insulating film material 14 is pressed by the lower surface of the upper heating / pressurizing plate 36 and thus becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the first upper insulating film material 14 is not necessary.

次に、図３３に示すように、第１の上層絶縁膜材料１４が補強材を含むため、レーザ加工により、柱状電極１１の上面中央部に対応する部分における第１の上層絶縁膜材料１４に開口部１５を形成する。以下、例えば、図１２〜図１７にそれぞれ示す製造工程を経ると、図２９に示す半導体装置が複数個得られる。   Next, as shown in FIG. 33, since the first upper insulating film material 14 includes a reinforcing material, the first upper insulating film material 14 in the portion corresponding to the center of the upper surface of the columnar electrode 11 is formed by laser processing. Opening 15 is formed. Hereinafter, for example, a plurality of semiconductor devices shown in FIG. 29 are obtained through the manufacturing steps shown in FIGS.

（第７実施形態）
例えば、図１に示す場合には、半導体構成体３上における第３の上層絶縁膜２０上にも半田ボール２２を配置しているが、これに限定されるものではない。例えば、図３４に示すこの発明の第７実施形態のように、絶縁材１３上における第３の上層絶縁膜２０上にのみ半田ボール２２を配置し、半導体構成体３上における第３の上層絶縁膜２０上に、シリコン基板４上の集積回路に光が入射するのを防止するための遮光性金属からなる遮光膜２６を設けるようにしてもよい。遮光膜２６は、金属シートであってもよく、スパッタや無電解メッキ等によって形成してもよい。 (Seventh embodiment)
For example, in the case shown in FIG. 1, the solder balls 22 are also disposed on the third upper insulating film 20 on the semiconductor structure 3, but the present invention is not limited to this. For example, as in the seventh embodiment of the present invention shown in FIG. 34, the solder ball 22 is disposed only on the third upper insulating film 20 on the insulating material 13, and the third upper insulating layer on the semiconductor structure 3. A light shielding film 26 made of a light shielding metal for preventing light from entering the integrated circuit on the silicon substrate 4 may be provided on the film 20. The light shielding film 26 may be a metal sheet or may be formed by sputtering, electroless plating, or the like.

（第８実施形態）
図３５はこの発明の第８実施形態としての半導体装置の断面図を示したものである。この半導体装置では、半導体構成体３として、図１に示す半導体構成体３と比較すると、柱状電極１１および封止膜１２を備えていないものを用いている。この場合、例えば、図２３および図２４にそれぞれ示すような製造工程を経ると、半導体構成体３の周囲における接着層２の上面に方形枠状の絶縁材１３が形成されるとともに、再配線１０を含む保護膜８および絶縁材１３の上面に第１の上層絶縁膜１４が形成される。そして、レーザ加工により、再配線１０の接続パッド部に対応する部分における第１の上層絶縁膜１４に開口部１５を形成し、この開口部１５を介して、再配線１０の接続パッド部に第１の上層再配線１６を接続する。 (Eighth embodiment)
FIG. 35 shows a sectional view of a semiconductor device as an eighth embodiment of the present invention. In this semiconductor device, as the semiconductor structure 3, a semiconductor structure 3 that does not include the columnar electrode 11 and the sealing film 12 is used as compared with the semiconductor structure 3 shown in FIG. 1. In this case, for example, after a manufacturing process as shown in FIGS. 23 and 24, a rectangular frame-shaped insulating material 13 is formed on the upper surface of the adhesive layer 2 around the semiconductor structure 3, and the rewiring 10 A first upper-layer insulating film 14 is formed on the upper surface of the protective film 8 and the insulating material 13. Then, an opening 15 is formed in the first upper insulating film 14 in a portion corresponding to the connection pad portion of the rewiring 10 by laser processing, and the opening 15 is formed in the connection pad portion of the rewiring 10 via the opening 15. 1 upper layer rewiring 16 is connected.

ところで、この場合の半導体構成体３は柱状電極１１および封止膜１２を備えていないが、例えば図２３を参照して説明すると、加熱加圧処理時に、感光性樹脂からなる第１の上層絶縁膜材料１４Ａを介して加圧されるため、半導体構成体３にかかるストレスが軽減され、別に支障はない。   By the way, although the semiconductor structure 3 in this case is not provided with the columnar electrode 11 and the sealing film 12, when it demonstrates with reference to FIG. 23, for example, the 1st upper-layer insulation which consists of photosensitive resin at the time of a heat pressurization process Since the pressure is applied through the film material 14A, the stress applied to the semiconductor structure 3 is reduced, and there is no problem.

（第９実施形態）
例えば、図１７に示す場合には、互いに隣接する半導体構成体３間において切断したが、これに限らず、２個またはそれ以上の半導体構成体３を１組として切断し、例えば、図３６に示すこの発明の第９実施形態のように、３個の半導体構成体３を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、３個で１組の半導体構成体３は同種、異種のいずれであってもよい。 (Ninth embodiment)
For example, in the case shown in FIG. 17, the semiconductor structures 3 adjacent to each other are cut, but not limited to this, two or more semiconductor structures 3 are cut as one set. As shown in the ninth embodiment of the present invention, the three semiconductor structures 3 may be cut as one set to obtain a multichip module type semiconductor device. In this case, the set of three semiconductor structures 3 may be the same type or different types.

（その他の実施形態）
上記各実施形態では、絶縁材１３を、補強材を含む熱硬化性樹脂によって形成した場合について説明したが、これに限らず、熱硬化性樹脂のみによって形成するようにしてもよく、また液晶ポリマーやＰＥＥＴ（ポリエーテルケトン）等の熱可塑性樹脂のみによって形成するようにしてもよい。 (Other embodiments)
In each of the above embodiments, the case where the insulating material 13 is formed of a thermosetting resin including a reinforcing material has been described. However, the invention is not limited thereto, and the insulating material 13 may be formed of only a thermosetting resin, or a liquid crystal polymer. Alternatively, it may be formed of only a thermoplastic resin such as PEET (polyether ketone).

絶縁材１３を熱可塑性樹脂のみによって形成する場合には、例えば、図９において符号１３Ａで示すように、液状の熱可塑性樹脂をスクリーン印刷法により印刷するようにしてもよい。また、例えば、図３７において符号１３Ｃで示すように、半導体構成体３を覆うように、液状の熱可塑性樹脂を塗布法により塗布し、半導体構成体３の上面を加圧制限面として加熱加圧して、半導体構成体３間等に絶縁材１３を形成するようにしてもよい。   When the insulating material 13 is formed of only a thermoplastic resin, for example, as shown by reference numeral 13A in FIG. 9, a liquid thermoplastic resin may be printed by a screen printing method. Further, for example, as shown by reference numeral 13C in FIG. 37, a liquid thermoplastic resin is applied by a coating method so as to cover the semiconductor structure 3, and the upper surface of the semiconductor structure 3 is heated and pressurized using the pressure limiting surface. Thus, the insulating material 13 may be formed between the semiconductor structural bodies 3 or the like.

例えば、図１に示す場合には、半導体構成体３および絶縁材１３の上面に設けられた第１の上層絶縁膜１４の上面に第１の上層再配線１６を設けているが、これに限らず、第１の上層絶縁膜１４を設けずに、半導体構成体３および絶縁材１３の上面に上層再配線１６を設けるようにしてもよい。   For example, in the case shown in FIG. 1, the first upper layer rewiring 16 is provided on the upper surface of the first upper insulating film 14 provided on the upper surfaces of the semiconductor structure 3 and the insulating material 13, but the present invention is not limited to this. Alternatively, the upper layer rewiring 16 may be provided on the upper surfaces of the semiconductor structure 3 and the insulating material 13 without providing the first upper layer insulating film 14.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図３に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図４に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図５に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図６に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図７に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図８に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図９に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１０に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１１に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１２に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１３に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１４に続く製造工程の断面図。FIG. 15 is a cross-sectional view of the manufacturing process following FIG. 14. 図１５に続く製造工程の断面図。FIG. 16 is a cross-sectional view of the manufacturing process following FIG. 15. 図１６に続く製造工程の断面図。FIG. 17 is a cross-sectional view of the manufacturing process following FIG. 16. 図１に示す半導体装置の製造方法の他の第１の例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in the other 1st example of the manufacturing method of the semiconductor device shown in FIG. 同他の第１の例において、所定の製造工程の断面図。Sectional drawing of a predetermined manufacturing process in the 1st example of others. 図１に示す半導体装置の製造方法の他の第２の例において、所定の製造工程の断面図。Sectional drawing of a predetermined manufacturing process in the other 2nd example of the manufacturing method of the semiconductor device shown in FIG. 図２０に続く製造工程の断面図。FIG. 21 is a cross-sectional view of the manufacturing process following FIG. 20. 図１に示す半導体装置の製造方法の他の第３の例において、所定の製造工程の断面図。Sectional drawing of a predetermined | prescribed manufacturing process in the other 3rd example of the manufacturing method of the semiconductor device shown in FIG. 図１に示す半導体装置の製造方法の他の第２の例において、所定の製造工程の断面図。Sectional drawing of a predetermined manufacturing process in the other 2nd example of the manufacturing method of the semiconductor device shown in FIG. 図２３に続く製造工程の断面図。FIG. 24 is a cross-sectional view of the manufacturing process following FIG. 23. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention. この発明の第４実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 4th Embodiment of this invention. この発明の第５実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 5th Embodiment of this invention. この発明の第６実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 6th Embodiment of this invention. 図２９に示す半導体装置の製造方法の一例において、所定の製造工程の断面図。FIG. 30 is a cross-sectional view of a predetermined manufacturing process in the example of the method for manufacturing the semiconductor device shown in FIG. 29. 図３０に続く製造工程の断面図。FIG. 31 is a cross-sectional view of the manufacturing process following FIG. 30. 図３１に続く製造工程の断面図。FIG. 32 is a cross-sectional view of the manufacturing process following FIG. 31. 図３２に続く製造工程の断面図。FIG. 33 is a cross-sectional view of the manufacturing process following FIG. 32. この発明の第７実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 7th Embodiment of this invention. この発明の第８実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 8th Embodiment of this invention. この発明の第９実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 9th Embodiment of this invention. この発明のその他の実施形態としての半導体装置の製造方法の一例を説明するために示す断面図。Sectional drawing shown in order to demonstrate an example of the manufacturing method of the semiconductor device as other embodiment of this invention.

符号の説明Explanation of symbols

１ ベース板
２ 接着層
３ 半導体構成体
４ シリコン基板
５ 接続パッド
１０ 再配線
１１ 柱状電極
１２ 封止膜
１３ 絶縁材
１４ 第１の上層絶縁膜
１６ 第１の上層再配線
１７ 第２の上層絶縁膜
１９ 第２の上層再配線
２０ 第３の上層絶縁膜
２２ 半田ボール DESCRIPTION OF SYMBOLS 1 Base board 2 Adhesion layer 3 Semiconductor structure 4 Silicon substrate 5 Connection pad 10 Rewiring 11 Columnar electrode 12 Sealing film 13 Insulating material 14 First upper layer insulating film 16 First upper layer rewiring 17 Second upper layer insulating film 19 Second upper layer rewiring 20 Third upper layer insulating film 22 Solder ball

Claims (22)

ベース板上に、各々が上面に複数の外部接続部を有する複数の半導体構成体および隣接する前記半導体構成体間に絶縁材を配置し、少なくともいずれかの前記外部接続部に接続される接続パッド部を前記絶縁材上に設け、前記半導体構成体間における前記絶縁材を切断して少なくともいずれかの前記接続パッド部が前記半導体構成体の側方に設けられた前記絶縁材上に配置された半導体装置を複数個得る半導体装置の製造方法であって、前記半導体構成体間における前記絶縁材を切断する前に前記ベース板上に配置された前記絶縁材を加熱または加圧して平坦化を行う処理を含むことを特徴とする半導体装置の製造方法。   On the base plate, a plurality of semiconductor structures each having a plurality of external connection portions on the upper surface, and a connection pad connected to at least one of the external connection portions by disposing an insulating material between the adjacent semiconductor structures A portion is provided on the insulating material, and the insulating material between the semiconductor structures is cut so that at least one of the connection pad portions is disposed on the insulating material provided on the side of the semiconductor structure. A semiconductor device manufacturing method for obtaining a plurality of semiconductor devices, wherein the insulating material disposed on the base plate is flattened by heating or pressurizing before cutting the insulating material between the semiconductor structures. The manufacturing method of the semiconductor device characterized by including a process. ベース板上に、各々が、半導体基板の上面に設けられた複数の再配線、前記各再配線の一端部上に形成された柱状電極および前記半田謡基板上において前記柱状電極間に設けられ、その上面が前記柱状電極の上面と同一平面に位置する封止膜を有する複数の半導体構成体および隣接する前記半導体構成体間に絶縁材を配置する工程と、
前記半導体構成体の外部接続部を除く上面および前記絶縁材の上面に絶縁膜を形成する工程と、
前記絶縁膜上に、接続パッド部を有し且ついずれかの前記半導体構成体の対応する前記外部接続部に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッド部が前記絶縁材上に配置されるように形成する工程と、
前記半導体構成体間における前記絶縁材を切断して少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体の側方に設けられた前記絶縁材上に配置された半導体装置を複数個得る工程とを有し、
前記絶縁材配置工程と前記絶縁膜形成工程とのうちの少なくともいずれかの工程で加熱処理または加圧処理を行なうことを特徴とする半導体装置の製造方法。 On the base plate, each is provided between the columnar electrodes on the plurality of rewirings provided on the upper surface of the semiconductor substrate, the columnar electrodes formed on one end of each of the rewirings, and the solder iron substrate, A step of disposing an insulating material between a plurality of semiconductor components having a sealing film whose upper surface is located in the same plane as the upper surface of the columnar electrode, and the adjacent semiconductor components;
Forming an insulating film on an upper surface of the semiconductor structure excluding an external connection portion and an upper surface of the insulating material;
An upper layer rewiring having a connection pad portion on the insulating film and connected to the corresponding external connection portion of any one of the semiconductor structures, and at least one of the upper layer rewiring connection pad portions is the Forming to be disposed on an insulating material;
A plurality of semiconductor devices in which the insulating material between the semiconductor structures is cut and at least one of the connection pads of the upper layer rewiring is disposed on the insulating material provided on the side of the semiconductor structure. A process of obtaining
A method for manufacturing a semiconductor device, wherein heat treatment or pressure treatment is performed in at least one of the insulating material arranging step and the insulating film forming step. 請求項１または２に記載の発明において、前記絶縁材切断工程は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating material cutting step is performed so that a plurality of the semiconductor structural bodies are included. 請求項１または２に記載の発明において、前記絶縁材は補強材を含む樹脂からなることを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating material is made of a resin including a reinforcing material. 請求項１または２に記載の発明において、前記絶縁材は樹脂からなることを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating material is made of a resin. 請求項１または２に記載の発明において、前記絶縁材配置工程において、前記ベース板上において前記半導体構成体間に配置された絶縁材材料を加熱加圧処理して、上面が前記半導体構成体の上面とほぼ面一となる前記絶縁材を形成することを特徴とする半導体装置の製造方法。   3. The invention according to claim 1, wherein, in the insulating material arranging step, an insulating material disposed between the semiconductor structural bodies on the base plate is subjected to heat and pressure treatment, and an upper surface of the semiconductor structural body is formed. A method for manufacturing a semiconductor device, comprising forming the insulating material substantially flush with an upper surface. 請求項１または２に記載の発明において、前記絶縁材配置工程において、前記ベース板上に配置された前記複数の半導体構成体上に配置されたシート状の絶縁材材料を加熱加圧処理して、上面が前記半導体構成体の上面とほぼ面一となる前記絶縁材を形成することを特徴とする半導体装置の製造方法。   3. The invention according to claim 1, wherein in the insulating material arranging step, a sheet-like insulating material material arranged on the plurality of semiconductor structures arranged on the base plate is subjected to heat and pressure treatment. A method of manufacturing a semiconductor device, comprising: forming the insulating material whose upper surface is substantially flush with the upper surface of the semiconductor structure. 請求項６または７に記載の発明において、前記加熱加圧処理は、前記半導体構成体の上面を加圧制限面として行なうことを特徴とする半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 6, wherein the heat and pressure treatment is performed using the upper surface of the semiconductor structure as a pressure limiting surface. 請求項７に記載の発明において、前記加熱加圧処理後に、前記半導体構成体の上面側および前記絶縁材の上面側をバフまたはエンドレス研磨ベルトを用いて研磨することを特徴とする半導体装置の製造方法。   8. The semiconductor device according to claim 7, wherein the upper surface side of the semiconductor structure and the upper surface side of the insulating material are polished using a buff or an endless polishing belt after the heat and pressure treatment. Method. 請求項１または２に記載の発明において、前記接続パッド部上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a solder ball on the connection pad portion. 請求項１または２に記載の発明において、前記絶縁材切断工程は前記絶縁材を切断するとともに前記ベース板を切断し、前記半導体装置としてベース板を備えたものを得ることを特徴とする半導体装置の製造方法。   3. The semiconductor device according to claim 1, wherein the insulating material cutting step cuts the insulating material and cuts the base plate to obtain the semiconductor device having a base plate. Manufacturing method. 請求項１１に記載の発明において、切断前の前記ベース板下に別のベース板を配置し、前記ベース板を切断した後に、前記別のベース板を取り除く工程を有することを特徴とする半導体装置の製造方法。   12. The semiconductor device according to claim 11, further comprising a step of disposing another base plate under the base plate before cutting, and removing the another base plate after cutting the base plate. Manufacturing method. 請求項２に記載の発明において、前記絶縁材配置工程および前記絶縁膜形成工程において、前記ベース板上において前記半導体構成体間に配置された絶縁材材料およびその上に配置されたシート状の絶縁膜材料を加熱加圧処理して、上面が前記半導体構成体の上面とほぼ面一となる前記絶縁材を形成するとともに、その上に前記絶縁膜を形成することを特徴とする半導体装置の製造方法。   3. The invention according to claim 2, wherein, in the insulating material arranging step and the insulating film forming step, an insulating material material arranged between the semiconductor structural bodies on the base plate and a sheet-like insulating material arranged thereon. A film material is heated and pressed to form the insulating material whose upper surface is substantially flush with the upper surface of the semiconductor structure, and the insulating film is formed thereon. Method. 請求項１３に記載の発明において、前記シート状の絶縁膜材料は樹脂からなることを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, wherein the sheet-like insulating film material is made of a resin. 請求項１４に記載の発明において、前記シート状の絶縁膜材料を配置した後に、該シート状の絶縁膜材料を仮硬化させることを特徴とする半導体装置の製造方法。   15. The method of manufacturing a semiconductor device according to claim 14, wherein the sheet-like insulating film material is temporarily cured after the sheet-like insulating film material is disposed. 請求項１４に記載の発明において、前記加熱加圧処理は、形成すべき前記絶縁膜の上面を加圧制限面として行なうことを特徴とする半導体装置の製造方法。   15. The method of manufacturing a semiconductor device according to claim 14, wherein the heat and pressure treatment is performed using the upper surface of the insulating film to be formed as a pressure limiting surface. 請求項２に記載の発明において、前記絶縁膜形成工程において、前記ベース板上において前記半導体構成体間に隙間をおいて配置された前記絶縁材上に配置されたシート状の絶縁膜材料を加熱加圧処理して、前記絶縁膜を形成するとともに、前記絶縁膜材料の一部によって前記隙間に絶縁膜を形成することを特徴とする半導体装置の製造方法。   3. The invention according to claim 2, wherein in the insulating film forming step, the sheet-like insulating film material disposed on the insulating material disposed with a gap between the semiconductor constituents is heated on the base plate. A method of manufacturing a semiconductor device, wherein the insulating film is formed by pressure treatment, and the insulating film is formed in the gap by a part of the insulating film material. 請求項１７に記載の発明において、前記絶縁材の厚さは前記半導体構成体の厚さよりもやや薄くなっており、前記絶縁材の上面を前記半導体構成体の上面よりもやや低い位置に配置することを特徴とする半導体装置の製造方法。   The thickness of the insulating material is slightly thinner than the thickness of the semiconductor structure, and the upper surface of the insulating material is disposed at a position slightly lower than the upper surface of the semiconductor structure. A method for manufacturing a semiconductor device. 請求項１８に記載の発明において、前記シート状の絶縁膜材料は補強材を含む樹脂からなることを特徴とする半導体装置の製造方法。   19. The method of manufacturing a semiconductor device according to claim 18, wherein the sheet-like insulating film material is made of a resin containing a reinforcing material. 請求項２に記載の発明において、前記加熱加圧処理は、前記半導体構成体の上面よりも前記補強材の直径だけ高い仮想面を加圧制限面として行なうことを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 2, wherein the heat and pressure treatment is performed by using a virtual surface that is higher than the upper surface of the semiconductor structure by the diameter of the reinforcing material as a pressure limiting surface. . 請求項２に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の外部接続部とそれに対応する前記上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とする半導体装置の製造方法。   The invention according to claim 2, wherein the insulating film has a plurality of layers, and a plurality of sets of interlayer rewirings connecting the external connection portions of the respective semiconductor structures and the corresponding upper layer rewirings between the insulating films. A method for manufacturing a semiconductor device, comprising the step of forming. 請求項２に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線の接続パッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。   3. The semiconductor device according to claim 2, further comprising a step of forming an uppermost layer insulating film on a portion of the upper surface of the insulating film including the upper layer rewiring except a connection pad portion of the upper layer rewiring. Manufacturing method.
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JP2011187473A (en) * 2010-03-04 2011-09-22 Nec Corp Wiring substrate with built-in semiconductor element

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011187473A (en) * 2010-03-04 2011-09-22 Nec Corp Wiring substrate with built-in semiconductor element

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