JP2007005699A - Nonvolatile semiconductor storage device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To rapidly perform a reading operation by lowering the resistance of a bit line, and to attain a refinement concerning a nonvolatile semiconductor storage device where an impurity diffusion layer is made to be the bit line. <P>SOLUTION: The nonvolatile semiconductor storage device includes a plurality of gate electrodes 103 which are arranged by isolation in matrix on a semiconductor substrate 101, and respectively formed by the interposition of a gate insulating film 102 between the gate electrodes 103 and the semiconductor substrate 101; and a plurality of diffusion layers 106 of the bit lines which are respectively formed in regions on the semiconductor substrate 101 between the gate electrodes arranged in a row direction among the plurality of gate electrodes 103. The diffusion layers 106 have a metallic layer or a metallic silicide layer 108 at least on the layers 106. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device having an impurity diffusion layer formed on a semiconductor substrate in a bit line and a method for manufacturing the same.

  In recent years, a nonvolatile semiconductor memory device using an impurity diffusion layer formed on a semiconductor substrate as a bit line among nonvolatile semiconductor memory devices has attracted attention as a device that can be highly integrated.

FIG. 25 shows a cross-sectional configuration of a conventional nonvolatile semiconductor memory device having a diffusion layer as a bit line (see, for example, Patent Document 1). As shown in FIG. 25, the memory cell according to the conventional example includes diffusion layers 2 and 3 serving as source / drain regions formed on an upper portion of a substrate 1 made of p-type silicon, and diffusion layers 2 and 3 on the substrate 1. Channel region 4 formed between the two. Above the channel region 4, a gate insulating film 8, which is a laminated film composed of a silicon oxide film 5, a silicon nitride film 6 and a silicon oxide film 7, is formed, and a gate electrode 9 is formed on the gate insulating film 8. Has been. The gate electrode 9 functions as a word line. An interlayer insulating film 10 is formed between the diffusion layers 2 and 3 and the gate electrode 9. Desired data is written by injecting hot electrons from the channel region 4 into the silicon nitride film 6 constituting the gate insulating film 8. Here, although not shown, the silicon nitride film 6 and the diffusion layer 3 are formed so as to partially overlap each other in the vertical direction, and between the silicon nitride film 6 and the diffusion layer 2. Is provided with an offset portion 11 for providing a predetermined interval 11.
JP 2000-031436 A

  However, the conventional nonvolatile semiconductor memory device has a problem that it is difficult to reduce the resistance of the impurity diffusion layer constituting the bit line. As shown in FIG. 25, in the conventional nonvolatile semiconductor memory device, an interlayer insulating film 10 is formed to be buried on the diffusion layers 2 and 3 which are bit lines. For this reason, the silicidation process by the metal which aims at low resistance cannot be implemented. As described above, when the resistances of the diffusion layers 2 and 3 are not lowered, it is difficult to speed up the read operation because the parasitic resistance in the diffusion layers 2 and 3 increases and the saturation current amount decreases. Become. Further, as a technique for reducing the resistance of the diffusion layers 2 and 3 in place of the silicidation process, when a plurality of contact plugs (so-called backing contacts) are provided in the diffusion layers 2 and 3, a plurality of contact plugs are used. As the area for forming increases, the area of an element formation region such as a transistor is pressed.

  In addition, since the conventional method for manufacturing a nonvolatile semiconductor memory device forms the interlayer insulating film 10 after the diffusion layers 2 and 3 are formed, in addition to forming a normal transistor with high-temperature heat treatment, Steps not implemented in the transistor manufacturing process are added. For this reason, the impurities in the diffusion layers 2 and 3 are thermally diffused, and it is difficult to miniaturize the diffusion layers 2 and 3. Further, when the non-volatile semiconductor memory device is mounted on the logic circuit portion and one chip, the gate electrodes of the transistors in the logic circuit portion must be formed after the diffusion layers 2 and 3 and the interlayer insulating film 10 are formed. In addition, the impurities in the diffusion layers 2 and 3 are further thermally diffused by the heat treatment on the logic circuit portion, and miniaturization becomes even more difficult.

  In view of the above-described conventional problems, the present invention can realize a high-speed read operation and miniaturization in a nonvolatile semiconductor memory device using an impurity diffusion layer as a bit line by reducing the resistance of the bit line. The purpose is to do.

  In order to achieve the above object, the present invention provides a method for manufacturing a nonvolatile semiconductor memory device adjacent to a direction in which a bit line extends (column direction) among a plurality of gate electrodes formed in a matrix and isolated. A buried insulating film (inter-gate insulating film) is formed between the gate electrodes to form a plurality of gate electrodes in a stripe pattern extending in the column direction including the buried insulating film, and then between the stripe patterns in the semiconductor region. A diffusion layer is formed in each region, and each formed diffusion layer is silicided with a metal.

  Specifically, a nonvolatile semiconductor memory device according to the present invention includes a plurality of gates that are arranged in a matrix and isolated on a semiconductor region, with a gate insulating film interposed between the gate electrode and the semiconductor region. A plurality of diffusion layers, each of which includes an electrode and a plurality of diffusion layers that are bit lines respectively formed in regions between the gate electrodes arranged in the row direction among the plurality of gate electrodes in the upper portion of the semiconductor region Has a metal layer or a metal silicide layer at least on the top thereof.

  In the nonvolatile semiconductor memory device of the present invention, the gate insulating film is preferably a stacked film including an insulating film capable of storing electric charge.

  In this case, the laminated film is preferably composed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.

  In the nonvolatile semiconductor memory device of the present invention, each gate electrode includes a floating gate electrode, a capacitor insulating film, and a control gate electrode, which are sequentially formed from the semiconductor region side, and the floating gate electrode accumulates electric charges. It is preferable.

  The nonvolatile semiconductor memory device of the present invention is formed in a region between gate electrodes arranged in the column direction among a plurality of gate electrodes, and is formed of a material that transmits less ultraviolet light than silicon oxide. It is preferable to further include an inter-gate insulating film.

  In the nonvolatile semiconductor memory device of the present invention, each gate electrode preferably has a metal layer or a metal silicide layer at least on the top thereof.

  In the nonvolatile semiconductor memory device of the present invention, each gate electrode has a cap insulating film formed on the upper surface of the gate electrode and a sidewall insulating film formed on the side surface thereof, and the nonvolatile semiconductor memory Preferably, the device further includes a plurality of contact plugs formed on the diffusion layer in a self-aligned manner and each electrically connected to the diffusion layer.

  In the nonvolatile semiconductor memory device of the present invention, the semiconductor region is preferably made of silicon, and the gate electrode is preferably made of polycrystalline silicon.

  A first non-volatile semiconductor memory device manufacturing method according to the present invention is directed to a non-volatile semiconductor memory device manufacturing method having a plurality of memory cells arranged in a matrix, and includes a gate over a semiconductor region. Step (a) of forming an insulating film, and after forming a gate electrode forming film on the gate insulating film, patterning is performed on the formed gate electrode forming film so that it is isolated in a matrix form from the gate electrode forming film. Forming a plurality of gate electrode structures arranged in a row, and a first embedding in a region between the gate electrode structures adjacent to each other in the column direction among the plurality of gate electrode structures. A step (c) of forming an insulating film, and ion implantation into the semiconductor region using each gate electrode structure and the first buried insulating film as a mask, thereby forming a plurality of gates in the upper portion of the semiconductor region. A step (d) of forming a plurality of diffusion layers each serving as a bit line in a region between the gate electrode structures arranged in the row direction in the first electrode structure, and silicidizing the upper portion of each diffusion layer with a metal And a step (e).

  In the first method for manufacturing a nonvolatile semiconductor memory device, the step (b) is performed by selectively etching the formed gate electrode formation film before forming the plurality of gate electrode structures. A step of forming a stripe pattern extending in the column direction from the gate electrode forming film, a step of filling each gap between the formed stripe patterns with a second buried insulating film, and a second buried insulating film formed Forming a plurality of gate electrode structures from the stripe pattern in a state where the first embedded insulating film is formed, and the step (c) forms the second embedded insulating film and the second embedded insulating film after forming the first embedded insulating film. Preferably, the method includes a step of removing the gate insulating film located below the two buried insulating films.

  In the first method for manufacturing a non-volatile semiconductor memory device, the step (b) includes forming a cap insulation on the gate electrode formation film after forming the gate electrode formation film and before forming the stripe pattern. A step of forming a film, and patterning the gate electrode forming film is performed together with the cap insulating film. In the step (d), a plurality of diffusion layers are formed, and then sidewalls are formed on the side surfaces of the gate electrode structure on the diffusion layer side. A step of forming a contact plug electrically connected to each diffusion layer in a self-alignment manner after the step (e) using the cap insulating film and the sidewall insulating film as a mask (f). ).

  In this case, it is preferable that the semiconductor region is made of silicon, the gate electrode formation film is made of polycrystalline silicon, the first buried insulating film is made of silicon nitride, and the second buried insulating film is made of silicon oxide.

  A second non-volatile semiconductor memory device manufacturing method according to the present invention is directed to a non-volatile semiconductor memory device manufacturing method having a plurality of memory cells arranged in a matrix. A gate insulating film is formed on a semiconductor region. Forming a gate electrode forming film on the gate insulating film, and then patterning the formed gate electrode forming film to form a first extending in the row direction from the gate electrode forming film. A step (b) of forming a stripe pattern, a step (c) of filling each gap between the formed first stripe patterns with a buried insulating film, and the first stripe pattern and the buried insulating film. By selectively etching to have a second stripe pattern extending in the column direction, the stripe pattern is arranged in a matrix and buried. A step (d) of forming a plurality of gate electrode structures in which the embedded insulating films are left between the wall surfaces facing each other in the column direction, and ions are formed in the semiconductor region using each gate electrode structure and the embedded insulating film as a mask. Step (e) of forming a plurality of diffusion layers each serving as a bit line in a region between the gate electrode structures aligned in the row direction among the plurality of gate electrode structures by performing implantation (e And a step (f) of siliciding the upper part of each diffusion layer with a metal.

  In the second method for manufacturing a non-volatile semiconductor memory device, in the step (b), a cap is formed on the gate electrode formation film after forming the gate electrode formation film and before forming the first stripe pattern. The step of forming an insulating film includes patterning the gate electrode forming film together with the cap insulating film, and the step (e) forms a plurality of diffusion layers and then forms a plurality of diffusion layers on the side surface of the gate electrode structure on the diffusion layer side. The method for manufacturing the second nonvolatile semiconductor memory device includes a step of forming a sidewall insulating film, and the second nonvolatile semiconductor memory device is electrically connected to each diffusion layer after the step (f) using the cap insulating film and the sidewall insulating film as a mask. Preferably, the method further includes a step (g) of forming the contact plug to be formed in a self-aligning manner.

  In the first or second method for manufacturing a nonvolatile semiconductor memory device, when the cap insulating film is provided, the gate electrode forming film is preferably made of polycrystalline silicon, and the cap insulating film and the sidewall insulating film are preferably made of silicon nitride. .

  In the first or second nonvolatile semiconductor memory device manufacturing method, in the step (a), the gate insulating film is formed on the semiconductor region with the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer. It is preferable to sequentially stack the layers.

  In the first or second method for manufacturing a nonvolatile semiconductor memory device, the gate electrode formation film is made of polycrystalline silicon, and the upper part of each gate electrode structure is also silicidized in the step of siliciding the diffusion layer. Is preferred.

  In the first or second method for manufacturing a nonvolatile semiconductor memory device, the gate insulating film is a tunnel insulating film, and in step (b), the gate electrode forming film is formed on the tunnel insulating film with a floating gate forming film and a capacitor. The gate electrode structure is formed by sequentially laminating an insulating film and a control gate forming film, and the gate electrode structure includes a floating gate electrode formed from the floating gate forming film, a capacitive insulating film, and a control gate electrode formed from the control gate forming film. It is preferable that it is comprised from these.

  In this case, at least the control gate formation film of the floating gate formation film and the control gate formation film is preferably made of polycrystalline silicon, and it is preferable that the upper part of the control gate electrode is also metal-silicided in the step of siliciding the diffusion layer. .

  According to the nonvolatile semiconductor memory device and the method for manufacturing the same according to the present invention, the resistance of the diffusion layer constituting the bit line can be reduced by metal silicidation, so that the read operation can be performed at a high speed and the semiconductor element can be miniaturized. It can be realized at the same time. In addition, in the mixed mounting process in which the memory circuit and the logic circuit are formed on one chip, the memory circuit of the present invention can easily share the process with the logic circuit. realizable.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a nonvolatile semiconductor memory device according to the first embodiment of the present invention. As shown in FIG. 1, on the main surface of a semiconductor substrate 101 made of, for example, p-type silicon (Si), a plurality of gate electrode structures each made of polycrystalline silicon doped with impurities are formed in isolation. The gate electrodes 103 are arranged in a matrix.

A gate insulating film 102 is formed between each gate electrode 103 and the semiconductor substrate 101. The gate insulating film 102 is made and the lower insulating film 102a made of silicon oxide (SiO _2), and the middle insulating layer 102b made of silicon nitride (SiN), by the upper insulating film 102c made of silicon oxide (SiO _2), Electric charges are accumulated in the middle insulating film 102b made of silicon nitride.

  A first buried insulating film (inter-gate insulating film) 104 made of silicon nitride is formed between the gate electrodes 103 adjacent in the column direction among the plurality of gate electrodes 103. Therefore, the plurality of gate electrodes 103 are formed as a stripe pattern extending in the column direction including the first buried insulating film 104.

  Impurity ions are selectively introduced into portions exposed from the stripe pattern in the semiconductor substrate 101, and a plurality of diffusion layers 106 functioning as bit lines (bit lines) are formed. A sidewall insulating film 107 made of silicon oxide is formed on each side surface on the diffusion layer 106 side of the stripe pattern.

  A silicide layer 108 made of, for example, cobalt (Co) is formed on the upper portion of each diffusion layer 106 and the upper portion of each gate electrode 103 exposed from the stripe pattern on which the sidewall insulating film 107 is formed.

  Among the plurality of gate electrodes 103, the gate electrode 103 adjacent in the row direction is above the silicide layer 108 and the silicide layer 108 with respect to the word line 110 that is a wiring provided so as to extend in the row direction. It is electrically connected via a contact plug 109 formed in the. Although not shown, the group of gate electrodes 103 adjacent to each other in the row direction is also connected to another word line different from the illustrated word line 110, similarly to the remaining gate electrodes 103. .

  As described above, in the first embodiment, since the diffusion layer 106 and the gate electrode 103 which are bit lines, particularly the diffusion layer 106, are silicided with metal, the resistance of the bit line can be reduced, so that the data read operation can be performed. Can be speeded up.

  Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

  2 (a) to 2 (d) and FIGS. 3 (a) to 3 (c) are partial cross-sectional views in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention. 1 shows a configuration and a perspective configuration.

First, as shown in FIG. 2A, a lower insulating film made of silicon oxide having a thickness of 7 nm over the entire main surface of the semiconductor substrate 101 by heat-treating the semiconductor substrate 101 in an oxidizing atmosphere having a temperature of 900 ° C. 102a is formed. Subsequently, an intermediate insulating film 102b made of silicon nitride having a film thickness of 15 nm is formed on the lower insulating film 102a by low pressure chemical vapor deposition (LPCVD) with a substrate temperature of 700 ° C. Subsequently, an upper insulating film 102c having a thickness of 7 nm is formed on the middle insulating film 102b by heat treatment in an oxidizing atmosphere having a temperature of 1000 ° C. Thereby, the gate insulating film 102 which is a so-called ONO film composed of the lower insulating film 102a, the middle insulating film 102b, and the upper insulating film 102c is formed. Thereafter, a gate electrode formation film made of polycrystalline silicon having a thickness of 200 nm is deposited on the gate insulating film 102 by LPCVD with a substrate temperature of 600 ° C. Subsequently, a first mask pattern (not shown) having a stripe-shaped opening pattern extending in the column direction is formed on the deposited gate electrode formation film by lithography, and the formed first mask pattern is used. Then, dry etching is performed on the gate electrode formation film with an etching gas containing chlorine (Cl ₂ ) as a main component. Thereby, the gate electrode formation film 103A having a stripe pattern extending in the column direction from the gate electrode formation film is formed.

  Next, as shown in FIG. 2B, after removing the first mask pattern, a silicon oxide film is formed on the entire surface including the stripe pattern formed of the gate electrode formation film 103A on the semiconductor substrate 101 by LPCVD. Then, the deposited silicon oxide film is etched back by dry etching using an etching gas containing carbon fluoride as a main component. As a result, the second buried insulating film 105 made of silicon oxide is left in each gap of the stripe pattern in the gate electrode formation film 103A.

  Next, on the gate electrode formation film 103A having a stripe pattern and the second buried insulating film 105 that fills the gap, a direction crossing the stripe direction of the gate electrode formation film 103A, that is, the row direction is formed by lithography. A second mask pattern (not shown) having an extended stripe-shaped opening pattern is formed, and an etching gas containing chlorine as a main component is used for the gate electrode formation film 103A using the formed second mask pattern. Perform dry etching. Since only the gate electrode formation film 103A made of polycrystalline silicon is selectively etched by this dry etching, the stripe-shaped gate electrode formation film 103A is arranged in a matrix form as shown in FIG. In addition, a plurality of isolated gate electrodes 103 can be obtained.

  Next, as shown in FIG. 2D, after the second mask pattern is removed, the entire surface including the gate electrode 103 and the second buried insulating film 105 on the semiconductor substrate 101 is silicon nitrided by LPCVD. A film is deposited, and the deposited silicon nitride film is etched back using an etching gas containing carbon fluoride as a main component. Thus, the first buried insulating film 104 made of silicon nitride is filled in the region between the gate electrodes 103 adjacent in the column direction.

  Next, as shown in FIG. 3A, wet etching is performed on the second buried insulating film 105 with an aqueous solution containing hydrofluoric acid while the first buried insulating film 104 is formed. The second buried oxide film 105 made of silicon oxide and the upper insulating film 102c therebelow are removed. Thereafter, the intermediate insulating film 102b and the lower insulating film 102a are sequentially removed by dry etching, thereby exposing a region between the gate electrodes 103 adjacent in the row direction on the main surface of the semiconductor substrate 101. As a result, the plurality of gate electrodes 103 arranged in a matrix form are in a state where the gate electrodes 103 adjacent to each other in the column direction are filled with the first buried insulating film 104, and the stripe pattern extending in the column direction Become.

Next, as shown in FIG. 3B, for example, in the direction perpendicular to the main surface of the semiconductor substrate 101, that is, using the stripe pattern formed of the gate electrode 103 and the first buried insulating film 104 as a mask, Arsenic (As) ions are ion-implanted into the semiconductor substrate 101 under an implantation condition in which the inclination is 0 ° with respect to the normal, the implantation energy is 30 KeV, and the dose is 3 × 10 ¹⁵ atoms / cm ^−2. As a result, a diffusion layer 106 serving as a bit line is formed in a region exposed from the stripe pattern of the semiconductor substrate 101. Subsequently, a silicon oxide film having a thickness of 100 nm is deposited on the entire surface including the gate electrode 103 and the first buried insulating film 104 on the semiconductor substrate 101 by LPCVD. Thereafter, etch back is performed on the deposited silicon oxide film using an etching gas mainly composed of carbon fluoride, and on each side surface of the stripe pattern including the gate electrode 103 and the first buried insulating film 104. Then, sidewall insulating films 107 are respectively formed. Subsequently, a metal film made of cobalt is deposited on the entire surface including the stripe pattern on the semiconductor substrate 101 by, for example, a sputtering method or a vacuum evaporation method, and a known heat treatment (for example, a heat treatment at a temperature of 800 ° C. for about 10 seconds). ) To form silicide layers 108 only on the gate electrodes 103 and the diffusion layers 106. Note that the silicide layer 108 is not necessarily alloyed (silicided) with silicon. For example, after forming a mask pattern that opens the top of each gate electrode 103 and each diffusion layer 106, depositing a metal layer with the formed mask pattern interposed, and then performing so-called lift-off to remove the mask pattern, silicide A metal layer can be formed independently from a metal that is not easily formed, such as tungsten (W).

  Next, as shown in FIG. 3C, contact plugs made of tungsten (W), for example, are arranged on the gate electrodes 103 arranged in a matrix in the direction intersecting the diffusion layer 106, that is, in the row direction. 109 is formed and the gate electrodes 103 arranged in the row direction are electrically connected to each other by the word line 110 to obtain a nonvolatile semiconductor memory device.

  According to the first embodiment, in the nonvolatile semiconductor memory device that uses the ONO film as the gate insulating film 102 to capture charges, the diffusion layer 106 constituting the bit line can be reliably silicided with a metal. The resistance of the bit line) 106 can be reduced. For this reason, delay due to the resistance of the bit line can be suppressed, so that a high-speed read operation can be realized.

  Further, since the thermal load (thermal budget) after forming the diffusion layer 106 is small, thermal diffusion in the diffusion layer 106 is also suppressed, so that further miniaturization can be realized.

  In the first embodiment, since it is not necessary to form the special interlayer insulating film 10 shown in the conventional example on the diffusion layer 106, the heat treatment and the silicidation processing on the diffusion layer 106 are performed with the logic circuit portion. It can be shared. Therefore, a memory cell can be formed with a minimum heat treatment.

  In the first embodiment, silicon nitride is used for the first buried insulating film 104 that fills the gaps between the isolated gate electrodes 103. As described above, by using silicon nitride, which has a higher ability to shield ultraviolet light than silicon oxide, as the first buried insulating film 104, electrons excited by ultraviolet light in the semiconductor substrate 101 are captured by the gate insulating film 102. Therefore, the problem of varying the threshold voltage of the memory cell can be suppressed.

  In the first embodiment, since the charge accumulation characteristics are excellent, the ONO film is used as the gate insulating film 102 of the memory cell. However, the present invention is not limited to this. For example, the gate insulating film 102 may be an ON film formed of a lower insulating film 102a made of silicon oxide and an intermediate insulating film 102b made of silicon nitride or the like as a trap film.

  In the first embodiment, a so-called virtual ground type array structure in which the diffusion layer 106 serving as a bit line is shared with adjacent memory cells (bits) is used. It is also possible to adopt a so-called AND type array structure that is not shared.

  In the first embodiment, cobalt is used as the metal material for forming the silicide layer 108, but other metal materials such as titanium (Ti) or nickel (Ni) may be used.

  In the first embodiment, the etch back method is used to form the first buried insulating film 104 and the second buried insulating film 105, but a chemical mechanical polishing (CMP) method can also be used.

(One modification of the first embodiment)
Hereinafter, a modification of the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 4 shows a nonvolatile semiconductor memory device according to a modification of the first embodiment of the present invention. In FIG. 4, the same components as those shown in FIG.

  As shown in FIG. 4, the nonvolatile semiconductor memory device according to this modification includes a cap layer 121 made of silicon nitride instead of providing the silicide layer 108 on the upper surface of each gate electrode 103. Further, the composition of the sidewall insulating film 117 is silicon nitride instead of silicon oxide.

  As a result, each gate electrode 103 is covered with silicon nitride on the top surface and side surfaces, so that when forming the bit line contact 122 that is electrically connected to each diffusion layer 106 constituting each bit line, self-alignment is achieved. Therefore, further miniaturization of the nonvolatile semiconductor memory device can be realized.

  Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

  FIG. 5A to FIG. 5D and FIG. 6A to FIG. 6C show the order of steps in the method of manufacturing the nonvolatile semiconductor memory device according to the modification of the first embodiment of the present invention. A partial cross-sectional configuration and a perspective configuration are shown.

  First, as shown in FIG. 5A, as in the first embodiment, a lower insulating film 102a made of silicon oxide having a thickness of 7 nm and a thickness of 15 nm are formed on the main surface of the semiconductor substrate 101. An intermediate insulating film 102b made of silicon nitride and an upper insulating film 102c with a thickness of 7 nm are sequentially formed to form a gate insulating film 102 having an ONO structure. Thereafter, a gate electrode formation film made of polycrystalline silicon having a thickness of 200 nm is deposited on the gate insulating film 102 by LPCVD. Subsequently, a cap layer 121 made of silicon nitride having a thickness of 100 nm is deposited on the gate electrode formation film by LPCVD. Thereafter, a first mask pattern (not shown) having a stripe-shaped opening pattern extending in the column direction is formed on the deposited cap layer 121 by lithography, and the first mask pattern thus formed is used. The cap layer 121 is dry-etched with an etching gas mainly containing fluorocarbon, and the gate electrode forming film is dry-etched with an etching gas mainly containing chlorine. Thereby, the gate electrode forming film 103A having a stripe pattern extending in the column direction is formed from the gate electrode forming film having the cap layer 121 formed on the upper surface thereof.

  Next, as shown in FIG. 5B, after removing the first mask pattern, a silicon oxide film is deposited over the entire surface including the stripe pattern having the cap layer 121 on the semiconductor substrate 101 by the LPCVD method. Then, etch back is performed on the deposited silicon oxide film using an etching gas mainly composed of carbon fluoride. As a result, the second buried insulating film 105 made of silicon oxide is left in each gap of the stripe pattern including the cap layer 121 and the gate electrode formation film 103A.

  Next, on the stripe pattern having the cap layer 121 and the second buried insulating film 105 filling the gap of the stripe pattern, a second pattern having a stripe-like opening pattern extending in the row direction is formed by lithography. A mask pattern (not shown) is formed. Using the formed second mask pattern, the cap layer 121 is etched with an etching gas mainly composed of carbon fluoride, and the gate electrode formation film 103A. Then, dry etching is performed with an etching gas mainly containing chlorine. Since only the gate electrode formation film 103A made of polycrystalline silicon is selectively etched by this dry etching, the stripe-shaped gate electrode formation film 103A is arranged in a matrix as shown in FIG. 5C. In addition, a plurality of isolated gate electrodes 103 can be obtained. At this time, the etching selectivity between the cap layer 121 made of silicon nitride and the second buried insulating film 105 made of silicon oxide is small, but the film thickness of the second buried insulating film 105 is larger than the film thickness of the cap layer 121. Is sufficiently large so that no malfunction occurs.

  Next, as shown in FIG. 5D, after the second mask pattern is removed, the entire surface including the cap layer 121 and the second buried insulating film 105 on the semiconductor substrate 101 is silicon nitrided by LPCVD. A film is deposited, and the deposited silicon nitride film is etched back using an etching gas containing carbon fluoride as a main component. As a result, the first buried insulating film 104 made of silicon nitride is filled in the region between the gate electrodes 103 adjacent to each other in the row direction, including the cap layer 121.

  Next, as shown in FIG. 6A, wet etching is performed on the second buried insulating film 105 with an aqueous solution containing hydrofluoric acid in a state where the first buried insulating film 104 is formed. The second buried oxide film 105 made of silicon oxide and the upper insulating film 102c therebelow are removed. Thereafter, the semiconductor substrate 101 is exposed by removing the middle insulating film 102b and the lower insulating film 102a by dry etching. As a result, the plurality of gate electrodes 103 arranged in a matrix form are in a state where the gate electrodes 103 adjacent to each other in the column direction are filled with the first buried insulating film 104, and the stripe pattern extending in the column direction Become.

Next, as shown in FIG. 6B, implantation is performed in a direction perpendicular to the main surface of the semiconductor substrate 101, for example, using a stripe pattern including the cap layer 121 and the first buried insulating film 104 as a mask. Arsenic (As) ions are ion-implanted into the semiconductor substrate 101 under an implantation condition in which the energy is 30 KeV and the dose is 3 × 10 ¹⁵ atoms / cm ⁻² , thereby exposing the stripe pattern of the semiconductor substrate 101. A diffusion layer 106 serving as a bit line is formed in the region. Subsequently, a silicon nitride film having a thickness of 100 nm is deposited on the entire surface including the cap layer 121 and the first buried insulating film 104 on the semiconductor substrate 101 by LPCVD. Thereafter, the deposited silicon nitride film is etched back using an etching gas containing carbon fluoride as a main component, and on each side surface of the striped pattern composed of the gate electrode 103 and the first buried insulating film 104. Then, sidewall insulating films 117 made of silicon nitride are formed. Subsequently, a metal film made of cobalt is deposited on the entire surface including the stripe pattern on the semiconductor substrate 101 by, for example, a sputtering method or a vacuum evaporation method, and a predetermined heat treatment is performed, so that a predetermined heat treatment is performed. Only the silicide layer 108 is formed.

  Next, as shown in FIG. 6C, contact plugs 109 are formed in a plurality of gate electrodes 103 arranged in a row direction, that is, in a direction intersecting the diffusion layer 106 among the gate electrodes 103 arranged in a matrix. The gate electrodes 103 arranged in the row direction are electrically connected to each other by a word line 110. Subsequently, the bit line contact 122 is formed on each diffusion layer 106 in a self-aligned manner with the silicide layer 108 interposed therebetween, thereby obtaining a nonvolatile semiconductor memory device.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 7 shows a nonvolatile semiconductor memory device according to the second embodiment of the present invention. In FIG. 7, the same components as those shown in FIG.

  As shown in FIG. 7, the nonvolatile semiconductor memory device according to the second embodiment is embedded between the gate electrodes 103 adjacent in the column direction (direction in which the diffusion layer 106 extends) among the plurality of gate electrodes 103. The insulating film (inter-gate insulating film) 114 is made of silicon oxide instead of silicon nitride. Thereby, the manufacturing process of the nonvolatile semiconductor memory device can be simplified as compared with the first embodiment.

  Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

  FIG. 8A to FIG. 8C, FIG. 9A and FIG. 9B are partial cross sections in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention. 1 shows a configuration and a perspective configuration.

  First, as shown in FIG. 8A, as in the first embodiment, a lower insulating film 102a made of silicon oxide having a thickness of 7 nm and a thickness of 15 nm are formed on the main surface of the semiconductor substrate 101. An intermediate insulating film 102b made of silicon nitride and an upper insulating film 102c with a thickness of 7 nm are sequentially formed to form a gate insulating film 102 having an ONO structure. Thereafter, a gate electrode formation film made of polycrystalline silicon having a thickness of 200 nm is deposited on the gate insulating film 102 by LPCVD. Thereafter, a first mask pattern (not shown) having a stripe-shaped opening pattern extending in the row direction is formed on the deposited gate electrode formation film by lithography, and the formed first mask pattern is used. Then, dry etching is performed on the gate electrode formation film with an etching gas containing chlorine as a main component. Thus, the gate electrode formation film 103B having a stripe pattern extending in the row direction is formed from the gate electrode formation film.

  Next, as shown in FIG. 8B, after removing the first mask pattern, a silicon oxide film is formed on the entire surface including the stripe-shaped pattern made of the gate electrode formation film 103B on the semiconductor substrate 101 by LPCVD. Then, etch back is performed on the deposited silicon oxide film using an etching gas containing carbon fluoride as a main component. As a result, the buried insulating film 114 made of silicon oxide is left in each gap of the stripe pattern in the gate electrode formation film 103B.

  Next, on the gate electrode formation film 103B having a stripe pattern and the buried insulating film 114 filling the gap, a stripe shape extending in the direction intersecting the stripe direction of the gate electrode formation film 103B, that is, the column direction is formed by lithography. A second mask pattern (not shown) having the opening pattern is formed, and the gate electrode formation film 103B made of polycrystalline silicon and the buried insulating film 114 made of silicon oxide are formed using the formed second mask pattern. On the other hand, dry etching is performed. At this time, the gate electrode formation film 103B and the buried insulating film 114 may be etched at the same time under the condition that the etching selectivity between polycrystalline silicon and silicon oxide is small, and the etching selectivity between polycrystalline silicon and silicon oxide is high. The gate electrode formation film 103B and the buried insulating film 114 may be sequentially etched under large conditions. Note that the order of the gate electrode formation film 103B and the buried insulating film 114 is not particularly limited when they are separately etched. By this dry etching, as shown in FIG. 8C, a plurality of gate electrodes 103 arranged in a matrix and isolated from each other can be obtained from the stripe-shaped gate electrode formation film 103B. Thereafter, wet etching is performed with an aqueous solution containing hydrofluoric acid to remove the upper insulating film 102c made of silicon oxide exposed from the stripe pattern. Subsequently, the intermediate insulating film 102b and the lower insulating film 102a are sequentially removed by dry etching, thereby exposing a region between the gate electrodes 103 adjacent in the row direction on the main surface of the semiconductor substrate 101. Thus, the plurality of gate electrodes 103 arranged in a matrix form a stripe pattern extending in the column direction in a state where the gate electrodes 103 adjacent in the column direction are filled with the buried insulating film 114.

Next, as shown in FIG. 9A, the implantation energy is set to 30 KeV in the direction perpendicular to the main surface of the semiconductor substrate 101, for example, using the stripe pattern formed of the gate electrode 103 and the buried insulating film 114 as a mask. And by implanting arsenic (As) ions into the semiconductor substrate 101 under the implantation conditions of a dose amount of 3 × 10 ¹⁵ atoms / cm ⁻² , a bit is formed in the region exposed from the stripe pattern of the semiconductor substrate 101. A diffusion layer 106 to be a line is formed. Subsequently, a silicon oxide film having a thickness of 100 nm is deposited on the entire surface including the gate electrode 103 and the buried insulating film 114 on the semiconductor substrate 101 by LPCVD. Thereafter, the deposited silicon oxide film is etched back using an etching gas mainly composed of carbon fluoride, and sidewall insulation is formed on each side surface of the stripe-shaped pattern including the gate electrode 103 and the buried insulating film 114. Films 107 are respectively formed. Subsequently, a metal film made of cobalt is deposited on the entire surface including the stripe pattern on the semiconductor substrate 101 by, for example, sputtering or vacuum evaporation, and subjected to a predetermined heat treatment, whereby each gate electrode 103 and each diffusion are formed. A silicide layer 108 is formed only on the layer 106.

  Next, as shown in FIG. 9B, among the gate electrodes 103 arranged in a matrix, a plurality of gate electrodes 103 arranged in the direction intersecting with the diffusion layer 106, that is, in the row direction are made of tungsten (W), for example. A contact plug 109 is formed, and the gate electrodes 103 arranged in the row direction are electrically connected to each other by a word line 110 to obtain a nonvolatile semiconductor memory device.

  According to the second embodiment, in the nonvolatile semiconductor memory device that uses the ONO film as the gate insulating film 102 to capture charges, the diffusion layer 106 constituting the bit line can be reliably silicided with metal, so that the diffusion layer ( The resistance of the bit line) 106 can be reduced. For this reason, delay due to the resistance of the bit line can be suppressed, so that a high-speed read operation can be realized. In addition, since one type of buried insulating film 114 shown in FIG. 8B is used to the end, the manufacturing process can be simplified, and the manufacturing cost can be reduced.

(One Modification of Second Embodiment)
Hereinafter, a modification of the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 10 shows a nonvolatile semiconductor memory device according to a modification of the second embodiment of the present invention. 10, the same components as those shown in FIGS. 1 and 4 are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 10, the nonvolatile semiconductor memory device according to this modification includes a cap layer 121 made of silicon nitride instead of providing the silicide layer 108 on the upper surface of each gate electrode 103. Further, the composition of the sidewall insulating film 117 is silicon nitride instead of silicon oxide.

  As a result, each gate electrode 103 is covered with silicon nitride on the top surface and side surfaces, so that when forming the bit line contact 122 that is electrically connected to each diffusion layer 106 constituting each bit line, self-alignment is achieved. Therefore, the nonvolatile semiconductor memory device can be miniaturized.

  Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

  11 (a) to 11 (c) and FIGS. 12 (a) to 12 (c) show the order of steps of the method of manufacturing the nonvolatile semiconductor memory device according to the modification of the second embodiment of the present invention. A partial cross-sectional configuration and a perspective configuration are shown.

  First, as shown in FIG. 11A, as in the first embodiment, a lower insulating film 102a made of silicon oxide having a film thickness of 7 nm and a film thickness of 15 nm are formed on the main surface of the semiconductor substrate 101. An intermediate insulating film 102b made of silicon nitride and an upper insulating film 102c with a thickness of 7 nm are sequentially formed to form a gate insulating film 102 having an ONO structure. Thereafter, a gate electrode formation film made of polycrystalline silicon having a thickness of 200 nm is deposited on the gate insulating film 102 by LPCVD. Thereafter, a first mask pattern (not shown) having a stripe-shaped opening pattern extending in the row direction is formed on the deposited gate electrode formation film by lithography, and the formed first mask pattern is used. Then, dry etching is performed on the gate electrode formation film with an etching gas containing chlorine as a main component. Thus, the gate electrode formation film 103B having a stripe pattern extending in the row direction is formed from the gate electrode formation film.

  Next, as shown in FIG. 11B, after removing the first mask pattern, a silicon oxide film is formed on the entire surface including the stripe-shaped pattern made of the gate electrode formation film 103B on the semiconductor substrate 101 by LPCVD. Then, etch back is performed on the deposited silicon oxide film using an etching gas containing carbon fluoride as a main component. As a result, the buried insulating film 114 made of silicon oxide is left in each gap of the stripe pattern in the gate electrode formation film 103B.

  Next, as shown in FIG. 11C, a cap made of silicon nitride having a film thickness of 100 nm is formed on the gate electrode forming film 103B having a stripe pattern and the buried insulating film 114 filling the gap by LPCVD. Layer 121 is deposited over the entire surface.

  Next, a second mask pattern (not shown) having a stripe-shaped opening pattern extending in the direction intersecting the stripe direction of the gate electrode formation film 103B, that is, the column direction is formed on the cap layer 121 by lithography. The cap layer 121 made of silicon nitride is first dry-etched using the formed second mask pattern, and then the gate electrode formation film 103B made of polycrystalline silicon and the buried insulating film 114 made of silicon oxide are formed. On the other hand, dry etching is performed. At this time, the gate electrode formation film 103B and the buried insulating film 114 may be etched at the same time under the condition that the etching selectivity between polycrystalline silicon and silicon oxide is small. Alternatively, the gate electrode formation film 103B and the buried insulating film 114 may be sequentially etched under a condition where the etching selectivity between polycrystalline silicon and silicon oxide is large. By this dry etching, as shown in FIG. 12A, a plurality of gate electrodes 103 arranged in a matrix and isolated from each other can be obtained from the stripe-shaped gate electrode formation film 103B. Thereafter, wet etching is performed with an aqueous solution containing hydrofluoric acid to remove the upper insulating film 102c made of silicon oxide exposed from the adjacent stripe pattern. Subsequently, the intermediate insulating film 102b and the lower insulating film 102a are sequentially removed by dry etching, thereby exposing a region between the gate electrodes 103 adjacent in the row direction on the main surface of the semiconductor substrate 101. As a result, the plurality of gate electrodes 103 arranged in a matrix are filled with the buried insulating film 114 between the gate electrodes 103 adjacent in the column direction, and the cap layer 121 is continuously formed on the upper surface thereof. The stripe pattern extends in the column direction of the state.

Next, as shown in FIG. 12B, using the stripe pattern including the cap layer 121 as a mask, for example, the implantation energy is set to 30 KeV in the direction perpendicular to the main surface of the semiconductor substrate 101, and the dose amount. Arsenic (As) ions are implanted into the semiconductor substrate 101 under an implantation condition of 3 × 10 ¹⁵ atoms / cm ⁻² to form a diffusion layer that becomes a bit line in a region exposed from the stripe pattern of the semiconductor substrate 101 106 is formed. Subsequently, a silicon nitride film having a thickness of 100 nm is deposited on the entire surface including the cap layer 121 and the buried insulating film 114 on the semiconductor substrate 101 by LPCVD. Thereafter, the deposited silicon nitride film is etched back using an etching gas containing carbon fluoride as a main component, and on each side surface of the striped pattern including the cap layer 121, the gate electrode 103, and the buried insulating film 114. Then, sidewall insulating films 117 are formed respectively. Subsequently, a metal film made of cobalt is deposited on the entire surface including the stripe pattern on the semiconductor substrate 101 by, for example, a sputtering method or a vacuum evaporation method, and a predetermined heat treatment is performed, so that a predetermined heat treatment is performed. Only the silicide layer 108 is formed.

  Next, as shown in FIG. 12C, contact plugs 109 are formed in a plurality of gate electrodes 103 aligned in the direction intersecting the diffusion layer 106, that is, in the row direction, among the gate electrodes 103 arranged in a matrix. The gate electrodes 103 arranged in the row direction are electrically connected to each other by a word line 110. Subsequently, the bit line contact 122 is formed on each diffusion layer 106 in a self-aligned manner with the silicide layer 108 interposed therebetween, thereby obtaining a nonvolatile semiconductor memory device.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 13 shows a nonvolatile semiconductor memory device according to the third embodiment of the present invention. As shown in FIG. 13, on the main surface of a semiconductor substrate 201 made of p-type silicon (Si), for example, a plurality of gate electrode structures made of polycrystalline silicon doped with impurities and formed in isolation. 216 are arranged in a matrix.

  Between each gate electrode structure 216 and the semiconductor substrate 201, a tunnel insulating film 213 that is a gate insulating film and causes a tunnel effect is formed.

  The gate electrode structure 216 includes a floating gate electrode 214, a capacitor insulating film 202, and a control gate electrode 215 that are sequentially formed from the bottom.

  The capacitive insulating film 202 includes a lower insulating film 202a made of silicon oxide, an intermediate insulating film 202b made of silicon nitride, and an upper insulating film 202c made of silicon oxide.

  A first buried insulating film (inter-gate insulating film) 204 made of silicon nitride is formed between the gate electrode structures 216 adjacent to each other in the column direction among the plurality of gate electrode structures 216. Therefore, the plurality of gate electrode structures 216 are formed as a stripe pattern extending in the column direction including the first buried insulating film 204.

  Impurity ions are introduced into portions of the semiconductor substrate 201 exposed from the stripe pattern, and a plurality of diffusion layers 206 functioning as bit lines (bit lines) are formed. A sidewall insulating film 207 made of silicon oxide is formed on each side surface of the stripe pattern on the diffusion layer 206 side.

  A silicide layer 208 made of, for example, cobalt (Co) is formed on the upper portion of each diffusion layer 206 and the upper portion of each gate electrode structure 216 exposed from the stripe pattern on which the sidewall insulating film 207 is formed.

  The control gate electrode 215 included in the upper part of the gate electrode structure 216 adjacent in the row direction among the plurality of gate electrode structures 216 is connected to the word line 210 that is a wiring provided so as to extend in the row direction above the control gate electrode 215. The silicide layers 208 and the contact plugs 209 formed on the silicide layers 208 are electrically connected. Although not shown, the group of gate electrode structures 216 adjacent to each other in the row direction in the same manner with respect to the remaining gate electrode structures 216 is different from the word lines 210 shown in the figure. It is connected.

  As described above, in the third embodiment, since the diffusion layer 206 serving as a bit line and the control gate electrode 215 in the gate electrode structure 216, particularly the diffusion layer 206, are silicided, the resistance of the bit line can be reduced. Thus, it is possible to realize a high-speed data reading operation.

  Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

  14 (a) to 14 (d) and FIGS. 15 (a) to 15 (c) are partial cross-sectional views in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment of the present invention. 1 shows a configuration and a perspective configuration.

  First, as shown in FIG. 14A, a semiconductor substrate 201 is heat-treated in an oxidizing atmosphere at a temperature of 900 ° C. to thereby form a tunnel insulating film made of silicon oxide having a thickness of 5 nm over the entire main surface of the semiconductor substrate 101. 213 is formed. Subsequently, a floating gate forming film made of polycrystalline silicon having a thickness of 100 nm is deposited on the tunnel insulating film 213 by LPCVD with a substrate temperature of 600 ° C. Subsequently, a lower insulating film 202a made of silicon oxide having a thickness of 7 nm is formed on the floating gate formation film by LPCVD with a substrate temperature of 800.degree. Subsequently, an intermediate layer insulating film 202b made of silicon nitride having a film thickness of 15 nm is formed on the lower insulating film 102a by an LPCVD method with a substrate temperature of 700 ° C., and a substrate temperature of 800 is formed on the intermediate insulating film 202b. An upper insulating film 202c having a thickness of 7 nm is formed by LPCVD at a temperature of 7 ° C. As a result, a capacitive insulating film 202 which is a so-called ONO film composed of the lower insulating film 202a, the middle insulating film 202b, and the upper insulating film 202c is formed. Subsequently, a control gate forming film made of polycrystalline silicon having a film thickness of 100 nm is deposited on the capacitor insulating film 202 by LPCVD with a substrate temperature of 600 ° C. Subsequently, a first mask pattern (not shown) having a stripe-shaped opening pattern extending in the column direction is formed on the deposited control gate formation film by lithography, and the formed first mask pattern is used. Then, the control gate formation film and the floating gate formation film are dry-etched with an etching gas containing chlorine as a main component and the capacitor insulating film 202 with carbon fluoride as a main component. As a result, the control gate forming film 215A, the capacitive insulating film 202, and the floating gate forming film 214A having a stripe pattern extending in the column direction are formed from the control gate forming film, the capacitive insulating film 202, and the floating gate forming film. Here, the tunnel insulating film 213 is not removed when the stripe pattern is formed, but the tunnel insulating film 213 may be removed following the etching of the floating gate formation film 214A.

  Next, as shown in FIG. 14B, after removing the first mask pattern, a silicon oxide film is deposited on the entire surface including the stripe pattern on the semiconductor substrate 201 by LPCVD, and the deposited silicon Etch back is performed on the oxide film using an etching gas mainly composed of carbon fluoride. As a result, the second buried insulating film 205 made of silicon oxide is left in each gap of the stripe pattern including the floating gate forming film 214A, the capacitor insulating film 202, and the control gate forming film 215A.

  Next, a stripe-shaped opening pattern extending in the direction crossing the stripe direction of the control gate formation film 215A, that is, the row direction is formed on the stripe-shaped pattern and the second buried insulating film 205 filling the gap by lithography. A second mask pattern (not shown) is formed, and the control gate formation film 215A, the capacitor insulating film 202, and the floating gate electrode 214A are sequentially dry etched using the formed second mask pattern. As a result of this dry etching, the control gate formation film 215A and the floating gate formation film 214A both made of polycrystalline silicon are mainly etched, and as shown in FIG. 14C, the stripe-shaped control gate formation film 215A, the capacitance A plurality of gate electrode structures 216 arranged in a matrix and isolated can be obtained from the insulating film 202 and the floating gate formation film 214A. Note that, when dry etching is performed on the capacitive insulating film 202, the capacitive insulating film 202, which is an ONO film, may have a lower etching selectivity than the second buried insulating film 205 made of silicon oxide. Since the film thickness 205 is sufficiently larger than the film thickness of the capacitor insulating film 202, there is no problem.

  Next, as shown in FIG. 14D, after the second mask pattern is removed, the entire surface including the gate electrode structure 216 and the second buried insulating film 205 is formed on the semiconductor substrate 201 by LPCVD. A silicon nitride film is deposited, and the deposited silicon nitride film is etched back using an etching gas mainly composed of carbon fluoride. Thus, the first buried insulating film 204 made of silicon nitride is filled in the region between the gate electrode structures 216 adjacent in the row direction.

  Next, as shown in FIG. 15A, wet etching is performed on the second embedded insulating film 205 with an aqueous solution containing hydrofluoric acid in a state where the first embedded insulating film 204 is formed. The second buried oxide film 205 made of silicon oxide and the tunnel insulating film 213 therebelow are removed. As a result, the plurality of gate electrode structures 216 arranged in a matrix form are filled with the first embedded insulating film 204 between the gate electrode structures 216 adjacent in the column direction, and extend in the column direction. A stripe pattern is formed.

Next, as illustrated in FIG. 15B, for example, in a direction perpendicular to the main surface of the semiconductor substrate 201 using a stripe pattern including the gate electrode structure 216 and the first buried insulating film 204 as a mask. By implanting arsenic (As) ions into the semiconductor substrate 201 under the implantation conditions of an implantation energy of 30 KeV and a dose amount of 3 × 10 ¹⁵ atoms / cm ⁻² , a stripe pattern of the semiconductor substrate 201 is removed. A diffusion layer 206 to be a bit line is formed in the exposed region. Subsequently, a silicon oxide film having a thickness of 100 nm is deposited on the entire surface including the gate electrode structure 216 and the first buried insulating film 204 on the semiconductor substrate 201 by LPCVD. Thereafter, etch back is performed on the deposited silicon oxide film using an etching gas mainly composed of carbon fluoride, and each side surface of the striped pattern including the gate electrode structure 216 and the first buried insulating film 204 is performed. A sidewall insulating film 207 is formed thereon. Subsequently, a metal film made of cobalt is deposited on the entire surface including the stripe pattern on the semiconductor substrate 201 by, for example, a sputtering method or a vacuum evaporation method, and a predetermined heat treatment is performed, so that each gate electrode structure 216 and A silicide layer 208 is formed only on the upper part of each diffusion layer 206.

  Next, as shown in FIG. 15C, a plurality of gate electrode structures 216 arranged in a matrix in a direction intersecting with the diffusion layer 206, that is, in the row direction, are formed on, for example, tungsten ( A contact plug 209 made of W) is formed, and the gate electrode structures 216 arranged in the row direction are electrically connected to each other by the word line 210 to obtain a nonvolatile semiconductor memory device.

  According to the third embodiment, in the nonvolatile semiconductor memory device that captures charges in the floating gate electrode 214, the diffusion layer 206 constituting the bit line can be surely silicided with metal, so that the diffusion layer (bit line) 206 Low resistance can be realized. For this reason, delay due to the resistance of the bit line can be suppressed, so that a high-speed read operation can be realized.

  In addition, since the thermal load (thermal budget) after forming the diffusion layer 206 is small, thermal diffusion in the diffusion layer 206 is also suppressed, so that further miniaturization can be realized.

  Further, although the ONO film is used for the capacitive insulating film 202 in the gate electrode structure 216, the present invention is not limited to this. For example, the capacitor insulating film 202 may be an ON film formed of a lower insulating film 202a made of silicon oxide and an intermediate insulating film 202b made of silicon nitride. Further, it may be a single layer film made of silicon oxide or silicon nitride.

  In the third embodiment, a so-called virtual ground type array structure in which the diffusion layer 206 serving as a bit line is shared with adjacent memory cells (bits) is used. It is also possible to adopt a so-called AND type array structure that is not shared.

  In the third embodiment, cobalt is used as the metal material for forming the silicide layer 208, but other metal materials such as titanium (Ti) or nickel (Ni) can be used.

  Further, although the etch-back method is used to form the first buried insulating film 204 and the second buried insulating film 205, a chemical mechanical polishing (CMP) method can also be used.

(One Modification of Third Embodiment)
Hereinafter, a modification of the third embodiment of the present invention will be described with reference to the drawings.

  FIG. 16 shows a nonvolatile semiconductor memory device according to a modification of the third embodiment of the present invention. In FIG. 16, the same components as those shown in FIG.

  As shown in FIG. 16, in the nonvolatile semiconductor memory device according to this modification, a cap layer 221 made of silicon nitride is provided instead of providing the silicide layer 208 on the upper surface of each gate electrode structure 216. Further, the composition of the sidewall insulating film 217 is silicon nitride instead of silicon oxide.

  As a result, each gate electrode structure 216 is covered with silicon nitride on the upper surface and side surfaces, and therefore, when forming the bit line contact 222 that is electrically connected to each diffusion layer 206 constituting each bit line, Since it can be formed in a consistent manner, further miniaturization of the nonvolatile semiconductor memory device can be realized.

  Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

  17 (a) to 17 (d) and FIGS. 18 (a) to 18 (c) show the order of steps of the method of manufacturing the nonvolatile semiconductor memory device according to the modification of the third embodiment of the present invention. A partial cross-sectional configuration and a perspective configuration are shown.

  First, as shown in FIG. 17A, as in the third embodiment, a tunnel insulating film 213 made of silicon oxide having a film thickness of 5 nm and a film thickness of 100 nm are formed on the main surface of the semiconductor substrate 201. A floating gate forming film made of polycrystalline silicon, a lower insulating film 202a made of silicon oxide with a thickness of 7 nm, an intermediate insulating film 202b made of silicon nitride with a thickness of 15 nm, and an upper insulating film 202c made of silicon nitride with a thickness of 7 nm. A capacitor insulating film 202 having an ONO structure including, and a control gate forming film made of polycrystalline silicon having a thickness of 100 nm are sequentially formed. Subsequently, a cap layer 221 made of silicon nitride having a thickness of 100 nm is deposited on the floating gate formation film by LPCVD. Thereafter, a first mask pattern (not shown) having a stripe-shaped opening pattern extending in the column direction is formed on the deposited cap layer 221 by lithography, and the first mask pattern thus formed is used. The cap layer 221, the capacitor insulating film 202 and the tunnel insulating film 213 are etched with an etching gas mainly containing carbon fluoride, and the control gate forming film and the floating gate electrode are etched with an etching gas mainly containing chlorine. Perform dry etching. Thereby, the cap layer 221 having the stripe pattern extending in the column direction from the control gate forming film, the capacitor insulating film 202 and the floating gate forming film having the cap layer 121 on the upper surface, the control gate forming film 215A, the capacitor insulating film 202, and A floating gate formation film 214A is formed. Here, the tunnel insulating film 213 may be left without being removed.

  Next, as shown in FIG. 17B, after removing the first mask pattern, a silicon oxide film is deposited over the entire surface including the stripe pattern having the cap layer 221 on the semiconductor substrate 201 by LPCVD. Then, etch back is performed on the deposited silicon oxide film using an etching gas mainly composed of carbon fluoride. As a result, the second buried insulating film 205 made of silicon oxide is left in each gap of the stripe pattern including the floating gate forming film 214A, the capacitor insulating film 202, the control gate forming film 215A, and the cap layer 221.

  Next, on the stripe pattern including the cap layer 221 and the second buried insulating film 205 filling the gap of the stripe pattern, a second opening pattern having a stripe-like opening pattern extending in the row direction is formed by lithography. A mask pattern (not shown) is formed, and the cap layer 221 is dry-etched with an etching gas mainly composed of fluorocarbon using the formed second mask pattern. Subsequently, the control gate formation film 215A, the capacitor insulating film 202, and the floating gate electrode 214A are sequentially dry etched. As a result of this dry etching, the control gate formation film 215A and the floating gate formation film 214A, both of which are made of polycrystalline silicon, are mainly etched. Therefore, as shown in FIG. A plurality of gate electrode structures 216 arranged in a matrix and isolated can be obtained from the insulating film 202 and the floating gate formation film 214A. In the dry etching for the cap layer 221 and the capacitor insulating film 202, the cap layer 221 made of silicon nitride and the capacitor insulating film 202 made of ONO are etched with respect to the second buried insulating film 205 made of silicon oxide. However, since the film thickness of the second buried insulating film 205 is sufficiently larger than the film thicknesses of the cap layer 221 and the capacitor insulating film 202, there is no problem.

  Next, as shown in FIG. 17D, after removing the second mask pattern, the entire surface including the cap layer 221 and the second buried insulating film 205 is formed on the semiconductor substrate 201 by LPCVD. A film is deposited, and the deposited silicon nitride film is etched back using an etching gas containing carbon fluoride as a main component. Thus, the first buried insulating film 204 made of silicon nitride is filled in the region between the gate electrode structures 216 adjacent in the row direction.

  Next, as shown in FIG. 18A, wet etching is performed on the second buried insulating film 205 with an aqueous solution containing hydrofluoric acid in a state where the first buried insulating film 204 is formed. The second buried oxide film 205 made of silicon oxide is removed. As a result, the plurality of gate electrode structures 216 arranged in a matrix form are filled with the first embedded insulating film 204 between the gate electrode structures 216 adjacent in the column direction, and extend in the column direction. A stripe pattern is formed. If the tunnel insulating film 213 is not removed in the stripe pattern forming step shown in FIG. 17A, the tunnel insulating film 213 below the second buried oxide film 205 is removed in this step. Also remove.

Next, as illustrated in FIG. 18B, for example, in a direction perpendicular to the main surface of the semiconductor substrate 201 using a stripe pattern formed of the gate electrode structure 216 and the first buried insulating film 204 as a mask. By implanting arsenic (As) ions into the semiconductor substrate 201 under the implantation conditions of an implantation energy of 30 KeV and a dose amount of 3 × 10 ¹⁵ atoms / cm ⁻² , a stripe pattern of the semiconductor substrate 201 is removed. A diffusion layer 206 to be a bit line is formed in the exposed region. Subsequently, a silicon nitride film having a thickness of 100 nm is deposited on the entire surface including the gate electrode structure 216 and the first buried insulating film 204 on the semiconductor substrate 201 by LPCVD. Thereafter, etch back is performed on the deposited silicon oxide film using an etching gas mainly composed of carbon fluoride, and each side surface of the striped pattern including the gate electrode structure 216 and the first buried insulating film 204 is performed. A sidewall insulating film 207 made of silicon nitride is formed thereon. Subsequently, a metal film made of cobalt is deposited on the entire surface including the stripe pattern on the semiconductor substrate 201 by, for example, a sputtering method or a vacuum evaporation method, and a predetermined heat treatment is performed, so that a predetermined heat treatment is performed. Only the silicide layer 208 is formed.

  Next, as shown in FIG. 18C, among the gate electrode structures 216 arranged in a matrix, a plurality of gate electrode structures 216 arranged in the direction intersecting with the diffusion layer 206, that is, in the row direction, are made of tungsten (for example). A contact plug 209 made of W) is formed, and the gate electrode structures 216 arranged in the row direction are electrically connected to each other by the word line 210. Subsequently, a bit line contact 222 is formed on each diffusion layer 206 in a self-aligned manner with a silicide layer 208 interposed therebetween, thereby obtaining a nonvolatile semiconductor memory device.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 19 shows a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. In FIG. 19, the same components as those shown in FIG.

  As shown in FIG. 19, the nonvolatile semiconductor memory device according to the fourth embodiment includes a plurality of gate electrode structures 216 adjacent to each other in the column direction (direction in which the diffusion layer 206 extends). A buried insulating film (inter-gate insulating film) 224 buried in between is replaced with silicon nitride and is made of silicon oxide. Thereby, the manufacturing process of the nonvolatile semiconductor memory device can be simplified as compared with the third embodiment.

  Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

  20 (a) to 20 (c), FIG. 21 (a) and FIG. 21 (b) are partial cross-sectional views in the order of steps of the method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. 1 shows a configuration and a perspective configuration.

  First, as shown in FIG. 20A, as in the third embodiment, a tunnel insulating film 213 made of silicon oxide having a film thickness of 5 nm and a film thickness of 100 nm are formed on the main surface of the semiconductor substrate 201. A floating gate forming film made of polycrystalline silicon, a lower insulating film 202a made of silicon oxide with a thickness of 7 nm, an intermediate insulating film 202b made of silicon nitride with a thickness of 15 nm, and an upper insulating film 202c made of silicon nitride with a thickness of 7 nm. A capacitor insulating film 202 having an ONO structure including, and a control gate forming film made of polycrystalline silicon having a thickness of 100 nm are sequentially formed. Thereafter, a first mask pattern (not shown) having a stripe-shaped opening pattern extending in the row direction is formed on the deposited control gate formation film by lithography, and the first mask pattern thus formed is used. The control gate formation film and the floating gate electrode are dry-etched with an etching gas mainly containing chlorine, and the capacitive insulating film 202 is dry-etched with an etching gas mainly containing carbon fluoride. Thereby, the control gate formation film 215B, the capacitance insulation film 202, and the floating gate formation film 214B having a stripe pattern extending in the row direction are formed from the control gate formation film, the capacitance insulation film 202, and the floating gate formation film. Note that the tunnel insulating film 213 may be removed following the etching of the floating gate formation film 214B.

  Next, as shown in FIG. 20B, after removing the first mask pattern, a silicon oxide film is deposited over the entire surface including the stripe pattern on the semiconductor substrate 201 by LPCVD, and the deposited silicon Etch back is performed on the oxide film using an etching gas mainly composed of carbon fluoride. As a result, the buried insulating film 224 made of silicon oxide is left in each gap of the stripe pattern including the floating gate forming film 214B, the capacitor insulating film 202, and the control gate forming film 215B.

  Next, on the stripe pattern having the control gate formation film 215B and the buried insulating film 224 filling the gap, a stripe shape extending in the direction intersecting the stripe direction of the control gate formation film 215B, that is, the column direction is formed by lithography. A second mask pattern (not shown) having the opening pattern is formed, and using the formed second mask pattern, a control gate formation film 215B made of polycrystalline silicon, a capacitive insulating film 202 that is an ONO film, and Dry etching is performed on the floating gate formation film 214B made of polycrystalline silicon and the buried insulating film 224 made of silicon oxide. At this time, the control gate formation film 215 </ b> B, the floating gate formation film 214 </ b> B, and the buried insulating film 224 may be etched at the same time under the condition that the etching selection ratio between polycrystalline silicon and silicon oxide is small. Alternatively, the etching may be sequentially performed under a condition where the etching selectivity between polycrystalline silicon and silicon oxide is large. Note that the order of the control gate formation film 215B and the like and the buried insulating film 224 are not particularly limited. By this dry etching, as shown in FIG. 20C, a plurality of gate electrode structures arranged in a matrix and isolated from the stripe-shaped control gate formation film 215B, the capacitor insulating film 202, and the floating gate formation film 214B. 216 can be obtained. Thereafter, the tunnel insulating film 213 made of silicon oxide exposed from the stripe pattern is removed by performing wet etching with an aqueous solution containing hydrofluoric acid. Through the above process, the plurality of gate electrode structures 216 arranged in a matrix form a stripe shape extending in the column direction in a state where the gate electrode structures 216 adjacent to each other in the column direction are embedded with the embedded insulating film 224. It becomes a pattern.

Next, as shown in FIG. 21A, the implantation energy is applied in a direction perpendicular to the main surface of the semiconductor substrate 201, for example, using a stripe pattern composed of the gate electrode structure 216 and the buried insulating film 224 as a mask. Is exposed from the stripe pattern of the semiconductor substrate 201 by implanting arsenic (As) ions into the semiconductor substrate 201 under implantation conditions of 30 KeV and a dose of 3 × 10 ¹⁵ atoms / cm ^−2. Then, a diffusion layer 206 to be a bit line is formed. Subsequently, a 100 nm-thickness silicon oxide film is deposited over the entire surface including the gate electrode structure 216 and the buried insulating film 224 on the semiconductor substrate 201 by LPCVD. Thereafter, the deposited silicon oxide film is etched back using an etching gas mainly composed of carbon fluoride, and on each side surface of the stripe-shaped pattern including the gate electrode structure 216 and the buried insulating film 224, Sidewall insulating films 207 are respectively formed. Subsequently, a metal film made of cobalt is deposited on the entire surface including the stripe pattern on the semiconductor substrate 201 by, for example, a sputtering method or a vacuum evaporation method, and a predetermined heat treatment is performed, so that each gate electrode structure 216 and A silicide layer 208 is formed only on the upper part of each diffusion layer 206.

  Next, as shown in FIG. 21B, among the gate electrode structures 216 arranged in rows and columns, a plurality of gate electrode structures 216 arranged in the direction intersecting the diffusion layer 206, that is, in the row direction are formed on, for example, tungsten ( A contact plug 209 made of W) is formed, and the gate electrode structures 216 arranged in the row direction are electrically connected to each other by the word line 210 to obtain a nonvolatile semiconductor memory device.

  According to the fourth embodiment, in the nonvolatile semiconductor memory device that captures charges in the floating gate electrode 214 that forms the gate electrode structure 216, the diffusion layer 206 that forms the bit line can be reliably silicided with metal. The resistance of the diffusion layer (bit line) 206 can be reduced. For this reason, delay due to the resistance of the bit line can be suppressed, so that a high-speed read operation can be realized. In addition, since one type of buried insulating film 224 shown in FIG. 20B is used to the end, the manufacturing process can be simplified, and the manufacturing cost can be reduced.

(One Modification of Fourth Embodiment)
FIG. 22 shows a nonvolatile semiconductor memory device according to a modification of the fourth embodiment of the present invention. In FIG. 22, the same components as those shown in FIGS. 13 and 16 are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 22, in the nonvolatile semiconductor memory device according to this modification, a cap layer 221 made of silicon nitride is provided instead of providing the silicide layer 208 on the upper surface of each gate electrode structure 216. Further, the composition of the sidewall insulating film 217 is silicon nitride instead of silicon oxide.

  As a result, each gate electrode structure 216 is covered with silicon nitride on the upper surface and side surfaces, and therefore, when forming the bit line contact 222 that is electrically connected to each diffusion layer 206 constituting each bit line, Since it can be formed in a consistent manner, miniaturization of the nonvolatile semiconductor memory device can be realized.

  Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

  FIG. 23A to FIG. 23C and FIG. 24A to FIG. 24C show the order of steps of the method of manufacturing the nonvolatile semiconductor memory device according to the modification of the fourth embodiment of the present invention. A partial cross-sectional configuration and a perspective configuration are shown.

  First, as shown in FIG. 23A, as in the third embodiment, a tunnel insulating film 213 made of silicon oxide having a film thickness of 5 nm and a film thickness of 100 nm are formed on the main surface of the semiconductor substrate 201. A floating gate forming film made of polycrystalline silicon, a lower insulating film 202a made of silicon oxide with a thickness of 7 nm, an intermediate insulating film 202b made of silicon nitride with a thickness of 15 nm, and an upper insulating film 202c made of silicon nitride with a thickness of 7 nm. A capacitor insulating film 202 having an ONO structure including, and a control gate forming film made of polycrystalline silicon having a thickness of 100 nm are sequentially formed. Thereafter, a first mask pattern (not shown) having a stripe-shaped opening pattern extending in the row direction is formed on the deposited control gate formation film by lithography, and the first mask pattern thus formed is used. The control gate formation film and the floating gate electrode are dry-etched with an etching gas mainly containing chlorine, and the capacitive insulating film 202 is dry-etched with an etching gas mainly containing carbon fluoride. Thereby, the control gate formation film 215B, the capacitance insulation film 202, and the floating gate formation film 214B having a stripe pattern extending in the row direction are formed from the control gate formation film, the capacitance insulation film 202, and the floating gate formation film. Here, the tunnel insulating film 213 may be removed.

  Next, as shown in FIG. 23B, after removing the first mask pattern, a silicon oxide film is deposited on the entire surface including the stripe pattern on the semiconductor substrate 201 by LPCVD, and the deposited silicon Etch back is performed on the oxide film using an etching gas mainly composed of carbon fluoride. As a result, the buried insulating film 224 made of silicon oxide is left in each gap of the stripe pattern including the floating gate forming film 214B, the capacitor insulating film 202, and the control gate forming film 215B.

  Next, as shown in FIG. 23C, a cap made of silicon nitride having a thickness of 100 nm is formed on the stripe pattern including the control gate formation film 215B and the buried insulating film 224 filling the gap by LPCVD. Layer 221 is deposited over the entire surface.

  Next, a second mask pattern (not shown) having a stripe-shaped opening pattern extending in the direction intersecting the stripe direction of the control gate formation film 215B, that is, the column direction is formed on the cap layer 221 by lithography. The cap layer 221 made of silicon nitride is first dry-etched using the formed second mask pattern, and then the control gate formation film 215B made of polycrystalline silicon, the capacitive insulating film 202 which is an ONO film, and Dry etching is performed on the floating gate formation film 214B made of polycrystalline silicon and the buried insulating film 214 made of silicon oxide. At this time, the control gate formation film 215 </ b> B, the floating gate formation film 214 </ b> B, and the buried insulating film 224 may be etched at the same time under the condition that the etching selection ratio between polycrystalline silicon and silicon oxide is small. Alternatively, the etching may be sequentially performed under a condition where the etching selectivity between polycrystalline silicon and silicon oxide is large. By this dry etching, as shown in FIG. 24A, a plurality of gate electrode structures that are arranged in a matrix and isolated from the stripe-shaped control gate forming film 215B, the capacitive insulating film 202, and the floating gate forming film 214B. 216 can be obtained. Thereafter, the tunnel insulating film 213 made of silicon oxide exposed from the stripe pattern is removed by performing wet etching with an aqueous solution containing hydrofluoric acid. Through the above steps, the plurality of gate electrode structures 216 arranged in a matrix are filled with the buried insulating film 224 between the gate electrode structures 216 adjacent in the column direction, and the cap layer 221 is further formed on the upper surface thereof. Patterning is performed as a stripe pattern extending in the column direction in a continuously formed state.

Next, as shown in FIG. 24B, using the stripe pattern including the cap layer 221 as a mask, for example, the implantation energy is set to 30 KeV in the direction perpendicular to the main surface of the semiconductor substrate 201, and the dose amount is set. Arsenic (As) ions are ion-implanted into the semiconductor substrate 201 under an implantation condition of 3 × 10 ¹⁵ atoms / cm ⁻² to form a diffusion layer that becomes a bit line in a region exposed from the stripe pattern of the semiconductor substrate 201 206 is formed. Subsequently, a 100 nm-thickness silicon oxide film is deposited over the entire surface including the gate electrode structure 216 and the buried insulating film 224 on the semiconductor substrate 201 by LPCVD. Thereafter, the deposited silicon oxide film is etched back using an etching gas containing carbon fluoride as a main component, and each stripe-shaped pattern including the cap layer 221, the gate electrode structure 216, and the buried insulating film 224 is formed. A sidewall insulating film 207 is formed on each side surface. Subsequently, a metal film made of cobalt is deposited on the entire surface including the stripe pattern on the semiconductor substrate 201 by, for example, a sputtering method or a vacuum evaporation method, and a predetermined heat treatment is performed, so that a predetermined heat treatment is performed. Only the silicide layer 208 is formed.

  Next, as shown in FIG. 21B, among the gate electrode structures 216 arranged in rows and columns, a plurality of gate electrode structures 216 arranged in the direction intersecting the diffusion layer 206, that is, in the row direction are formed on, for example, tungsten ( A contact plug 209 made of W) is formed, and the gate electrode structures 216 arranged in the row direction are electrically connected to each other by the word line 210. Subsequently, a bit line contact 222 is formed on each diffusion layer 206 in a self-aligned manner with a silicide layer 208 interposed therebetween, thereby obtaining a nonvolatile semiconductor memory device.

  The nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention can simultaneously realize a high-speed read operation by reducing the resistance of a diffusion layer constituting a bit line and high integration by miniaturizing a semiconductor element, and In the manufacturing process in which the memory part and the logic part are mixedly mounted on one chip, the process can be easily shared, and a stable process can be realized at low cost, and a nonvolatile layer having a diffusion layer in the bit line This is useful for a conductive semiconductor memory device and a method for manufacturing the same.

1 is a partial cross-sectional perspective view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIGS. 4A to 4D are partial cross-sectional perspective views in order of steps showing a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIGS. FIGS. 4A to 4C are partial cross-sectional perspective views in order of steps showing a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIGS. FIG. 6 is a partial cross-sectional perspective view showing a nonvolatile semiconductor memory device according to a modification of the first embodiment of the present invention. (A)-(d) is a partial cross-sectional perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on one modification of the 1st Embodiment of this invention. (A)-(c) is a partial cross-sectional perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the modification of the 1st Embodiment of this invention. FIG. 6 is a partial cross-sectional perspective view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention. (A)-(c) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device based on the 2nd Embodiment of this invention. (A) And (b) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device based on the 2nd Embodiment of this invention. FIG. 16 is a partial cross-sectional perspective view showing a nonvolatile semiconductor memory device according to a modification of the second embodiment of the present invention. (A)-(c) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device concerning the modification of the 2nd Embodiment of this invention. (A)-(c) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device concerning the modification of the 2nd Embodiment of this invention. FIG. 7 is a partial cross-sectional perspective view showing a nonvolatile semiconductor memory device according to a third embodiment of the present invention. (A)-(d) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device based on the 3rd Embodiment of this invention. (A)-(c) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device based on the 3rd Embodiment of this invention. FIG. 10 is a partial cross-sectional perspective view showing a nonvolatile semiconductor memory device according to a modification of the third embodiment of the present invention. (A)-(d) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device concerning the modification of the 3rd Embodiment of this invention. (A)-(c) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the modification of the 3rd Embodiment of this invention. FIG. 6 is a partial cross-sectional perspective view showing a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. (A)-(c) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device based on the 4th Embodiment of this invention. (A) And (b) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device based on the 4th Embodiment of this invention. FIG. 16 is a partial cross-sectional perspective view showing a nonvolatile semiconductor memory device according to a modification of the fourth embodiment of the present invention. (A)-(c) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the modification of the 4th Embodiment of this invention. (A)-(c) is a partial cross section perspective view of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the modification of the 4th Embodiment of this invention. It is sectional drawing which shows the conventional non-volatile semiconductor memory device.

Explanation of symbols

101 Semiconductor substrate (semiconductor region)
102 Gate insulating film 102a Lower insulating film 102b Middle insulating film 102c Upper insulating film 103 Gate electrode (gate electrode structure)
103A Gate electrode forming film 103B Gate electrode forming film 104 First embedded insulating film (inter-gate insulating film: nitride film)
105 Second buried insulating film (oxide film)
106 Diffusion layer (bit line)
107 Side wall insulating film (oxide film)
108 Silicide layer 109 Contact plug 110 Word line 114 Embedded insulating film (inter-gate insulating film: oxide film)
117 Side wall insulating film (nitride film)
121 Cap layer 122 Bit line contact 201 Semiconductor substrate (semiconductor region)
202 Capacitance insulating film 202a Lower insulating film 202b Middle insulating film 202c Upper insulating film 204 First buried insulating film (inter-gate insulating film: nitride film)
205 Second buried insulating film (oxide film)
206 Diffusion layer (bit line)
207 Side wall insulating film (oxide film)
208 Silicide layer 209 Contact plug 210 Word line 213 Tunnel insulating film (gate insulating film)
214 Floating gate electrode 214A Floating gate forming film 214B Floating gate forming film 215 Control gate electrode 215A Control gate forming film 215B Control gate forming film 216 Gate electrode structure 217 Side wall insulating film (nitride film)
221 Cap layer 222 Bit line contact 224 Buried insulating film (inter-gate insulating film: oxide film)

Claims (19)

A plurality of gate electrodes arranged in a matrix and isolated on the semiconductor region, each formed with a gate insulating film interposed between the semiconductor region; and
A plurality of diffusion layers which are bit lines respectively formed in regions between the gate electrodes arranged in the row direction among the plurality of gate electrodes in the upper part of the semiconductor region;
The non-volatile semiconductor memory device, wherein the plurality of diffusion layers have a metal layer or a metal silicide layer on at least an upper part thereof.   The nonvolatile semiconductor memory device according to claim 1, wherein the gate insulating film is a laminated film including an insulating film capable of storing electric charge.   The nonvolatile semiconductor memory device according to claim 2, wherein the stacked film includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. Each of the gate electrodes includes a floating gate electrode, a capacitor insulating film, and a control gate electrode, which are sequentially formed from the semiconductor region side,
The nonvolatile semiconductor memory device according to claim 1, wherein the floating gate electrode accumulates electric charges.   It further includes an inter-gate insulating film formed in a region between the gate electrodes arranged in the column direction among the plurality of gate electrodes and formed of a material that transmits less ultraviolet light than silicon oxide. The nonvolatile semiconductor memory device according to claim 1, wherein:   6. The nonvolatile semiconductor memory device according to claim 1, wherein each of the gate electrodes has a metal layer or a metal silicide layer at least on an upper portion thereof. Each of the gate electrodes has a cap insulating film formed on the upper surface of the gate electrode and a sidewall insulating film formed on the side surface thereof,
6. The device according to claim 1, further comprising a plurality of contact plugs formed in a self-aligned manner on the diffusion layer and electrically connected to the diffusion layer. Nonvolatile semiconductor memory device.   The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor region is made of silicon, and the gate electrode is made of polycrystalline silicon. A method for manufacturing a nonvolatile semiconductor memory device having a plurality of memory cells arranged in a matrix,
Forming a gate insulating film on the semiconductor region;
After forming a gate electrode formation film on the gate insulating film, patterning is performed on the formed gate electrode formation film, and a plurality of gate electrodes arranged in a matrix and isolated from the gate electrode formation film Forming a structure (b);
Forming a first buried insulating film in a region between the gate electrode structures adjacent to each other in the column direction among the plurality of gate electrode structures;
Gates arranged in the row direction among the plurality of gate electrode structures above the semiconductor region by performing ion implantation into the semiconductor region using the gate electrode structures and the first buried insulating film as a mask. A step (d) of forming a plurality of diffusion layers each serving as a bit line in a region between the electrode structures;
And a step (e) of siliciding the upper part of each diffusion layer with a metal. The step (b)
Prior to forming the plurality of gate electrode structures, the formed gate electrode formation film is selectively etched to form a stripe pattern extending in the column direction from the gate electrode formation film Process,
A step of filling each gap between the formed stripe-shaped patterns with a second buried insulating film;
Forming the plurality of gate electrode structures from the stripe pattern while leaving the second buried insulating film formed,
The step (c) includes a step of removing the second buried insulating film and the gate insulating film located under the second buried insulating film after forming the first buried insulating film. The method for manufacturing a nonvolatile semiconductor memory device according to claim 9. The step (b) includes a step of forming a cap insulating film on the gate electrode forming film after forming the gate electrode forming film and before forming the stripe pattern. Patterning the formation film is performed together with the cap insulating film,
The step (d) includes a step of forming a sidewall insulating film on a side surface of the gate electrode structure on the diffusion layer side after forming the plurality of diffusion layers,
After the step (e), the method further includes a step (f) of forming a contact plug electrically connected to each diffusion layer in a self-alignment manner using the cap insulating film and the sidewall insulating film as a mask. The method for manufacturing a nonvolatile semiconductor memory device according to claim 9 or 10.   The semiconductor region is made of silicon, the gate electrode forming film is made of polycrystalline silicon, the first buried insulating film is made of silicon nitride, and the second buried insulating film is made of silicon oxide. The method for manufacturing a nonvolatile semiconductor memory device according to claim 10. A method for manufacturing a nonvolatile semiconductor memory device having a plurality of memory cells arranged in a matrix,
Forming a gate insulating film on the semiconductor region;
Forming a first stripe pattern extending in a row direction from the gate electrode forming film by forming a gate electrode forming film on the gate insulating film and then patterning the formed gate electrode forming film; (B) and
A step (c) of filling each gap between the formed first stripe patterns with a buried insulating film;
The first stripe pattern and the buried insulating film are selectively etched so as to have a second stripe pattern extending in the column direction, so that the stripe pattern is arranged in a matrix and the A step (d) of forming a plurality of gate electrode structures in which the buried insulating film is left between the wall surfaces facing each other in the column direction;
Using each gate electrode structure and the buried insulating film as a mask, ion implantation is performed on the semiconductor region, thereby forming a gate electrode structure aligned in the row direction among the plurality of gate electrode structures above the semiconductor region. Forming a plurality of diffusion layers each serving as a bit line in a region between them (e);
And a step (f) of siliciding the upper part of each diffusion layer with a metal. The step (b) includes a step of forming a cap insulating film on the gate electrode formation film after forming the gate electrode formation film and before forming the first stripe pattern, The gate electrode forming film is patterned together with the cap insulating film,
The step (e) includes a step of forming a sidewall insulating film on a side surface of the gate electrode structure on the diffusion layer side after forming the plurality of diffusion layers,
After the step (f), the method further includes a step (g) of forming a contact plug electrically connected to each diffusion layer in a self-alignment manner using the cap insulating film and the sidewall insulating film as a mask. 14. The method of manufacturing a nonvolatile semiconductor memory device according to claim 13, The gate electrode formation film is made of polycrystalline silicon,
15. The method of manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein the cap insulating film and the sidewall insulating film are made of silicon nitride.   In the step (a), the gate insulating film is formed by sequentially laminating a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on the semiconductor region. Item 14. A method for manufacturing a nonvolatile semiconductor memory device according to Item 9 or 13. The gate electrode formation film is made of polycrystalline silicon,
14. The method of manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein, in the step of siliciding the diffusion layer, the upper portion of each gate electrode structure is also silicidized. The gate insulating film is a tunnel insulating film;
In the step (b), the gate electrode formation film is formed by sequentially laminating a floating gate formation film, a capacitor insulation film, and a control gate formation film on the tunnel insulation film,
The gate electrode structure includes a floating gate electrode formed from the floating gate formation film, the capacitive insulating film, and a control gate electrode formed from the control gate formation film. Item 14. A method for manufacturing a nonvolatile semiconductor memory device according to Item 9 or 13. At least the control gate formation film of the floating gate formation film and the control gate formation film is made of polycrystalline silicon,
19. The method of manufacturing a nonvolatile semiconductor memory device according to claim 18, wherein, in the step of siliciding the diffusion layer, the upper portion of the control gate electrode is also silicidized.

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