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JP2007005561A - Electronic device having double sided mounting circuit substrate with built-in capacitor - Google Patents

Electronic device having double sided mounting circuit substrate with built-in capacitor Download PDF

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JP2007005561A
JP2007005561A JP2005183815A JP2005183815A JP2007005561A JP 2007005561 A JP2007005561 A JP 2007005561A JP 2005183815 A JP2005183815 A JP 2005183815A JP 2005183815 A JP2005183815 A JP 2005183815A JP 2007005561 A JP2007005561 A JP 2007005561A
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circuit board
capacitor
double
electronic device
ground
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JP4486553B2 (en
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Daisuke Mizutani
大輔 水谷
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

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  • Combinations Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting structure which raises mounting density of a semiconductor element and enables a capacitor to be disposed near the semiconductor element in the double sided mounting circuit substrate unit. <P>SOLUTION: The double sided mounting circuit substrate unit 10 has two circuit substrates 12 with a surface for mounting the semiconductor element 11 and a surface exposing a ground layer 14, and a plate-like capacitor which has a power supply layer formed held between two dielectric layers and exposes the ground layer 14 insulated from the power supply layer by the dielectric layer to a surface. The two circuit substrates and the plate-like capacitor are electrically connected, and the plate-like capacitor is inserted between the two circuit substrates disposed such that the ground layers thereof are opposed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、回路基板を用いて半導体素子を高密度に電気接続したキャパシタ内蔵両面実装回路基板を有する電子装置に関する。   The present invention relates to an electronic device having a circuit board with a built-in capacitor in which semiconductor elements are electrically connected with high density using a circuit board.

従来、電子機器に半導体素子を高密度に実装する形態としては、パッケージ基板と呼ばれる小型の回路基板に半導体素子を実装し、その半導体素子を実装したパッケージ基板を、マザーボードと呼ばれる、より大きな回路基板にさらに実装するという、２段階の実装構造が用いられている。マザーボードには電子機器全体の回路が形成される。   Conventionally, as a form of mounting semiconductor elements on an electronic device at a high density, a semiconductor element is mounted on a small circuit board called a package board, and the package board on which the semiconductor element is mounted is referred to as a motherboard, which is a larger circuit board. In this case, a two-stage mounting structure is used. A circuit for the entire electronic device is formed on the motherboard.

これは、半導体素子とマザーボードの配線ルールが、形状、製造方法、要求特性の点で大きく異なるためである。半導体素子表面に形成される入出力用接続端子は、マザーボード表面に形成される入出力用接続端子より微細であるため、両者のインターフェースとして、半導体素子表面に形成された入出力用接続端子と、マザーボード表面に形成された入出力用接続端子の両方を有するパッケージ基板を用いている。   This is because the wiring rules between the semiconductor element and the mother board are greatly different in terms of shape, manufacturing method, and required characteristics. Since the input / output connection terminal formed on the surface of the semiconductor element is finer than the input / output connection terminal formed on the motherboard surface, as an interface between them, the input / output connection terminal formed on the semiconductor element surface, A package substrate having both input / output connection terminals formed on the surface of the motherboard is used.

したがって、マザーボードにおける半導体素子の実装密度を上げる手段として様々な考案がなされている。例えば、特許文献１には、マザーボードにおける半導体素子の実装密度を上げる手段として、半導体素子を実装したフレキシブルプリント配線板を折りたたむことで、半導体素子を積み重ねる構造が提案されている。   Therefore, various ideas have been made as means for increasing the mounting density of semiconductor elements on the mother board. For example, Patent Document 1 proposes a structure in which semiconductor elements are stacked by folding a flexible printed wiring board on which semiconductor elements are mounted as means for increasing the mounting density of semiconductor elements on a motherboard.

一方、特許文献２には、実装面積の増加を少なくしながら、半導体素子近傍にキャパシタを配置するための電子部品の実装構造が提案されている。この構造においては、キャパシタを構成するように、誘電体層の両面に電極層を対向配置し、配線基板上に電子部品を実装し、その上に半導体素子を実装する。半導体素子と配線基板を貫通電極を介して接続するとともに、半導体素子又は配線基板を取り出し電極に接続する。
特開２０００−３０７０５５号公報 特開２０００−３０６７７１号公報 On the other hand, Patent Document 2 proposes an electronic component mounting structure for arranging a capacitor in the vicinity of a semiconductor element while reducing an increase in mounting area. In this structure, so as to constitute a capacitor, electrode layers are arranged opposite to each other on both sides of a dielectric layer, an electronic component is mounted on a wiring board, and a semiconductor element is mounted thereon. The semiconductor element and the wiring board are connected via the through electrode, and the semiconductor element or the wiring board is taken out and connected to the electrode.
JP 2000-307055 A JP 2000-306791 A

ネットワーク機器の高速化，大容量化にともない、半導体素子間の配線距離を短縮し，実装密度を上げることが要求されている。一方、電源スイッチング等による高周波ノイズを除去するには，半導体素子近傍にキャパシタを配設する必要がある。しかし、キャパシタの配設面積は半導体素子の高密度実装の障害となるため、キャパシタの近接配置と半導体素子の高密度実装を両立することが困難であった。   As network devices increase in speed and capacity, it is required to reduce the wiring distance between semiconductor elements and increase the mounting density. On the other hand, in order to remove high frequency noise due to power switching or the like, it is necessary to dispose a capacitor near the semiconductor element. However, since the capacitor area is an obstacle to high-density mounting of semiconductor elements, it is difficult to achieve both close proximity of capacitors and high-density mounting of semiconductor elements.

本発明は、上記の点に鑑みてなされたものであり、両面実装回路基板ユニットにおいて、半導体素子の実装密度を上げると共に、半導体素子近傍にキャパシタを配設することを可能とする実装構造を提供することを目的とする。   The present invention has been made in view of the above points, and in a double-sided mounting circuit board unit, provides a mounting structure capable of increasing the mounting density of semiconductor elements and disposing a capacitor near the semiconductor elements. The purpose is to do.

上記の課題を解決するために、本発明の両面実装回路基板ユニットを有する電子装置は、複数の両面実装回路基板ユニットが搭載された電子装置であって、前記両面実装回路基板ユニットが、半導体素子を実装する一方の面と、グランド層が露出した他方の面とを有する２つの回路基板と、前記２つの回路基板の間に配置され、中心の電源層を挟んで２つの誘電体層が形成されると共に、前記誘電体層の外側に前記電源層から電気的に絶縁されたグランド層を更に有する板状キャパシタとを備え、前記２つの回路基板と前記板状キャパシタとが、それぞれのグランド層を対向するように配置され、グランド層同士が電気的に接続されることを特徴とする。   In order to solve the above problems, an electronic device having a double-sided mounting circuit board unit according to the present invention is an electronic device in which a plurality of double-sided mounting circuit board units are mounted. The two circuit boards having one surface for mounting and the other surface from which the ground layer is exposed, and two dielectric layers formed between the two circuit boards and sandwiching the central power supply layer And a plate capacitor further having a ground layer electrically insulated from the power supply layer outside the dielectric layer, wherein the two circuit boards and the plate capacitor are respectively connected to the ground layers. Are arranged so as to face each other, and the ground layers are electrically connected to each other.

上記の両面実装回路基板ユニットを有する電子装置は、前記板状キャパシタが少なくともその一辺に、電源端子およびグランド端子を有する構成としてもよい。   The electronic device having the above-described double-sided mounted circuit board unit may be configured such that the plate capacitor has a power supply terminal and a ground terminal on at least one side thereof.

上記の両面実装回路基板ユニットを有する電子装置は、各回路基板のグランド層の接続端子部が半導体素子を実装する面の反対側の面に露出させたグランド層のみであり、配線および電源の接続端子部が設けられた回路基板の端部には存在しない構成としてもよい。   In the electronic device having the above-described double-sided mounting circuit board unit, the connection terminal portion of the ground layer of each circuit board is only the ground layer exposed on the surface opposite to the surface on which the semiconductor element is mounted. It is good also as a structure which does not exist in the edge part of the circuit board provided with the terminal part.

上記の両面実装回路基板ユニットを有する電子装置は、前記板状キャパシタとして、電源層の両面に３層以上の誘電体層を有する積層型キャパシタを用いる構成としてもよい。   The electronic device having the above-described double-sided mounted circuit board unit may employ a multilayer capacitor having three or more dielectric layers on both sides of the power supply layer as the plate capacitor.

上記の両面実装回路基板ユニットを有する電子装置は、前記２つの回路基板と前記板状キャパシタとの電気的接続に導電性ペーストを用いる構成としてもよい。   The electronic device having the above-described double-sided mounting circuit board unit may use a conductive paste for electrical connection between the two circuit boards and the plate capacitor.

本発明の両面実装回路基板を有する電子装置においては、半導体素子を実装する面と、グランド層あるいは電源層が露出した面を有する回路基板２枚を、グランド層が露出した面を向かい合わせて配置し、２つの回路基板の間に、グランド層が露出したキャパシタフィルムを挿入して、２つの回路基板とその間に挿入されたキャパシタフィルムを電気的に接続するとともに、２つの回路基板とその間に挿入されたキャパシタフィルムを接着することにより、半導体素子が両面に実装された両面実装回路基板ユニットとすると共に、２つの回路基板の内部にキャパシタ層を内蔵することが可能となる。   In an electronic device having a double-sided mounting circuit board according to the present invention, two circuit boards having a surface on which a semiconductor element is mounted and a surface on which a ground layer or a power supply layer is exposed are arranged with the surface on which the ground layer is exposed facing each other. The capacitor film with the ground layer exposed is inserted between the two circuit boards to electrically connect the two circuit boards and the capacitor film inserted therebetween, and between the two circuit boards. By adhering the capacitor film thus formed, it is possible to form a double-sided mounting circuit board unit in which semiconductor elements are mounted on both sides, and to incorporate a capacitor layer inside two circuit boards.

本発明の両面実装回路基板ユニットは、片面実装回路基板を製造後、回路基板の一面に露出させた電源層あるいはグランド層２つでキャパシタフィルムを挟み込み、電気的に接続する構成を有する。このため、容易かつ低コストにキャパシタを２つの回路基板間に内蔵し、かつ、高密度実装に有効な両面実装回路基板ユニットを提供することが可能となる。   The double-sided mounted circuit board unit according to the present invention has a configuration in which after a single-sided mounted circuit board is manufactured, a capacitor film is sandwiched between two power supply layers or ground layers exposed on one surface of the circuit board and electrically connected. For this reason, it is possible to provide a double-sided mounting circuit board unit in which a capacitor is built in between two circuit boards easily and at low cost and is effective for high-density mounting.

さらに、電源層とグランド層を有するキャパシタフィルムのグランド電極を各回路基板の半導体素子を実装していない面に設けたグランド電極と電気的に接続して、マザーボードのグランド電極と電気的に接続されたキャパシタフィルムのグランド電極をマザーボードにおけるグランド電極の延長とする構成を有する。このため、従来、半導体素子を実装した回路基板の入出力端子において、並列接続によるインダクタンス低減を目的に半数以上を占めていたグランド電極数を、キャパシタフィルムのグランド電極と電気的に接続するための１つにすることで、各回路基板の入出力端子数を半数以下に低減することができる。   Further, the ground electrode of the capacitor film having the power supply layer and the ground layer is electrically connected to the ground electrode provided on the surface of each circuit board where the semiconductor element is not mounted, and is electrically connected to the ground electrode of the motherboard. The capacitor film has a configuration in which the ground electrode of the capacitor film is an extension of the ground electrode on the motherboard. For this reason, the number of ground electrodes, which conventionally accounted for more than half of the input / output terminals of the circuit board on which the semiconductor element is mounted, for the purpose of reducing inductance by parallel connection, is electrically connected to the ground electrode of the capacitor film. By using one, the number of input / output terminals of each circuit board can be reduced to half or less.

本発明を実施するための形態について図面と共に説明する。   A mode for carrying out the present invention will be described with reference to the drawings.

まず、本発明者が特願２００５−０１２９３７号において提案した、両面実装回路基板ユニットの実装構造について、図１を用いて説明する。   First, a mounting structure of a double-sided mounting circuit board unit proposed by the present inventor in Japanese Patent Application No. 2005-012937 will be described with reference to FIG.

図１の両面実装回路基板ユニット２０において、ＬＳＩ等の半導体素子２１が、回路基板２２の表面及び裏面にそれぞれ実装されている。図１の例では、２つの半導体素子２１が上下対称の位置に実装されている。しかし、必ずしも対称の位置に２つの半導体素子２１を配設する必要はない。また、各半導体素子２１の内部配線構造も、必ずしも対称である必要はない。   In the double-sided mounting circuit board unit 20 of FIG. 1, semiconductor elements 21 such as LSI are mounted on the front and back surfaces of the circuit board 22, respectively. In the example of FIG. 1, two semiconductor elements 21 are mounted at positions that are vertically symmetrical. However, it is not always necessary to dispose the two semiconductor elements 21 at symmetrical positions. Further, the internal wiring structure of each semiconductor element 21 is not necessarily symmetrical.

図２は、マザーボードに図１の両面実装回路基板ユニットを複数段スタックして積み重ねて構成した電子装置を示す。   FIG. 2 shows an electronic device configured by stacking the double-sided mounting circuit board units of FIG.

図２に示すように、各両面実装回路基板ユニット２０の両端には、電気的接続用の端子（図示なし）が設けられており、コネクタ４と接続することにより、複数の両面実装回路基板ユニット２０間の電気的接続がなされる。   As shown in FIG. 2, terminals (not shown) for electrical connection are provided at both ends of each double-sided mounting circuit board unit 20, and a plurality of double-sided mounting circuit board units are connected to the connector 4. An electrical connection between the 20 is made.

コネクタ４はマザーボード６と電気的に接続されており、半導体素子２１とマザーボード６上に実装される他の電子部品（図示なし）との間の電気的接続がなされる。   The connector 4 is electrically connected to the motherboard 6, and electrical connection is made between the semiconductor element 21 and other electronic components (not shown) mounted on the motherboard 6.

図２の電子装置１のスタック構造において、回路基板２２の両面に実装された半導体素子２１は、互いに向かい合う配置となる。この向かい合う半導体素子２１の間に生じる空間には、放熱板５が挿入されている。図２の例では、複数の放熱板５の各々が、向かい合う半導体素子２１の間に生じる空間に挿入されているが、これら複数の放熱板５は後方において一体化されるように形成され、放熱板アセンブリを構成している。   In the stack structure of the electronic device 1 of FIG. 2, the semiconductor elements 21 mounted on both surfaces of the circuit board 22 are arranged to face each other. A heat radiating plate 5 is inserted in a space generated between the semiconductor elements 21 facing each other. In the example of FIG. 2, each of the plurality of heat dissipation plates 5 is inserted into a space generated between the semiconductor elements 21 facing each other. It constitutes a plate assembly.

放熱板５の材質は、熱伝導率が高く、安価で、しかも機械加工が容易な材質であることが望ましい。例えば、放熱板５の材質として、アルミニウム、又はアルミニウム合金を用いるとよい。   The material of the heat radiating plate 5 is preferably a material having high thermal conductivity, low cost, and easy machining. For example, as the material of the heat sink 5, aluminum or an aluminum alloy may be used.

電子装置１全体の小型化の観点から、この例における放熱板５の厚さは、１ｍｍ未満に設定されている。放熱板５の表面と半導体素子２１の表面との隙間を埋めるために、放熱用のグリースを予め、半導体素子２１上又は放熱板５の表面に塗布しておいてもよい。   From the viewpoint of miniaturization of the entire electronic device 1, the thickness of the heat sink 5 in this example is set to less than 1 mm. In order to fill a gap between the surface of the heat radiating plate 5 and the surface of the semiconductor element 21, a heat radiating grease may be applied on the semiconductor element 21 or the surface of the heat radiating plate 5 in advance.

図２の電子装置１は、実装された半導体素子の高さ方向に、両面実装回路基板ユニット２０が複数個、スタックして積み重ねられた実装構造を有するとともに、積み重ねられた複数の両面実装回路基板ユニット２０の少なくとも一辺側が開口するように配置され、かつ、両面実装回路基板ユニット２０の端部で、各両面実装回路基板ユニット２０間の電気的な接続を行なうコネクタ４と、スタック構造で互いに対向する半導体素子２１の間に設けられ、各半導体素子２１にそれぞれ接触する冷却構造（放熱板５）を有している。   The electronic device 1 in FIG. 2 has a mounting structure in which a plurality of double-sided mounting circuit board units 20 are stacked and stacked in the height direction of the mounted semiconductor element, and a plurality of stacked double-sided mounting circuit boards. The unit 20 is arranged so that at least one side is open, and at the end of the double-sided mounting circuit board unit 20, the connector 4 for electrical connection between the double-sided mounting circuit board units 20 and the stacking structure face each other. And a cooling structure (heat radiating plate 5) provided between the semiconductor elements 21 to be in contact with each of the semiconductor elements 21.

図３は、図２の電子装置に用いられるコネクタの接続例を示す概略図である。   FIG. 3 is a schematic diagram illustrating a connection example of a connector used in the electronic apparatus of FIG.

図３に示すように、マザーボード６の向かい合う２辺に沿って複数のコネクタピン２４が設けられている。   As shown in FIG. 3, a plurality of connector pins 24 are provided along two opposing sides of the mother board 6.

また、両面実装回路基板ユニット２０の回路基板２２には、その向かい合う２辺に沿って、電気的接続及び位置あわせのための貫通穴２７が形成されている。隣り合う２つの両面実装回路基板ユニット２０の間にそれぞれスペーサ２５が挿入されている。このスペーサ２５にも、回路基板２２の貫通穴２７の位置と対応する位置に、貫通穴２５ｈが形成されている。   Further, the circuit board 22 of the double-sided mounting circuit board unit 20 is formed with through holes 27 for electrical connection and alignment along two opposing sides. Spacers 25 are respectively inserted between two adjacent double-sided mounting circuit board units 20. The spacer 25 is also formed with a through hole 25 h at a position corresponding to the position of the through hole 27 of the circuit board 22.

スペーサ２５の材質は、例えばゴムなどの絶縁体である。スペーサ２５の厚さを調整することにより、隣り合う２つの両面実装回路基板ユニット２０間の距離を調整することができる。   The material of the spacer 25 is an insulator such as rubber. By adjusting the thickness of the spacer 25, the distance between two adjacent double-sided mounting circuit board units 20 can be adjusted.

回路基板２２の貫通穴２７と、スペーサ２５の貫通穴２５ｈとに、マザーボード６の導電性のコネクタピン２４を差し込むことにより、各両面実装回路基板ユニット２０が位置決めされると共に、両面実装回路基板ユニット２０とマザーボード６の間の電気的接続が行われる。   By inserting the conductive connector pins 24 of the mother board 6 into the through holes 27 of the circuit board 22 and the through holes 25h of the spacer 25, each double-side mounted circuit board unit 20 is positioned and the double-side mounted circuit board unit. Electrical connection between 20 and the mother board 6 is made.

両面実装回路基板ユニット２０の回路基板２２に形成された複数の貫通穴２７は、選択的にその内壁に導電処理がなされている。すなわち、各両面実装回路基板ユニット２０は、その回路基板２２内に形成された配線パターン（図示なし）に応じて、導電処理がなされた貫通穴２７と、導電処理がなされない貫通穴２７とを有する。導電処理がなされた貫通穴２７は、その内壁に、例えばめっき処理等により形成される金属層を有する。回路基板２２の配線パターンとコネクタピン２４とが、導電処理のなされた貫通穴２７を介して導通され、各両面実装回路基板ユニット２０間の電気的な接続がなされている。導電処理がなされない貫通穴２７は、もっぱら位置合わせのために形成されている。   The plurality of through holes 27 formed in the circuit board 22 of the double-sided mounting circuit board unit 20 are selectively subjected to conductive treatment on the inner walls thereof. That is, each double-sided mounting circuit board unit 20 includes a through hole 27 that has been subjected to a conductive process and a through hole 27 that has not been subjected to a conductive process according to a wiring pattern (not shown) formed in the circuit board 22. Have. The through hole 27 subjected to the conductive treatment has a metal layer formed on the inner wall thereof, for example, by plating. The wiring pattern of the circuit board 22 and the connector pins 24 are conducted through the through holes 27 subjected to the conductive treatment, and electrical connection between the double-sided mounted circuit board units 20 is made. The through hole 27 that is not subjected to the conductive treatment is formed exclusively for alignment.

このように、両面実装回路基板ユニット２０の回路基板２２に形成された複数の貫通穴２７を選択的に導電処理することにより、複数の両面実装回路基板ユニット２０をスタックして積み重ねられた実装構造における所望の回路基板間の導通を実現することができる。   In this way, a mounting structure in which a plurality of double-sided mounting circuit board units 20 are stacked and stacked by selectively conducting a plurality of through holes 27 formed in the circuit board 22 of the double-sided mounting circuit board unit 20. The desired conduction between the circuit boards can be realized.

図４は、本発明の一実施形態に係るキャパシタ内蔵両面実装回路基板ユニットの構成を示す。図４（ａ）は２つの回路基板とキャパシタフィルムを張り合わせる前の状態を示し、図４（ｂ）は２つの回路基板とキャパシタフィルムを張り合わせてグランド電極間接続が完了した後の状態を示す。   FIG. 4 shows the configuration of a circuit board unit with a built-in capacitor according to an embodiment of the present invention. 4A shows a state before the two circuit boards and the capacitor film are bonded together, and FIG. 4B shows a state after the connection between the ground electrodes is completed by bonding the two circuit boards and the capacitor film. .

図４（ａ）に示すように、ＬＳＩ等の半導体素子１１は、回路基板１２の片面に実装されている。回路基板１２は、半導体素子１１を実装した面と、半導体素子１１を実装していない反対側の面を有し、この反対側の面にグランド電極１４が露出されている。各々半導体素子１１を実装した２つの回路基板１２を、グランド電極１４が露出した面を向かい合わせて配置する。２つの回路基板１２の間に、グランド電極１４が両面に露出したキャパシタフィルム１３を配置する。   As shown in FIG. 4A, a semiconductor element 11 such as an LSI is mounted on one side of a circuit board 12. The circuit board 12 has a surface on which the semiconductor element 11 is mounted and an opposite surface on which the semiconductor element 11 is not mounted, and the ground electrode 14 is exposed on the opposite surface. Two circuit boards 12 each mounted with a semiconductor element 11 are arranged so that the surfaces where the ground electrodes 14 are exposed face each other. A capacitor film 13 with the ground electrode 14 exposed on both sides is disposed between the two circuit boards 12.

図４（ｂ）に示すように、キャパシタフィルム１３を２つの回路基板１２の間に挿入して、回路基板１２とキャパシタフィルム１３の向かい合うグランド電極１４間の電気的な接続を行なうと共に、２つの回路基板１２とキャパシタフィルム１３を接着することにより、キャパシタ内蔵の両面実装回路基板ユニット１０が作製されている。   As shown in FIG. 4B, the capacitor film 13 is inserted between the two circuit boards 12, and electrical connection is made between the ground electrodes 14 facing the circuit board 12 and the capacitor film 13, and the two By bonding the circuit board 12 and the capacitor film 13, the double-sided mounting circuit board unit 10 with a built-in capacitor is produced.

前述したように、従来の実装構造は、個々のキャパシタを別々に回路基板内部に配設する構成や、回路基板内部の電源層・グランド層間をキャパシタとして利用する構成を用いている。個々のキャパシタを歩留まり良く回路基板内部に別々に配設することは困難である。また、キャパシタとして使用する材料が回路基板の製造プロセスに適合する必要があり、低コストでキャパシタ内蔵の回路基板を製造することは困難である。   As described above, the conventional mounting structure uses a configuration in which individual capacitors are separately provided in the circuit board, or a configuration in which the power supply layer / ground layer in the circuit board is used as a capacitor. It is difficult to separately arrange individual capacitors in a circuit board with a high yield. In addition, the material used as the capacitor needs to be compatible with the circuit board manufacturing process, and it is difficult to manufacture a circuit board with a built-in capacitor at low cost.

これに対し、本実施形態では、キャパシタ内蔵両面実装回路基板ユニット１０を複数個マザーボード上にスタックして積み重ねる際の実装構造として、図２及び図３の実装構造を採用する。   On the other hand, in the present embodiment, the mounting structure shown in FIGS. 2 and 3 is adopted as a mounting structure when a plurality of double-sided mounting circuit board units 10 with built-in capacitors are stacked on the motherboard.

この場合、図３の構成例と同様に、図４（ｂ）の両面実装回路基板ユニット１０において回路基板１２の両端には、電気的接続用の端子１２ａが設けられている。マザーボード６上に複数の両面実装回路基板ユニット１０をスタックして積み重ねた実装構造とした場合に、マザーボード６のコネクタピン２４と、各両面実装回路基板ユニット１０の電気的接続用の端子１２ａとの電気的接続を容易に行うことができる。   In this case, similarly to the configuration example of FIG. 3, terminals 12a for electrical connection are provided at both ends of the circuit board 12 in the double-sided mounting circuit board unit 10 of FIG. 4B. In the case of a mounting structure in which a plurality of double-sided mounting circuit board units 10 are stacked and stacked on the mother board 6, the connector pins 24 of the mother board 6 and the electrical connection terminals 12a of each double-sided mounting circuit board unit 10 Electrical connection can be made easily.

また、図３のコネクタの接続例と同様に、図４（ｂ）の両面実装回路基板ユニット１０において、回路基板１２には、その向かい合う２辺に沿って、電気的接続及び位置あわせのために複数の貫通穴（図示なし）を形成しておくとよい。隣り合う２つの両面実装回路基板ユニット１０の間にそれぞれスペーサ（図示なし）を挿入する。このスペーサにも、回路基板１２の貫通穴の位置と対応する位置に、貫通穴が形成されている。   As in the connector connection example of FIG. 3, in the double-sided mounting circuit board unit 10 of FIG. 4B, the circuit board 12 is provided for electrical connection and alignment along two opposite sides. A plurality of through holes (not shown) may be formed in advance. Spacers (not shown) are respectively inserted between two adjacent double-sided mounting circuit board units 10. Also in this spacer, through holes are formed at positions corresponding to the positions of the through holes of the circuit board 12.

回路基板１２の貫通穴と、スペーサの貫通穴とに、マザーボード６の導電性のコネクタピン２４を差し込むことにより、各両面実装回路基板ユニット１０が位置決めされると共に、両面実装回路基板ユニット１０とマザーボード６の間の電気的接続が行われる。さらに、図３のコネクタの接続例と同様に、図４（ｂ）の両面実装回路基板ユニット１０の回路基板１２に形成される複数の貫通穴は、選択的にその内壁に導電処理がなされている。   By inserting the conductive connector pins 24 of the mother board 6 into the through holes of the circuit board 12 and the through holes of the spacer, each double-side mounted circuit board unit 10 is positioned, and the double-side mounted circuit board unit 10 and the mother board are positioned. The electrical connection between 6 is made. Further, similarly to the connection example of the connector in FIG. 3, the plurality of through holes formed in the circuit board 12 of the double-sided mounting circuit board unit 10 in FIG. Yes.

この実装構造を用いることにより、片面実装回路基板を製造後、２つの回路基板１２の一面に露出させた電源層又はグランド層にてキャパシタフィルム１３を挟み込み、電気的に接続する構成を有する。このため、容易かつ低コストに、キャパシタを半導体素子１１近傍の位置で回路基板１２間に内蔵し、かつ、高密度実装に有効な両面実装回路基板ユニットを提供することが可能となる。   By using this mounting structure, the capacitor film 13 is sandwiched between the power supply layer or the ground layer exposed on one surface of the two circuit boards 12 after the single-sided mounting circuit board is manufactured and electrically connected. For this reason, it is possible to provide a double-sided mounting circuit board unit that incorporates a capacitor between the circuit boards 12 at a position near the semiconductor element 11 and that is effective for high-density mounting, easily and at low cost.

図６は、本発明のキャパシタ内蔵両面実装回路基板ユニットに用いられる回路基板の構成例を示す平面図である。   FIG. 6 is a plan view showing a configuration example of a circuit board used in the double-sided mounting circuit board unit with a built-in capacitor according to the present invention.

図６に示すように、この回路基板１２において、ＬＳＩ等の半導体素子１１を実装する面の中央部には、複数のＬＳＩ実装用パッド３２が形成されている。回路基板１２のＬＳＩ実装用パッド３２と半導体素子１１との間の電気的な接続はバンプ等を介して行われる。   As shown in FIG. 6, in this circuit board 12, a plurality of LSI mounting pads 32 are formed at the center of the surface on which the semiconductor element 11 such as an LSI is mounted. Electrical connection between the LSI mounting pad 32 of the circuit board 12 and the semiconductor element 11 is made through bumps or the like.

また、この回路基板１２には、その向かい合う２辺に沿って、上述した複数の貫通穴上に、複数の信号接続用パッド３４が形成されている。各信号接続用パッド３４は、回路基板１２上に形成された配線パターンにより、対応するＬＳＩ実装用パッド３２と接続されている。   The circuit board 12 has a plurality of signal connection pads 34 formed on the plurality of through holes described above along two opposite sides thereof. Each signal connection pad 34 is connected to a corresponding LSI mounting pad 32 by a wiring pattern formed on the circuit board 12.

図３の構成例と同様に、図６の回路基板１２の上述した複数の貫通穴の位置と対応する位置に、各信号接続用パッド３４を配置することで、回路基板１２とマザーボード６との間の電気的な接続を、コネクタピン２４を介して容易に行うことができる。   Similar to the configuration example of FIG. 3, the signal connection pads 34 are arranged at positions corresponding to the above-described positions of the plurality of through holes of the circuit board 12 of FIG. 6. The electrical connection between them can be easily performed via the connector pins 24.

図７は、本発明のキャパシタ内蔵両面実装回路基板ユニットに用いられる積層型キャパシタの構成を示す。   FIG. 7 shows the configuration of a multilayer capacitor used in the double-sided mounting circuit board unit with a built-in capacitor according to the present invention.

図７の積層型キャパシタ１３は、くし形状の電源電極３６とくし形状のグランド電極３８とを互いに向かい合うように配置して、誘電体３７内に埋め込むことにより形成されている。この積層型キャパシタ１３において、片方の面に電源電極３６が露出されており、他方の面にグランド電極３８が露出されている。   The multilayer capacitor 13 of FIG. 7 is formed by disposing a comb-shaped power supply electrode 36 and a comb-shaped ground electrode 38 so as to face each other and burying them in a dielectric 37. In the multilayer capacitor 13, the power supply electrode 36 is exposed on one side, and the ground electrode 38 is exposed on the other side.

上述した図４の実施形態と同様に、図７の積層型キャパシタ１３を２つの回路基板１２の間に挿入して、各回路基板１２と積層型キャパシタ１３の向かい合うグランド電極又は電源電極間の電気的な接続を行うと共に、２つの回路基板１２と積層型キャパシタ１３を接着することで、キャパシタ内蔵の両面実装回路基板ユニット１０を作成することができる。   Similar to the above-described embodiment of FIG. 4, the multilayer capacitor 13 of FIG. 7 is inserted between the two circuit boards 12, and the electric power between the ground electrodes or the power supply electrodes facing each circuit board 12 and the multilayer capacitor 13. By connecting the two circuit boards 12 and the multilayer capacitor 13, the double-sided mounting circuit board unit 10 with a built-in capacitor can be created.

図７の積層型キャパシタ１３を両面実装回路基板ユニット１０に内蔵することにより、容易かつ低コストに、キャパシタを回路基板に内蔵し、かつ、高密度実装に有効な両面実装回路基板ユニットを提供することが可能となる。   By providing the multilayer capacitor 13 of FIG. 7 in the double-sided mounting circuit board unit 10, a double-sided mounting circuit board unit in which the capacitor is easily built in the circuit board and effective for high-density mounting is provided. It becomes possible.

次に、図５は、本発明の他の実施形態に係るキャパシタ内蔵両面実装回路基板ユニットの構成を示す。   Next, FIG. 5 shows a configuration of a double-sided mounting circuit board unit with a built-in capacitor according to another embodiment of the present invention.

図５（ａ）は２つの回路基板とキャパシタフィルムを張り合わせる前の状態を示し、図５（ｂ）は２つの回路基板とキャパシタフィルムを張り合わせてグランド電極間接続が完了した後の状態を示す。   5A shows a state before the two circuit boards and the capacitor film are bonded together, and FIG. 5B shows a state after the connection between the ground electrodes is completed by bonding the two circuit boards and the capacitor film. .

図５（ａ）に示すように、ＬＳＩ等の半導体素子１１が、回路基板１２の片面に実装されている。回路基板１２は、半導体素子１１を実装した面と、半導体素子１１を実装していない反対側の面を有し、この反対側の面にグランド電極１４が露出している。各々半導体素子１１を実装した２つの回路基板１２を、グランド電極１４が露出した面を向かい合わせて配置する。２つの回路基板１２の間に、グランド電極１４が両面に露出したキャパシタフィルム１３ａを配置する。   As shown in FIG. 5A, a semiconductor element 11 such as an LSI is mounted on one side of a circuit board 12. The circuit board 12 has a surface on which the semiconductor element 11 is mounted and an opposite surface on which the semiconductor element 11 is not mounted, and the ground electrode 14 is exposed on the opposite surface. Two circuit boards 12 each mounted with a semiconductor element 11 are arranged so that the surfaces where the ground electrodes 14 are exposed face each other. A capacitor film 13a with the ground electrode 14 exposed on both sides is disposed between the two circuit boards 12.

キャパシタフィルム１３ａは、表面及び裏面に露出させたグランド層１４と、高誘電率を有する樹脂にて形成した２つの樹脂層１５の間に挿入された、導電性金属にて形成した電源層１６とを含む、少なくとも５層の層構造を有している。各樹脂層１５の高誘電率を有する樹脂として、誘電率１０以上の材料（ε＞１０）が望ましい。   The capacitor film 13a includes a ground layer 14 exposed on the front and back surfaces, and a power supply layer 16 formed of a conductive metal inserted between two resin layers 15 formed of a resin having a high dielectric constant. And a layer structure of at least 5 layers. As the resin having a high dielectric constant of each resin layer 15, a material having a dielectric constant of 10 or more (ε> 10) is desirable.

図５（ｂ）に示すように、キャパシタフィルム１３ａのグランド電極１４は、各回路基板１２のグランド電極１４と向かい合わせに配置されて、電気的接続が行なわれると共に、導電性接着剤１７によって、各回路基板１２とキャパシタフィルム１３ａとを接着することにより、キャパシタ内蔵の両面実装回路基板ユニット１０Ａが作製されている。   As shown in FIG. 5 (b), the ground electrode 14 of the capacitor film 13a is arranged facing the ground electrode 14 of each circuit board 12 to be electrically connected, and by the conductive adhesive 17, By bonding each circuit board 12 and the capacitor film 13a, a double-sided mounted circuit board unit 10A with a built-in capacitor is manufactured.

また、このキャパシタフィルム１３ａには、高誘電率を有する樹脂の代わりに、無機絶縁材料を用いても良い。導電性接着剤１７を用いた接着においては、回路基板１２、キャパシタフィルム１３ａともに、基板短部の接続端子部を除き、グランド電極以外の露出面は絶縁体であるため、工業的な製造において導電性接着剤１７を用いて、容易に電気的接続と接着を行なうことができる。   In addition, an inorganic insulating material may be used for the capacitor film 13a instead of the resin having a high dielectric constant. In the adhesion using the conductive adhesive 17, both the circuit board 12 and the capacitor film 13a except for the connection terminal part of the short part of the board except for the ground electrode are insulators. Electrical connection and adhesion can be easily performed by using the adhesive 17.

また、図３の構成例と同様に、図５（ｂ）の両面実装回路基板ユニット１０Ａにおいて回路基板１２の両端には、電気的接続用の端子１２ａが設けられている。マザーボード６上に複数の両面実装回路基板ユニット１０をスタックして積み重ねた実装構造とした場合に、マザーボード６のコネクタピン２４と、各両面実装回路基板ユニット１０Ａの電気的接続用の端子１２ａとの電気的接続を容易に行うことができる。   As in the configuration example of FIG. 3, terminals 12a for electrical connection are provided at both ends of the circuit board 12 in the double-sided mounting circuit board unit 10A of FIG. In the case of a mounting structure in which a plurality of double-sided mounting circuit board units 10 are stacked and stacked on the mother board 6, the connector pins 24 of the mother board 6 and the terminals 12a for electrical connection of each double-sided mounting circuit board unit 10A Electrical connection can be made easily.

また、図３のコネクタの接続例と同様に、図５（ｂ）の両面実装回路基板ユニット１０Ａにおいて、回路基板１２には、その向かい合う２辺に沿って、電気的接続及び位置あわせのために複数の貫通穴（図示なし）を形成しておくとよい。隣り合う２つの両面実装回路基板ユニット１０Ａの間にそれぞれスペーサ（図示なし）を挿入する。このスペーサにも、回路基板１２の貫通穴の位置と対応する位置に、貫通穴が形成されている。   Similarly to the connector connection example of FIG. 3, in the double-sided mounting circuit board unit 10A of FIG. 5B, the circuit board 12 is electrically connected and aligned along the two opposite sides. A plurality of through holes (not shown) may be formed. Spacers (not shown) are respectively inserted between two adjacent double-sided mounting circuit board units 10A. Also in this spacer, through holes are formed at positions corresponding to the positions of the through holes of the circuit board 12.

回路基板１２の貫通穴と、スペーサの貫通穴とに、マザーボード６の導電性のコネクタピン２４を差し込むことにより、各両面実装回路基板ユニット１０Ａが位置決めされると共に、両面実装回路基板ユニット１０Ａとマザーボード６の間の電気的接続が行われる。さらに、図３のコネクタの接続例と同様に、図５（ｂ）の両面実装回路基板ユニット１０Ａの回路基板１２に形成される複数の貫通穴は、選択的にその内壁に導電処理がなされている。   By inserting the conductive connector pins 24 of the mother board 6 into the through holes of the circuit board 12 and the through holes of the spacer, each double-sided mounted circuit board unit 10A is positioned, and the double-sided mounted circuit board unit 10A and the mother board are positioned. The electrical connection between 6 is made. Further, similarly to the connection example of the connector in FIG. 3, the plurality of through holes formed in the circuit board 12 of the double-sided mounting circuit board unit 10A in FIG. Yes.

従って、図５の実施形態の両面実装回路基板ユニット１０Ａによれば、上述の図４の実施形態と同様の効果を得ることができる。   Therefore, according to the double-sided mounted circuit board unit 10A of the embodiment of FIG. 5, the same effects as those of the embodiment of FIG. 4 described above can be obtained.

また、本実施形態の両面実装回路基板においては、電源層とグランド層を有するキャパシタフィルムのグランド電極を回路基板の半導体を実装していない面に設けたグランド電極と電気的に接続して、マザーボードのグランド電極と電気的に接続されたキャパシタフィルムのグランド電極をマザーボードにおけるグランド電極の延長とする構成を有する。このため、従来、半導体素子を実装した回路基板の入出力端子において、並列接続によるインダクタンス低減を目的に半数以上を占めていたグランド電極数を、キャパシタフィルムのグランド電極と電気的に接続するための一つにすることで、回路基板の入出力端子数を半数以下に低減することができる。   Further, in the double-sided mounting circuit board of the present embodiment, the ground electrode of the capacitor film having the power supply layer and the ground layer is electrically connected to the ground electrode provided on the surface of the circuit board where the semiconductor is not mounted, The ground electrode of the capacitor film electrically connected to the ground electrode is an extension of the ground electrode on the motherboard. For this reason, the number of ground electrodes, which conventionally accounted for more than half of the input / output terminals of the circuit board on which the semiconductor element is mounted, for the purpose of reducing inductance by parallel connection, is electrically connected to the ground electrode of the capacitor film. By using one, the number of input / output terminals of the circuit board can be reduced to half or less.

以上の如く、本明細書は以下の発明を開示する。
（付記１）
複数の両面実装回路基板ユニットが搭載された電子装置であって、
前記両面実装回路基板ユニットは、
半導体素子を実装する一方の面と、グランド層が露出した他方の面とを有する２つの回路基板と、
前記２つの回路基板の間に配置され、中心の電源層を挟んで２つの誘電体層が形成されると共に、前記誘電体層の外側に前記電源層から電気的に絶縁されたグランド層を更に有する板状キャパシタと
を備え、前記２つの回路基板と前記板状キャパシタとが、それぞれのグランド層を対向するように配置され、グランド層同士が電気的に接続されることを特徴とする電子装置。
（付記２）
前記板状キャパシタが少なくともその一辺に、電源端子およびグランド端子を有することを特徴とする付記１記載の電子装置。
（付記３）
各回路基板のグランド層の接続端子部が、半導体素子を実装する面の反対側の面に露出させたグランド層のみであり、配線および電源の接続端子部が設けられた回路基板の端部には存在しないことを特徴とする付記２記載の電子装置。
（付記４）
前記板状キャパシタとして、電源層の両面に３層以上の誘電体層を有する積層型キャパシタを用いることを特徴とする付記１記載の電子装置。
（付記５）
前記２つの回路基板と前記板状キャパシタとの電気的接続に導電性ペーストを用いることを特徴とする付記１記載の電子装置。
（付記６）
半導体素子を実装する一方の面と、グランド層が露出した他方の面とを有する２つの回路基板と、
前記２つの回路基板の間に配置され、中心の電源層を挟んで２つの誘電体層が形成されると共に、前記誘電体層の外側に前記電源層から電気的に絶縁されたグランド層を更に有する板状キャパシタと
を備え、前記２つの回路基板と前記板状キャパシタとが、それぞれのグランド層を対向するように配置され、グランド層同士が電気的に接続されることを特徴とする両面実装回路基板ユニット。
（付記７）
前記板状キャパシタが少なくともその一辺に、電源端子およびグランド端子を有することを特徴とする付記６記載の両面実装回路基板ユニット。
（付記８）
各回路基板のグランド層の接続端子部が、半導体素子を実装する面の反対側の面に露出させたグランド層のみであり、配線および電源の接続端子部が設けられた回路基板の端部には存在しないことを特徴とする付記７記載の両面実装回路基板ユニット。
（付記９）
前記板状キャパシタとして、電源層の両面に３層以上の誘電体層を有する積層型キャパシタを用いることを特徴とする付記６乃至８のいずれか一項に記載の両面実装回路基板ユニット。
（付記１０）
前記２つの回路基板と前記板状キャパシタとの電気的接続に導電性ペーストを用いることを特徴とする付記６乃至９のいずれか一項に記載の両面実装回路基板ユニット。 As described above, the present specification discloses the following invention.
(Appendix 1)
An electronic device on which a plurality of double-sided mounting circuit board units are mounted,
The double-sided mounting circuit board unit is
Two circuit boards having one surface on which a semiconductor element is mounted and the other surface on which the ground layer is exposed;
Two dielectric layers are formed between the two circuit boards, with a central power supply layer interposed therebetween, and a ground layer electrically insulated from the power supply layer is further provided outside the dielectric layer. An electronic device, wherein the two circuit boards and the plate capacitor are disposed so as to face each other, and the ground layers are electrically connected to each other. .
(Appendix 2)
The electronic device according to claim 1, wherein the plate capacitor has a power supply terminal and a ground terminal on at least one side thereof.
(Appendix 3)
The connection terminal part of the ground layer of each circuit board is only the ground layer exposed on the surface opposite to the surface on which the semiconductor element is mounted, and is connected to the end of the circuit board provided with the connection terminal part of the wiring and power supply. The electronic device according to appendix 2, wherein the electronic device does not exist.
(Appendix 4)
2. The electronic device according to claim 1, wherein a multilayer capacitor having three or more dielectric layers on both sides of the power supply layer is used as the plate capacitor.
(Appendix 5)
The electronic device according to appendix 1, wherein a conductive paste is used for electrical connection between the two circuit boards and the plate capacitor.
(Appendix 6)
Two circuit boards having one surface on which a semiconductor element is mounted and the other surface on which the ground layer is exposed;
Two dielectric layers are formed between the two circuit boards, with a central power supply layer interposed therebetween, and a ground layer electrically insulated from the power supply layer is further provided outside the dielectric layer. A double-sided mounting, wherein the two circuit boards and the plate-like capacitor are disposed so as to face each other, and the ground layers are electrically connected to each other. Circuit board unit.
(Appendix 7)
The double-sided mounting circuit board unit according to appendix 6, wherein the plate capacitor has a power supply terminal and a ground terminal on at least one side thereof.
(Appendix 8)
The connection terminal part of the ground layer of each circuit board is only the ground layer exposed on the surface opposite to the surface on which the semiconductor element is mounted, and is connected to the end of the circuit board provided with the connection terminal part of the wiring and power supply. The double-sided mounting circuit board unit according to appendix 7, wherein there is no existing.
(Appendix 9)
The double-sided mounted circuit board unit according to any one of appendices 6 to 8, wherein a multilayer capacitor having three or more dielectric layers on both sides of a power supply layer is used as the plate capacitor.
(Appendix 10)
The double-sided mounting circuit board unit according to any one of appendices 6 to 9, wherein a conductive paste is used for electrical connection between the two circuit boards and the plate capacitor.

従来の両面実装回路基板の構成を示す側面図である。It is a side view which shows the structure of the conventional double-sided mounting circuit board. マザーボードに図１の両面実装回路基板を複数段スタックして構成した電子装置の側面図である。FIG. 2 is a side view of an electronic device configured by stacking a plurality of double-sided mounting circuit boards of FIG. 1 on a motherboard. 図２の電子装置に用いられるコネクタの接続例を示す概略図である。It is the schematic which shows the example of a connection of the connector used for the electronic device of FIG. 本発明の一実施形態に係るキャパシタ内蔵両面実装回路基板ユニットの構成を示す図である。It is a figure which shows the structure of the circuit board unit with a built-in capacitor which concerns on one Embodiment of this invention. 本発明の他の実施形態に係るキャパシタ内蔵両面実装回路基板ユニットの構成を示す図である。It is a figure which shows the structure of the circuit board unit with a built-in capacitor which concerns on other embodiment of this invention. 本発明のキャパシタ内蔵両面実装回路基板ユニットに用いられる回路基板の構成を示す平面図である。It is a top view which shows the structure of the circuit board used for the circuit board unit with a built-in capacitor of this invention. 本発明のキャパシタ内蔵両面実装回路基板ユニットに用いられる積層型キャパシタの構成を示す側面図である。It is a side view which shows the structure of the multilayer capacitor used for the circuit board unit with a built-in capacitor of this invention.

符号の説明Explanation of symbols

１ 電子装置
４ コネクタ
５ 放熱板
６ マザーボード
１０、１０Ａ 両面実装回路基板ユニット
１１ 半導体素子
１２ 回路基板
１２ａ 端子接続部
１３、１３ａ キャパシタフィルム
１４ グランド電極
１５ 樹脂層
１６ 電源層
１７ 導電性接着剤
２０ 両面実装回路基板ユニット
２１ 半導体素子
２２ 回路基板
２４ コネクタピン
２５ スペーサ
２５ｈ 貫通穴
２７ 貫通穴
DESCRIPTION OF SYMBOLS 1 Electronic device 4 Connector 5 Heat sink 6 Mother board 10, 10A Double-sided mounting circuit board unit 11 Semiconductor element 12 Circuit board 12a Terminal connection part 13, 13a Capacitor film 14 Ground electrode 15 Resin layer 16 Power supply layer 17 Conductive adhesive 20 Double-sided mounting Circuit board unit 21 Semiconductor element 22 Circuit board 24 Connector pin 25 Spacer 25h Through hole 27 Through hole

Claims (5)

複数の両面実装回路基板ユニットが搭載された電子装置であって、
前記両面実装回路基板ユニットは、
半導体素子を実装する一方の面と、グランド層が露出した他方の面とを有する２つの回路基板と、
前記２つの回路基板の間に配置され、中心の電源層を挟んで２つの誘電体層が形成されると共に、前記誘電体層の外側に前記電源層から電気的に絶縁されたグランド層を更に有する板状キャパシタと
を備え、前記２つの回路基板と前記板状キャパシタとが、それぞれのグランド層を対向するように配置され、グランド層同士が電気的に接続されることを特徴とする電子装置。 An electronic device on which a plurality of double-sided mounting circuit board units are mounted,
The double-sided mounting circuit board unit is
Two circuit boards having one surface on which a semiconductor element is mounted and the other surface on which the ground layer is exposed;
Two dielectric layers are formed between the two circuit boards, with a central power supply layer interposed therebetween, and a ground layer electrically insulated from the power supply layer is further provided outside the dielectric layer. An electronic device, wherein the two circuit boards and the plate capacitor are disposed so as to face each other, and the ground layers are electrically connected to each other. . 前記板状キャパシタは少なくともその一辺に、電源端子およびグランド端子を有することを特徴とする請求項１記載の電子装置。   2. The electronic device according to claim 1, wherein the plate capacitor has a power supply terminal and a ground terminal on at least one side thereof. 各回路基板のグランド層の接続端子部が、半導体素子を実装する面の反対側の面に露出させたグランド層のみであり、配線および電源の接続端子部が設けられた回路基板の端部には存在しないことを特徴とする請求項２記載の電子装置。   The connection terminal portion of the ground layer of each circuit board is only the ground layer exposed on the surface opposite to the surface on which the semiconductor element is mounted, and is connected to the end portion of the circuit board provided with the connection terminal portions for wiring and power The electronic device according to claim 2, wherein the electronic device does not exist. 前記板状キャパシタとして、電源層の両面に３層以上の誘電体層を有する積層型キャパシタを用いることを特徴とする請求項１乃至３のいずれか一項に記載の電子装置。   4. The electronic device according to claim 1, wherein a multilayer capacitor having three or more dielectric layers on both surfaces of a power supply layer is used as the plate capacitor. 5. 前記２つの回路基板と前記板状キャパシタとの電気的接続に導電性ペーストを用いることを特徴とする請求項１乃至４のいずれか一項に記載の電子装置。
5. The electronic device according to claim 1, wherein a conductive paste is used for electrical connection between the two circuit boards and the plate capacitor. 6.
JP2005183815A 2005-06-23 2005-06-23 Electronic device having double-sided mounting circuit board with built-in capacitor Expired - Fee Related JP4486553B2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010079445A (en) * 2008-09-24 2010-04-08 Toshiba Corp Ssd device
JP2010245269A (en) * 2009-04-06 2010-10-28 Nec Corp Semiconductor device
CN109801889A (en) * 2017-11-16 2019-05-24 富士电机株式会社 Power semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11168157A (en) * 1997-10-01 1999-06-22 Toshiba Corp Multi-chip semiconductor device
JP2000208669A (en) * 1999-01-18 2000-07-28 Rohm Co Ltd Structure of hybrid integrated circuit device
JP2004055769A (en) * 2002-07-18 2004-02-19 Fujitsu Ltd Semiconductor device
JP2004288834A (en) * 2003-03-20 2004-10-14 Fujitsu Ltd Mounting method and structure for electronic component, and package board
JP2004311987A (en) * 2003-03-27 2004-11-04 Tdk Corp Multilayered substrate
JP2005150443A (en) * 2003-11-17 2005-06-09 Sharp Corp Laminated semiconductor device and its manufacturing method
JP2006202975A (en) * 2005-01-20 2006-08-03 Fujitsu Ltd Electronic device with cooling structure for high-density mounting

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11168157A (en) * 1997-10-01 1999-06-22 Toshiba Corp Multi-chip semiconductor device
JP2000208669A (en) * 1999-01-18 2000-07-28 Rohm Co Ltd Structure of hybrid integrated circuit device
JP2004055769A (en) * 2002-07-18 2004-02-19 Fujitsu Ltd Semiconductor device
JP2004288834A (en) * 2003-03-20 2004-10-14 Fujitsu Ltd Mounting method and structure for electronic component, and package board
JP2004311987A (en) * 2003-03-27 2004-11-04 Tdk Corp Multilayered substrate
JP2005150443A (en) * 2003-11-17 2005-06-09 Sharp Corp Laminated semiconductor device and its manufacturing method
JP2006202975A (en) * 2005-01-20 2006-08-03 Fujitsu Ltd Electronic device with cooling structure for high-density mounting

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010079445A (en) * 2008-09-24 2010-04-08 Toshiba Corp Ssd device
JP2010245269A (en) * 2009-04-06 2010-10-28 Nec Corp Semiconductor device
CN109801889A (en) * 2017-11-16 2019-05-24 富士电机株式会社 Power semiconductor device
CN109801889B (en) * 2017-11-16 2023-09-22 富士电机株式会社 Semiconductor device for electric power

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