JP2007004364A - Debug system, debug method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an interactive debug function via a communication port if an abnormal condition occurs in a debug objective processor in a multiprocessor system composed of a plurality of processors. <P>SOLUTION: A reset notification/operation status monitoring device 4 detecting an abnormal condition occurring in the debug objective processor A restarts it and notifies the fact to a processor B. In restarting, a debug means 20 installed inside the debugger side processor B changes normal start instruction data into stop status instruction data in permission/prohibition information complying with another processor inside an operation permission/prohibition information area 5. In receipt of notification notifying that restart of the debug objective processor is carried out from the reset notification/operation status monitoring device 4, the debug means 20 gives a connection destination changing instruction, which instructs connection to a host side debug application 11, to a communication port 1 for communication with an external host machine 8. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a debugging system, a debugging method, and a program in a multiprocessor system (parallel processing system) having a plurality of execution units (processors), and in particular, using one processor among a plurality of processors as a debugger-side processor, The present invention relates to a debugging system, a debugging method, and a program for performing debugging when an abnormality occurs in another debug target processor.

  In recent years, the scale of programs to be developed has been increasing year by year, and the time required for debugging work has a greater influence on the product development schedule. For this reason, construction of an environment that can be debugged efficiently is desired. As a technique for efficient debugging, there is a method using a dedicated diagnostic processor for performing debugging as in the debugging system described in Patent Document 1 (see, for example, Patent Document 1).

  However, such a debugging system uses a dedicated diagnostic processor, and thus wastes hardware resources that are used only during debugging. In particular, when debugging while performing communication processing with an external host terminal, the diagnostic processor is required to have a high processing speed, and valuable hardware resources are allocated for debugging means that are not used during normal operation. turn into.

  In order to eliminate such an adverse effect, a method is conceivable in which the above-described diagnostic processor is realized by software on the debug target processor itself. However, when a debugging program is started on the debug target processor itself and used as a diagnostic processor, the storage area is consumed for debugging processing and communication with the outside, and the amount of debug information that can be saved is reduced. This results in a trade-off between debugging functions.

  Further, in a multiprocessor system having a plurality of processors, an apparatus has been proposed in which each processor is divided into a processor to be debugged and a debugger-side processor, and a debugging process is performed after the system is restarted (for example, Patent Documents). 2). According to such a system, when some processors fall into an abnormal state, it is possible to provide debugging means by other processors. In that case, debug information of the processor that has fallen into an abnormal state, The problem was how to provide the communication means used by the debugging means.

  In the system of Patent Document 2, the operation availability information area ("Strap information" in Patent Document 2) is read when restarting after a failure occurs, normal startup and debug mode are selected, and a processor that enters the debug function is selected. However, it is difficult to provide an input / output path for debugging, and the degree of freedom in debugging processing is limited.

  Furthermore, Section 4.5.5 of Non-Patent Document 1 describes two implementation examples on Linux (Linux) for a system that saves dump information at the time of failure to a hard disk connected to the system and analyzes it later. ing.

However, the system that analyzes the dump information at the time of failure occurrence as described in Section 4.5.5 of Non-Patent Document 1 is for performing the most basic processing for operating the OS (Operating System). The system assumes that the kernel, which is a program, is operable even after a failure occurs. For this reason, there is a problem that it cannot be used when an abnormal operation / hang-up is caused including the kernel at the same time as the occurrence of a failure.
Japanese Patent Application Laid-Open No. 11-184736 JP 2004-164113 A Alessandro Rubini, written by Jonathan Corbet, Yasuhiro Yamazaki, Kuniko Yamazaki, Koji Nagahara, Yoko Nagahara, “LINUX Device Driver 2nd Edition”, O'Reilly Japan, Inc., May 31, 2002, Section 4.5.5, p. 135-136

  In the conventional debugging system described above, in a multiprocessor system in which a plurality of processors operate in cooperation with each other, it is difficult to provide an input / output path for debugging when an abnormality occurs in the debug target processor. There was a problem that debugging information could not be sent and received between them and the debugging function was limited.

  An object of the present invention is to dump debug information from a debugger processor via a communication port, interactive debugging work with a debugger processor, etc. when an abnormality occurs in a debug target processor in a multiprocessor system composed of a plurality of processors. A debugging system and a debugging method capable of realizing a debugging function are provided.

In order to achieve the above object, a debugging system of the present invention is a system constituted by a plurality of processors, wherein one of the plurality of processors is used as a debugger side processor, and the other debugging target processors are used. A debugging system that debugs when an abnormality occurs.
Reset notification that detects an abnormality that has occurred in any of the debug target processors, restarts the debug target processor in which the abnormality has occurred, and notifies the debugger processor that the debug target processor has been restarted An operating state monitoring device;
Storage means having an operation availability information area storing operation availability information for instructing whether to start normally or stop when each debug target processor is restarted;
Provided in the debugger-side processor, when activated, the operation availability information corresponding to other processors other than the debugger-side processor stored in the operation availability information area is instructed from the data for instructing normal activation to the stop state. When the notification of the reset to the debug target processor is received from the reset notification / operation state monitoring device, the debug application is connected to the communication port for communication with the external host machine. Debugging means for issuing a connection destination change instruction to connect.

  The debugging means issues a connection change instruction with the debug application of the external host machine by any of the processes of initializing the communication port, disconnecting the normal system connection, establishing the connection for the debugger, or any combination of these processes. You may do it.

  According to the present invention, the debugging means provided in the debugger-side processor changes the operation availability information stored in the operation availability information area in advance so that the debugging target processor is stopped when the debug target processor is restarted. deep. As a result, the reset notification / operation state monitoring apparatus detects an abnormality in the debug target processor and restarts the debug target processor, so that the debug target processor is stopped. The debugging means initializes or resets the communication port so that it can be connected to the debug application of the external host machine so that the communication port can be used for debugging. As a result, when the debug target processor is abnormal, a debug function including dumping of debug information from the debugger processor via the communication port and interactive debugging work with the debugger processor is realized.

  As described above, according to the present invention, in a multiprocessor system, when an abnormality occurs in a processor to be debugged, the debugger-side processor can realize the debugging means while establishing communication means with the outside. An effect can be obtained.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the debug system according to the first embodiment of the present invention.

  As shown in FIG. 1, the debug system of the present embodiment includes a communication port 1, a plurality of execution units (hereinafter referred to as processors) A and B, a reset notification / operation state monitoring device 4, and storage means. 2 and program storage means 3 and connected to an external host machine 8.

  The storage unit 2 includes an execution unit A storage area 6, an execution unit B storage area 7, and an operation availability information area 5 for storing operation availability information.

  Here, the operation availability information is information for instructing whether to normally start or stop when each processor to be debugged is restarted.

  The external host device 8 includes a communication management driver 9, a host-side normal system application 10, and a debug application 11.

  The reset notification / operation state monitoring device 4 provides each function of a reset function to each of the processors A and B, an operation state notification, and an operation state grasp by a watchdog timer function.

  In addition, when there are a plurality of debug target processors, the reset notification / operation state monitoring device 4 detects an abnormality that has occurred in any of these processors, restarts the debug target processor in which the abnormality has occurred, and Notifies the debugger processor that the processor has been restarted.

  The communication port 1 communicates with the external host machine 8. The program storage unit 3 stores applications in the area for each processor stored in the storage unit 2.

  In the following description, it is assumed that the processor A is the processor to be debugged and the processor B is the processor on the debugger side. For this reason, the processor B is provided with debugging means 20 realized by starting a debugging program.

  The debugging means 20 provided in the processor B which is the debugger side processor performs normal activation of the operation availability information corresponding to other processors other than the debugger side processor stored in the operation availability information area 5 when activated. The data to be instructed is changed to data instructing the stop state. Further, when receiving the reset notification / operation state monitoring device 4 from the reset notification / operation state monitoring device 4 that the debugging means 20 has restarted, the debugging means 20 communicates with the communication port 1 for communicating with the external host device 8. A connection destination change instruction is issued so as to connect to the host-side debug application 11.

  In this embodiment, a system including two processors A and B is described for the sake of simplicity. However, a system including three or more processors can be easily expanded.

  When there are a plurality of processors as described above, it is preferable that all the processors other than the debugger-side processor are stopped and waited. Therefore, the debugger-side processor sets all other processors in the operation availability information stored in the operation availability information area 5 to be in a stopped state. The reset notification / operation state monitoring apparatus 4 selects a processor to be debugged and notifies the debugger-side processor when a failure of a certain processor is detected. In this way, the only debugger-side processor that is not stopped among a plurality of processors can know which of the other processors that are stopped is the debug target. .

  When there are multiple processors, the number of debug-side processors equipped with debugging means is not necessarily limited to one, and multiple debug-side processors are prepared, and exclusive control is performed when an error occurs in one of the debug target processors It is also possible to operate only one debugger-side processor. As described above, by preparing a plurality of debugger-side processors, it is possible to perform debugging as long as no abnormality occurs in all the debugger-side processors.

  Next, the operation of the debug system of this embodiment will be described in detail with reference to the sequence chart shown in FIG.

  When the processor A is operating normally without any abnormality, the processor A as the debug target processor communicates with the external host device 8 via the communication port 1 as shown in FIG. Of course, other processors constituting the parallel processing environment may use the communication port 1 or may not use the communication port 1. In either case, the following description of the operation is affected. It doesn't reach. In the external host device 8, the communication management driver 9 connects communication with the communication port 1 to the host-side normal system application 10.

  In the case of a normal operation, the processor B, which is a processor on the debugger side, may be an operation in which the debugging means 20 is in a standby state as shown in FIG. Also good. In addition, the debugger-side processor may be a multitask system, and in this case, the debugger-side processor may be operating as a processor that constitutes parallel processing equivalent to other processors.

  First, in the processor B as the debugger-side processor, when the debugging means 20 is prepared or activated, the availability information corresponding to the processor A as the debug target processor in the availability information area 5 is obtained from the data for instructing normal activation. The data is changed to data indicating the stop state (step 101).

  When the processor A as the debug target processor falls into some abnormal state such as a hardware or software failure (step 201), as shown in FIG. 4, the reset notification / operation monitoring apparatus 4 Is detected (step 202), the target processor is restarted (step 203), and the restart of the target processor is notified to the debugger processor (step 204).

  During the restart process, the processor A, which is the debug target processor, acquires operation availability information from the operation availability information area 5 as shown in FIG. 5 (step 205), and stores data instructing to enter a stop or standby state. If yes, stop or enter a standby state (step 206).

  In this way, in the state where the processor A which is the debug target processor is stopped, in the processor B which is the debugger side processor, the debug means 20 starts to operate by the notification from the reset notification / operation state monitoring device 4, and FIG. As shown, initialize the communication port 1 with the outside, disconnect the normal connection, establish the connection of the debugger connection, etc., or any combination of processes, or similar connection processing (Step 207), as shown in FIG. 7, the host-side debug application 11 of the external host machine 8 is connected (Step 208).

  In the case of notifying the connection partner of the communication port 1 that the debugging means uses the communication port 1, in a preferred implementation example of the present invention, a communication path in which insertion / extraction control such as USB (Universal Serial Bus) is implemented at the protocol level Is used to notify the communication partner that the processor B, which is the processor on the debugger side, operates the debugging means 20 using the protocol for insertion / extraction control.

  After connecting to the external host machine 8, the processor B, which is a debugger side processor, executes each debugging function (steps 209 and 210). For example, the example of FIG. 8 shows a process of dumping the contents of the storage area 6 for the execution unit A of the processor A, which is the processor to be debugged, by the processor B, which is the debugger-side processor, to the external host machine 8.

  Next, the processing at the time of restarting the debug target processor described above will be described with reference to the flowchart of FIG. The processor that has received the reset from the reset notification / operation monitoring apparatus 4 undergoes a memory access related initialization process for accessing the storage area (step 801), and acquires operation availability information from the operation availability information area 5 (step 802). ), It is determined whether or not operation is possible (step 803). When it is instructed in the operation availability information in step 803 that operation is possible, this processor performs normal operating system activation processing. On the other hand, if stop / standby is instructed as operation availability information in step 803, the processor performs stop / standby processing.

  On the other hand, the operation of the debugging means 20 in the processor B which is a debugger side processor will be described with reference to flowcharts of FIGS.

  The debugging means 20 performs an initialization process in the normal operating state. Then, as shown in FIG. 10, operation availability information is set so as to enter a standby state when the debug target processor is restarted (step 901). Further, when the debug target processor is restarted, the debugging unit 20 requests the reset notification / operation monitoring device 4 so that the notification from the reset notification / operation monitoring device 4 arrives directly or via the operating system (step S40). 902), a standby state is entered.

  When notified that the target processor has been restarted, the debugging means 20 continues monitoring until the debug target processor enters a stop state / standby state as shown in FIG. 11 (steps 1001 and 1002). After confirming that the processor to be debugged has entered the stopped state / standby state, the debugging means 20 initializes the communication port 1 with the outside, disconnects the normal system connection, establishes a connection for the debugger, etc. Any one of these or any combination of processes or a similar connection process is performed to connect to the debug application 11 of the external host machine 8 (step 1003).

  After the connection with the debug application 11 of the external host machine 8, the debug means 20 notifies the external host machine 8 that it has become ready to accept an instruction relating to debug processing (step 1004), and the debug from the external host machine 8 The instruction is accepted and executed (steps 1005 to 1007).

  In FIG. 11, the case where the debugging unit 20 performs the debugging process based on the instruction from the external host machine 8 has been described. However, the debugging unit 20 receives the instruction from the external host machine 8 and performs the debugging process. In addition, after the connection with the external host device 8 is completed, an autonomous operation such as automatically outputting debug information directly or via an operating system may be implemented. Thus, the flow in the case where the debug means 20 performs an autonomous operation is shown in the flowchart of FIG.

  In FIG. 12, the processing from steps 1001 to 1003 is the same as that in FIG. The debugging means 20 that has connected to the debug application 11 of the external host machine 8 acquires debugging information from the debug target processor storage area (for example, the execution unit A storage area 6) (step 1201), and the communication port. The debugging information is transmitted to the debugging application 11 by requesting the OS to output debugging information via 1 (step 1202).

  In the debugging system of the present embodiment, in the processor B which is the debugger side processor, when the debugging unit 20 is prepared or activated, an instruction to stop when the target processor abnormality occurs is set in the operation availability information area 5. The debug target processor performs the stop / standby process according to the contents of the operation availability information area 5 in the processor initialization process.

  Furthermore, the debugger-side processor can detect the stop / standby of the debug target processor by the reset notification / operation state monitoring device 4 or the like. Then, the debugger-side processor that has detected the stop / standby of the debug target processor can use the communication port 1 for debugging by initializing or resetting the communication port.

  As a result, when the debug target processor is abnormal, a debug function including dumping debug information from the debugger side processor through the communication port 1 and interactive debugging work with the debugger side processor is realized.

  That is, according to the debug system of the present embodiment, even if the target processor suddenly falls into an abnormal state, it is possible to safely lead to a stop procedure by setting the operation availability information in advance. In addition, the debugger-side processor can use the communication port 1 with the outside after stopping.

(Second Embodiment)
Next, a debug system according to a second embodiment of the present invention will be described.

  In the debugging system according to the first embodiment described above, the debugging means 20 of the processor B which is the debugger-side processor is in a standby state and is waiting for a notification from the reset notification / operation state monitoring device 4. The side processor may accept the reset from the reset notification / operation state monitoring device 4 and restart with the processor to be debugged, and then the debugging unit 20 may be operated based on the contents of the operation availability information area 5.

  In this case, the debugger-side processor can recognize that it is the debugger side from the contents of the operation availability information area 5, so that the debugger-side processor can be started, and the other processors continue to be stopped. It will be.

It is a block diagram which shows the structure of the debug system of the 1st Embodiment of this invention. It is a sequence chart which shows operation | movement of the debug system of FIG. It is an operation | movement conceptual diagram at the time of normal system operation | movement. It is an operation | movement conceptual diagram at the time of abnormality detection. It is an operation | movement conceptual diagram at the time of the target processor restart. FIG. 3 is a conceptual diagram of operation for switching communication ports 1. It is a communication conceptual diagram at the time of debug means execution. It is a debugging conceptual diagram which made the debug information dump of the object processor an example. It is a starting process flowchart. 5 is a flowchart (initialization process) showing the operation of the debugging means 20. 5 is a flowchart (operation state) showing the operation of the debugging means 20. 5 is a flowchart (autonomous processing) showing the operation of the debugging means 20.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Communication port 2 Memory | storage means 3 Program storage means 4 Operation | movement state monitoring apparatus 5 Operation availability information area 6 Storage area for execution unit A 7 Storage area for execution unit B 8 External host machine 9 Communication management driver 10 Host side normal system application 11 Host Debug application 20 Debugging means 801 to 803 Steps 901 and 902 Steps 1001 to 1007 Steps 1201 and 1202 Steps

Claims (6)

In a system constituted by a plurality of processors, a debugging system that performs debugging when an abnormality occurs in another debug target processor using one of the plurality of processors as a debugger-side processor,
Reset notification that detects an abnormality that has occurred in any of the debug target processors, restarts the debug target processor in which the abnormality has occurred, and notifies the debugger processor that the debug target processor has been restarted An operating state monitoring device;
Storage means having an operation availability information area storing operation availability information for instructing whether to start normally or stop when each debug target processor is restarted;
Provided in the debugger-side processor, when activated, the operation availability information corresponding to other processors other than the debugger-side processor stored in the operation availability information area is instructed from the data for instructing normal activation to the stop state. When the notification of the reset to the debug target processor is received from the reset notification / operation state monitoring device, the debug application is connected to the communication port for communication with the external host machine. A debugging system comprising debugging means for issuing a connection destination change instruction to connect.   The debugging means issues a connection change instruction with the debug application of the external host machine by any of the processes of initializing the communication port, disconnecting the normal system connection, establishing the connection for the debugger, or any combination of these processes. The debugging system according to claim 1. This is a debugging method for performing debugging when an abnormality occurs in another debug target processor using one of the plurality of processors as a debugger-side processor in a system including a plurality of processors. And
When the debugger means provided in the debugger-side processor is activated, the operation availability information corresponding to other processors other than the debugger-side processor stored in the operation availability information area is stopped from the data for instructing normal activation. Changing to data indicating the state;
The reset notification / operation state monitoring device detects an abnormality that has occurred in any of the debug target processors, restarts the debug target processor in which the abnormality has occurred, and restarts the debug target processor. Informing the side processor;
When the debugger means receives a notification from the reset notification / operation state monitoring device that the debug target processor has been restarted, it connects to the debug application to the communication port for communication with the external host machine. And a step of instructing to change the connection destination.   In the step in which the debugging means performs the connection destination changing process, the external host machine is debugged by any one of initialization of the communication port, normal system connection disconnection, debugger connection establishment, or any combination of these processes. The debugging method according to claim 3, wherein a connection change instruction with an application is issued. In a system constituted by a plurality of processors, a computer uses a debugging method for performing debugging when an abnormality occurs in another processor to be debugged using one of the plurality of processors as a debugger-side processor. A program for executing
When the debugger means provided in the debugger-side processor is activated, the operation availability information corresponding to other processors other than the debugger-side processor stored in the operation availability information area is stopped from the data for instructing normal activation. Processing to change to data indicating the state;
The reset notification / operation state monitoring device detects an abnormality that has occurred in any of the debug target processors, restarts the debug target processor in which the abnormality has occurred, and restarts the debug target processor. Processing to notify the side processor,
When the debugger means receives a notification from the reset notification / operation state monitoring device that the debug target processor has been restarted, it connects to the debug application to the communication port for communication with the external host machine. A program for causing a computer to execute a process for instructing a connection destination change instruction. In the process in which the debugging means performs the connection destination changing process, the external host machine is debugged by any one of the processes for initializing the communication port, disconnecting the normal system connection, establishing the connection for the debugger, or any combination of these processes. 6. The program according to claim 5, wherein an instruction to change connection with an application is issued.

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