JP2007088054A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable adequate control of a plurality of FET's in different threshold voltages with a single substrate bias voltage, which has been difficult in the conventional semiconductor devices. <P>SOLUTION: The semiconductor device 1 comprises a semiconductor substrate 10 and FET's 20, 30. These FET's 20, 30 have different threshold voltages, respectively. A second impurity peak at the location deeper than a first impurity peak as the impurity peak of impurity implanted region for adjusting the threshold voltage, exists in the region held by the source regions and drain regions of the FET's 20, 30. Here, the FET 20 and the FET 30 are different each other at least in one of the depth and amplitude of the second impurity peak. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  In manufacturing a semiconductor device including an FET (field effect transistor), an impurity such as phosphorus ion is implanted into a semiconductor substrate in order to adjust the threshold voltage of the FET. In addition to this implantation, impurity implantation for forming a punch-through stopper region may be performed as disclosed in Patent Document 1. The punch-through stopper region is provided deeper in the semiconductor substrate than the above-described threshold voltage adjusting impurity implantation region. This punch-through stopper region prevents the depletion layer from spreading too much in the FET.

  In a semiconductor device in which these two types of implantation are performed, a punch appearing at a deeper position than the impurity peak in the impurity implantation region for adjusting the threshold voltage in a region sandwiched between the source region and the drain region of the FET. The impurity peak in the through stopper region coexists.

In order to prevent the depletion layer from spreading too much, a pocket region may be provided instead of the punch-through stopper region. The pocket region is provided immediately below an LDD (Light Doped Drain) region in the FET.
JP 2002-368126 A

By the way, in recent years, the substrate bias effect has been used in order to reduce the power consumption of the FET. The substrate bias effect is a phenomenon in which the threshold voltage of the FET changes depending on the substrate potential. That is, by adjusting the substrate bias voltage and setting the threshold voltage relatively low during operation and relatively high during standby, the power consumption of the FET can be reduced. Here, the ease of change of the threshold voltage V _th with respect to the change of the substrate potential V _bs is called a substrate bias coefficient γ and is defined by the following equation.
γ = ΔV _th / ΔV _bs (1)

  However, since the substrate bias coefficient depends on the threshold voltage, the substrate bias coefficient also differs between a plurality of FETs having different threshold voltages. Therefore, in a semiconductor device including a plurality of FETs having different threshold voltages, if an attempt is made to control the threshold voltages of these FETs with a single substrate bias voltage, the characteristic shift amount (threshold voltage change amount) will be reduced. It will be different. This can cause the circuit to lose its speed balance and cause malfunction.

  On the other hand, if it is attempted to control with different substrate bias voltages for each threshold voltage in order to alleviate the difference in the characteristic shift amount between the FETs, a plurality of substrate bias voltages must be generated. Will increase. This is a factor that hinders downsizing of the semiconductor device.

  A semiconductor device according to the present invention includes a semiconductor substrate and first and second field effect transistors provided on the semiconductor substrate and having different threshold voltages, and at least one of the first and second field effect transistors. One has a first impurity peak which is an impurity peak in the impurity implantation region for adjusting the threshold voltage, and each field effect transistor is deeper than the first impurity peak and has a junction interface between the source and drain regions. A second impurity peak appearing at a shallower position, and in the first field effect transistor and the second field effect transistor, at least one of the depth or the size of the second impurity peak is a phase. It is characterized by being different.

  In this semiconductor device, the first and second FETs having different threshold voltages are provided with impurity implantation regions different from the threshold voltage adjusting impurity implantation region. The impurity peak (second impurity peak) in this impurity implantation region is different between the first and second FETs. Here, the substrate bias coefficient depends not only on the threshold voltage but also on the second impurity peak. Therefore, by making the second impurity peak different between the first and second FETs, the difference in the characteristic shift amount can be suppressed smaller than when the peak is the same between the two. This makes it possible to control the threshold voltages of the first and second FETs having different threshold voltages with a single substrate bias voltage without breaking the circuit speed balance.

  According to the present invention, a semiconductor device having excellent reliability and suitable for downsizing can be realized.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. The semiconductor device 1 includes a semiconductor substrate 10 and FETs 20 and 30. In the present embodiment, the semiconductor substrate 10 is a P-type silicon substrate. In the semiconductor substrate 10, P-type well regions 12 and 14 and an STI (shallow trench isolation) 16 as an element isolation region are formed.

  The FET 20 (first field effect transistor) is an N-type FET, and includes a source / drain region 22, an LDD region 23, a gate electrode 24, and a gate insulating film 25. The source / drain region 22 and the LDD region 23 are formed in the P-type well region 12. A sidewall 26 is formed on the side surface of the gate electrode 24 via an offset spacer 29.

  The FET 30 (second field effect transistor) is an N-type FET, and includes a source / drain region 32, an LDD region 33, a gate electrode 34, and a gate insulating film 35. The source / drain region 32 and the LDD region 33 are formed in the P-type well region 14. A sidewall 36 is formed on the side surface of the gate electrode 34 via an offset spacer 39.

  The material of the gate electrodes 24 and 34 is, for example, polysilicon or metal. The gate electrodes 24 and 34 may have a laminated structure of polysilicon and metal. The gate insulating films 25 and 35 have the same thickness. The gate insulating films 25 and 35 are, for example, a silicon oxide film, an oxynitride film, or a high dielectric constant film. The high dielectric constant film is a film having a relative dielectric constant higher than that of a silicon oxide film or an oxynitride film, and a so-called high-k film can be used. The high dielectric constant film can be made of a material having a relative dielectric constant of 10 or more. Specifically, the high dielectric constant film can be an oxide film or a silicate film containing one or more elements selected from the group consisting of Hf, Zr, Ta, Al, and a lanthanoid element. Note that N (nitrogen) may be contained in the film.

  These FETs 20 and 30 have different threshold voltages. Specifically, the FET 30 has a higher threshold voltage than the FET 20. Although not shown in FIG. 1, the semiconductor device 1 is provided with a P-type FET in addition to the FETs 20 and 30 which are N-type FETs.

  FIG. 2 is a sectional view showing a part of FET 20 (a part including source / drain region 22 and LDD region 23). In the figure, a dotted line L1 indicates the position of the impurity peak (first impurity peak) in the impurity implantation region for adjusting the threshold voltage. That is, the FET 20 has an impurity implantation region for adjusting the threshold voltage of the FET 20. A dotted line L2 indicates the position of the impurity peak (second impurity peak) in the punch-through stopper region. The second impurity peak appears at a position deeper than the first impurity peak. Here, the depths of the first and second impurity peaks are defined as distances from the surface of the semiconductor substrate 10 to the impurity peaks, and are indicated by d1 and d2 in the drawing, respectively.

  These first and second impurity peaks are present in a region sandwiched between the source region and the drain region of the FET 20 (a hatched region in the drawing). That is, the second impurity peak is deeper than the first impurity peak and shallower than the junction interface of the source / drain regions 22. Therefore, if the depth of the bonding interface is d3, the relationship d1 <d2 <d3 is established.

  FIG. 3 is a graph showing an example of an impurity profile in a region sandwiched between the source region and the drain region of the FET 20. In the figure, the horizontal axis and the vertical axis represent depth and impurity concentration, respectively. The magnitudes of the first and second impurity peaks are indicated by h1 and h2, respectively. h2 is preferably (h1) / 10 or more.

Similarly, the FET 30 has first and second impurity peaks, and the relationship d1 <d2 <d3 is also established. Here, the FET 20 and the FET 30 are different from each other in at least one of the depth and the size of the second impurity peak. That is, if the depth and size of the second impurity peak in the FET 20 are d2 ₁ and h2 ₁ , respectively, and the depth and size of the second impurity peak in the FET 30 are d2 ₂ and h2 ₂ , respectively, “d2 ₁ ≠ d2 ₂ or h2 ₁ ≠ h2 ₂ ”is satisfied. For example, d2 ₁ <d2 ₂ and h2 ₁ <h2 ₂ .

  An example of a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. First, after forming a predetermined pattern on the semiconductor substrate 10, the STI 16 is formed by performing etching or the like. Further, an oxide film 52 to be the gate insulating films 25 and 35 later is formed on the entire surface of the semiconductor substrate 10 (FIG. 4A). Subsequently, a P-type impurity such as boron is implanted using the resist R1 having an opening in the region where the FET 20 is formed as a mask (FIG. 4B).

This implantation includes (1) well implantation, (2) implantation for adjusting a threshold voltage, and (3) three implantations for forming a punch-through stopper region. The order of these three injections is arbitrary. On the other hand, the depth of implantation increases in the order of (2), (3), and (1). In the implantation of (2), for example, an impurity peak (first impurity peak) appears in a region having a depth of 0.1 μm or less, and the dose amount is, for example, 1 × 10 ^{11 to} 5 × 10 ¹³ cm ⁻² . . On the other hand, in the implantation of (3), for example, an impurity peak (second impurity peak) appears in a region having a depth of 0.05 μm or more and 0.15 μm or less, and the dose amount is, for example, 1 × 10 ^{12 to} 5 × 10. ¹³ cm ⁻² . However, the implantation conditions are such that the depth of the second impurity peak is deeper than the first impurity peak and shallower than the junction interface of the source / drain regions.

  Similarly, P-type impurities are implanted using the resist R2 having an opening in the region where the FET 30 is to be formed as a mask (FIG. 4C). This injection also includes the above three injections (1) to (3). However, since the desired threshold voltage is different between the FET 20 and the FET 30, the conditions for the implantation in (2) are also different. Also, the implantation of (3) is performed under different implantation conditions so that the depth or size of the second impurity peak is different between the FETs 20 and 30. For example, the implantation of (3) for the FET 30 is performed under the condition that the second impurity peak is deeper and larger than that for the FET 20. Note that the order of the process described in FIG. 4B and the process described in FIG. 4C may be interchanged.

  Next, a polysilicon film 54 to be gate electrodes 24, 34 and the like later is formed on the semiconductor substrate 10 (FIG. 5A). At this time, ions may be implanted into the polysilicon film 54 as necessary. In the following steps, the same processing is performed on the region where the FET 20 is formed and the region where the FET 30 is formed. Therefore, FIG. 2 shows a region where the FET 20 is formed and a region where the P-type FET is formed. The N-type well region 18 is a well region for the P-type FET.

  Subsequently, patterning and etching are performed on the polysilicon film 54 to form gate electrodes 24 and 44 (FIG. 5B). Further, offset spacers 29 and 49 are formed on the side surfaces of the gate electrodes 24 and 44, respectively. Thereafter, N-type impurities such as phosphorus are implanted using the resist R3 covering the region where the P-type FET is formed as a mask. Thereby, the LDD region 23 is formed (FIG. 5C). At this time, an extension and / or a pocket region may be formed together with the LDD region 23. Similarly, a P-type impurity is implanted using a resist R4 covering a region where an N-type FET is to be formed as a mask. Thereby, the LDD region 43 is formed (FIG. 5D). Also at this time, an extension and / or pocket region may be formed together with the LDD region 43. Note that the order of the process described in FIG. 5C and the process described in FIG. 5D may be interchanged. Further, after the step of FIG. 5C, annealing for activating the impurities implanted in this step may be performed.

  Next, side walls 26 and 46 are formed on the side surfaces of the gate electrodes 24 and 44 on which the offset spacers 29 and 49 are formed (FIG. 6A). Thereafter, N-type impurities are implanted using the resist R5 covering the region where the P-type FET is formed as a mask. As a result, source / drain regions 22 are formed (FIG. 6B). Similarly, P-type impurities are implanted using the resist R6 covering the region where the N-type FET is formed as a mask. As a result, source / drain regions 42 are formed (FIG. 6C). Thus, the semiconductor device 1 shown in FIG. 1 is obtained. Note that the order of the process described in FIG. 6B and the process described in FIG. 6C may be interchanged. Further, after the steps shown in FIGS. 6B and 6C, annealing for activating the impurities implanted in these steps may be performed.

  The effect of this embodiment will be described. In the semiconductor device 1, the second impurity peak is different between the FETs 20 and 30. Here, the substrate bias coefficient depends not only on the threshold voltage but also on the second impurity peak. Therefore, by making the second impurity peak different between the FETs 20 and 30, it is possible to suppress the difference in the characteristic shift amount smaller than when the peak is the same between the two. For example, the second impurity peak for the FET 30 may be deeper and larger than that for the FET 20.

  FIG. 7 is a graph showing the results of experiments conducted to confirm the effects of the present invention. In this experiment, when the second impurity peak is fixed and the threshold voltage is changed by the first impurity peak (Conventional channel: conventional technology), and the second impurity peak is changed and the threshold voltage is changed. In each case (Proposed channel: present invention), the threshold voltage shift amount at the time of applying the substrate bias voltage was measured. The horizontal axis represents the threshold voltage when the substrate bias voltage is not applied with the same gate length. The vertical axis represents the threshold voltage shift amount when the substrate bias voltage is applied at -1 V, that is, the threshold voltage when the substrate bias voltage is not applied from the threshold voltage when the substrate bias voltage is applied at -1 V. Represents a value. In the former case, there is a strong correlation between the threshold voltage and the threshold voltage shift amount, while in the latter case, the threshold voltage shift amount is substantially constant even if the threshold voltage changes. That is, it can be seen that by adjusting the second impurity peak, the threshold shift amount when the substrate bias voltage is applied can be kept substantially constant over a wide threshold voltage range.

  As a result, even if a single substrate bias voltage is applied to the FETs 20 and 30 having different threshold voltages, the characteristic shift amounts (change amounts of the threshold voltages) of the FETs 20 and 30 are substantially equal to each other, so that the circuit speed balance is maintained. can do. In other words, the threshold voltages of the FETs 20 and 30 having different threshold voltages can be controlled with a single substrate bias voltage without breaking the circuit speed balance. For this reason, the semiconductor device 1 which is excellent in reliability and suitable for downsizing is realized.

  As described above, the second impurity peak is different between the FETs 20 and 30 because the implantation conditions for forming the punch-through stopper region are different between the FETs 20 and 30 in the manufacturing method described above. Due to that. In this regard, conventionally, even if the threshold voltages are different between a plurality of FETs of the same conductivity type formed in the same semiconductor substrate for reasons such as reduction in the number of processes, the plurality of the same conductivity types. The same implantation conditions were applied to the FETs except for the threshold voltage adjustment implantation.

  Therefore, in the conventional semiconductor device, the first impurity peak is different among the plurality of FETs of the same conductivity type having different threshold voltages, while the second impurity peak is equal to each other. Here, the phrase “impurity peaks are equal” means that the depth and size of the impurity peaks are both equal. Therefore, as described above, the threshold voltage difference appears as it is in the substrate bias coefficient difference, which makes it difficult to suitably control the threshold voltages of a plurality of FETs with a single substrate bias voltage. It was. Further, an FET having a low threshold voltage has a low substrate bias coefficient, and therefore requires a high substrate bias voltage. However, when the substrate bias voltage is increased, there is a problem that the reliability of the semiconductor device is deteriorated.

  On the other hand, in the present embodiment, focusing on the fact that the substrate bias coefficient depends not only on the threshold voltage but also on the second impurity peak, the first bias is applied between a plurality of FETs of the same conductivity type having different threshold voltages. These problems are solved by making the two impurity peaks different.

  The second impurity peak is an impurity peak in the punch-through stopper region of each FET 20, 30. By using the punch-through stopper region in this way, the second impurity peak can be provided without complicating the manufacturing process of the semiconductor device 1.

Here, an example of a method for setting the sizes of the first and second impurity peaks will be described. In the transistor having a low threshold voltage within the range of the threshold voltage shown in FIG. 7, the channel impurity concentration is originally low (implantation of about 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² ). Therefore, if the implantation amount of the second impurity peak is ½ or more of the first impurity peak, the effect of the Proposed channel (see FIG. 7) can be sufficiently obtained. On the other hand, in a transistor having a high threshold voltage, the concentration of the first impurity peak is as high as about 5 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² . Therefore, since the contribution of the second impurity peak is small, the implantation amount of the second impurity peak is 1/10 or more (about 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² ) of the first impurity peak. If so, the effect of the Proposed channel can be sufficiently obtained. For this reason, when it is intended to control a wide threshold voltage range, the substrate bias coefficient is suitably adjusted by setting the size of the second impurity peak to 1/10 or more of the size of the first impurity peak. can do.

Further, according to the present embodiment, it is possible to realize a semiconductor device in which threshold voltage variations due to manufacturing variations are suppressed in addition to the effects described above. FIG. 9A shows a case where no substrate bias voltage is applied (V _body = 0V) and a substrate bias voltage of −0.6 V is applied to the conventional semiconductor devices Die-A and Die-B whose substrate bias coefficients are not constant. It is the figure which plotted the occurrence frequency (the number of samples) of the threshold voltage in the case of (V _body = −0.6 V). FIG. 9B shows a case where the substrate bias voltage is not applied to the semiconductor devices Die-a and Die-b of this embodiment in which the substrate bias coefficient is substantially constant when the substrate bias voltage is not applied (V _body = 0V). It is the figure which plotted the occurrence frequency (sample number) of the threshold voltage at the time of applying .6V (V _body = -0.6V).

  The threshold voltages of Die-A, Die-B, Die-a, and Die-b are designed to have two types of threshold voltages of 0.46 V and 0.55 V without applying the substrate bias voltage. As shown in the upper graphs of FIGS. 9A and 9B, the threshold voltages of B and Die-b deviate from the desired threshold voltages due to manufacturing variations. By applying a substrate bias voltage to Die-B and Die-b that have deviated from the desired values due to manufacturing variations, the threshold voltages of Die-A and Die-a that are desired values are adjusted. Do. This result is shown in the lower graph of FIG. When the substrate bias voltage is applied, as shown in the lower graph of FIG. 9A, in Die-B, two types of threshold voltages cannot be adjusted by applying the substrate bias voltage. On the other hand, as shown in the lower graph of FIG. 9B, two types of threshold voltages substantially overlap in Die-b. Therefore, according to the present invention, by applying the substrate bias voltage, it is possible to adjust the deviation of the threshold voltage due to the manufacturing variation by applying the substrate bias, and it is possible to suppress the variation between different chips.

  The thicknesses of the gate insulating films 25 and 35 of the FETs 20 and 30 are equal to each other. For this reason, compared with the case where these thickness differs, the manufacturing process of the semiconductor device 1 is simplified. Although the FETs 20 and 30 have different threshold voltages, the gate insulating films 25 and 35 can have the same thickness because the FETs 20 and 30 are provided with impurity implantation regions for adjusting the threshold voltage.

  When high dielectric constant films are used as the gate insulating films 25 and 35, the threshold voltage can be controlled by changing the work function. This increases the degree of freedom in designing the depth and size of the second impurity peak. This is because it is not necessary to provide the second impurity peak with the role of threshold voltage control.

  Even when the material of the gate electrodes 24 and 34 is a metal such as Ti, W, Ta, Ru, or Hf or a nitride thereof, the threshold voltage can be controlled by changing the work function. Further, as shown in FIG. 8, when the gate electrodes 24 and 34 have a laminated structure of polysilicon 27 and 37 and a metal such as Ni, Ti, Co, W or Pt or metal silicide 28 and 38. It is possible to control the threshold voltage by changing the work function. This increases the degree of freedom in designing the depth and size of the second impurity peak.

  Offset spacers 29, 39, 49 are formed on the side surfaces of the gate electrodes 24, 34, 44, respectively. Thereby, the short channel effect of the FET can be suppressed and the overlap capacitance between the gate electrode and the LDD region can be reduced.

  The semiconductor device according to the present invention is not limited to the above embodiment, and various modifications are possible. In the above embodiment, the second impurity peak is an impurity peak in the punch-through stopper region. However, the second impurity peak is the first impurity in the region sandwiched between the source region and the drain region. As long as it exists at a position deeper than the peak, it may be an impurity peak other than the punch-through stopper region.

  In the above-described embodiment, the example in which the impurity implantation region for adjusting the threshold voltage is provided in both the FETs 20 and 30 is shown. However, the impurity implantation region may be provided in only one of the FETs 20 and 30. In other words, the FET 20 having a relatively low threshold voltage may not be provided with the impurity implantation region.

It is sectional drawing which shows one Embodiment of the semiconductor device by this invention. FIG. 2 is a cross-sectional view showing a part of the semiconductor device of FIG. 1. 2 is a graph showing an example of an impurity profile of an FET provided in the semiconductor device of FIG. 1. (A)-(c) is process drawing which shows an example of the manufacturing method of the semiconductor device of FIG. (A)-(d) is process drawing which shows an example of the manufacturing method of the semiconductor device of FIG. (A)-(c) is process drawing which shows an example of the manufacturing method of the semiconductor device of FIG. It is a graph which shows the result of the experiment conducted in order to confirm the effect of this invention. It is sectional drawing which shows the modification of the semiconductor device which concerns on embodiment. (A) And (b) is a graph which shows the result of the experiment conducted in order to confirm the effect of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor substrate 12, 14 P-type well region 18 N-type well region 20 FET
22 Source / drain region 23 LDD region 24 Gate electrode 25 Gate insulating film 26 Side wall 29 Offset spacer 30 FET
32 Source / drain region 33 LDD region 34 Gate electrode 35 Gate insulating film 36 Side wall 39 Offset spacer

Claims (7)

A semiconductor substrate;
First and second field effect transistors provided on the semiconductor substrate and having different threshold voltages,
At least one of the first and second field effect transistors has a first impurity peak that is an impurity peak of the impurity implantation region for adjusting the threshold voltage,
Each field effect transistor has a second impurity peak that appears at a position deeper than the first impurity peak and shallower than the junction interface between the source and drain regions,
The semiconductor device, wherein the first field effect transistor and the second field effect transistor are different in at least one of the depth and the size of the second impurity peak. The semiconductor device according to claim 1,
The semiconductor device, wherein a size of the second impurity peak is 1/10 or more of a size of the first impurity peak. The semiconductor device according to claim 1 or 2,
A semiconductor device in which the gate insulating films of the first and second field effect transistors have the same thickness. The semiconductor device according to claim 1,
The gate insulating film of each said field effect transistor is a semiconductor device which is a high dielectric constant film | membrane. The semiconductor device according to claim 1,
A semiconductor device in which a material of a gate electrode of each field effect transistor is a metal. The semiconductor device according to claim 1,
The gate electrode of each field effect transistor is a semiconductor device having a laminated structure of polysilicon and metal. The semiconductor device according to claim 1,
A semiconductor device configured to apply a substrate bias voltage to the semiconductor substrate.

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