JP2007086898A - Memory controller, program, method, memory and rfid tag - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the number of data to be stored while preventing alternation for a resettable memory where an operation to switch a bit value from 0 to 1 is made more difficult than an operation to switch the bit value from 1 to 0. <P>SOLUTION: A memory having the storage capacity of a plurality of bits(for example, 5 bits) is set with N pieces of storage units of bit length m<SB>1</SB>, m<SB>2</SB>, through m<SB>n</SB>to m<SB>N</SB>(for example, round bits 30 and data bits 32 as two storage units of bit length 2 and 3). As for each storage unit, 1 is assigned to any one bit, and 0 is assigned to the residual bits so that a storage status that alteration is impossible can be set. Then, one data are associated with each of m<SB>1</SB>×m<SB>2</SB>× through ×m<SB>n</SB>× to ×m<SB>N</SB>pieces of storage status columns constituted by combining the N pieces of storage units. The writing or reading of data is operated according to the assignment. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for using a resettable memory, and more particularly to a technique for associating bit states with data.

  The memory resettable area (Re-Settable Area) is an area where 1 can be set to 0 in each bit by a normal write command, but 0 cannot be set to 1 unless special steps are taken. It is. When data is written in this area, 1 may be changed to 0 and the data may be falsified. For example, 9 [1001] written in binary notation (the values of 0 and 1 enclosed in [and] here indicate the bit state), as well as 0 [0000], 1 [0001] and 8 It is easily rewritten to [1000]. Therefore, conventionally, an expression method has been used in which 1 is set only for some bit.

  This expression method will be described with reference to FIGS. FIG. 5 is a diagram showing a storage state when a 5-bit storage area is used. In the case of 5 bits, if 1 is set in only one of the bits, five states from [00001] shown in FIG. 5 (a) to [10000] shown in FIG. 5 (e) are taken. sell. When these storage states are manipulated and 1 is changed to 0, all of them only become [00000] storage states, which coincides with any storage state from FIG. 5 (a) to FIG. 5 (e). do not do. That is, under this representation method, there are five types of storage states that cannot be tampered with when a 5-bit storage area is used.

  Similarly, in the 8-bit example shown in FIG. 6, eight types of data from [00000001] shown in FIG. 6 (a) to [10000000] shown in FIG. 8 (d) can be expressed. For example, if data is associated with a natural number, a number from 1 to 8 can be expressed.

  When the above-described expression method is used, only the same number of data as the bit length can be stored in the resettable area. Therefore, the number of data that can be stored in the storage area is significantly limited.

  An object of the present invention is to increase the number of data that can be stored in a resettable memory while preventing falsification.

  Another object of the present invention is to establish a new data representation method in a resettable memory.

The memory control device of the present invention has a bit length m ₁ , m ₂ , a resettable memory that has a storage capacity of a plurality of bits and is difficult to operate from 0 to 1 compared to an operation to change a bit value from 1 to 0. . . . , M _n,. . . , _M N unit setting means for setting N storage units and a storage state in which 1 is assigned to any one bit and 0 is assigned to the remaining bits in each storage unit in combination with N storage units. Corresponding means for associating one or a plurality of data with one or a plurality of storage state strings, and changing the storage state of each storage unit to a state corresponding to certain data based on the association by the associating means Reading means for writing data to the memory, or reading the storage state of each storage unit, obtaining the corresponding data based on the association by the association means, and thereby reading the data from the memory Means. However, N is a natural number of 2 or more, n is a natural number of N or less, m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} is a natural number, m ₁ + m ₂ +. . . + M _n +. . . + _{M N} is a natural number of 5 or more.

  A resettable memory is a memory in which an operation to change from 0 to 1 is more difficult than an operation to set 1 to 0 in each bit. Here, 1 and 0 represent two possible states of the bit, and the value itself has no special meaning. The structure of the resettable memory is not particularly limited. For example, the resettable memory can be created using physical or chemical irreversible phenomena (code cutting, element destruction, etc.), or ordinary semiconductor memory and cryptographic technology. Can also be created by making the operation from 0 to 1 difficult. The resettable memory may be formed alone on the chip, for example, or may be formed on the chip together with a general semiconductor memory (ROM, RAM, etc.).

The memory control device is a device that controls the resettable memory, and can be constituted by hardware having an arithmetic function and software (program) for controlling the operation thereof. It is also possible to implement a part or all of the software functions as hardware. The memory control device includes unit setting means, association means, and one or both of writing means and reading means. The unit setting means stores bit lengths m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} N storage units are set. For example, when the memory is composed of a set of 1-bit storage elements, the storage unit of the bit length _mn is composed of _mn storage elements. Each storage unit may not be physically continuous, and each storage element in the storage unit may not be physically continuous.

  The associating means associates one or a plurality of storage status sequences created by N storage units with one or a plurality of data. Here, the storage state sequence indicates the entire bit state obtained by combining the storage states of N storage units, and the storage state indicates the bit state in each storage unit. In order to prevent falsification, this storage state is limited to a state where 1 is assigned to any one bit in each storage unit and 0 is assigned to the remaining bits. Also, the correspondence between the storage state and the data means that the data (usually expressed in binary) as a certain code identified inside the apparatus and the storage state sequence of the memory are unidirectional or bidirectional. It means tying to. The association may be performed in software or hardware. In the association means, typically, one piece of data is associated with one storage state sequence. However, for example, a combination of a storage state sequence and another storage state (for example, ROM or RAM state) can be associated with data. In this case, one storage state sequence corresponds to a plurality of data. It is attached.

  The writing means or the reading means gives a command to the means for directly accessing the memory and writing or reading. The means for directly accessing the memory for writing or reading may be built in the memory control device or provided externally.

  According to this configuration, it is possible to store a larger number of data in the memory than in an expression method in which only one bit for setting 1 is set. In addition, even if tampering is performed to change 1 to 0, it can be found, and a reduction in security can be avoided.

In one aspect of the memory control device of the present invention, the associating means obtains _mn storage states that can be taken in the nth storage unit having a bit length of _mn by combining the N storage units. M ₁ × m ₂ ×. . . × _mn ×. . . Xm One piece of data is associated with each of _N storage state columns. In n-th memory unit bit length is m _n, it can take m _n number of storage state by the bit difference assign a. And by uniquely combining this with respect to N storage units, m ₁ × m ₂ ×. . . × _mn ×. . . Xm _N storage state columns are set.

According to this configuration, the bit length is m ₁ + m ₂ +. . . + M _n +. . . + _{M N} , m ₁ × m ₂ ×. . . × _mn ×. . . × m _N data can be stored. This storage amount is less than the (m ₁ + m ₂ +... + _{M n} +... + _{M N} ) power of the storage amount 2 in a normal memory, but the storage amount m ₁ + m ₂ in a conventional resettable memory. +. . . + M _n +. . . It becomes larger than the + _{m N.}

In one aspect of the memory control device of the present invention, the bit lengths m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} are all 2 or more. This is because, in order to prevent tampering, it is necessary to estimate that the storage state in a storage unit having a bit length of 1 is the same value regardless of whether it is 0 or 1.

In one aspect of the memory control device of the present invention, the bit lengths m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} are all 4 or less. Rather than setting a storage unit with a bit length of 5 or more, it is possible to increase the storage amount by dividing this and setting a plurality of storage units of 4 or less.

In one aspect of the memory control device of the present invention, the bit lengths m ₁ , m ₂ ,. . . , M _n,. . . , _MN , 4 is none and 2 is one or two, or 2 is none and 4 is none or one. Even if one storage unit with a bit length of 4 is provided or divided into two storage units with a bit length of 2, the storage amount does not change. However, it is effective to impose such a restriction because a larger amount of storage is provided by providing a large number of storage units having a bit length of 3 than by providing a large number of storage units having a bit length of 2 or 4.

  In one aspect of the memory control device of the present invention, the unit setting means provides a hierarchical structure for the set N storage units, and the associating means associates a plurality of data with a lower-level storage. This is done by sequentially updating the storage state from the unit. In other words, if you use a variation of the storage status of a certain hierarchy, update the storage status of the higher hierarchy by one, and then update the storage status of that hierarchy sequentially from the first status. Data can be allocated systematically and efficiently.

  In the memory of the present invention, certain data is stored by the memory control device. From another viewpoint, it can be said that the memory control device is a device for manufacturing a memory in which certain data is stored. The RFID (Radio Frequency IDentification) tag of the present invention includes the memory. An RFID tag is a very small device called an IC (integrated circuit) tag and has a memory and a wireless communication function. By incorporating the memory described above into an RFID tag, an RFID tag having a function of preventing stored data from being falsified can be realized. Note that the memory control device may be incorporated in the RFID tag, or may be incorporated in a reader / writer that communicates with the RFID tag from the outside.

  FIG. 1 is a block diagram showing a schematic configuration of an RFID tag 10 according to the present embodiment. The RFID tag 10 includes a memory 12, and the memory 12 includes a ROM (Read Only Memory) 14, a resettable (Re-Settable) area 16, and a RAM (Random Access Memory) 18. The ROM 14 is a read-only storage device, and is used for storing a program for controlling the RFID tag 10. The RAM 18 is a readable / writable storage device, and is mainly used for temporary storage during the arithmetic processing. The resettable area 16 is a storage device that can change the bit value 1 to 0 with a normal write command, but requires a special procedure for the operation to change 0 to 1. It is used for storing identification information of an article to which the tag 10 is attached.

  The RFID tag 10 further includes a read / write IF (interface) 20 that is a means for reading and writing data to the memory 12, a control unit 22 that functions as a CPU (central processing unit), and an antenna. A transmission / reception unit 24 for transmitting / receiving data to / from an external device is provided. Operations of the transmission / reception unit 24 and the read / write I / F 20 are controlled by the control unit 22.

  2 and 3 are diagrams showing examples of storage state sequences used in the resettable area 16. 2 is an example of 5 bits, and FIG. 3 is an example of 8 bits.

  The six storage status strings from [01001] to FIG. 2 (f) [10100] in FIG. 2A are the upper 2 bits round bit 30 and the lower 3 bits data bit 32 with respect to the 5-bit storage area. Each storage unit is set, and the storage states given in each storage unit are combined. The storage state of the round bit 30 and the data bit 32 is created by setting only one bit to 1 and the remaining bits to 0. Specifically, the two bits of the round bit 30 can take two storage states, [01] and [10], and the three bits of the data bit 32 are [001], [010], and Three storage states of [100] can be taken. The storage state sequence from FIG. 2A to FIG. 2C is created by fixing the round bit 30 to [01] and sequentially updating the storage state of the data bits 32. FIG. ) To FIG. 2F are created by updating the round bit 30 and fixing it to [10], and sequentially updating the storage state of the data bit 32 again.

  Each of the six storage state columns thus created does not match any of these six storage state columns even if an operation of rewriting 1 to 0 is performed. For example, the storage state sequence in FIG. 6A can be changed to three of [01000] [000001] [00000] by rewriting, all of these from FIG. 6 (a) to FIG. 6 (f). This is different from the memory state sequence. In other words, the storage state sequence from FIG. 6A to FIG. 6F cannot be altered to another storage state sequence by an operation of rewriting 1 to 0, and tampering can be discovered. It is set to be.

  The control unit 22 shown in FIG. 1 represents six types of data by associating the 2 × 3 = 6 types of storage state sequences from FIG. 2A to FIG. 2F with appropriate data. be able to. That is, it is possible to input / output these six types of data by writing or reading the storage state sequence according to the association. The type of data to be associated is not particularly limited. For example, a natural number can be adopted as the data. In this case, each storage state column in FIGS. 2A to 2F represents a number from 1 to 6, respectively. Further, for example, data obtained by combining a plurality of data elements corresponding to the number of storage units can be employed. When natural numbers are used as data elements, a set of natural numbers (1,1), (1,2), (1,3), (2,1), (2,2), (2,3) Can be expressed. This mode is effective in giving meaning to each data element, for example, in the case of recognizing (i, j) as the j-th data in the i-th round.

  When this representation format is adopted, six types of data can be represented using a storage area having a bit length of five. This is superior to the expression format that can express the five types of data shown in FIG. This advantage becomes more prominent as the bit length of the storage area to be used becomes longer, as shown below.

  FIG. 3 shows an example in which an 8-bit storage area is used. In this example, 8 bits are divided into three storage units, the upper 2 bits are called the second round bit 40, the next 3 bits are called the first round bit 42, and the lower 3 bits are called the data bit 44. . As in the example of FIG. 2, in the second round bit 40, the first round bit 42, and the data bit 44, the storage state is set under the rule that only one bit is set to 1 and the other bits are set to 0. Producing. Then, by combining these storage state sequences, 2 × 3 × 3 = 18 storage state sequences that are partially omitted in FIGS. 3A to 3F can be expressed. This is more than twice the eight types that can be expressed in the expression format of FIG.

  FIG. 4 is a table comparing the relationship between the total number of bits and the number of data that can be expressed in the conventional expression format and the present expression format. In the conventional representation format, the same number of data as the total number of bits is represented. That is, when 8, 12, and 16-bit storage areas are used, 8, 12, and 16 types of data are expressed, respectively. On the other hand, in the present invention, 2 × 3 × 3 = 18 types of data can be expressed by dividing an 8-bit storage area into each storage unit of bit length 2, 3, and 3. Similarly, a 12-bit storage area can represent 3 × 3 × 3 × 3 = 81 types, and a 16-bit storage area can represent 3 × 3 × 3 × 3 × 4 = 324 types of data.

  The mode of dividing the storage area to be used into a plurality of storage units is arbitrary. For example, it is possible to divide an 8-bit storage area into four storage units having bit lengths of 2, 2, 2, and 2. However, in this case, only 2 × 2 × 2 × 2 = 16 types of data can be stored. In general, it is effective to divide the storage area into 3-bit storage units as much as possible. Then, only when it cannot be divided into 3 bits, it is divided into one or two 2-bit storage units (however, one 4-bit storage unit may be provided instead of two 2-bit storage units). Thus, the maximum storage amount can be ensured.

It is a functional block diagram which shows the structural example of a RFID tag. It is a figure which shows the example which applied this expression system to the storage area of 5 bit length. It is a figure which shows the example which applied this expression system to the storage area of bit length 8. It is a table | surface which shows the relationship between bit length and the number of expressible data. FIG. 11 is a diagram illustrating an example in which a conventional expression format is applied to a storage area having a bit length of 5. FIG. 10 is a diagram illustrating an example in which a conventional expression format is applied to a storage area having a bit length of 8.

Explanation of symbols

  10 RFID tag, 12 memory, 14 ROM, 16 resettable area, 18 RAM, 20 read / write I / F, 22 control unit, 24 transceiver unit, 30 round bits, 32, 44 data bits, 40 second round bit, 42 1st Round bit.

Claims (10)

Bit length m ₁ , m ₂ ,. . . , M _n,. . . , _M N unit setting means for setting N storage units;
In each storage unit, one or a plurality of storage state columns each formed by combining a storage state in which 1 is assigned to any one bit and 0 is assigned to the remaining bits for N storage units. Association means for associating data;
Based on the association by the associating means, the storage state of each storage unit is changed to a state corresponding to certain data, and thereby the writing means for writing data to the memory, or the storage state of each storage unit is read. Obtaining the corresponding data based on the association by the association means, thereby reading the data from the memory,
A memory control device comprising:
However, N is a natural number of 2 or more, n is a natural number of N or less, m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} is a natural number, m ₁ + m ₂ +. . . + M _n +. . . + _{M N} is a natural number of 5 or more. The memory control device according to claim 1.
The association means obtains m ₁ × m ₂ × .m obtained by combining _mn storage states that can be taken in the nth storage unit having a bit length of _mn with respect to N storage units. . . × _mn ×. . . Xm A memory control device, wherein one piece of data is associated with each of _N storage state columns. The memory control device according to claim 1 or 2,
Bit lengths m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} are all 2 or more. The memory control device according to any one of claims 1 to 3,
Bit lengths m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} are all 4 or less. The memory control device according to claim 4.
Bit lengths m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} , 4 is none and 2 is one or two, or 2 is none and 4 is none or one. The memory control device according to claim 2.
The unit setting means provides a hierarchical structure for the set N storage units,
The association means performs association with a plurality of data by sequentially updating the storage state from the storage unit of the lower hierarchy.   The memory in which certain data is stored by the memory control device according to claim 1, comprising the writing unit.   An RFID tag comprising the memory according to claim 7. Against the computer
Bit length m ₁ , m ₂ ,. . . , M _n,. . . , _M N unit setting procedure for setting N storage units,
In each storage unit, one or a plurality of storage state columns each formed by combining a storage state in which 1 is assigned to any one bit and 0 is assigned to the remaining bits for N storage units. A matching procedure for associating data;
Based on the association by the association procedure, the storage state of each storage unit is changed to a state corresponding to certain data, and thereby the writing procedure for writing data to the memory, or the storage state of each storage unit is read. And obtaining the corresponding data based on the association by the association procedure, thereby reading the data from the memory,
A memory control program characterized by the above.
However, N is a natural number of 2 or more, n is a natural number of N or less, m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} is a natural number, m ₁ + m ₂ +. . . + M _n +. . . + _{M N} is a natural number of 5 or more. A method performed by a computer,
Bit length m ₁ , m ₂ ,. . . , M _n,. . . , _M N unit setting procedure for setting N storage units,
In each storage unit, one or a plurality of storage state columns each formed by combining a storage state in which 1 is assigned to any one bit and 0 is assigned to the remaining bits for N storage units. A matching procedure for associating data;
Based on the association by the association procedure, the storage state of each storage unit is changed to a state corresponding to certain data, and thereby the writing procedure for writing data to the memory, or the storage state of each storage unit is read. And obtaining the corresponding data based on the association by the association procedure, thereby reading the data from the memory,
A memory control method comprising:
However, N is a natural number of 2 or more, n is a natural number of N or less, m ₁ , m ₂ ,. . . , M _n,. . . , _{M N} is a natural number, m ₁ + m ₂ +. . . + M _n +. . . + _{M N} is a natural number of 5 or more.

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