JP2007081312A - Method of manufacturing nitride-based semiconductor light-emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing nitride-based semiconductor light-emitting elements which is reduced in warpage after being peeled off from a substrate and can efficiently extract light from a side face. <P>SOLUTION: The method of manufacturing a plurality of nitride-based semiconductor light-emitting elements 2 is provided with a process of laminating at least an n-type semiconductor layer 103, a light-emitting layer 104 and a p-type semiconductor layer 105 in this order on a substrate 101 to form a laminate; a process of dividing the laminate so as to correspond to each of the elements 2 on which the laminate is manufactured by forming grooves 4 on the substrate 101; a process of filling each of the grooves 4 with a sacrificial layer 106; and a plating process of forming a plated substrate 111 by a plating method on the p-type semiconductor layer 105 and the sacrificial layer 106. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nitride-based semiconductor light-emitting device and a manufacturing method thereof, and more particularly to a structure for improving light extraction efficiency and a manufacturing method thereof in a nitride-based semiconductor light-emitting device having an upper and lower electrode structure including a substrate peeling process.

  In recent years, GaN-based compound semiconductor materials have attracted attention as semiconductor materials for short wavelength light emitting devices. GaN-based compound semiconductors include sapphire single crystals, various oxide substrates and III-V group compounds as substrates, and metalorganic vapor phase chemical reaction method (MOCVD method) or molecular beam epitaxy method (MBE method). ) Etc.

  The sapphire single crystal substrate has a lattice constant different from that of GaN by 10% or more, but by forming a buffer layer such as AlN or AlGaN, a good nitride semiconductor can be formed thereon, and it is generally widely used. ing. When a sapphire single crystal substrate is used, an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are stacked in this order. Since the sapphire substrate is an insulator, the element structure has a positive electrode formed on the p-type semiconductor layer and a negative electrode formed on the n-type semiconductor layer on the same plane. There are two types: a face-up method that uses a transparent electrode such as ITO as the positive electrode and extracts light from the p-type semiconductor side, and a flip-chip method that uses a highly reflective film such as Ag as the positive electrode and extracts light from the sapphire substrate side.

  As described above, the sapphire single crystal substrate is generally widely used. However, since it is an insulator, there are some problems. First, in order to form the negative electrode by removing the light emitting layer by etching or the like to expose the n-type semiconductor layer, the area of the light emitting layer is reduced only by the negative electrode portion, and the output is reduced accordingly. Second, since the positive electrode and the negative electrode are on the same plane, the current flow becomes horizontal, creating a local high current density, and the element generates heat. Thirdly, since the thermal conductivity of the sapphire substrate is low, the generated heat does not diffuse and the temperature of the device rises.

In order to solve the above problems, a conductive substrate is bonded to an element in which an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are stacked in this order on a sapphire single crystal substrate, and then the sapphire single crystal substrate is removed. And the method of arrange | positioning a positive electrode and a negative electrode up and down is disclosed (patent document 1). Furthermore, a method is disclosed in which a conductive substrate is not bonded but made by plating (Patent Document 2).
Japanese Patent No. 3511970 JP 2004-47704 A

  As a method for adhering the conductive substrate, there are a method for adhering a low melting point metal compound such as AuSn as an adhesive, and an active bonding method for activating and bonding the bonding surface with argon plasma in a vacuum. . With this method, the bonding surface is required to be extremely smooth, and if there is a foreign substance such as a particle, it is difficult to form a uniform bonding surface because the portion floats and bonding does not work well.

  GaN laminated on a substrate such as sapphire has a very high film stress because it is a thick film with a thickness of 1 to 10 μm and the temperature at the time of lamination is as high as about 1000 degrees. For example, when 5 μm of GaN is stacked on a sapphire substrate having a plate pressure of 0.4 mm, warping of about 50 to 100 μm occurs.

  When creating a support substrate by plating, the mechanical strength is weaker than that of sapphire, and the film thickness is limited to 10 μm to 200 μm due to production efficiency. End up.

  In order to reduce the influence of the GaN warp, it is effective to previously divide the GaN stacked on the substrate. Stress relaxation occurs at the portion where GaN is divided, and the warpage of the entire substrate is reduced.

However, when the plating support substrate is formed after dividing GaN, it is effective in reducing warpage of the entire substrate, but the following two problems occur.
(1) Since the n-type semiconductor layer is exposed, if the plating is performed as it is, the n-type semiconductor layer and the p-type semiconductor layer are short-circuited.
(2) Since the plating enters the side surfaces of the exposed p-type semiconductor layer, light emitting layer, and n-type semiconductor layer, light cannot be extracted from the side surfaces.

  (1) can be easily solved by forming a protective film on the side surfaces of the p-type semiconductor layer, the light emitting layer, and the n-type semiconductor layer, but (2) is easy because the depth of the side surface is as deep as 1 to 10 μm. Difficult to solve.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a nitride-based semiconductor light-emitting element that has less warping after substrate peeling and can efficiently extract light from the side surface.

  As a result of diligent efforts to solve the above problems, the present inventors have made a laminate comprising at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer corresponding to each nitride-based semiconductor light-emitting device. By filling the grooves between the light emitting elements formed by the division with a sacrificial layer that is removed after forming the plated substrate, the side surface of the laminate is plated when the plated substrate is subsequently formed. It has been found that it is possible to prevent penetration, and by removing the sacrificial layer after plating, a product with excellent light extraction efficiency from the side surface of the laminate can be obtained, and the warpage when the substrate is peeled can be reduced. That is, the present invention relates to the following.

(1) A method of manufacturing a plurality of nitride-based semiconductor light-emitting elements, comprising: forming a laminate by laminating at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer in this order on a substrate; Forming a groove on the substrate to divide the stacked body corresponding to each nitride semiconductor light emitting element to be manufactured; filling the groove with a sacrificial layer; and p-type And a plating step of forming a plating substrate on the semiconductor layer and the sacrificial layer by a plating method.
(2) The method for producing a nitride-based semiconductor light-emitting element according to (1), comprising a step of removing the sacrificial layer.
(3) The method for producing a nitride-based semiconductor light-emitting element according to (1), wherein a metal layer is stacked on the p-type semiconductor layer before the plating step.
(4) A buffer layer is formed on the substrate before the stacked body is formed, and the n-type semiconductor layer is exposed by removing the substrate and the buffer layer after the plating step. The method for producing a nitride-based semiconductor light-emitting device according to any one of (1) to (3).
(5) The metal layer is composed of a plurality of metal layers, and before filling the groove with the sacrificial layer, forming a metal layer disposed only on the p-type semiconductor layer among the plurality of metal layers. A method for producing a nitride-based semiconductor light-emitting device according to (3) or (4), which is characterized in that
(6) The method for manufacturing a nitride-based semiconductor light-emitting element according to (4) or (5), wherein the substrate is removed by a laser.
(7) The method for manufacturing a nitride-based semiconductor light-emitting element according to any one of (1) to (6), wherein the sacrificial layer is made of a resist.
(8) The method for producing a nitride-based semiconductor light-emitting element according to any one of (3) to (7), wherein the metal layer includes an ohmic contact layer.
(9) The method for producing a nitride-based semiconductor light-emitting element according to any one of (3) to (8), wherein the metal layer includes a reflective layer.
(10) The method for producing a nitride-based semiconductor light-emitting element according to any one of (3) to (9), wherein the metal layer includes an adhesion layer.
(11) The nitride-based semiconductor light-emitting device according to (8), wherein the ohmic contact layer is made of a single metal of Pt, Ru, Os, Rh, Ir, Pd, or Ag and an alloy thereof. Device manufacturing method.
(12) The method for producing a nitride-based semiconductor light-emitting element according to (9), wherein the reflective layer is made of an Ag alloy or an Al alloy.
(13) The nitride system according to (10), wherein the adhesion layer is made of a single metal of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, or W and an alloy thereof. A method for manufacturing a semiconductor light emitting device.
(14) The method for producing a nitride-based semiconductor light-emitting element according to any one of (1) to (13), wherein the thickness of the plated substrate is 10 μm to 200 μm.
(15) The method for manufacturing a nitride-based semiconductor light-emitting element according to any one of (1) to (14), wherein the plated substrate is formed of NiP alloy, Cu, or Cu alloy.
(16) The method for producing a nitride-based semiconductor light-emitting element according to any one of (1) to (15), wherein heat treatment is performed at 100 ° C. to 300 ° C. after the plating step.
(17) The nitride-based semiconductor light-emitting element according to any one of (1) to (16), wherein a plating adhesion layer is formed between the metal layer and the plating substrate so as to be in contact with the plating substrate Manufacturing method.
(18) The method for producing a nitride-based semiconductor light-emitting element according to (17), wherein the plating adhesion layer has 50 wt% or more of the same composition as a main component occupying 50 wt% or more of the plating substrate.
(19) The method for producing a nitride-based semiconductor light-emitting element according to (17) or (18), wherein the plating adhesion layer is formed of a NiP alloy or a Cu alloy.

According to the present invention, a stacked body is formed on a substrate, and a groove is formed on the substrate, whereby the stacked body is divided corresponding to each nitride-based semiconductor light emitting element, and the groove is formed as a sacrificial layer. After filling, the plating substrate is formed on the p-type semiconductor layer and the sacrificial layer by a plating method, so that it is possible to prevent plating from entering the side surface of the laminate when the plating substrate is formed.
Moreover, the thing excellent in the light extraction efficiency from the side surface of a laminated body is obtained by removing a sacrificial layer after plating.
Furthermore, since the plated substrate is formed after the laminate is divided corresponding to each nitride-based semiconductor light-emitting element, warping when the substrate is peeled can be reduced. Therefore, a nitride semiconductor light emitting device with high reliability and high output can be produced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments, and for example, the constituent elements of these embodiments may be appropriately combined.
FIG. 1 is a schematic view showing a cross section of a nitride-based semiconductor light-emitting device obtained by using the manufacturing method of the present invention, and FIG. 2 illustrates a method for manufacturing the nitride-based semiconductor light-emitting device shown in FIG. It is a schematic diagram for doing. In FIG. 2, only two nitride-based semiconductor light-emitting elements are shown among the plurality of nitride-based semiconductor light-emitting elements that are manufactured for easy viewing of the drawing.

  A nitride-based semiconductor light-emitting element 2 “hereinafter abbreviated as a light-emitting element” shown in FIG. It is equipped with. The side surface 5 of the nitride-based semiconductor layer 3 is exposed, and an ohmic contact constituting the metal layer 6 is formed at the center of the surface of the nitride-based semiconductor layer 3 on the p-type semiconductor layer 105 side (upper surface in FIG. 1). The layer 107, the reflective layer 108, and the adhesion layer 109 are laminated in order from the bottom. The adhesion layer 109 is provided continuously with the covering portion 109b and the covering portion 109b covering the upper surface of the reflecting layer 108, the side surfaces of the ohmic contact layer 107 and the reflecting layer 108, and the edge on the p-type semiconductor layer 105. , And a flange 109a extending outward from the end of the p-type semiconductor layer 105. A plating substrate 111 is formed on the adhesion layer 109 with a plating adhesion layer 110 interposed therebetween. Further, a positive electrode 212 is formed on the upper surface of the plating substrate 111, and a negative electrode 213 is formed on the lower surface of the n-type semiconductor layer 103.

In order to manufacture the light emitting element 2 shown in FIG. 1, as shown in FIG. 2, first, a substrate 101 is prepared, and a buffer layer 102 is formed on the substrate 101.
As the substrate 101, sapphire single crystal (Al ₂ O ₃ ; A plane, C plane, M plane, R plane), spinel single crystal (AgAl ₂ O ₄ ), ZnO single crystal, LiAlO ₂ single crystal, LiGaO ₂ single crystal. Any known substrate material such as oxide single crystal such as MgO single crystal, Si single crystal, SiC single crystal, and GaAs single crystal can be used without any limitation. When a conductive substrate such as SiC is used as the substrate 101, the light-emitting element 2 in which the positive electrode 212 and the negative electrode 213 are vertically arranged can be formed without peeling off the substrate 101. However, in that case, since the buffer layer 102 which is an insulator cannot be used on the substrate 101, the crystal of the nitride-based semiconductor layer 3 grown on the buffer layer 102 is deteriorated and is good. In some cases, the light emitting element 2 cannot be formed. Therefore, in this embodiment, even when conductive SiC or Si is used as the substrate 101, the substrate 101 is peeled off in a later step.

  The buffer layer 102 is for improving the crystallinity of the material constituting the n-type semiconductor layer 103. For example, when a sapphire single crystal substrate is used as the substrate 101 and GaN is used as the n-type semiconductor layer 103, the lattice constants of the substrate 101 and the n-type semiconductor layer 103 are different by 10% or more. In this case, by using AlN or AlGaN having a lattice constant between the substrate 101 and the n-type semiconductor layer 103 as the buffer layer 102, the crystallinity of GaN constituting the n-type semiconductor layer 103 is improved. Can do.

  Next, on the buffer layer 102, at least the n-type semiconductor layer 103, the light emitting layer 104, and the p-type semiconductor layer 105 are stacked in this order to form the nitride-based semiconductor layer 3. The nitride-based semiconductor layer 3 has a heterojunction structure including, for example, an n-type semiconductor layer 103, a light emitting layer 104, and a p-type semiconductor layer 105. As the nitride-based semiconductor layer 3, many semiconductors represented by the general formula AlxInyGa1-xyN (0 ≦ x <1, 0 ≦ y <1, x + y <1) are known, and are generally used in the present invention. A nitride-based semiconductor represented by the formula AlxInyGa1-xyN (0 ≦ x <1, 0 ≦ y <1, x + y <1) is used without any limitation.

  These nitride-based semiconductor layers 3 are used for growing group III nitride-based semiconductors such as metal organic chemical vapor deposition (MOCVD), hydride vapor deposition (HPVE), molecular beam epitaxy (MBE), and the like. It can be manufactured by applying all possible growth methods. A preferred growth method is the MOCVD method from the viewpoint of film thickness controllability and mass productivity.

In the MOCVD method, hydrogen (H ₂ ) or nitrogen (N ₂ ) as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source which is a group III source, trimethyl aluminum (TMA) or triethyl aluminum as an Al source (TEA), trimethylindium (TMI) or triethylindium (TEI) as the In source, and ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), etc. as the N source as the group V source. As dopants, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a Si raw material for n-type, germane (GeH ₄ ) is used as a Ge raw material, and biscyclohexane is used as an Mg raw material for p-type. Pentadienyl magnesium (Cp ₂ Mg) or bisethylcyclopentadienyl magnesium ((EtCp) ₂ Mg) is used.

As shown in FIG. 2, subsequently, by forming a groove 4 on the substrate 101, the nitride-based semiconductor layer 3 is divided corresponding to each light-emitting element 2 to be manufactured. The side surface 5 of the nitride-based semiconductor layer 3 is exposed on the inner wall of the groove 4, and the buffer layer 2 is exposed on the bottom surface of the groove 4.
For example, when a sapphire substrate is used as the substrate 101, a known technique such as an etching method or a laser cutting method can be used without any limitation as a method for dividing the nitride-based semiconductor layer 3 formed on the substrate 101. I can do it. When the laser lift-off method is used, the nitride-based semiconductor 3 is divided, but it is preferable not to damage the sapphire substrate in order to peel off the good substrate 101. Therefore, when dividing | segmenting by an etching method, it is preferable to use the method with a quick etching rate with respect to the nitride-type semiconductor layer 3, and a slow etching rate with respect to a sapphire substrate. When dividing by a laser, it is preferable to use a laser having a wavelength of 300 to 400 nm because of the difference in absorption wavelength between the nitride semiconductor layer 3 and the sapphire substrate.

  Next, as shown in FIG. 2, the trench 4 is filled with a sacrificial layer 106. When the nitride-based semiconductor layer 3 is divided corresponding to each light emitting element 2, the width of the groove 4 exposing the side surface 5 of the nitride-based semiconductor 3 is about 1 to 30 μm and the depth is about 1 to 10 μm. As a means for filling the groove 4, a film forming method such as CVD, sputtering, or vapor deposition has a low film forming rate and is difficult to use as a practical production means. In the present invention, a sacrificial layer 106 is formed to fill the groove 4.

As the sacrificial layer 106, it is preferable to select a material that does not damage the compound semiconductor layer 3, the adhesion layer 109, and the plating substrate 111 when the sacrificial layer 106 is removed. As a material for the sacrificial layer 106, a resist material, resin, ceramics, or the like is preferable. In particular, if the resist material is developed, it is more preferable because the groove can be selectively filled as it is, and if a special release material is used, it can be easily removed. When a ceramic is preferred because SiO ₂ can be easily removed by HF. Furthermore, when forming SiO ₂ , it is preferable to use an SOG (spin-on-glass) material because the groove can be sufficiently filled.

When a resist is used as the sacrificial layer 106, it is preferable to form the metal layer 6 to be patterned before filling the groove 4 with the resist. In particular, the ohmic contact layer 107 and the reflective layer 108 disposed only on the p-type semiconductor layer 105 are more preferably implemented before the trench 4 is filled with a resist. This is because a resist is used for patterning, and therefore, if the groove 4 is filled with the resist first, the resist buried in the groove 4 is peeled off.
As a method of forming the sacrificial layer 106, it is preferable to use a method of applying a resist by a known method such as a spin coating method, a spray method, or a dip coating method. Furthermore, it is preferable to use a spin coat method from the viewpoint of productivity.

Next, as illustrated in FIG. 2, the metal layer 6 including the ohmic contact layer 107, the reflective layer 108, and the adhesion layer 109 is stacked on the p-type semiconductor layer 105.
First, the ohmic contact layer 107 is formed in the central portion on the p-type semiconductor layer 105 corresponding to each light emitting element 2. As the performance required for the ohmic contact layer 107, it is essential that the contact resistance with the p-type semiconductor layer 105 is small. The material of the ohmic contact layer 107 is preferably a platinum group such as Pt, Ru, Os, Rh, Ir, Pd, or Ag from the viewpoint of contact resistance with the p-type semiconductor layer 105. More preferred are Pt, Ir, Rh and Ru. Pt is particularly preferred. Using Ag is preferable for obtaining good reflection, but the contact resistance is lower than Pt. Therefore, Ag can be used for applications that do not require much contact resistance.
The thickness of the ohmic contact layer 107 is preferably 0.1 nm or more in order to stably obtain a low contact resistance. More preferably, it is 1 nm or more, and uniform contact resistance is obtained.

Next, a reflective layer 108 is formed on the ohmic contact layer 107 in order to improve light reflection. As the reflective layer 108, an Ag alloy or the like can be used. Pt, Ir, Rh, Ru, OS, Pd, and the like have a lower reflectance from visible light to ultraviolet region than Ag alloys. Therefore, light from the light emitting layer 104 is not sufficiently reflected, and it is difficult to obtain the light emitting element 2 with high output. In this case, it is better to form the ohmic contact layer 107 thin enough to allow light to pass therethrough, and to form the reflective layer 108 such as an Ag alloy to obtain reflected light, thereby obtaining good ohmic contact and higher output. The light emitting element 2 can be created. In this case, the film thickness of the ohmic contact layer 107 is preferably 30 nm or less. More preferably, it is 10 nm or less.
A method for forming the ohmic contact layer 107 and the reflective layer 108 is not particularly limited, and a known sputtering method or vapor deposition method can be used.

  Next, as shown in FIG. 2, adhesion is performed so as to cover the side surfaces of the ohmic contact layer 107 and the reflective layer 108, the reflective layer 108, the edge on the p-type semiconductor layer 105, and the sacrificial layer 106. Layer 109 is formed. The adhesion layer 109 is for improving adhesion between the reflective layer 108 and the p-type semiconductor layer 105 and the plating substrate 111. For the adhesion layer 109, a metal having good adhesion to the p-type semiconductor layer 105 can be used. As a material for the adhesion layer 109, a single metal of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, or W or an alloy that combines them can be used.

  Next, the plating adhesion layer 110 is formed on the adhesion layer 109. The plating adhesion layer 110 is for improving the adhesion between the plating substrate 111 and the adhesion layer 109. The material of the plating adhesion layer 110 differs depending on the plating component to be used, but the adhesion is improved when a substance mainly contained in the plating component is included. For example, when NiP plating is used, it is preferable to use a Ni-based alloy for the plating adhesion layer 110. More preferably, NiP is used. When using Cu plating, it is preferable to use a Cu-based alloy for the plating adhesion layer 110. More preferably, Cu is used.

The thickness of the adhesion layer 109 and the plating adhesion layer 110 is preferably 0.1 nm or more in order to obtain good adhesion. More preferably, it is 1 nm or more, and uniform adhesion is obtained. The upper limit of the thickness is not particularly limited, but is preferably 2 μm or less from the viewpoint of productivity.
The method for forming the adhesion layer 109 and the plating adhesion layer 110 is not particularly limited, and a known sputtering method or vapor deposition method can be used. In the sputtering method, since the sputtered particles collide with the substrate surface with high energy to form a film, a film having high adhesion can be obtained. Therefore, it is more preferable to use the sputtering method.

Next, a plated substrate 111 is formed on the p-type semiconductor layer 105 and the sacrificial layer 106 by a plating method. Either electroless plating or electrolytic plating can be used for plating. In the case of electroless plating, it is preferable to use NiP alloy plating as the material. In the case of electrolytic plating, it is preferable to use Cu or a Cu alloy as the material.
The thickness of the plated substrate 111 is preferably 10 μm or more in order to maintain the strength as a substrate. However, when the thickness is increased, the plating substrate 111 is likely to be peeled off and the productivity is lowered.

  Before carrying out plating, it is preferable to degrease and clean using a general-purpose neutral detergent or the like. Further, it is preferable to remove the natural oxide film on the plating adhesion layer 110 by performing chemical etching on the surface of the plating adhesion layer 110 or the like using an acid such as nitric acid.

As a plating treatment method such as NiP plating, an electroless plating treatment method using a nickel bath such as nickel sulfate or nickel chloride and a phosphorus source such as hypophosphite as a plating bath is employed. be able to. A commercially available product suitable as a plating bath used in the electroless plating method includes Nimden HDX manufactured by Uemura Kogyo. The pH of the plating bath when performing the electroless plating treatment is preferably 4 to 10, and the temperature is preferably 30 to 95 ° C.
As a plating method for Cu or Cu alloy, an electrolytic plating method using a Cu source such as copper sulfate can be employed as a plating bath. The pH of the plating bath when performing electroplating is preferably 2 or less under strong acid conditions. The temperature is preferably 10 to 50 ° C, and more preferably at room temperature (25 ° C). The current density is preferably 0.5 to 10 A / dm2. More preferably, the current density is 2 to 4 A / dm2. It is more preferable to add a leveling agent in order to smooth the surface. As a commercial item used for the leveling agent, for example, ETN-1-A and ETN-1-B manufactured by Uemura Kogyo are used.

  Heat treatment is preferably performed in order to improve the adhesion of the plated substrate 111 thus obtained. The heat treatment temperature is preferably 100 to 300 ° C. for improving adhesion. If the temperature is raised further, the adhesion may be further improved, but there is a risk that the ohmic property is lowered.

  After the plating substrate 111 is formed, the substrate 101 and the buffer layer 102 are removed. As a method for peeling the substrate 101, a known technique such as a polishing method, an etching method, or a laser lift-off method can be used without any limitation. After the substrate 101 is peeled off, the buffer layer 102 is removed by a polishing method, an etching method, or the like, and the n-type semiconductor layer 103 is exposed.

  After removing the substrate 101, the sacrificial layer 106 is removed. As a method for removing the sacrificial layer 106, a known method such as a wet etching method or a dry etching method can be used without any limitation.

Next, the negative electrode 213 is formed over the n-type semiconductor layer 103. As the negative electrode 213, negative electrodes having various compositions and structures are known, and these known negative electrodes can be used without any limitation.
Various structures using materials such as Au, Al, Ni, and Cu are known for the positive electrode 213, and these known materials can be used without any limitation.
Subsequently, the light emitting element 2 shown in FIG. 1 is formed by dividing the plated substrate 111.

Hereinafter, an example is shown and the operation effect of the present invention is clarified. However, the present invention is not limited to the following examples.
Example 1
The light emitting element 2 shown in FIG. 1 was prepared as follows.
That is, as shown in FIG. 2, a 10 nm thick buffer layer 102 made of AlN is formed on a substrate 101 made of sapphire, and an Si-doped n-type GaN contact layer having a thickness of 5 μm is formed on the buffer layer 102. A 30-nm thick n-type In0.1Ga0.9N cladding layer (n-type semiconductor layer 103), a 30-nm thick Si-doped GaN barrier layer, and a 2.5-nm thick In0.2Ga0.8N well layer are stacked five times. A light emitting layer 104 having a multi-well structure provided with a barrier layer, a Mg-doped p-type Al0.07Ga0.93N cladding layer having a thickness of 50 nm, and a Mg-doped p-type GaN contact layer (p-type semiconductor layer 105) having a thickness of 150 nm in this order. Lamination was performed to obtain a nitride-based semiconductor layer 3.

  Next, the nitride-based semiconductor layer 3 was dug to the buffer layer 102 by dry etching to form a groove 4, and the nitride-based semiconductor layer 3 was divided corresponding to each light emitting element 2. Next, a 1.5-nm-thick Pt layer was formed as a ohmic contact layer 107 on the p-type contact layer of the nitride-based semiconductor layer 3 by sputtering. Further, Ag was deposited as a reflective layer 108 on the ohmic contact layer 107 by a 20 nm sputtering method. The Pt and Ag patterns were formed using a known photolithography technique and lift-off technique.

  Thereafter, the grooves 4 between the respective light emitting elements 2 obtained by dividing the nitride-based semiconductor layer 3 were filled by applying a resist which is a sacrificial layer 106. As the resist material, AZ5214 manufactured by Lariant was used. After applying the resist, it was pre-baked at 110 ° C. for 30 minutes, exposed and developed, and post-baked at 110 ° C. for 15 minutes. Thereafter, Cr was deposited as the adhesion layer 109 by a 20 nm sputtering method, and a NiP alloy (Ni: 80 at%, P: 20 at%) was deposited as a plating adhesion layer 110 on the adhesion layer 109 by a 30 nm sputtering method. Next, the surface of the adhesion layer 110 was immersed in an aqueous nitric acid solution (5N) and treated at a temperature of 25 ° C. for 30 seconds to remove the oxide film.

  Next, electroless plating made of a 50 μm NiP alloy was formed on the adhesion layer 110 using a plating bath (Nimden HDX-7G manufactured by Uemura Kogyo Co., Ltd.) to obtain a plated substrate 111. The treatment conditions at this time were pH 4.6, temperature 90 ° C., and time 3 hours. Next, the plated substrate 111 was washed with water, dried, and treated for 1 hour at 250 ° C. using a clean oven. Next, the substrate 101 and the buffer layer 102 were separated by a laser lift-off method, and the n-type semiconductor layer 103 was exposed.

Next, the sacrificial layer 106 was removed using N-methyl-2-pyrrolidone (NMP) as a release material. Thereafter, ITO (SnO ₂ : 10 wt%) was deposited on the surface of the n-type semiconductor layer 103 by vapor deposition at 400 nm. Next, a negative electrode 213 made of Cr (40 nm), Ti (100 nm), and Au (1000 nm) was formed on the central portion of the ITO surface by vapor deposition. A known photolithography technique and lift-off technique were used for the pattern of the negative electrode 213.

  A positive electrode 212 made of Au (1000 nm) was formed on the surface of the p-type semiconductor layer 105 by a vapor deposition method. Next, the plated substrate 111 was divided by dicing to obtain a 350 μm square light emitting device 2 shown in FIG.

  About the obtained light emitting element 2, it mounted in the TO-18 can package, and the light emission output in 20 mA of applied currents was measured with the tester. The light emission output was 18 mW.

(Example 2)
The same treatment as in Example 1 except that Cu was deposited by sputtering as the plating adhesion layer 110 in place of the NiP alloy film by sputtering, and Cu was deposited by electrolytic plating instead of the NiP alloy film by 50 μm. Was given.
As Cu plating conditions, CuSO4: 80 g / L, sulfuric acid: 200 g / L, leveling agent (UTN-MURA ETN-1-A: 1.0 mL / L, ETN-1-B: 1-mL / L) The plating was carried out at room temperature at a current density of 2.5 A / dm2. The plating time was 3 hours, and a 50 μm Cu film was formed. Moreover, copper-containing copper phosphate was used for the anode.

  About the obtained element, it mounted in the TO-18 can package, and the light emission output in 20 mA of applied currents was measured with the tester. The light emission output was 18 mW.

(Comparative example)
A SiO ₂ film having a thickness of 100 nm was formed on the side surface 5 of the nitride-based semiconductor layer 3 exposed in the groove 4. CVD was used as the SiO ₂ film formation method. Otherwise, the same treatment as in Example 1 was performed.

  About the obtained light emitting element, it mounted in the TO-18 can package, and the light emission output in 20 mA of applied currents was measured with the tester. The light emission output was 12 mW.

In Example 1 and Example 2, since the trench 4 was filled with the resist as the sacrificial layer 106, the intrusion of plating from the side surface 5 of the nitride-based semiconductor layer 3 was prevented, so that after the sacrificial layer 106 was removed, Thus, light extraction from the side surface 5 of the nitride-based semiconductor layer 3 was possible. Therefore, in Example 1, an output as high as 18 mW was obtained. In Example 2 where Cu was used for the plated substrate, an output as high as 18 mW was obtained.
On the other hand, in the comparative example, since the plating entered the side surface 5 of the nitride-based semiconductor layer 3, light extraction from the side surface 5 of the nitride-based semiconductor layer 3 could not be performed. For this reason, the output was as low as 12 mW.

(Industrial applicability)
The nitride semiconductor device provided by the present invention has excellent characteristics and stability, and is useful as a material for light emitting diodes and lamps.

FIG. 1 is a schematic view showing a cross section of a nitride-based semiconductor light-emitting device obtained by using the manufacturing method of the present invention. FIG. 2 is a schematic diagram for explaining a method of manufacturing the nitride-based semiconductor light-emitting element shown in FIG.

Explanation of symbols

2 ... light emitting element (nitride semiconductor light emitting element), 3 ... nitride semiconductor layer (laminated body), 4 ... groove, 5 ... side surface, 6 ... metal layer, 101. ..Substrate, 102 ... Buffer layer, 103 ... n-type semiconductor layer, 104 ... Light emitting layer, 105 ... P-type semiconductor layer, 106 ... Sacrificial layer, 107 ... Ohmic contact layer 108 ... reflective layer, 109 ... adhesion layer, 109a ... collar, 109b ... coating, 110 ... plating adhesion layer, 111 ... plating substrate, 212 ... positive electrode, 213 ... Negative electrode.

Claims (19)

A method of manufacturing a plurality of nitride-based semiconductor light-emitting elements,
Forming a laminate by laminating at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer in this order on a substrate;
Forming a groove on the substrate to divide the laminate in accordance with each nitride-based semiconductor light-emitting element to be manufactured; and
Filling the groove with a sacrificial layer;
And a plating step of forming a plating substrate on the p-type semiconductor layer and the sacrificial layer by a plating method.   The method for producing a nitride-based semiconductor light-emitting element according to claim 1, further comprising a step of removing the sacrificial layer.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein a metal layer is stacked on the p-type semiconductor layer before the plating step. Before forming the laminate, forming a buffer layer on the substrate,
The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein the n-type semiconductor layer is exposed by removing the substrate and the buffer layer after the plating step. . The metal layer comprises a plurality of metal layers;
5. The nitridation according to claim 3, wherein a metal layer disposed only on the p-type semiconductor layer among the plurality of metal layers is formed before filling the trench with a sacrificial layer. 6. A method for manufacturing a physical semiconductor light emitting device.   6. The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 4, wherein the substrate is removed by a laser.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein the sacrificial layer is made of a resist.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 3, wherein the metal layer includes an ohmic contact layer.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 3, wherein the metal layer includes a reflective layer.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 3, wherein the metal layer includes an adhesion layer.   9. The nitride semiconductor light emitting device according to claim 8, wherein the ohmic contact layer is made of a single metal of Pt, Ru, Os, Rh, Ir, Pd, or Ag and an alloy thereof. Method.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 9, wherein the reflective layer is made of an Ag alloy or an Al alloy.   The nitride-based semiconductor light-emitting device according to claim 10, wherein the adhesion layer is made of a single metal of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, or W and an alloy thereof. Manufacturing method.   14. The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein the plating substrate has a thickness of 10 μm to 200 μm.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein the plated substrate is formed of NiP alloy, Cu, or Cu alloy.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein heat treatment is performed at 100 ° C. to 300 ° C. after the plating step.   The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein a plating adhesion layer is formed between the metal layer and the plating substrate so as to be in contact with the plating substrate.   18. The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 17, wherein the plating adhesion layer has 50 wt% or more of the same composition as a main component occupying 50 wt% or more of the plating substrate. The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 17, wherein the plating adhesion layer is formed of a NiP alloy or a Cu alloy.

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