JP2007081211A - Insulated gate semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove Fermi level pinning by a process that is easy to become familiar with an existing manufacturing process without deteriorating device characteristics, with respect to an insulated gate semiconductor device and a manufacturing method thereof.
A level generating Fermi level pinning is generated in a band gap of a gate electrode 5 between a high dielectric film 3 containing Hf as a constituent element and a gate electrode 5 made of polycrystalline silicon or metal silicide. An amorphous SiO ₂ film 4 capable of relaxing the structure of the re-network with the gate electrode 5 is interposed to such an extent that it does not occur.
[Selection] Figure 1

Description

  The present invention relates to an insulated gate semiconductor device and a method for manufacturing the same, and more particularly, to prevent Fermi level pinning in an insulated gate semiconductor device using a high dielectric film having Hf as a component as a gate insulating film. The present invention relates to an insulated gate semiconductor device having a characteristic structure and a method for manufacturing the same.

  With the recent development of wireless communication technology and diversification of information contents, the amount of information processed by portable information terminals has increased dramatically, and LSIs that play a central role in information processing have become smaller, lower power consumption, and faster operation. And lowering of voltage is required.

  In order to meet such demands, the gate oxide film of MOSFETs constituting an LSI has been rapidly thinned. If the gate insulating film already thinned to the physical limit is further thinned, carriers directly There is a problem in that the gate leakage current increases due to tunneling of the gate insulating film.

For example, in the MISFET gate length is 65 nm, equivalent oxide thickness (EOT: Equivalent Oxide Thickness) In the gate insulating film of 1.2~1.6nm is required, conventionally used as the gate insulating film as well as SiO ₂ When the film is used, the gate leakage current exceeds the allowable value due to the tunnel current.

Therefore, in order to maintain the above-mentioned film thickness as EOT and suppress gate leakage current, an insulating film having a high dielectric constant instead of SiO ₂ (relative dielectric constant˜3.9), that is, a high-k film is used. Adoption has been studied, and examples of such a High-k film include HfO ₂ (relative dielectric constant˜25) and Al ₂ O ₃ (relative dielectric constant 9˜11).

  By adopting such a High-k film as the gate insulating film, the physical film thickness can be increased even with the same EOT, thereby preventing the tunneling of carriers and suppressing the gate leakage current. it can.

In particular, when HfO ₂ having a very high relative dielectric constant is used as the gate insulating film, the effect of suppressing the gate leakage current is increased. Therefore, as the High-k film, HfO ₂ , HfSiON, HfAlO _x , HfAlON, etc. Researches on high-k films containing Hf have been actively conducted.

  However, when a High-k film containing Hf is used as a gate insulating film, Fermi level pinning occurs in which the work function of the polycrystalline Si gate electrode does not change depending on the impurity concentration. It has been reported to be prominent.

As a cause of such Fermi level pinning,
(1) It has been reported that bonding occurs between Hf and Si due to the loss of oxygen at the High-k / Si interface, and pinning occurs due to this Hf-Si bonding. (For example, refer nonpatent literature 1).

Also,
(2) At the High-k / Si interface, there are many oxygen vacancies in the High-k film, and the charge of the oxygen vacancies is 2 ⁻ , and electric dipoles are present at the interface due to this charge. A hypothesis has been proposed that this occurs and causes bending of the band to cause pinning (see, for example, Non-Patent Document 2).

(3) Alternatively, it has also been reported that B and Hf in p-type polycrystalline Si are combined to greatly shift V _th (see, for example, Patent Document 1).

  However, as a result of intensive studies by the present inventors, the Hf-B bond in (3) above has a very large atomic weight of Hf, so that solid phase diffusion hardly occurs and bonds with B in p-type polycrystalline Si. I came to the conclusion that this is not possible.

  In addition, the oxygen deficiency theory in (2) has not been subjected to the first principle calculation of the Order (N) method based on the Gaussian basis function. As a result of detailed examination by the present inventor, It came to the conclusion that the phenomenon of Fermi level pinning cannot be explained.

That is, the level generated by neutral oxygen vacancies is in the band gap in HfO ₂ , but is generated just below the top of the valence band of Si when compared with Si. Since no level is generated in the pin, pinning is not affected.

  Thus, as a result of examining the oxygen desorption at the interface of (1) above, when there is oxygen desorption at the interface, the phase of the p orbit of the nearby Si and the d orbit of the nearby Hf coincided by chance. It was found that bonding orbitals were created, surplus electrons were taken in, and levels were formed in the Si band gap (see, for example, Non-Patent Document 3).

This level is just below the conduction band of Si. Even if Si is doped with B, Fermi is suppressed in order to prevent surplus electrons taken into this level from flowing to the Si side and becoming p-type. Level pinning phenomenon occurs.
In the case of the n-type, since the level filled with surplus electrons only increases the Fermi level, it has no effect and can explain the experimental results well.

When such Fermi level pinning occurs, it becomes impossible to control the work function, especially for p-type polycrystalline Si, and V _th control cannot be performed, which is a major obstacle to the practical use of high-k films. It has become.

Therefore, in order to avoid Fermi level pinning, it has been studied to insert a SiO ₂ film or a SiN film at the High-k / polycrystalline Si interface.
Further, when the gate electrode is a silicide electrode such as Pt silicide or Ni silicide, it has been attempted to remove Fermi level pinning by changing the composition ratio.
Japanese Patent Laying-Open No. 2005-079306 C. Hobbs et al. , IEEE Trans. Electron Devices, vol. 51, pp. 971-983, 2004 K. Shiraishi et al. , VLSI Symp. Tech. Dig. , 2004, pp. 108-110 Satoshi Ikeda et al., The 33rd Thin Film and Surface Seminar hosted by the Japan Society of Applied Physics, Thin Film and Surface Subcommittee, “Interface Control and Electronic Structure of Cutting-Edge Devices”, JSAP Catalog Number: AP052330, pp. 41-50, 2005

However, it has been found that the Fermi level pinning cannot be removed when the SiO ₂ film is inserted.
This is because, as will be described later, a normal thermal oxide film is an amorphous SiO ₂ film close to a hard Tridymite structure that lacks flexibility, so that the structure cannot be relaxed by recombination of bonds generated due to oxygen deficiency. is there.

  Further, when a SiN film is inserted, it is necessary to have a film thickness of about 2 nm. As a result, there is a problem that EOT is increased and device characteristics are deteriorated.

  Further, when the composition ratio of the silicide electrode is changed, the work function of the silicide electrode depends on the composition ratio, so that it is difficult to arbitrarily set the work function of the gate electrode.

  Therefore, an object of the present invention is to remove Fermi level pinning by a process that does not deteriorate device characteristics and is easily adapted to an existing manufacturing process.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
In the figure, reference numeral 2 denotes a gate insulating film.
In order to solve the above problem, in the insulated gate semiconductor device, the present invention provides a high dielectric film 3 containing Hf as a constituent element and a gate electrode 5 made of polycrystalline silicon or metal silicide. It is characterized in that an SiO ₂ film 4 having an amorphous structure capable of relaxing the structure of the re-network with the gate electrode 5 is interposed so as not to generate a level that generates Fermi level pinning in the band gap of the gate electrode 5.

Thus, as a SiO ₂ film 4 of amorphous structure as a cap layer for high dielectric film 3, by the SiO ₂ film 4 of soft structure capable structural relaxation re networks between the gate electrode 5, the high dielectric Oxygen deficiency due to oxygen loss at the interface between the body film 3 and the SiO ₂ film 4 can be eliminated by recombination of bonds, so that no level is generated in the band gap of the gate electrode 5, thereby allowing Fermi level pinning. Can be suppressed.

As the SiO ₂ film 4 of amorphous structure of soft structure capable structural relaxation re network with such a gate electrode 5, alpha-quartz or SiO ₂ film 4 of amorphous structure closer to β- quartz is typically It is a thing.

Such an SiO ₂ film 4 shows an amorphous state in X-ray diffraction or the like, but has a structure close to α-quartz or β-quartz when the fine structure is confirmed by an electron microscope.
When single crystal Si or polycrystal Si is thermally oxidized, or when the SiO ₂ film 4 is deposited by a CVD method or the like, an amorphous SiO ₂ film close to the Trimitite structure is obtained. In an SiO ₂ film having an amorphous structure close to the Tridymite structure, bond recombination cannot be performed and oxygen vacancies cannot be eliminated, so that Fermi level pinning cannot be removed as described above.

In this case, the film thickness of the SiO ₂ film 4 is preferably 0.45 nm or more and less than 1 nm. If the film thickness is less than 0.45 nm, the structure relaxation of the re-network with the gate electrode 5 is insufficient, while 1 nm or more. Then, EOT increases and device characteristics deteriorate.

The high dielectric film 3 containing Hf as a constituent element may be any film as long as it contains Hf, but HfO ₂ , HfSiO, HfSiON, HfAlO, or HfAlON is typical, In particular, it is desirable to contain Al in order to maintain the characteristics as an amorphous film by increasing the crystallization temperature and to maintain a high relative dielectric constant, and since the Al ₂ O ₃ film does not generate Fermi level pinning. From this point, it is desirable to mix Al.
Note that HfSiON is desirable to reduce the decrease in mobility.

  In this case, it is desirable that the atomic ratio of Hf in the metal elements including Si in the high dielectric film 3 containing Hf as a constituent element is 50% or more, whereby the relative dielectric constant of the high dielectric film 3 Since the rate can be sufficiently high, the EOT can be kept small even if the physical film thickness is increased, and the gate leakage current can be suppressed.

In order to manufacture the above-described insulated gate type semiconductor device, a high dielectric film 3 containing amorphous silicon film and an amorphous silicon film containing Hf as a constituent element are sequentially deposited on the semiconductor substrate 1 and then heat-treated in an oxidizing atmosphere. To convert the amorphous silicon film into the SiO ₂ film 4, and then deposit polycrystalline silicon or metal silicide to be the gate electrode 5 on the SiO ₂ film 4.
The “semiconductor substrate” includes a semiconductor substrate and a semiconductor epitaxial layer.

The heat treatment temperature in this case is preferably in the range of 300 ° C. to 400 ° C. as the substrate temperature. When the temperature is lower than 300 ° C., the oxidation becomes insufficient. On the other hand, when the temperature exceeds 400 ° C., the oxidation rate increases. It becomes difficult to uniformly form the SiO ₂ film 4 having an amorphous structure close to α-quartz or β-quartz.

In the present invention, the structure of the re-network with the gate electrode to such an extent that a level causing Fermi level pinning is not generated in the band gap of the gate electrode between the high dielectric film containing Hf as a constituent element and the gate electrode. Since the SiO ₂ film having an amorphous structure that can be relaxed, typically an SiO ₂ film having an amorphous structure close to α-quartz or β-quartz is inserted as a cap layer, the level is not within the band gap of the gate electrode. It does not occur, thereby suppressing the occurrence of Fermi level pinning.

Here, with reference to FIG. 2 thru | or FIG. 6, embodiment of this invention is described.
See Figure 2
FIG. 2 is a schematic configuration diagram of the MISFET according to the embodiment of the present invention, and a high-level element comprising Hf such as HfO ₂ , HfSiO, HfSiON, HfAlO, or HfAlON on the n-type silicon substrate 11 as a constituent element. A dielectric structure 12, a cap layer 13 made of an SiO ₂ film having an amorphous structure close to α-quartz or β-quartz, and a gate electrode 14 made of polycrystalline silicon or metal silicide are sequentially stacked to constitute a gate structure. The p-type source / drain regions 15 are formed on both sides of the gate structure, and the source / drain electrodes 16 are formed thereon.

See Figure 3
FIG. 3 is a model diagram of the molecular structure of the cap layer interface, and shows that the oxygen vacancies 17 generated at the interface between the cap layer 13 and the high dielectric film 12 have disappeared due to the recombination of bonds.
In order to simplify the description, HfO ₂ is used as the high dielectric film 12, an amorphous SiO ₂ film close to β-quartz is used as the cap layer 13, and polycrystalline silicon is used as the gate electrode 14. Used to show.

See Figure 4
FIG. 4 is a model diagram of the molecular structure of the interface of the cap layer when the conventional SiO ₂ film shown for comparison is used as the cap layer 18, and has an amorphous structure SiO ₂ close to the Trimitite structure that constitutes the cap layer 18. Since the film is not flexible compared to the SiO ₂ film having an amorphous structure close to β-quartz, bond recombination does not occur, and oxygen deficiency 17 generated at the interface between the cap layer 18 and the high dielectric film 12 still exists. become.
Here, in order to simplify the description, HfO ₂ is used as the high dielectric film 12, an SiO ₂ film having an amorphous structure close to the tridite structure is used as the cap layer 18, and polycrystalline silicon is used as the gate electrode 14. It shows.

See Figure 5
FIG. 5 is an explanatory diagram of the state density in the polycrystalline silicon constituting the gate electrode in the embodiment of the present invention, and it can be seen that no level due to the oxygen vacancy 17 is formed in the band gap.

See FIG.
FIG. 6 is an explanatory diagram of state density in polycrystalline silicon when the conventional SiO ₂ film shown for comparison is used as the cap layer 18, and a level 19 due to the oxygen deficiency 17 is formed in the band gap. The Fermi level is pinned to this level 19 and cannot move.

As described above, in the embodiment of the present invention, a soft α-quartz or amorphous structure SiO ₂ close to β-quartz capable of recombination of bonds between the high dielectric film and the gate electrode. Since the film is interposed as a cap layer, even if an oxygen defect due to oxygen loss occurs at the interface of the high dielectric film / cap layer, the oxygen defect disappears due to the recombination of the bond, and as a result, within the band gap of the gate electrode. Thus, no level that causes Fermi level pinning is generated.
In addition to the Quartz structure and the Trimitite structure, the SiO ₂ fine structure includes a Cristobalite structure. However, since the Cristobalite structure is higher in energy and unstable than the Quartz structure and the Trimitite structure, it is excluded as an interface structure.

Next, on the premise of the above matters, the manufacturing process of the MISFET of Example 1 of the present invention will be described with reference to FIGS.
See FIG.
First, after the element isolation region 22 is formed on the n-type silicon substrate 21, the thickness is 1.6 nm to 5.0 nm, for example, 2 nm, using the LL-D & A (Layer-by-Layer Deposition & Annealing) method on the entire surface. A high dielectric film 23 made of .4 nm HfAlO _x is deposited.

In the growth process by the LL-D & A method, for example, Hf [N (CH ₃ ) ₂ ] ₄ (TDMAH) is used as the Hf source and Al is used as the Al source in a state where the substrate temperature is 300 to 400 ° C. Using (NH ₃ ) ₃ (TMA), using H ₂ O as the O source, and using N ₂ gas as the carrier gas, growth is performed in units of one atomic layer.

For example, Al ₂ O ₃ atomic layers and HfO ₂ atomic layers are alternately deposited, and RTA (Rapid Thermal Anneal) is performed every time they are deposited, and the ratio of Hf: Al in HfAlO _x is Al ₂ O ₃ atomic layer and may be controlled by the number of stacked HfO ₂ atomic layers, where, for example, Hf: Al = 6: and 4.

Next, for example, an α-Si film 24 is deposited using a plasma CVD method at a substrate temperature of 450 ° C.
At this time, since the α-Si film 24 is expanded by oxidation in the next step, the film is formed so that the film thickness when it becomes the α-SiO ₂ film is 0.45 nm to 1 nm (excluding 1 nm). .

Next, the α-Si film 24 is oxidized and converted to an α-SiO ₂ film by heat treatment in an oxidizing atmosphere, for example, a dry O ₂ atmosphere at a substrate temperature of 300 ° C. to 400 ° C., for example, 350 ° C. The cap layer 25 is formed.
Further, since the oxidation at this time is performed slowly at a low temperature, the α-SiO ₂ film has an amorphous structure close to α-quartz or β-quartz reflecting the crystal state of the α-Si film 24.
Further, since it is a low-temperature oxidation, HfAlO _x is not crystallized in this oxidation step.

  Next, a polycrystalline silicon film 26 is deposited on the cap layer 25 using the CVD method.

See FIG.
Next, the polycrystalline silicon film 26 to the high dielectric film 23 are formed to a length of, for example, 65 nm by using a photolithography process and a dry etching process, thereby forming a gate structure including the gate insulating film 27 and the gate electrode 28. .

  Next, the p-type extension region 30 is formed by implanting B ions 29 shallowly using the gate structure as a mask.

Next, after forming a SiO ₂ film on the entire surface, anisotropic etching is performed to form a sidewall 31. Next, B ions 32 are implanted using the gate structure and the sidewall 31 as a mask to form a p-type source. The drain region 33 is formed and the gate electrode 28 is doped with B.

See FIG.
Next, a Co film is deposited on the entire surface, and then alloyed by heat treatment to form a Co silicide electrode 34 on the surfaces of the p-type source / drain regions 33 and the gate electrode 28, and then the unreacted Co film is removed. .

  Next, after depositing an interlayer insulating film 35 made of BPSG on the entire surface, a via hole for the Co silicide electrode 34 is formed, and then the via hole is filled with W through a TiN film to form a plug 36. The basic structure of MISFET is completed.

Thus, in Example 1 of the present invention, when a high dielectric constant HfAlO _x is used as the gate insulating film, α-quartz obtained by low-temperature oxidation of α-Si as the cap layer or α-SiO close to β-quartz. _{Since two} films are used, even if oxygen vacancies occur due to oxygen loss at the interface of the HfAlO _x / α-SiO ₂ film, the oxygen vacancies at the interface disappear due to recombination of bonds by the soft α-SiO ₂ film.

  As a result, levels due to oxygen vacancies do not occur in the band gap of polycrystalline silicon, so Fermi level pinning does not occur.

In Example 1 of the present invention, HfAlO _x containing Al is used as the high dielectric film, but Al ₂ O ₃ itself does not cause pinning and has a high crystallization temperature, so that it is an amorphous film. It is easy to maintain the above characteristics, and Al ₂ O ₃ is preferable because it has a higher relative dielectric constant than SiO ₂ and can maintain a higher relative dielectric constant.

Next, the MISFET according to the second embodiment of the present invention will be described with reference to FIG. 10. However, since the composition of the high dielectric film and the manufacturing method are different, other configurations are the same as those of the first embodiment. Only the final device structure is shown.
See FIG.
FIG. 10 is a schematic cross-sectional view of a MISFET according to Example 2 of the present invention. First, an element isolation region 22 is formed on an n-type silicon substrate 21, and then the entire surface is thickened by LPCVD (low pressure CVD). A high dielectric film 37 made of HfSiON having a thickness of 1.6 nm to 5.0 nm, for example, 2.4 nm is deposited.

In the growth process by this LPCVD method, (t-C ₄ H ₉ O) ₄ Hf is used as the Hf source, Si ₂ H ₆ is used as the Si source, O ₂ or O ₃ is used as the O source, and the carrier A film is formed using N ₂ gas as a gas, and N is introduced after the film formation by nitriding with NH ₃ at 650 ° C. or N ₂ plasma processing at 450 ° C. or lower.
The composition ratio of Hf is to control the flow rate ratio of _{(t-C 4 H 9 O} ) 4 Hf.

Thereafter, in the same manner as in the first embodiment, the α-Si film 24 is deposited and then oxidized at a low temperature to obtain an α-SiO ₂ film having an amorphous structure close to α-quartz or β-quartz. A polycrystalline Si layer is deposited to form a gate structure, and a p-type extension region 30, a sidewall 31, a p-type source / drain region 33, a Co silicide electrode 34, an interlayer insulating film 35, and a plug 36 are sequentially formed. Thus, the basic structure of the MISFET of Example 2 of the present invention is completed.

Also in the second embodiment of the present invention, when HfSiON having a high dielectric constant is used as the gate insulating film, α-quartz obtained by low-temperature oxidation of α-Si or α-SiO ₂ film close to β-quartz is used as the cap layer. Therefore, even if oxygen vacancies occur due to oxygen loss at the interface of the HfSiON / α-SiO ₂ film, the oxygen vacancies at the interface disappear due to recombination of bonds by the soft α-SiO ₂ film.

Further, since HfSiON serving as a gate insulating film does not contain Al (Al ₂ O ₃ ) that causes a decrease in carrier mobility, the mobility is higher than that in the case of using HfAlO _x as a high dielectric film. As a result, the speed can be increased.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, in each embodiment, p The channel type MISFET is described as an example, but the present invention is also applied to an n channel type MISFET.

  In each of the above embodiments, polycrystalline Si is used as the gate electrode. However, the gate electrode is not limited to polycrystalline Si, and Ni silicide (work function = 4.7 eV) or Pt silicide (work function = 4). .9 eV) or a metal silicide such as Pt (work function = 5.7 eV) may be used, but Ni silicide is particularly desirable from the viewpoint of the work function.

  In the first embodiment, the LL-D & A method is used as a method for manufacturing the high dielectric film. However, the method is not limited to the LL-D & A method, and a normal ALD method or LPCVD method may be used. It is good, and furthermore, a sputtering method may be used.

  In the second embodiment, the LPCVD method is used as a method for producing the high dielectric film. However, the present invention is not limited to the LPCVD method, and a normal ALD method or LL-D & A method may be used. Furthermore, a sputtering method may be used.

In Example 1 or Example 2 described above, HfAlO _x or HfSiON is used as the high dielectric film, but it is not limited to HfAlO _x or HfSiON, and the high dielectric film having Hf as a constituent element is used. For example, HfO ₂ , HfSiO, or HfAlON may be used.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Again see Figure 1
(Supplementary Note 1) A level for generating Fermi level pinning in the band gap of the gate electrode 5 between the high dielectric film 3 containing Hf as a constituent element and the gate electrode 5 made of polycrystalline silicon or metal silicide. An insulated gate semiconductor device comprising an amorphous SiO ₂ film 4 capable of relaxing the structure of the re-network with the gate electrode 5 to the extent that it does not occur.
(Supplementary Note 2) An SiO ₂ film 4 having an amorphous structure close to α-quartz or β-quartz is interposed between the high dielectric film 3 containing Hf as a constituent element and the gate electrode 5 made of polycrystalline silicon or metal silicide. An insulated gate semiconductor device characterized by being made.
(Supplementary Note 3) film thickness of the SiO ₂ film 4, the insulated gate semiconductor device according to Note 1 or 2, characterized in that a 1nm or less than 0.45 nm.
(Supplementary note 4) The high dielectric film 3 containing Hf as a constituent element is made of any one of HfO ₂ , HfSiO, HfSiON, HfAlO, or HfAlON. Insulated gate type semiconductor device.
(Appendix 5) Any one of appendices 1 to 4, wherein an atomic ratio of Hf in metal elements including Si in the high dielectric film 3 containing Hf as a constituent element is 50% or more. Insulated gate type semiconductor device.
(Supplementary Note 6) A high dielectric film 3 containing Hf as a constituent element and an amorphous silicon film are sequentially deposited on the semiconductor substrate 1, and then heat treatment is performed in an oxidizing atmosphere to thereby convert the amorphous silicon film into SiO _2. A method of manufacturing an insulated gate semiconductor device, comprising the step of converting the film 4 and then depositing polycrystalline silicon or metal silicide to be the gate electrode 5 on the SiO ₂ film 4.
(Additional remark 7) The substrate temperature in the said heat processing is 300 to 400 degreeC, The manufacturing method of the insulated gate semiconductor device of Additional remark 6 characterized by the above-mentioned.

  As a practical example of the present invention, a MISFET is typical, but it can also be applied to a MIS type diode or a capacitive element using a semiconductor substrate and a polycrystalline wiring.

It is explanatory drawing of the fundamental structure of this invention. It is a schematic block diagram of MISFET of an embodiment of the invention. It is a model figure of the molecular structure of a cap layer interface. It is a model figure of the molecular structure of a cap layer interface. It is explanatory drawing of the density of states in the polycrystalline silicon which comprises the gate electrode in embodiment of this invention. A conventional SiO ₂ film is an explanatory view of a state density in the polycrystalline silicon in the case of the cap layer. It is explanatory drawing of the manufacturing process to the middle of MISFET of Example 1 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 7 or subsequent of MISFET of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 8 of MISFET of Example 1 of this invention. It is a schematic sectional drawing of MISFET of Example 2 of this invention.

1 semiconductor substrate 2 gate insulating film 3 high dielectric film 4 SiO ₂ film 5 gate electrode 11 n-type silicon substrate 12 a high dielectric film 13 cap layer 14 gate electrode 15 p-type source and drain electrode 16 source and drain electrodes 17 oxygen deficiency 18 Cap layer 19 Level 21 N-type silicon substrate 22 Element isolation region 23 High dielectric film 24 α-Si film 25 Cap layer 26 Polycrystalline silicon film 27 Gate insulating film 28 Gate electrode 29 B ion 30 p-type extension region 31 Side Wall 32 B ion 33 p-type source / drain region 34 Co silicide electrode 35 Interlayer insulating film 36 Plug 37 High dielectric film

Claims (5)

Between the high-dielectric film containing Hf as a constituent element and the gate electrode made of polycrystalline silicon or metal silicide, the gate electrode does not generate a level that causes Fermi level pinning in the band gap of the gate electrode. An insulated gate semiconductor device characterized by interposing an amorphous SiO ₂ film that can restructure the network. An SiO ₂ film having an amorphous structure close to α-quartz or β-quartz is interposed between a high dielectric film containing Hf as a constituent element and a gate electrode made of polycrystalline silicon or metal silicide. Insulated gate semiconductor device. _3. The insulated gate semiconductor device according to claim 1, wherein the thickness of the SiO ₂ film is 0.45 nm or more and 1 nm or less. 4. The insulated gate according to claim 1, wherein the high dielectric film containing Hf as a constituent element is made of any one of HfO ₂ , HfSiO, HfSiON, HfAlO, and HfAlON. 5. Type semiconductor device. A high dielectric film and an amorphous silicon film containing Hf as a constituent element are sequentially deposited on a semiconductor substrate, and then the amorphous silicon film is converted into a SiO ₂ film by performing a heat treatment in an oxidizing atmosphere. A method of manufacturing an insulated gate semiconductor device comprising the step of depositing polycrystalline silicon or metal silicide to be a gate electrode on the SiO ₂ film.

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