JP2007066722A - Plasma display panel, and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel capable of preventing delay of discharge timing by a voltage pulse of a third electrode, or of reducing its voltage pulse. <P>SOLUTION: This plasma display panel is provided which has: a first substrate (1); a second substrate arranged opposed to the first substrate; a first and second electrode groups (27, 28) which are arranged on the first substrate in parallel and which carry out discharge; a third electrode group (29) that is arranged at a gap which carries out discharge of the first and second electrode groups; a dielectric layer (19) to cover the first to the third electrode groups; and a fourth electrode group arranged so as to cross the first to the third electrode groups on the second substrate. The thickness of the dielectric layer covering the third electrode group is thinner than that of the dielectric layer covering the first and second electrode groups. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a plasma display panel and a plasma display device.

  FIG. 3 of Patent Document 1 below describes a plasma display panel in which a first address electrode (cathode) is formed between a pair of display electrodes on a front glass substrate. A dielectric layer and a protective film are formed on the display electrode pair and the first address electrode (cathode).

  Further, Patent Document 2 below describes a plasma display panel in which a trench penetrating a high dielectric layer is formed between an X electrode and a Y electrode.

JP-A-10-199427 JP 2001-15038 A

  In the plasma display panel, a sustain discharge is performed between the first electrode and the second electrode. It is known that increasing the distance between the first electrode and the second electrode improves the discharge efficiency. However, increasing the distance between the two electrodes increases the drive voltage. In contrast, a third electrode is provided between the first electrode and the second electrode, and a trigger discharge is generated between the third electrode and the first or second electrode, and the first electrode and the second electrode There is a method that leads to a discharge between the electrodes. When the third electrode is provided between the first electrode and the second electrode, it is necessary to control the discharge timing by the voltage pulse of the third electrode with high accuracy.

  An object of the present invention is to provide a plasma display panel and a plasma display apparatus that can prevent a delay in discharge timing due to a voltage pulse of a third electrode and further reduce the voltage of the pulse.

  The plasma display panel according to the present invention includes a first substrate, a second substrate disposed opposite to the first substrate, and a first substrate and a second substrate disposed in parallel on the first substrate and performing discharge. A second electrode group and a third electrode group disposed in a gap for discharging the first and second electrode groups; a dielectric layer covering the first to third electrode groups; and a second substrate. A fourth electrode group disposed so as to intersect the first to third electrode groups, and the thickness of the dielectric layer covering the third electrode group is the same as that of the first and second electrode groups. It is characterized by being thinner than the thickness of the covering dielectric layer.

  By reducing the thickness of the dielectric layer covering the third electrode group, the discharge timing is delayed by the voltage pulse between the third electrode and the first electrode or between the third electrode and the second electrode. Can be prevented, and the voltage of the pulse can be lowered. Thereby, the discharge timing between the third electrode and the first electrode or between the third electrode and the second electrode can be controlled with high accuracy, or the power can be reduced.

(First embodiment)
FIG. 3 is a diagram illustrating a configuration example of an AC type plasma display device having a four-electrode structure according to the first embodiment of the present invention. The power supply circuit 8 supplies power to the control circuit 7. The control circuit 7 controls the X drive circuit 4, the Y drive circuit 5, the Z drive circuits 9 and 10, and the address drive circuit 6. The X drive circuit 4 supplies a predetermined voltage to a plurality of X electrodes (sustain electrodes) X1, X2,. Hereinafter, each of the X electrodes X1, X2,... Or their generic name is referred to as an X electrode X. The Y drive circuit 5 supplies a predetermined voltage to a plurality of Y electrodes (scan electrodes) Y1, Y2,. Hereinafter, each of the Y electrodes Y1, Y2,... Or their generic name is referred to as a Y electrode Y. The Z drive circuit 9 supplies a predetermined voltage to odd-numbered Z electrodes (trigger electrodes) Zo. The Z drive circuit 10 supplies a predetermined voltage to even-numbered Z electrodes (trigger electrodes) Ze. Hereinafter, each of the Z electrodes Zo and Ze or their generic name is referred to as a Z electrode Z. The address drive circuit 6 supplies a predetermined voltage to the plurality of address electrodes A1, A2,. Hereinafter, each of the address electrodes A1, A2,... Or their generic name is referred to as an address electrode A. This four-electrode structure has an address electrode A, an X electrode X, a Y electrode Y, and a Z electrode Z. The Z electrode Z is provided between the X electrode X and the Y electrode Y.

  In the plasma display panel 3, X electrodes X, Z electrodes Z, and Y electrodes Y form rows extending in parallel in the horizontal direction, and address electrodes A form columns extending in the vertical direction. The address electrode A is disposed so as to intersect the X electrode X, the Z electrode Z, and the Y electrode Y. The X electrode X, the Y electrode Y, and the Z electrode Z are alternately arranged in the vertical direction. The Y electrode Yi and the address electrode Aj form a two-dimensional matrix with i rows and j columns. The display cell C11 is formed by the intersection of the Y electrode Y1 and the address electrode A1, and the corresponding Z electrode Zo and X electrode X1 corresponding thereto. This display cell C11 corresponds to a pixel. With this two-dimensional matrix, the panel 3 can display a two-dimensional image. The Z electrode Zo is, for example, an electrode for assisting discharge between the X electrode X1 and the Y electrode Y1, and the Z electrode Ze is, for example, an electrode for assisting discharge between the Y electrode Y1 and the X electrode X2.

  FIG. 2 is an exploded partial perspective view showing a structural example of the plasma display panel 3 according to the present embodiment. The X electrode 11 is a transparent electrode, and the X electrode 12 is a bus electrode. The X electrodes 11 and 12 correspond to the X electrode X in FIG. The bus electrode has a lower electrical resistance value than the transparent electrode. The Y electrode 13 is a transparent electrode, and the Y electrode 14 is a bus electrode. The Y electrodes 13 and 14 correspond to the Y electrode Y in FIG. The Z electrodes 15 and 17 are transparent electrodes, and the Z electrodes 16 and 18 are bus electrodes. The Z electrodes 15 to 18 correspond to the Z electrode Z in FIG. For example, the Z electrodes 15 and 16 correspond to odd-numbered Z electrodes Zo, and the Z electrodes 17 and 18 correspond to even-numbered Z electrodes Ze. The address electrode 21 corresponds to the address electrode A in FIG. The Z electrode Z is disposed in a gap where the X electrode X and the Y electrode Y are discharged. The X electrode X, Y electrode Y, Z electrode Z, and address electrode A are formed in the same process.

  X electrodes 11 and 12, Y electrodes 13 and 14, and Z electrodes 15 to 18 are formed on front glass substrate 1. A dielectric layer 19 for insulating the discharge space is deposited thereon. Further thereon, an MgO (magnesium oxide) protective layer 20 is deposited. On the other hand, the address electrode 21 is formed on the rear glass substrate 2 disposed to face the front glass substrate 1. A dielectric layer 22 is deposited thereon. Further thereon, phosphors 24-26 are deposited. On the inner surface of the partition wall (rib) 23, red, blue and green phosphors 24 to 26 are arranged and applied in stripes for each color. The phosphors 24 to 26 are excited by the sustain discharge between the X electrodes 11 and 12 and the Y electrodes 13 and 14, and each color emits light. In the discharge space between the front glass substrate 1 and the back glass substrate 2, Ne + Xe Penning gas (discharge gas) or the like is enclosed.

  FIG. 4 is a diagram illustrating a configuration example of one field FD1 of an image. One field FD1 is formed by, for example, a first subfield 31, a second subfield 32,. The number of subfields is 10, for example, and is related to the number of gradation bits. A field FD2 following the field FD1 is the same as the field FD1. Each field can display one image and is displayed at 60 fields / second.

  Each subfield 31 to 40 includes a reset period 41, an address period 42, and a sustain (sustain discharge) period 43. In the reset period 41, the display cell C11 and the like are initialized. In the address period 42, light emission or non-light emission of each display cell can be selected by address discharge between the address electrode A and the Y electrode Y. Specifically, a scan pulse is sequentially applied to the Y electrodes Y1, Y2, Y3, Y4,..., An address pulse is applied to the address electrode A corresponding to the scan pulse, and the potential of the X electrode X is applied. Is set to a potential that can be discharged between the Y electrode Y, and the discharge between the Y electrode Y and the address electrode A is used as a trigger to discharge between the X electrode X and the Y electrode Y. Can be selected. In the sustain period 43, using the Z electrode Z, a sustain discharge is performed between the X electrode X and the Y electrode Y of the selected display cell to emit light. In each subfield 31 to 40, the number of times of light emission by the sustain pulse between the X electrode X and the Y electrode Y (the length of the sustain period 43) is different. Thereby, the gradation value can be determined.

  FIG. 12 is a diagram illustrating an example of a progressive voltage waveform. An example of voltage waveforms in the reset period 41, the address period 42, and the sustain period 43 in FIG. 4 is shown. The voltage Vx is a voltage waveform of the X electrode X. The voltage Vy is a voltage waveform of the Y electrode Y. The voltage Vzo is a voltage waveform of the odd-numbered Z electrode Zo. The voltage Va is a voltage waveform of the address electrode A. Further, since the even-numbered Z electrode Ze is unnecessary, it is only necessary to always maintain the ground potential.

  First, the reset period 41 will be described. A write voltage 50 and an adjustment voltage 51 are applied as the voltage Vx. Further, as the voltage Vy, a write blunt wave voltage 60 and an adjustment blunt wave voltage 61 are applied. Thereby, between the X electrode X and the Y electrode Y, a write discharge and a reset discharge for reset are generated.

  Next, the address period 42 will be described. A scan voltage 52 is applied as the voltage Vx. A scan pulse 62 is applied as the voltage Vy. Specifically, the scan pulse 62 is sequentially applied to the Y electrodes Y1, Y2, Y3, Y4,. Further, an address pulse 90 is applied to the display cell to be selected as the voltage Va in synchronization with the scan pulse 62 of each row. When the address pulse 90 is applied corresponding to the scan pulse 62, a discharge occurs between the Y electrode Y and the address electrode A. Using this discharge as a fire, a discharge occurs between the X electrode X and the Y electrode Y, and wall charges are generated in the vicinity of the X electrode X and the Y electrode Y.

  Another voltage waveform example of the address period 42 will be described. The address period 42 is divided into a first half address period and a second half address period. As the voltage Vy, the scan pulse 62 is sequentially applied only to the odd-numbered Y electrodes Y1, Y3, etc. in the first half address period, and the scan pulse 62 is sequentially applied only to the even-numbered Y electrodes Y2, Y4, etc. in the subsequent second address period. To do. In the first half address period, the scan voltage 52 is applied to the odd-numbered X electrodes X1 and X3 as the voltage Vx, and the display cell to be selected is synchronized with the scan pulse 62 of the odd-numbered Y electrodes Y1 and Y3 as the voltage Va. An address pulse 90 is applied to. In the latter half address period, the scan voltage 52 is applied to the even-numbered X electrodes X2 and X4 as the voltage Vx, and the display cell to be selected is synchronized with the scan pulse 62 of the even-numbered Y electrodes Y2 and Y4 as the voltage Va. An address pulse 91 is applied.

  Next, the sustain period 43 will be described. As the voltage Vx, a first sustain pulse 53, repetitive sustain pulses 54 and 55, and an erase pulse 56 are applied. The repetitive sustain pulses 54 and 55 are repeatedly applied with pulses whose polarities are alternately inverted. In addition, a first sustain pulse 63, repeated sustain pulses 64 and 65, and an erase pulse 66 are applied as the voltage Vy. The repetitive sustain pulses 64 and 65 are pulses that are alternately applied with pulses whose polarities are alternately reversed, and are reversed with respect to the repetitive sustain pulses 54 and 55. Further, as the voltage Vzo, the trigger pulse 70 is applied corresponding to the first sustain pulses 53 and 63, the trigger pulses 71 and 72 are applied corresponding to the repeated sustain pulses 54, 55, 64, 65, and the erase pulse. A trigger pulse 73 is applied corresponding to 56 and 66.

  In the sustain period 43, only the display cells in which the wall charges are generated by applying the address pulses 90 and 91 in the address period 42 can be discharged. The trigger pulse 70 and the first sustain pulse 53 cause a discharge between the Z electrode Z and the X electrode X, and then the first sustain pulse 53 and 63 causes a discharge between the X electrode X and the Y electrode Y. Thereby, the sustain discharge is subsequently started.

  Further, the trigger pulse 71 and the repetitive sustain pulse 64 cause a discharge between the Z electrode Z and the Y electrode Y, and then the repetitive sustain pulses 54 and 64 cause a discharge between the X electrode X and the Y electrode Y. Further, the trigger pulse 72 and the repetitive sustain pulse 55 cause discharge between the Z electrode Z and the X electrode X, and then the repetitive sustain pulses 55 and 65 cause discharge between the X electrode X and the Y electrode Y. The discharge is repeated as many times as the number of sustain pulses. The sustain discharge emits light.

  Further, the trigger pulse 73 and the erase pulse 66 cause a discharge between the Z electrode Z and the Y electrode Y, and the erase pulses 56 and 66 thereafter cause an erase discharge between the X electrode X and the Y electrode Y. By this erasing discharge, the wall charge of the emitted display cell is reduced, so that the sustain discharge does not occur.

  Next, at the beginning of the reset period 41, the obtuse wave voltage 58 is applied as the voltage Vx, and the pulse 68 is applied as the voltage Vy. Then, it leads to the reset period 41 described above.

  FIG. 7 is an enlarged view of the pulse 54 of the voltage Vx, the pulse 71 of the voltage Vzo, and the pulse 64 of the voltage Vy of FIG. Before the pulse 64, for example, the voltage Vx is a negative voltage -Vs (for example, -88V), the voltage Vzo is a ground, and the voltage Vy is a positive voltage + Vs (for example, + 88V). Next, as the pulse 64, the voltage Vy is lowered from the positive voltage + Vs to the negative voltage -Vs. Next, as the pulse 71, the voltage Vzo is raised from the ground to a positive voltage (for example, + Vs). Then, 2 × Vs [V] (for example, 176 [V]) is applied between the Z electrode Zo and the Y electrode Y, and a discharge is generated between the Z electrode Zo and the Y electrode Y. Thereby, the charged particle density in the discharge space is increased, and the discharge start voltage between the X electrode X and the Y electrode Y having a wide electrode interval is decreased. Next, as the pulse 71, the voltage Vzo is lowered from the positive voltage to the ground, and as the pulse 54, the voltage Vx is raised from the negative voltage -Vs to the positive voltage + Vs. Then, 2 × Vs [V] is applied between the X electrode X and the Y electrode Y, a main discharge is generated between the X electrode X and the Y electrode Y, and discharge light emission is started. Thereafter, the voltage Vx is lowered from the positive voltage + Vs to the negative voltage −Vs as a pulse 55. Next, as the pulse 72, the voltage Vzo is raised from the ground to a positive voltage (for example, + Vs). Then, 2 × Vs [V] (for example, 176 [V]) is applied between the Z electrode Zo and the X electrode X, and a discharge is generated between the Z electrode Zo and the X electrode X. Thereby, the charged particle density in the discharge space is increased, and the discharge start voltage between the X electrode X and the Y electrode Y having a wide electrode interval is decreased. Next, as the pulse 72, the voltage Vzo is lowered from the positive voltage to the ground, and as the pulse 65, the voltage Vy is raised from the negative voltage -Vs to the positive voltage + Vs. Then, discharge occurs between the X electrode X and the Y electrode Y, and main discharge light emission starts. By repeating the above processing, a sustain discharge is generated between the X electrode X and the Y electrode Y.

  The plasma display device of this embodiment has a four-electrode structure having X electrodes X, Y electrodes Y, Z electrodes Z, and address electrodes A. On the other hand, a plasma display device having a three-electrode structure including the X electrode X, the Y electrode Y and the address electrode A also exists, and the Z electrode Z does not exist. Even with a three-electrode structure, sustain discharge can be performed. The longer the distance between the X electrode X and the Y electrode Y, the better the light emission efficiency. However, if the distance is increased, unless a higher voltage is applied between the X electrode X and the Y electrode Y, no discharge occurs between the X electrode X and the Y electrode Y, and a large power consumption is required.

  The four-electrode structure of the present embodiment realizes improvement in light emission efficiency and low power consumption. By increasing the distance between the X electrode and the Y electrode Y, the light emission efficiency can be improved. Furthermore, by providing the Z electrode Z, a low voltage can be applied between the X electrode X and the Y electrode Y to cause discharge light emission. In the four-electrode structure, the voltage applied between the X electrode X and the Y electrode Y during discharge light emission is lower than the lowest voltage that is discharged between the X electrode X and the Y electrode Y without applying a pulse to the Z electrode Z. A voltage is sufficient.

  In the case of FIG. 7, first, auxiliary discharge is performed between the Z electrode Zo and the Y electrode Y, and then main discharge is performed between the X electrode X and the Y electrode Y. This discharge timing is very important. However, when the pulse 71 of the voltage Vzo and the pulse 64 of the voltage Vy are applied, if the electric field between the Z electrode Zo and the Y electrode Y is weak, the discharge timing between the Z electrode Zo and the Y electrode Y is delayed. In order to solve this, the electric field between the Z electrode Zo and the Y electrode Y may be increased. In the present embodiment, a delay in discharge timing between the Z electrode Zo and the Y electrode Y (or X electrode X) is prevented without changing the voltage applied between the Z electrode Zo and the Y electrode Y. This will be described below.

FIG. 1 is an enlarged cross-sectional view of a part of the front glass substrate 1 of FIG. The X electrode 27 includes the transparent electrode 11 and the bus electrode 12. The Z electrode 29 includes the transparent electrode 15 and the bus electrode 16. The Y electrode 28 includes the transparent electrode 13 and the bus electrode 14. The Z electrode 30 includes a transparent electrode 17 and a bus electrode 18. The dielectric layer 19 is formed so as to cover the X electrode 27, the Y electrode 28, and the Z electrodes 29 and 30. The thickness T1 of the dielectric layer 19 is, for example, 30 μm. The dielectric layer 19 on the Z electrodes 29 and 30 is provided with a recess 19a. The depth T2 of the recess 19a is, for example, 10 to 20 μm. The height of the recess 19a of the dielectric layer 19 on the Z electrodes 29 and 30 changes gently. The dielectric layer 19 covering the Z electrodes 29 and 30 is thinner than the dielectric layer 19 covering the X electrode 27 and the Y electrode 28. The materials of the Z electrodes 29 and 30 are the same as the materials of the X electrode 27 and the Y electrode 28. The bus electrodes 12, 14, 16 and 18 are made of, for example, a three-layer structure of Cr—Cu—Cr. The dielectric layer 19 is a low-melting glass containing lead, for example. As another example, the thickness T1 of the dielectric layer 19 is, for example, 20 μm, and the depth T2 of the recess 19a is about 10 μm. At this time, the material of the dielectric layer 19 is, for example, low-melting glass not containing lead. As yet another example, the thickness T1 of the dielectric layer 19 is, for example, 10 μm, and the depth T2 of the recess 19a is about 5 μm. At this time, the dielectric layer 19 is, for example, silicon oxide (SiO ₂ ) formed by vapor deposition.

  Since the dielectric layer 19 covering the Z electrode 29 is thin, the electric field between the Z electrode 29 and the X electrode 27 becomes strong. Similarly, the electric field between the Z electrode 29 and the Y electrode 28 becomes strong. On the other hand, the electric field between the X electrodes 27 and 28 hardly changes. Since the electric field between the Z electrode 29 and the X electrode 27 becomes strong, a delay in discharge between the Z electrode 29 and the X electrode 27 can be prevented. Similarly, since the electric field between the Z electrode 29 and the Y electrode 28 becomes strong, a delay in discharge between the Z electrode 29 and the Y electrode 28 can be prevented. As a result, it is possible to perform a sustain discharge with low power and good luminous efficiency (ratio of luminance with respect to input power).

  FIG. 8 is a plan view of the plasma display panel of FIG. The recess 19a in FIG. 1 is provided continuously along the Z electrodes 15 and 16 and across a plurality of display cells. The barrier ribs 23 are arranged in stripes between the address electrodes 21. The concave portion 19a of the dielectric layer on the Z electrodes 15 and 16 partially overlaps the partition wall 23.

(Second Embodiment)
FIG. 9 is a plan view of a plasma display panel (FIG. 2) according to the second embodiment of the present invention, and corresponds to FIG. Hereinafter, the points of the present embodiment different from the first embodiment will be described. The barrier ribs 23 are arranged in stripes between the address electrodes 21. The recess 19a in FIG. 1 is provided independently for each display cell and does not overlap the partition wall 23. As a result, charge crosstalk between display cells adjacent in the horizontal (lateral) direction of FIG. 9 can be prevented.

(Third embodiment)
FIG. 11 is an exploded partial perspective view showing a structural example of the plasma display panel 3 (FIG. 3) according to the third embodiment of the present invention, and corresponds to FIG. FIG. 10 is an enlarged cross-sectional view of a part of the front glass substrate 1 and the back glass substrate 2 of FIG. Hereinafter, the points of the present embodiment different from the first embodiment will be described. In the present embodiment, box-type partition walls 23a and 23b are provided in place of the stripe-type partition wall 23 of the first embodiment. The vertical partition walls 23 a are arranged so as to extend in the vertical direction in parallel with the address electrodes 21, similarly to the stripe-type partition walls 23. The horizontal partition 23b is arranged to extend in the horizontal direction in parallel with the X electrodes 11, 12, the Y electrodes 13, 14, and the Z electrodes 15-18. The box-type partition walls 23a and 23b are provided so as to separate and surround all the display cells. The display cell includes an X electrode, a Y electrode, and a Z electrode. As in FIG. 8, the recess 19 a partially overlaps with the vertical partition wall 23 a (the partition wall 23 in FIG. 8).

  In the case of the box-type partition walls 23a and 23b, the display cells are separated and sealed. In this case, the discharge space between the front glass substrate 1 and the back glass substrate 2 cannot be evacuated and the discharge gas cannot be enclosed. In the present embodiment, since the recess 19a overlaps the vertical partition wall 23a, the discharge spaces of all the display cells are connected via the recess 10a. The discharge space can be evacuated and filled with discharge gas through the path of the recess 19a.

(Fourth embodiment)
FIG. 5 is an exploded partial perspective view showing a structural example of the plasma display panel 3 (FIG. 3) according to the fourth embodiment of the present invention, and corresponds to FIG. 6 is an enlarged cross-sectional view of a part of the front glass substrate 1 of FIG. 5, and corresponds to FIG. Hereinafter, the points of the present embodiment different from the first embodiment will be described. In the present embodiment, bus electrodes 16a and 18a are provided instead of the bus electrodes 16 and 18 of the first embodiment. The bus electrode 16a will be described as an example, but the bus electrode 18a is the same as the bus electrode 16a. In the present embodiment, the surface of the dielectric layer 19 is a plane. The thickness T3 of the dielectric layer 19 is, for example, 10 μm. The thickness T4 of the bus electrode 12 of the X electrode 27 and the bus electrode 14 of the Y electrode 28 is, for example, 2 to 3 μm. A thickness T5 of the bus electrode 16a of the Z electrode 29 is, for example, 5 μm. The transparent electrodes 11, 13, and 15 have the same thickness T6, for example, 0.1 to 0.2 μm. The Z electrode 29 is thicker than the X electrode 27 and the Y electrode 28. As a result, the thickness of the dielectric layer 19 covering the Z electrode 29 is thinner than the thickness of the dielectric layer 19 covering the X electrode 27 and the Y electrode 28. The material of the Z electrode 29 is different from the material of the X electrode 27 and the Y electrode 28. The material of the bus electrodes 12 and 14 of the X electrode 27 and the Y electrode 28 is, for example, a three-layer structure of Cr—Cu—Cr. The material of the bus electrode 16a of the Z electrode 29 is, for example, silver (Ag). The dielectric layer 19 is, for example, silicon oxide (SiO ₂ ) formed by a vapor deposition method.

  Since the dielectric layer 19 covering the Z electrode 29 is thin, the electric field between the Z electrode 29 and the X electrode 27 becomes strong. Similarly, the electric field between the Z electrode 29 and the Y electrode 28 becomes strong. On the other hand, the electric field between the X electrodes 27 and 28 hardly changes. Since the electric field between the Z electrode 29 and the X electrode 27 becomes strong, a delay in discharge between the Z electrode 29 and the X electrode 27 can be prevented. Similarly, since the electric field between the Z electrode 29 and the Y electrode 28 becomes strong, a delay in discharge between the Z electrode 29 and the Y electrode 28 can be prevented. As a result, it is possible to perform a sustain discharge with low power and good luminous efficiency (ratio of luminance with respect to input power).

(Fifth embodiment)
As a fifth embodiment of the present invention, an ALIS (Alternate Lighting of Surfaces Method) plasma display device will be described. 4, in the odd field FD1, etc., the display cell between the X electrode X1 and the Y electrode Y1, the display cell between the X electrode X2 and the Y electrode Y2, the display cell between the X electrode X3 and the Y electrode Y3, the X electrode X4 and Display is performed by a sustain discharge in a display cell or the like between the Y electrodes Y4. At this time, the sustain discharge is performed using the odd-numbered Z electrodes Zo. Thereafter, in the even field FD2, etc., display is performed by sustain discharge in the display cell between the Y electrode Y1 and the X electrode X2, the display cell between the Y electrode Y2 and the X electrode X3, the display cell between the Y electrode Y3 and the X electrode X4, and the like. I do. At this time, the sustain discharge is performed using the even-numbered Z electrodes Ze.

  In the ALIS system, the X electrode X has a discharge slit between the Y electrode Y adjacent to both sides, and can be discharged. Similarly, the Y electrode Y has a discharge slit between the X electrode X adjacent on both sides and can discharge. The discharge slit for discharging varies from field to field.

  FIG. 13 is a diagram illustrating an example of the voltage waveform of the ALIS system according to the present embodiment, and corresponds to FIG. An example of voltage waveforms in the reset period 41, the address period 42, and the sustain period 43 in FIG. 4 is shown. The voltage Vxo is a voltage of the odd-numbered X electrodes X1, X3 and the like. The voltage Vyo is a voltage of the odd-numbered Y electrodes Y1, Y3 and the like. The voltage Vzo is a voltage of the odd-numbered Z electrode Zo. The voltage Vze is the voltage of the even-numbered Z electrode Ze. The voltage Va is a voltage of the address electrode A. FIG. 13 shows an example of the voltage waveform of the odd field FD1 and the like. The voltage Vxo is the same as the voltage Vx in FIG. The voltage Vyo is the same as the voltage Vy in FIG. The voltage Vzo is the same as the voltage Vzo in FIG. In the odd field FD1 or the like, the Z electrode Ze is located between discharge slits that do not discharge. Therefore, the voltage Vze maintains the ground. The voltage Va is the same as the voltage Va in FIG. In the sustain period 43, the voltage Vxe of the even-numbered X electrodes X2, X4 etc. is inverted with respect to the voltage Vxo, and the voltage Vye of the even-numbered Y electrodes Y2, Y4 etc. is inverted with respect to the voltage Vyo.

  Next, voltage waveforms in the even field FD2 and the like will be described. The voltage Vyo is the same as the voltage Vyo of the odd field FD1 etc. (FIG. 13). The voltage Vxe of the even-numbered X electrodes X2, X4, etc. is the same as the voltage Vxo of the odd-numbered field FD1, etc. (FIG. 13). In the repetitive sustain pulse of the sustain period 43, the voltage Vxo of the odd-numbered X electrodes X1, X3 etc. is inverted with respect to the voltage Vxe, and the voltage Vye of the even-numbered Y electrodes Y2, Y4 etc. is inverted with respect to the voltage Vyo. Is. The voltages Vzo and Vze are obtained by reversing the odd field FD1 and the like (FIG. 13). That is, the voltage Vzo maintains the ground potential. The voltage Vze has trigger pulses 70 to 73.

  12, the display cell between the X electrode X1 and the Y electrode Y1, the display cell between the X electrode X2 and the Y electrode Y2, the display cell between the X electrode X3 and the Y electrode Y3, the X electrode X4 and the Y electrode Y4. Only the display by the sustain discharge in the display cell or the like is possible. In the ALIS system shown in FIG. 14, the sustain discharge is further caused in the display cell between the Y electrode Y1 and the X electrode X2, the display cell between the Y electrode Y2 and the X electrode X3, the display cell between the Y electrode Y3 and the X electrode X4, and the like. Since display is also possible, high resolution can be realized.

  As described above, according to the first to fifth embodiments, the thickness of the dielectric layer 19 covering the Z electrode group (a group of a plurality of Z electrodes) is set to the X electrode group (a group of a plurality of X electrodes). And a thickness of the dielectric layer 19 covering the Y electrode group (group of Y electrodes). Thereby, the electric field in the discharge space between the Z electrode and the X electrode can be strengthened, and the electric field in the discharge space between the Z electrode and the Y electrode can be strengthened. By strengthening the electric field, the delay of the discharge timing between the Z electrode and the X electrode can be prevented, and the delay of the discharge timing between the Z electrode and the Y electrode can be prevented, and the luminous efficiency of the plasma display device having a four-electrode structure Can be high. In addition, since the voltages of the X electrode, the Y electrode, and the Z electrode can be lowered, the power can be reduced.

  The plasma display device of the present embodiment can be used for a display device such as a personal computer or a workstation, a flat wall-mounted television, or a display device for displaying advertisements or information.

  In the above embodiment, the voltage applied to the Z electrode is Vs, which is the same as the sustain pulse, but may be lower than Vs by reducing the thickness of the dielectric layer on the Z electrode. In addition, each of the above-described embodiments is merely a specific example for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is sectional drawing to which some front glass substrates by the 1st Embodiment of this invention were expanded. It is a disassembled partial perspective view which shows the structural example of the plasma display panel by 1st Embodiment. It is a figure which shows the structural example of the AC type plasma display apparatus of the 4 electrode structure by 1st Embodiment. It is a figure which shows the structural example of 1 field of an image. It is a disassembled partial perspective view which shows the structural example of the plasma display panel by the 4th Embodiment of this invention. It is sectional drawing to which some front glass substrates of FIG. 5 were expanded. FIG. 13 is an enlarged view of a pulse 54 of voltage Vx, a pulse 71 of voltage Vz, and a pulse 64 of voltage Vy in FIG. 12. It is a top view of the plasma display panel of FIG. It is a top view of the plasma display panel by the 2nd Embodiment of this invention. It is sectional drawing to which some front glass substrates and back glass substrates of FIG. 11 were expanded. It is a disassembled partial perspective view showing a structural example of a plasma display panel according to a third embodiment of the present invention. It is a figure which shows the voltage waveform example of a progressive system. It is a figure which shows the voltage waveform example of the ALIS system by the 5th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Front glass substrate 2 Back glass substrate 3 Plasma display panel 4 X drive circuit 5 Y drive circuit 6 Address drive circuit 7 Control circuit 8 Power supply circuit 9, 10 Z drive circuit 11 X transparent electrode 12 X bus electrode 13 Y transparent electrode 14 Y Bus electrodes 15 and 17 Z transparent electrodes 16 and 18 Z bus electrode 19 Dielectric layer 19 a Recess 20 Protective layer 21 Address electrode 22 Dielectric layer 23 Partitions 24 to 26 Phosphor layer 27 X electrode 28 Y electrodes 29 and 30 Z electrode 31 -40 Subfield 41 Reset period 42 Address period 43 Sustain period

Claims (11)

A first substrate;
A second substrate disposed opposite the first substrate;
A first electrode group that is disposed in parallel on the first substrate, and a third electrode group that is disposed in a gap that discharges the first and second electrode groups;
A dielectric layer covering the first to third electrode groups;
A fourth electrode group disposed on the second substrate so as to intersect the first to third electrode groups,
The plasma display panel according to claim 1, wherein a thickness of the dielectric layer covering the third electrode group is thinner than a thickness of the dielectric layer covering the first and second electrode groups.   The plasma display panel according to claim 1, wherein the dielectric layer on the third electrode group is provided with a recess.   3. The plasma display panel according to claim 2, wherein a material of the third electrode group is the same as that of the first and second electrode groups. And a partition disposed between the fourth electrodes,
4. The plasma display panel according to claim 2, wherein the concave portion of the dielectric layer on the third electrode group does not overlap the partition wall. Furthermore, it has a box-type partition for separating a display cell including the set of the first to third electrodes,
4. The plasma display panel according to claim 2, wherein the concave portion of the dielectric layer on the third electrode group overlaps with the partition wall.   6. The plasma display panel according to claim 2, wherein the dielectric layer is silicon oxide formed by a vapor deposition method.   The plasma display panel according to claim 2, wherein the height of the concave portion of the dielectric layer on the third electrode group changes gently.   The plasma display panel according to claim 1, wherein the thickness of the third electrode group is thicker than the thicknesses of the first and second electrode groups.   9. The plasma display panel according to claim 8, wherein a material of the third electrode group is different from a material of the first and second electrode groups.   10. The plasma display panel according to claim 8, wherein a surface of the dielectric layer is a flat surface.   A plasma display device comprising the plasma display panel according to claim 1.

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