JP2007048978A - Semiconductor device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which defective products are reduced by preventing the occurrence of plating burrs. <P>SOLUTION: In the method for manufacturing a semiconductor device 28 by: forming plating masks 38 and 39 having a noble metal plating layer 35 as an uppermost layer at a predetermined part on the surface or the backside of a lead frame material 10; etching the lead frame material 10 sequentially using the plating masks 38 and 39 as a resist mask and conducting it electrically with a semiconductor element 18 arranged in a sealing resin 21; and then forming a projecting external connection terminal 22 at a lower portion, wherein lowermost layer of the plating masks 38 and 39 includes base metal plating or noble metal plating 33 exhibiting etching liquid resistance. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to, for example, a CSP (chip size package) semiconductor device, and more particularly, to a semiconductor device in which an external connection terminal portion protrudes to the bottom surface side of a sealing resin and a manufacturing method thereof.

From the demand for miniaturization of semiconductor devices, tape CSP type semiconductor devices using polyimide resin tape and solder balls, and BCC (bump chip carrier) type semiconductor devices using base metal are known. However, in the tape CSP type semiconductor device, there is a problem that the polyimide resin tape is expensive and is not suitable for strip conveyance due to its softness. Further, in the BCC type semiconductor device, when the base metal is removed by etching, it becomes a solid piece, so that there is a problem that it is necessary to fix the mold surface with an adhesive tape and the cost is increased. Therefore, the present applicant has previously proposed a method of manufacturing a semiconductor device described in Patent Document 1.

An example of the manufacturing method of this semiconductor device is shown in FIGS. 4A to 4J. Resist films are formed on the front and back of the lead frame material 10 made of Cu, Cu alloy, or iron nickel alloy (for example, 42 alloy). After coating 11 on the entire surface, a predetermined lead pattern is exposed and then developed to form an etching pattern 12 for a plating mask. Then, when the lead frame material 10 is entirely plated and the resist film 11 is removed, plating masks 13 and 14 are formed on the front and back surfaces (A to D).
Next, after coating the entire lower surface (that is, the back surface side) with another resist film 15, half etching is performed on the upper surface side (that is, the front surface side) using the plating mask 13 as a resist mask. In this case, since the portion covered with the plating mask 13 on the surface of the lead frame material 10 is not etched, the element mounting portion 16 and the wire bonding portion 17 formed in advance with a resist film will eventually protrude. In addition, the surface of this element mounting part 16 and the wire bonding part 17 is covered with the plating mask 13 (above, E, F).

Next, after removing the resist film 15 on the lower surface side, the semiconductor element 18 is placed on the element mounting portion 16, and wire bonding between each electrode pad portion of the semiconductor element 18 and the wire bonding portion 17 is performed. Then, the resin sealing of the bonding wire 20 and the wire bonding portion 17 is performed. 21 shows sealing resin (G, H above).
Thereafter, the back side is half-etched, but the portion where the plating mask 14 is formed on the lead frame material 10 remains without being etched with the plating mask 14 serving as a resist mask. As a result, the external connection terminal portion 22 is left. And the back surface of the element mounting part 16 protrudes. Since the external connection terminal portion 22 and the wire bonding portion 17 are in communication with each other, each external connection terminal portion 22 (and the wire bonding portion 17 in communication therewith) is independently connected to each electrode pad portion of the semiconductor element 18. Connected. Since a plurality of these semiconductor devices 23 are generally manufactured in a lattice form and are manufactured simultaneously, the individual semiconductor devices 23 are manufactured by cutting and separating (solidifying) (I, J).

JP 2001-24135 A

However, in the conventional semiconductor device described above, the plating masks 13 and 14 are configured as shown in FIG. That is, the plating masks 13 and 14 are formed by performing Ni base plating 24 having a thickness of, for example, 1 μm on the front surface (including the back surface) of the lead frame material 10, and precious metal plating having a thickness of approximately 0.2 μm (for example, Au ) 25 is performed. Of course, the noble metal plating 25 on the upper layer side (the layer far from the lead frame material 10 is the upper layer and the closer layer is the lower layer) has etching solution resistance, so it is not eroded during etching. Alternatively, the lead frame material 10 made of a copper alloy and the Ni underlayer plating 24 on the lower layer side are eroded by the etching solution as shown in FIG. 6A, and as shown in FIGS. 6A and 6B. In addition, the periphery of the noble metal plating 25 is formed in a foil shape and adheres to the periphery of the wire bonding portion 17, the element mounting portion 16, and the external connection terminal portion 22 to form a plating burr (plating foil piece) 26.
When such a plating burr 26 is present, the plating burr 26 is peeled off in a wire bonding process, a resin sealing process (that is, a molding process), etc., causing a semiconductor device defect such as a wire bonding defect or a short circuit between terminals. .

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device with few defective products by suppressing the occurrence of plating burrs and a semiconductor device manufactured thereby.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a plating mask having a noble metal plating layer as an uppermost layer at a predetermined position on a front surface side or a back surface side of a lead frame material; In the method of manufacturing a semiconductor device in which the lead frame material is sequentially etched using a resist mask to electrically communicate with a semiconductor element disposed inside a sealing resin, and to form an external connection terminal portion protruding downward. The bottom layer of the plating mask was subjected to base metal plating or noble metal plating having etching solution resistance.
In the present invention, the lowermost plating of the plating mask refers to a plating layer that is in direct contact with the surface (and back surface) of the lead frame material, and the uppermost plating refers to the plating layer farthest from the lead frame material. Say.
In the method for manufacturing a semiconductor device according to the present invention, the plating mask is preferably thick, for example, 1 to 10 μm. In this case, when a plating layer (for example, Ni plating layer) that is easily eroded by the etching solution is disposed in the intermediate portion, the plating layer is eroded by the etching solution, so that the total thickness is 9/10 or less (preferably 4/5 or less). Moreover, since tin plating is hard to be eroded by the etching solution, it can be used in place of the lowermost noble metal plating layer (the same applies to the following inventions).
Moreover, in this invention (namely, 1st-5th invention), base metal plating which has etching-liquid resistance means tin plating, tin bismuth plating, leaded solder plating, lead-free solder plating, etc., for example.

According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a wire bonding portion formed around a semiconductor element portion on a surface side of a lead frame material; and a back surface of the lead frame material corresponding to the wire bonding portion. A first step of forming a plating mask having a noble metal plating layer as the uppermost layer on the external connection terminal formed on the side, and an etching resistant resist film is formed on the back side of the lead frame material, and then formed on the front side Etching the lead frame material to a predetermined depth from the surface side using the plated mask as a resist mask, a second step of projecting the wire bonding portion, and mounting a semiconductor element on the lead frame material, Connection between the electrode pad portion of the semiconductor element and the corresponding wire bonding portion by a bonding wire A third step of forming an electrically conductive circuit; a fourth step of resin-sealing the surface side of the lead frame material including the semiconductor element, the bonding wire, and the wire bonding portion; and the etching resistant resist film. A method of manufacturing a semiconductor device comprising: a fifth step of performing etching on the rear surface side of the removed lead frame material using the formed plating mask as a resist mask to project the external connection terminal portion independently. In
The bottom layer of the plating mask was subjected to base metal plating or noble metal plating having etching solution resistance.

In the semiconductor device manufacturing method according to the first and second inventions, an element mounting portion may be formed independently of the external connection terminal portion at the center of the lead frame material. . In this method of manufacturing a semiconductor device, a terminal for heat dissipation may be provided immediately below the semiconductor element.

According to the third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein the uppermost portion is a noble metal plating at a position corresponding to an electrode pad portion disposed at a lower portion of a semiconductor element mounted on the front surface side of the lead frame material. A first step of forming a plating mask comprising layers, and after forming an etching resistant resist film on the back side of the lead frame material, the lead frame material from the surface side using the plating mask formed on the front side as a resist mask. A second step of performing an etching process to a predetermined depth to project an internal connection terminal portion for electrical connection with the electrode pad portion, mounting the semiconductor element on the lead frame material, and the semiconductor element and the internal A third step of resin-sealing the surface side of the lead frame material including the semiconductor element after electrical connection with the connection terminal portion; and the etching resistance Etching is performed using the formed plating mask as a resist mask on the back surface side of the lead frame material from which the dies film has been removed, and the external connection terminal portion that communicates integrally with the internal connection terminal portion is projected to be independent. In the manufacturing method of the semiconductor device which has the 4th process to make
The bottom layer of the plating mask was subjected to base metal plating or noble metal plating having etching solution resistance.

A semiconductor device according to a fourth invention is manufactured by the method for manufacturing a semiconductor device according to the first to third inventions.
According to a fifth aspect of the present invention, there is provided a semiconductor device having an external connection terminal portion that is electrically connected to a resin-sealed semiconductor element and protrudes to the back surface side.
A connection terminal part (including a wire bonding part and an internal connection terminal part that is in direct contact with the semiconductor element) electrically connected to the electrode pad part of the semiconductor element, and the external connection terminal part are precious metal plated In addition to being composed of layers, the lowermost layer is also subjected to base metal plating or noble metal plating having resistance to etching liquid.

In the method for manufacturing a semiconductor device according to any one of claims 1 to 5, since base metal plating or noble metal plating having etching solution resistance is applied to the bottom layer of the plating mask, generation of plating burrs is suppressed as much as possible, and deburring work is unnecessary. As a result, a method for manufacturing a semiconductor device with a low defect rate can be provided.
In the semiconductor device according to any one of claims 6 and 7, the uppermost layer of the connection terminal portion and the external connection terminal portion electrically connected to the electrode pad portion of the semiconductor element is constituted by a noble metal plating layer. Since the base metal plating or the noble metal plating having the etchant resistance is also applied to the lowermost layer, the thickness of the plating is ensured, and a semiconductor device with less quality and defective products can be provided.

Next, embodiments of the present invention will be described with reference to the accompanying drawings for understanding of the present invention.
FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing details of a wire bonding portion, and FIGS. 3A to 3C are other embodiments of the present invention. It is explanatory drawing of the semiconductor device which concerns on a form.

First, the semiconductor device 28 shown in FIG. 1 will be described. The same components as those in the semiconductor device shown in FIG.
As shown in FIG. 1, a semiconductor device 28 according to an embodiment of the present invention has a semiconductor element 18 at the center, an area array around the semiconductor element 18, and an upper surface side (surface side) as a wire bonding portion 17. A conductor terminal 29 whose lower surface side (back surface side) is the external connection terminal portion 22 is disposed. The wire bonding portion 17 and each electrode pad portion 30 of the semiconductor element 18 are electrically connected by a bonding wire 20, and the upper half of the semiconductor element 18, the bonding wire 20, and the conductor terminal 29 is sealed with a sealing resin 21. It has been stopped.

Details of the conductor terminal 29 are shown in FIG. 1, but an example of a noble metal plating having resistance to an etching solution is first formed above and below a rod-shaped copper conductor 32 formed by etching the lead frame material 10 (see FIG. 4A). A gold plating 33 having a thickness of 0.15 to 0.5 μm, a base plating 34 having a thickness of about 0.5 to 2 μm thereon, and a thickness of 0.15 to 0.5 μm as an example of a noble metal plating thereon. The gold plating 35 is made. In this embodiment, Ni plating is performed as the base plating 34. In addition, although the thickness of the lead frame material 10 is about 0.1 to 0.3 mm, the present invention is not limited to these thicknesses.

The structure of the element mounting portion 16 is plated with the same structure as that of the conductor terminal 29. The lower half of the element mounting portion 16 and the conductor terminal 29 protrudes from the sealing resin 21 and is exposed to the outside. The external connection terminal portion 22 is provided with a plating having good solder wettability at the bottom, and by melting the cream solder provided on the other substrate 36, as shown in FIG. Connection is being made.
An element mounting portion 16 is disposed on the bottom surface side of the semiconductor element 18, thereby promoting heat dissipation from the semiconductor element 18.

Subsequently, a method for manufacturing the semiconductor device 28 will be described, but only differences from the method for manufacturing the conventional semiconductor device 23 shown in FIG. 4 will be described in detail. In FIG. 4, the steps from (A) to (C) are the same, and in the step (D), when plating the entire surface, first, gold having a thickness of 0.15 to 0.5 μm, which is an example of noble metal plating, is used. Plating 33 is performed, and base plating 34 having a thickness of about 0.5 to 2 μm is formed thereon. Next, gold plating 35 having a thickness of 0.15 to 0.5 μm, which is an example of noble metal plating, is performed thereon.
Next, as shown in FIG. 4E, the lower surface side of the lead frame material 10 is entirely covered with an etching resistant resist film 15, and front side half etching is performed as shown in FIG. In this case, since the gold platings 33 and 35 are not eroded by the etching solution, the wire bonding portion 17 is formed as shown in FIG. That is, the lower lead frame material 10 is etched into a predetermined shape, and further, the lead frame material 10 is eroded to the lower peripheral portion of the plating mask 38 made of the gold plating 35, the base plating 34, and the gold plating 33, respectively. . Therefore, although the plating mask 38 protrudes from the periphery of the copper material constituting the wire bonding portion 17, the thickness thereof has the thickness of the gold platings 33 and 35 and the base plating 34. It is not a plating burr that can be removed or removed. Therefore, the defect rate of the semiconductor device 28 is significantly reduced.

Thereafter, as shown in FIG. 4G, after the resist film 15 on the lower surface side is removed and the semiconductor element 18 is placed on the element mounting portion 16, the electrical connection between the semiconductor element 18 and the wire bonding portion 17 is bonded. The wire 20 is used, and the upper side of the lead frame material 10 is resin-sealed (FIG. 4H).
Then, as shown in FIG. 4I, half etching on the back surface side of the lead frame material 10 is performed. Also in this case, the external connection terminal portion 22 and the back surface side of the element mounting portion 16 are covered with the plating mask 39 made of the gold plating 35, the base plating 34, and the gold plating 33, so that the entire configuration is relatively thick. The plating mask 39 is not eroded by the etching solution. Moreover, since the plating mask 39 has a certain thickness (preferably 1 to 10 μm, more preferably 1.5 to 4 μm), it does not become a plating burr.
Next, as shown in FIG. 4J, each semiconductor device 28 is cut and separated to obtain individual semiconductor devices.

Next, semiconductor devices 40, 42, and 45 to which the semiconductor device manufacturing method of the present invention is applied will be described with reference to FIGS.
FIG. 3A shows a semiconductor device 40 of a type in which an element mounting portion (die pad) is omitted, with a gap around the semiconductor element 18 and conductor terminals 29 arranged in a grid array. The upper side of the conductor terminal 29 is the wire bonding portion 17, and the lower side is the external connection terminal portion 22. On the surfaces of the wire bonding portion 17 and the external connection terminal portion 22, plating masks 38 and 39 made of a gold plating 35, a base plating 34, and a gold plating 33 are formed, respectively.
Since the surface areas of these plating masks 38 and 39 are larger than the cross-sectional area of the copper conductor 32, the electrical joining efficiency is improved. Note that the plating mask 38 shown in FIGS. 3A to 3C bulges outward as shown in the enlarged view of FIG.

Next, FIG. 3B shows a semiconductor device 42 in which the element mounting portion is omitted, and a plurality of conductor terminals 29 (heat dissipation terminals) are provided directly below the semiconductor element 18 instead. The conductor terminal 29 disposed immediately below the semiconductor element 18 does not form an energization circuit, but assists heat dissipation from the semiconductor element 18.
On the upper and lower surfaces of each conductor terminal 29, plating masks 38 and 39 made of a gold plating 35, a base plating 34 and a gold plating 33 are formed to prevent the occurrence of plating burrs.

In the semiconductor device 45 shown in FIG. 3C, the electrode pads 44 of the semiconductor elements 43 are arranged in a grid array, and the semiconductor elements 43 are arranged with the electrode pads 44 facing downward. A flip chip (FC) type semiconductor device is provided in which an internal connection terminal portion is provided on the upper side of the semiconductor device 43 and the electrode pad portion 44 of the semiconductor element 43 is directly joined. As a result, the semiconductor device can be further downsized.
In this case as well, plating masks 38 and 39 made of gold plating 35, base plating 34 and gold plating 33 are formed on the upper and lower surfaces of each conductor terminal 29 to prevent generation of plating burrs.

In the above embodiment, the plating masks 38 and 39 perform noble metal plating on the lowermost layer and the uppermost layer, and Ni plating which acts as a base plating on the middle portion. The plating can be a thick base metal plating. In this case, the base metal plating may be any metal as long as it is not eroded by the etching solution, and tin plating, tin bismuth plating, leaded solder plating, lead-free solder plating, etc. having etching solution resistance are used. Is preferred. Since these metals are not easily eroded by the etchant, noble metal plating with a thin surface does not become a plating burr. These base metal platings are sufficient if they are harder to be eroded by the etchant than Ni plating (for example, the etching rate is 1/10 or less), and even if they are somewhat eroded, their thickness is increased (for example, 4 to 4). 8 μm).
4 (F) and 4 (G), the resist film 15 on the lower surface side of the lead frame material 10 was removed after the first half etching, but the resin sealing was completed in FIG. 4 (H). After that, the resist film 15 may be removed.

It is explanatory drawing of the semiconductor device which concerns on one embodiment of this invention. It is sectional drawing which shows the detail of a wire bonding part. (A)-(C) are explanatory drawings of the semiconductor device which concerns on other embodiment of this invention. (A)-(J) are explanatory drawings of the manufacturing method of the semiconductor device which concerns on a prior art example. It is explanatory drawing of the plating mask which concerns on a prior art example. (A), (B) is explanatory drawing which shows the generation | occurrence | production situation of a plating burr | flash.

Explanation of symbols

10: lead frame material, 11: resist film, 12: etching pattern, 13, 14: plating mask, 15: anti-hatch resist film, 16: element mounting part, 17: wire bonding part, 18: semiconductor element, 20: Bonding wire, 21: sealing resin, 22: external connection terminal, 23: semiconductor device, 24: Ni base plating, 25: noble metal plating, 26: plating burr, 28: semiconductor device, 29: conductor terminal, 30: electrode Pad part, 32: Copper conductor, 33: Gold plating, 34: Base plating, 35: Gold plating, 36: Substrate, 38, 39: Plating mask, 40, 42: Semiconductor device, 43: Semiconductor element, 44: Electrode pad Part, 45: semiconductor device

Claims (7)

Form a plating mask having a noble metal plating layer as the uppermost layer at a predetermined position on the front or back side of the lead frame material, and then sequentially etch the lead frame material using the plating mask as a resist mask to form a sealing resin In a method of manufacturing a semiconductor device that forms an external connection terminal portion that is in electrical communication with a semiconductor element disposed inside and protrudes downward.
A method of manufacturing a semiconductor device, characterized in that base metal plating or noble metal plating having an etchant resistance is applied to a lowermost layer of the plating mask. A noble metal on the uppermost layer is formed on the wire bonding portion formed around the semiconductor element portion on the surface side of the lead frame material, and on the external connection terminal portion formed on the back surface side of the lead frame material corresponding to the wire bonding portion. A first step of forming a plating mask having a plating layer; and after forming an etching resistant resist film on the back side of the lead frame material, the lead frame from the front side using the plating mask formed on the front side as a resist mask. A second step of etching the material to a predetermined depth and projecting the wire bonding part; and after mounting the semiconductor element on the lead frame material, the wire bonding part respectively corresponding to the electrode pad part of the semiconductor element A third step of forming an electrically conductive circuit by connecting them with a bonding wire, and the semiconductor A fourth step of resin-sealing the surface side of the lead frame material including the element, the bonding wire, and the wire bonding portion; and a back surface side of the lead frame material from which the etching resistant resist film has been removed. And a fifth step of performing an etching process using the plating mask as a resist mask and causing the external connection terminal portion to protrude and become independent.
A method of manufacturing a semiconductor device, characterized in that base metal plating or noble metal plating having an etchant resistance is applied to a lowermost layer of the plating mask. 3. The method of manufacturing a semiconductor device according to claim 1, wherein an element mounting portion is formed independently of the external connection terminal portion at the center of the lead frame material. A method of manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a terminal for heat dissipation is provided immediately below the semiconductor element. 4. A first step of forming a plating mask whose uppermost portion is made of a noble metal plating layer at a position corresponding to an electrode pad portion disposed on a lower surface of a semiconductor element mounted on the front side on the front and back sides of the lead frame material; After forming an etching resistant resist film on the back side of the frame material, the lead frame material is etched to a predetermined depth from the surface side using the plating mask formed on the front side as a resist mask, and the electrode pad portion and A second step of projecting an internal connection terminal portion for electrical connection; and mounting the semiconductor element on the lead frame material to achieve electrical continuity between the semiconductor element and the internal connection terminal portion. A third step of resin-sealing the surface side of the lead frame material including the element, and the back surface of the lead frame material from which the etching resist film has been removed. And a fourth step of performing an etching process using the formed plating mask as a resist mask to project and make the external connection terminal portion communicating with the internal connection terminal portion integral and independent. ,
A method of manufacturing a semiconductor device, characterized in that base metal plating or noble metal plating having an etchant resistance is applied to a lowermost layer of the plating mask. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. In a semiconductor device having an external connection terminal portion that is electrically connected to a resin-sealed semiconductor element and protrudes to the back surface side,
The connection terminal portion electrically connected to the electrode pad portion of the semiconductor element, and the external connection terminal portion are composed of a noble metal plating layer at the uppermost layer, and a base metal having an etching solution resistance at the lowermost layer. A semiconductor device that is plated or precious metal plated.

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