JP2006332214A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of effectively preventing an influence of parasitic current and of preventing an increase of a chip area in a semiconductor integrated circuit where an n-type region of a transistor is negative potential. <P>SOLUTION: There is disposed a p-type region 10 of a resistance region where a contact region 11 as an n-type island region is taken as power supply potential, in a p-type separation region 12 between a transistor Q1 where an n region is negative potential and a transistor Q2 adjacent to the transistor Q1. The p-type separation region 12 is disposed to surround the transistor Q1, and further the contact region 11 is disposed to surround the outside of the transistor Q1. Consequently, an influence of parasitic transistors Q3, Q4 is reduced without an increase of a chip area. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure of a semiconductor integrated circuit, and more particularly to a structure suitable for preventing a circuit malfunction caused by a parasitic current in a semiconductor integrated circuit including a circuit element serving as a negative voltage input.

  In an integrated circuit in which a linear circuit or the like is constructed, as shown in FIG. 5, a plurality of transistors are formed in a semiconductor formation region 40 of a P-type substrate 2 as a semiconductor chip, and a resistance formation region 41 is adjacent to the semiconductor formation region 40. And a linear circuit is formed by the resistance formed in the resistance formation region 41 and the transistor formed in the semiconductor formation region. Each resistance of the resistance formation region 41 is configured by forming the P-type region 10 in the N-type island region 28 formed on the P-type substrate 2. Reference numeral 30 denotes a contact region for taking the island potential of the resistance region.

  For example, when forming a differential amplifier circuit by forming a lateral PNP transistor Q1 and an NPN transistor Q2 in the semiconductor formation region 40 of the P-type substrate 2 as shown in FIG. 7 as shown in FIG. 6, the transistor Q1 Is formed by forming a grounded P-type isolation region 1 between the NPN transistor Q2 and the NPN transistor Q2.

  The transistor Q1 is configured by forming a base region 15, a collector region 16, and an emitter region 17 in the N-type island region 18 in the lateral direction. Reference numerals 3 and 14 denote N-type buried regions, and 25 denotes an insulating film. In the transistor Q 2, an N + collector region 6 and a P + base region 5 are formed in the N-type island region 7, and an N + emitter region 4 is formed in the base region 5.

  Thus, in the semiconductor integrated circuit having the transistors Q1 and Q2 separated by the grounded P-type isolation region 1, the base region 15 of the transistor Q1 is the emitter, the P-type isolation region 1 and the P-type substrate 2 are the base, and the transistor An NPN-type parasitic transistor Q5 using the collector region of Q2 as a collector is generated. When the base of the transistor Q1 is a positive voltage, a normal amplification operation can be obtained even if the parasitic transistor Q5 is present. However, in the following usage mode in which the base of the transistor Q1 is a negative voltage, the parasitic transistor Q5 Abnormal operation occurs due to the influence.

  Specifically, as shown in FIGS. 6 and 7, the output signal of this differential amplifier circuit is such that the emitter of the transistor Q2 is grounded, the current source 42 is connected to the collector of the transistor Q2, and the collector of the transistor Q2 is connected. A signal is output from the output terminal 43.

  Here, the usage pattern in which the base of the transistor Q1 is a negative voltage can be exemplified, for example, when the GND level of the semiconductor integrated circuit is higher than the GND level of other circuits. In such a usage mode, even when the transistor Q2 is in an off state and the output terminal 43 is at a high level, a negative voltage is applied to the input terminal 44 of the input terminals 44 and 45, and the base of the transistor Q1 is applied. When the voltage becomes negative, a current sucking operation occurs through the collector-emitter of the parasitic transistor Q5, and a malfunction occurs in that the level of the output terminal 43 decreases.

  Therefore, in order to reduce the influence of the parasitic transistor in the semiconductor integrated circuit as described above, (Patent Document 1) is configured as shown in FIGS. 8 (a) and 8 (b).

  FIG. 8A is a cross-sectional view taken along line AB of FIG. 8B, and a lateral PNP transistor Q1 having an N-type base region 15, a P-type collector region 16, and a P-type emitter region 17 on a P-type substrate 2. And an NPN transistor Q2 having an N-type collector region 6, a P-type base region 5, and an N-type emitter region 4, and a P-type isolation region 1 that electrically isolates the transistor Q1 and the NPN transistor Q2, and these And N-type island region 12 which is electrically floating and is arranged between the two transistors.

In this configuration, a negative voltage may be applied to the base region 15 of the transistor Q1. In the usage pattern as described above, the base region 15 of the transistor Q1 is the emitter, the P isolation region 1 and the P-type substrate 2 are the base, and the transistor Q2 NPN-type parasitic transistor Q3 using the collector region 6 as a collector is generated. Since the N-type island region 12 that is floating in potential is provided between the transistors Q1 and Q2, the N-type island region 12 is Compared to the case of FIG. 7, the base width of the P-type substrate 2, that is, the parasitic transistor Q <b> 3 is increased by the width of the N-type island region 12, and as a result, the hFE of the parasitic transistor Q <b> 3 decreases. The amount of current that Q3 sinks from the collector region 6 of transistor Q2 can be reduced, preventing abnormal operation of the circuit. It can be.
Japanese Patent Publication No. 6-91193

  According to the above prior art, the N-type island region 12 having a floating potential is provided in order to reduce the parasitic current due to the parasitic transistor Q3. This leads to an increase in the chip area. Further, if the area of the N-type island region 12 at the floating potential is reduced in order to suppress an increase in the chip area, the base width of the parasitic transistor Q3 is not sufficiently increased, so that the hFE of the parasitic transistor Q3 is not sufficiently reduced. Since the effect of preventing the parasitic current is reduced, the N-type island region 12 must have a certain area.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of effectively preventing the influence of a parasitic current and preventing an increase in chip area in a semiconductor integrated circuit in which an N-type region of a transistor has a negative potential. .

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit in which a plurality of transistors are formed on a P-type substrate by being electrically isolated by a grounded P-type isolation region, and the N-type region of the transistors is an input terminal. A resistance region including an N-type island region and a P-type diffusion region connected to a power source is formed in the P-type isolation region that electrically isolates the connected first transistor and the second transistor adjacent thereto. It is characterized by that.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the resistance region is formed so as to surround the first transistor.
According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, a contact region for connecting the N-type island region in the resistance region to a power source is formed so as to surround the outside of the first transistor. It is characterized by that.

  A semiconductor integrated circuit according to a fourth aspect of the present invention is the semiconductor integrated circuit according to the first aspect, wherein the first transistor is arranged at a corner of the semiconductor chip and faces an end of the semiconductor chip out of the periphery of the first transistor. It is characterized in that a resistance region is formed in an L shape so as to guard a portion that is not present.

  According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit in which a plurality of transistors are formed on a P-type substrate by being electrically isolated by a grounded P-type isolation region, and the N-type region of the transistors is an input terminal. A resistance region including an N-type island region and a P-type diffusion region connected to a power source is formed in the P-type isolation region that electrically isolates the connected first transistor and the second transistor adjacent thereto. Then, at least a part of the electric circuit is constructed by a plurality of transistors electrically separated by the P-type isolation region and formed on the P-type substrate and the resistance of the resistance region formed in the P-type isolation region. It is characterized by that.

  According to the present invention, in a semiconductor integrated circuit in which a plurality of transistors separated by a P-type isolation region exist on a P-type substrate and the N-type region of one of the transistors has a negative potential, the chip area is reduced. Parasitic current can be efficiently reduced without increasing it, and abnormal circuit operation can be prevented.

The semiconductor integrated circuit of the present invention will be described below with reference to FIGS.
In addition, the same code | symbol is attached | subjected and demonstrated to what comprises the same effect | action as FIG. 8 (a) (b). An example of an integrated circuit in which a linear circuit is constructed will be described as an example.

(Embodiment 1)
FIG. 1 shows (Embodiment 1) of the present invention.
FIG. 1B is a plan view, and FIG. 1A is a cross-sectional view taken along the line AB in FIG. 1B, and an N-type formed between the lateral PNP transistor Q1 and the NPN transistor Q2. Only the point that the P-type region 10 is formed in the island region 12 to form a resistor is different from the conventional example shown in FIGS. Reference numeral 11 denotes a contact region for taking the island potential of the resistance region.

  Specifically, the semiconductor integrated circuit in which the differential amplifier circuit shown in FIG. 6 is constructed is a lateral PNP transistor having an N-type base region 15, a P-type collector region 16, and a P-type emitter region 17 on a P-type substrate 2. An NPN transistor Q2 having Q1, an N-type collector region 6, a P-type base region 5, and an N-type emitter region 4 is formed, and each element of the lateral PNP transistor Q1 and the NPN transistor Q2 is surrounded by a P-type isolation region. 1 is electrically separated. In the N-type island region 12, a P-type region 10 that forms a resistor R 1 and contact regions 46 and 47 that conduct through the P-type region 10 are formed, and the N-type island region 12 is connected to a power source via the contact region 11. It is connected to the. Reference numeral 9 denotes an N-type buried region.

  According to this configuration, in a usage pattern in which a negative voltage may be applied to the base region 15 of the transistor Q1, when the base region 15 becomes a negative potential, the P-type isolation region 1 and the P-type substrate 2 adjacent to the base region 15 are Since it is grounded, in addition to the parasitic transistor Q3 having the base region 15 as an emitter, the P-type isolation region 1 and the P-type substrate 2 as a base, and the contact region 3 as a collector, the N-type base region 15 is an emitter and P-type isolation. A parasitic transistor Q4 having the region 1 and the P-type substrate 2 as a base and the contact region 11 and the N-type island region 12 as a collector is generated.

  When the parasitic transistor Q3 sucks current from the N-type collector region 6 of the transistor Q2, the circuit operates abnormally. However, the base width of the parasitic transistor Q3 is increased due to the arrangement of the resistor formed by the P-type region 10. Therefore, the hFE of the parasitic transistor Q3 is reduced, the current that the parasitic transistor Q3 sucks from the collector region 6 of the transistor Q2 is reduced, and abnormal circuit operation due to the parasitic current can be prevented.

  Further, since the N-type island region 12 is connected to the power supply via the contact region 11 and the base width of the parasitic transistor Q4 is smaller than the base width of the parasitic transistor Q3, the parasitic transistor Q4 supplies the negative power supply from the power supply. As a result, the amount of current that is supplied increases, and the current that the parasitic transistor Q3 sinks from the collector region 6 of the transistor Q2 can be further reduced, and the effect of preventing abnormal operation due to the parasitic current can be enhanced.

  The resistor R1 formed in the N-type island region 12 is used for setting a bias voltage and various reference voltages by resistance division in the semiconductor integrated circuit in which the differential amplifier circuit shown in FIG. 6 is constructed.

  Further, in this embodiment, as shown in FIG. 5, conventionally, the resistance formed in the resistance formation region 41 adjacent to the semiconductor formation region 40 is at least partially transferred to the N type of the semiconductor formation region 40. Since it is formed in the island region 12, the resistance forming region 41 can be reduced as compared with the conventional case, and the chip area can be reduced.

(Embodiment 2)
FIG. 2 shows (Embodiment 2) of the present invention.
2B is a plan view, and FIG. 2A is a cross-sectional view taken along the line AB in FIG. 2B, and an N-type formed between the lateral PNP transistor Q1 and the NPN transistor Q2. The only difference from Embodiment 1 is that the island region 12 is formed not only between the lateral PNP transistor Q1 and the NPN transistor Q2 but also around the lateral PNP transistor Q1. Further, in the N-type island region 12 surrounding the lateral PNP transistor Q1, a plurality of P-type regions 10 are formed around the lateral PNP transistor Q1 to form a plurality of resistors. Contact regions 11 provided in the vicinity of each P-type region 10 are connected to a power source. Reference numeral 20 denotes an N-type buried region.

  According to this configuration, the junction area between the collector and base of the parasitic transistor Q4 can be increased, the collector resistance of the parasitic transistor Q4 can be reduced, and the current flowing through the parasitic transistor Q4 can be increased. The flowing current can be further reduced, and the effect of preventing the abnormal operation of the circuit due to the parasitic current can be enhanced. Further, even when the area of the resistor R1 that can be arranged is limited, it is possible to obtain a high parasitic current reduction effect by arranging the resistor in the above shape.

(Embodiment 3)
FIG. 3 shows (Embodiment 3) of the present invention.
FIG. 3B is a plan view, and FIG. 3A is a cross-sectional view taken along the line AB in FIG. 3B, and a contact region 11 for taking the potential of the N-type island region 12 of the resistor R1. Is different from (Embodiment 2) only in that it is formed so as to surround the periphery of the lateral PNP transistor Q1.

  According to this structure, since the impurity concentration in the collector region of the parasitic transistor Q4 is increased and the collector resistance of the parasitic transistor Q4 can be reduced, thereby increasing the current flowing through the parasitic transistor Q4, the current flowing through the parasitic transistor Q3 is further increased. The effect of preventing abnormal operation of the circuit due to parasitic current can be enhanced. Further, even when the area of the resistor R1 that can be arranged is limited, it is possible to obtain a high parasitic current reduction effect by arranging the resistor in the above shape.

(Embodiment 4)
FIG. 4 shows (Embodiment 4) of the present invention.
4B is a plan view, FIG. 4A is a cross-sectional view taken along the line AB of FIG. 4B, and the virtual line 31 represents a scribe lane.

  The lateral PNP transistor Q1 is arranged at the corner of the chip, and a specific example is shown in which two of the four sides around the lateral PNP transistor Q1 face the end of the chip.

  In such a case, the N-type island region 12 formed between the lateral PNP transistor Q1 and the NPN transistor Q2 is not only between the lateral PNP transistor Q1 and the NPN transistor Q2, but also facing the chip end. Since there are no elements on the two sides, an N-type island region 12 is formed in an L shape so as to guard the remaining two sides excluding the two sides facing the chip end, and a resistor is formed here. A P-type region 10 and a contact region 11 are provided.

  Thus, by arranging the resistance region R1 only in the other two side directions, the parasitic current due to the parasitic transistor Q3 can be reduced. Others are the same as those in the above embodiments.

  This is effective in improving the reliability of a semiconductor integrated circuit such as a linear circuit that requires a resistor for circuit construction.

Sectional view and plan view of semiconductor integrated circuit according to (Embodiment 1) of the present invention Sectional drawing and top view of the semiconductor integrated circuit by (Embodiment 2) of this invention Sectional drawing and top view of the semiconductor integrated circuit by (Embodiment 3) of this invention Sectional drawing and top view of the semiconductor integrated circuit by (Embodiment 4) of this invention The top view which shows the semiconductor formation area and resistance formation area in the conventional semiconductor integrated circuit The figure which shows the example of the circuit where abnormal operation with the parasitic element occurs Sectional view showing the configuration when abnormal operation occurs due to parasitic elements Sectional view and plan view of conventional semiconductor integrated circuit

Explanation of symbols

Q1 Lateral PNP transistor Q2 NPN transistor Q3, Q4 Parasitic transistor 1 P-type isolation region 2 P-type substrate 4 N-type emitter region 5 P-type base region 6 N-type collector region 9 N-type buried region 10 P-type region 11 Contact region 12 N Type island region 15 N type base region 16 P type collector region 17 P type emitter region 31 Scribe lane

Claims (5)

A plurality of transistors are formed on a P-type substrate by being electrically separated by a grounded P-type isolation region, and a first transistor having an N-type region connected to the input terminal of the transistors and a first transistor adjacent thereto. A semiconductor integrated circuit in which a resistance region including an N-type island region and a P-type diffusion region connected to a power source is formed in the P-type isolation region that electrically isolates two transistors. The semiconductor integrated circuit according to claim 1, wherein the resistance region is formed so as to surround a periphery of the first transistor. 3. The semiconductor integrated circuit according to claim 2, wherein a contact region for connecting an N-type island region in the resistance region to a power source is formed so as to surround the outside of the first transistor. The first transistor is disposed at a corner of a semiconductor chip, and an L-shaped resistance region is formed so as to guard a portion of the periphery of the first transistor that does not face the end of the semiconductor chip. 2. The semiconductor integrated circuit according to 1. A plurality of transistors are formed on a P-type substrate by being electrically separated by a grounded P-type isolation region, and a first transistor having an N-type region connected to the input terminal of the transistors and a first transistor adjacent thereto. Forming a resistance region including an N-type island region and a P-type diffusion region connected to a power source in the P-type isolation region that electrically isolates the two transistors;
A semiconductor integrated circuit in which at least a part of an electric circuit is constructed by a plurality of transistors electrically separated by a P-type isolation region and formed on a P-type substrate and a resistance of a resistance region formed in the P-type isolation region circuit.

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