JP2006323739A - Memory module, memory system and information apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory system that includes a convenient large capacity ROM and RAM. <P>SOLUTION: The memory system includes a nonvolatile memory, a cache memory, a control circuit and an information processor. For high speed, data in the nonvolatile memory is transferred to and retained in the cache memory. The data transfer from the nonvolatile memory to the cache memory involves error corrections to provide improved reliability. The information processor can access the cache memory and the nonvolatile memory independently to provide improved convenience. The memory system comprising the plurality of chips is configured as a memory system module in which the chips are stacked and wired by a ball grid array (BGA) and chip bonding. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory system including a nonvolatile memory and a control method of the memory system.

  Conventionally, there is a composite semiconductor memory in which a flash memory (32 Mbit capacity) and a static random access memory (NOR (4 Mbit capacity)) are integrally sealed in a FBGA (Fine pitch Ball Grid Array) type package with a stack chip. The flash memory and NOR share an address input terminal and a data input / output terminal with respect to the input / output electrodes of the FBGA type package. However, each control terminal is independent (for example, refer nonpatent literature 1).

  There is also a composite semiconductor memory in which a flash memory chip and a DRAM chip are integrally sealed in a lead frame type package. In this composite semiconductor memory, the flash memory and the DRAM are input / output with the address input terminal, the data input / output terminal, and the control terminal in common with respect to the input / output electrodes of the package (for example, FIG. And FIG. 15 and Patent Document 2).

  In addition, there is a system including a flash memory, a cache memory, a controller, and a CPU that are handled as a main storage device (see, for example, FIG. 1 of Patent Document 3).

There is also a semiconductor memory including a flash memory, a DRAM, and a transfer control circuit (see, for example, FIG. 2 of Patent Document 4 and Patent Document 5).
“Composite Memory (Stacked CSP) Flash Memory + RAM Data Sheet”, Model LRS1380, [online], December 10, 2001, Sharp Corporation, [Search August 21, 2002], Internet <URL: http : //www.sharp.co.jp/products/device/flash/cmlist.html> JP 05-299616 A European Patent Application Publication No. 0566306 Japanese Patent Application Laid-Open No. 07-146820 JP 2001-5723 A JP 2002-366429 A

  Prior to the present application, the inventors of the present application examined a memory system including a mobile phone and a processor used therefor, a flash memory, and a random access memory and its operation.

  As shown in FIG. 33, an information processing device PRC and a memory module MCM are used in a mobile phone.

  The information processing apparatus PRC includes a central processing unit CPU and an SRAM controller. The memory module MCM includes a NOR flash memory NOR FLASH and SRAM. The information processing apparatus PRC accesses the memory module MCM, and reads and writes data.

  After the power is turned on, the information processing apparatus PRC reads the boot data stored in the NOR flash memory NOR FLASH and starts up itself. Thereafter, the information processing apparatus PRC reads an application program from the NOR flash memory NOR FLASH as necessary, and executes it on the central processing unit CPU. The SRAM functions as a work memory, and stores the results of operations performed by the central processing unit CPU.

  In recent years, applications, data, and work areas handled by mobile phones have become larger as functions added to mobile phones (distribution of music, games, etc.) increase, and it is expected that flash memory and random access memory with larger storage capacity will be required. The Furthermore, recent mobile phones are remarkably advanced in functionality, and the need for high-speed and large-capacity memory is increasing.

  The NOR type flash memory currently used for mobile phones is a NOR type flash memory using a memory array system called a NOR configuration. The NOR type has an array configuration in which the parasitic resistance of the memory cell array is suppressed to a low level, and the resistance is reduced by providing one metal bit line contact for every two memory cells connected in parallel. For this reason, the read time can be approximately the same as the NOR read time of about 80 ns. However, since it is necessary to provide one contact for every two cells, the ratio of the contact area to the chip area is high, and the area per 1-bit memory cell is large. There is no problem.

  Typical large-capacity flash memories include an AND flash memory using an AND configuration for a memory array and a NAND flash memory using a NAND configuration. Since these flash memories are provided with one bit line contact for 16 to 128 cells, a high-density memory array can be realized. Accordingly, the area per 1-bit memory cell can be made smaller than that of the NOR flash memory, and the capacity can be increased. However, on the other hand, it has been found that the read time until the first data is output is as slow as about 25 μs to 100 μs, and the consistency with the NOR type flash memory cannot be obtained.

  It has been found that by rewriting the flash memory, the reliability decreases, and the data written at the time of writing becomes different data at the time of reading or the data is rarely written at the time of rewriting.

  In addition, the α-rays emitted from radioactive substances such as uranium in the semiconductor encapsulant are incident on the memory array of the random access memory RAM, so that the stored data held in the memory array is rarely destroyed. It has been found that this is a factor that degrades the reliability of the random access memory RAM.

  Accordingly, one of the objects of the present invention is to provide a memory system including a ROM and a RAM that have a large storage capacity, are low in cost, and are easy to use.

  Representative means of the present invention are as follows. An information processing device, a flash memory, a cache memory, and a memory controller are mounted on one sealing body, an electrode for wiring the semiconductor chip to the sealing body, the sealing body and the sealing body outside, An electrode is provided for connection.

  At this time, in order to speed up the read time in response to the data read request from the information processing device, the memory controller is connected to the cache memory and the flash memory, and the memory controller transfers the data from the flash memory to the cache memory. Do.

  After the power is turned on, control for transferring at least part of the data in the flash memory to the cache memory may be performed.

  Control may be performed so that addresses input from the information processing apparatus are distributed to the index addresses of the cache memory.

  The memory controller may be controlled in advance to transfer data used by the information processing apparatus to the cache memory.

  Further, it is preferable to use a buffer in the flash memory as a cache memory.

  The memory controller may perform error detection and correction when reading data from the flash memory, and may perform substitution processing for defective addresses that were not correctly written during writing. Further, it is preferable to perform control for averaging the number of times of writing to the memory cells in the flash memory. Further, error detection may be performed after data is also read from the cache memory.

  It is preferable to provide a signal line that can know the arrival of data requested by the information processing apparatus.

  The memory controller may be configured to receive read and write access to the flash memory from the information processing apparatus and read and write data while reading data from the cache memory. .

  A highly functional memory can be realized.

  Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The circuit elements constituting each block in the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor). The

  FIG. 1 shows a memory system composed of an information processing device CPU_CHIP and a memory module MSM, which is a first embodiment to which the present invention is applied. Each will be described below.

  The memory module MSM is composed of FLASH_CHIP and CT_CHIP. FLASH_CHIP is a nonvolatile memory. As the nonvolatile memory, ROM (read-only memory), EEPROM (electrically erasable and programmable ROM), flash memory, or the like can be used. In this embodiment, a flash memory will be described as an example.

  Typical large-capacity flash memories include an AND flash memory using an AND configuration and a NAND flash memory using a NAND configuration for the memory array. Both flash memories can be used in the present invention. it can. In addition, there are a large-capacity flash memory equipped with a NAND interface and a large-capacity flash memory equipped with an AND interface. Both flash memories can be used in the present invention. In this embodiment, a large-capacity flash memory equipped with a NAND interface will be described as an example.

  Although not particularly limited, a typical flash memory used as FLASH_CHIP is a large-capacity flash memory equipped with a NAND interface, has a large storage capacity of about 2 Gbit, and has a read time (until data is output from a read request) Is relatively slow, about 25 μs to 100 μs.

  DRAM_CHIP is a dynamic random access memory, and there are various types such as EDO (Extended Data Out), SDRAM (Synchronous DRAM), and DDR (Double Data Rate) due to differences in internal configuration and interface. Any DRAM can be used for the memory module MSM. In the present embodiment, an example of SDRAM will be described. The dynamic random access memory DRAM_CHIP is used as a temporary work memory for executing an application program in the information processing device CPU_CHIP.

  Although not particularly limited, a typical SDRAM used as DRAM_CHIP has a large storage capacity of about 256 Mbit.

  The control circuit CT_CHIP is a control circuit that controls data transfer between the FLASH_CHIP and the information processing device CPU_CHIP. Although not particularly limited, the control circuit CT_CHIP has a built-in cache memory L2Cache with a storage capacity of 1 Mbyte, and a read time of about 30 ns to 90 ns Therefore, it is shorter or equivalent to the conventional NOR type flash.

  The cache memory L2Cache can be implemented with magnetic random access memory MRAM and phase change memory PRAM, which are non-volatile memories, and static random access memory SRAM, which is volatile memory, and any random access memory can be used for the memory module MSM. Can do. In the present embodiment, an example in which a static random access memory SRAM that is a volatile memory is used as the cache memory L2Cache will be described.

  Data transfer between the flash memory FLASH_CHIP and the control circuit CT_CHIP is performed by the NAND interface NAND IF2, and data transfer between the information processing device CPU_CHIP and the dynamic random access memory DRAM_CHIP is performed by the SDRAM interface SDRAM IF.

  The information processing device CPU_CHIP includes a central processing unit CPU, a NOR flash controller NRC, a NAND flash controller NDC, and a DRAM controller SDC. The NOR controller NRC accesses the memory module MSM through the NOR interface, and reads and writes data. The DRAM controller SDC accesses the DRAM_CHIP through the SDRAM interface (SDRAM IF) to read / write data.

  The NAND flash controller NDC accesses the memory module MSM through a NAND interface (NAND IF1), and reads and writes data.

  The flash memory FLASH_CHIP includes a control circuit FCNT, a data buffer DREG, and a memory cell array MARY. The control circuit FCNT is a circuit that operates according to read and write commands from the NAND interface NAND IF2 of the control circuit CT_CHIP.

  When a read request is input to the control circuit FCNT, data having a data size of about 2 KB is transferred from the memory cell array MARY to the data buffer DREG, but is not limited thereto, and is transferred from the NAND interface NAND IF2 to the control circuit CT_CHIP.

  Further, the data transferred to the data buffer DREG is held as it is.

  When a write request and write data are input to the control circuit FCNT, although not particularly limited, data having a data size of about 2 KB is input to the data buffer DREG and finally written to the memory cell array MARY. Further, the data input to the data buffer DREG is held as it is.

  The flash memory FLASH_CHIP is not particularly limited, but is divided into a main data area and an alternative area REPAREA.

The main data area includes an initial program area, and in the initial program area, immediately after power-on, a boot program for starting up the information processing device CPU_CHIP and automatic transfer from the flash memory FLASH_CHIP to the cache memory L2Cache The automatic transfer area designating data indicating the data range in the cache area is stored.
<Configuration of control circuit CT_CHIP>
The control circuit CT_CHIP includes a NOR interface circuit NRIF that receives read and write requests from the NOR interface (NOR IF), a NAND interface circuit NDIF that receives read and write requests from the NAND interface (NAND IF), a register block REG, and an address conversion circuit It comprises a DSTR, a cache memory L2Cache, PL2A, PL2B, a prefetch control circuit PREF, a flash control circuit FLCT, a buffer circuit BFBK, and a flash error control circuit FLSP.

  The cache memory L2Cache is not particularly limited, but has a capacity of about 1 MB. Further, the cache memories PL2A and PL2B have a capacity of 512 bytes, although not particularly limited.

  The prefetch control circuit PREF includes hit determination circuits PL2Hit and L3Hit and a prefetch control circuit. The buffer circuit BFBK includes a read buffer RBUF and a write buffer WBUF.

  The flash control circuit FLCT includes a clock control circuit OSC, a memory address management circuit MMG, an access arbitration circuit ARB, and a control circuit RWCL.

  The flash error control circuit FLSP includes an error detection / correction circuit ECC, a buffer circuit BUF, an alternative processing circuit REP, and a write number averaging circuit WLV.

The operation of this memory system will be described below. First, the operation immediately after the power is turned on will be described.
<Description of operation immediately after power-on>
When power is turned on to the information processing device CPU_CHIP, dynamic random access memory DRAM_CHIP, control circuit CT_CHIP, and flash memory FLASH_CHIP, the flash control circuit FLCT reads data in the initial program area of FLASH_CHIP to the buffer circuit BUF, and an error detection and correction circuit ECC Check if there is an error. If there is no error, the boot program in the initial program area is transferred to the cache memory PL2A. If there is an error, the boot program is corrected, and the boot program in the initial program area is transferred to the cache memory PL2A. In this way, by automatically transferring the boot program from FLASH_CHIP to the cache memory PL2A immediately after the power is turned on, the information processing device CPU_CHIP reads this boot program, quickly launches itself, and further initializes the dynamic random access memory DRAM_CHIP. It can be carried out.

  While the information processing device CPU_CHIP is starting up, the flash control circuit FLCT reads the automatic transfer area designation data from the buffer circuit BUF, and the data in the flash memory FLASH_CHIP in the range indicated by this data is sent to the buffer circuit BUF. Read sequentially and check whether there is an error in the error detection and correction circuit ECC. If there is no error, it is transferred to the cache memory L2Cache via the cache memory PL2B, and if there is an error, it is corrected and transferred to the cache memory L2Cache via the cache memory PL2B. When this automatic data transfer is completed, the memory module MSM sets the initial operation completion signal PCMP indicating High to indicate that a series of initial operations has ended.

  Further, the access arbitration circuit ARB may be configured to write a transfer completion flag indicating completion of data transfer to the register block REG. In this case, since the initial operation completion signal PCMP is not necessary, the number of signal pins can be reduced.

  Since the information processing device CPU_CHIP can know that the data transfer immediately after power-on is completed by checking the initial operation completion signal PCMP of the memory module MSM, it can immediately access the cache memory L2Cahce.

As described above, by automatically transferring the boot program from the FLASH_CHIP to the cache memory L2Cache immediately after the power is turned on, the information processing device CPU_CHIP can read this boot data and quickly start itself up. Furthermore, by automatically transferring the data of FLASH_CHIP to the cache memory L2Cache while the information processing device CPU_CHIP is starting up, the memory module MSM can be accessed immediately when the information processing device CPU_CHIP is started up. High performance can be achieved.
<Description of register block>
Next, the register block REG will be described. The register block REG includes, but is not limited to, a read mode setting register RModeReg, a cache area setting register CAreaReg, a cache lock area setting register CaLockReg, a write protect area setting register WproReg, and a write count averaging process area setting register WlvlReg.

  When changing the cache area and the non-cache area, the cache area and the non-cache area can be changed by rewriting the value of the cache area setting register CAreaReg from the NOR interface NOR IF. Although not particularly limited, immediately after the power is turned on, the entire area of the flash memory FLASH_CHIP is a cache area.

  Data in the cache area is transferred to the cache memories L2Cache, PL2A, and PL2B, and data in the non-cache area is not transferred to the cache memories L2Cache, PL2A, and PL2B.

  The cache lock area and the non-cache lock area are not particularly limited, but the cache lock area and the non-cache lock area can be changed by rewriting the value of the cache area setting register CAreaReg from the NOR interface NOR IF. . Although not particularly limited, immediately after the power is turned on, the entire area of the flash memory FLASH_CHIP is a non-cache lock area.

  Once the data in the cache lock area is transferred to the cache memory L2Cache, it can exist in the cache memory L2Cache until the cache area setting register is rewritten by a cache lock release instruction. Further, there is a possibility that data in the non-cache lock area is evicted from the cache memory L2Cache.

  When changing the write count averaging processing area and non-write count averaging process area, there is no particular limitation, but the number of writes is averaged by rewriting the value of the write count averaging process area setting register WLvlReg from the NOR interface NOR IF. The processing area and the non-write count averaging processing area can be changed. Although there is no particular limitation, immediately after the power is turned on, a half area of the flash memory FLASH_CHIP is a write frequency averaging process area.

  When the write number averaging circuit WLV determines that rewriting is concentrated on the data within the write number averaging process area, the write number average process is performed.

  The write count averaging process is not performed on the data in the non-write count averaging process area.

  When changing the write protect area and non-write protect area, there is no particular limitation, but the write protect area and non-write protect area can be changed by rewriting the value of the write protect area setting register WproReg from the NOR interface NOR IF. it can. Although not particularly limited, immediately after the power is turned on, the entire area of the flash memory FLASH_CHIP is a non-write protected area.

  Writing is not performed in the write protect area, and writing is possible in the non-write protect area.

  The NOR interface provided in the memory module MSM is a synchronous NOR interface that operates in synchronization with the clock signal CLK, and an asynchronous NOR interface that does not synchronize with the clock signal CLK, and operates with one of the NOR interfaces. Although not particularly limited, the memory module MSM operates with an asynchronous NOR interface immediately after power-on.

  Although not particularly limited, the address conversion circuit DSTR can realize a plurality of address conversion methods (simple index conversion method, index bit shift conversion method, index calculation method), and operates in any one of the address conversion methods. Although there is no particular limitation, immediately after the power is turned on, the address conversion circuit DSTR operates by the index calculation method.

  Although not particularly limited, the NOR interface and the address conversion method provided in the memory module MSM can be changed by rewriting the value of the read mode setting register RModeReg from the NOR interface NOR IF.

As described above, synchronous NOR interface and asynchronous NOR interface, address conversion method, cache area and non-cache area, cache lock area and non-cache lock area, write count averaging process area and non-write count averaging process area The write protect area and the non-write protect area can be set independently, and can be freely selected by the user according to the system.
<Description of normal operation>
Data transfer between the flash memory FLASH_CHIP and the information processing device CPU_CHIP after the power-on sequence at power-on is completed will be described.

  First, an operation when the information processing device CPU_CHIP inputs a read request from the NOR interface NOR IF will be described.

  When the information processing device CPU_CHIP inputs a read command and an address RADD from the NOR interface (NOR IF) to the control circuit CT_CHIP, the NOR interface circuit NRIF in the control circuit CT_CHIP holds these read commands and addresses. The read command and the address RADD held in the NOR interface circuit NRIF are input to the memory address management circuit MMG, the access arbitration circuit ARB, and the address conversion circuit DSTR.

  The memory address management circuit MMG compares the address information indicating the cache area held in the register block REG with the address RADD.

  If the address RADD is out of the cache area, the out-of-cache area information is notified from the memory address management circuit MMG to the information processing device CPU_CHIP from the NOR interface NOR IF through the NOR interface circuit NRIF.

  The access arbitration circuit arbitrates between a read request input from the NOR interface circuit NRIF and a read or write request from the NAND interface circuit NDIF.

  First, when a read request is input from the NOR interface circuit NRIF to the access arbitration circuit, the access arbitration circuit checks whether there is a read or write request from the NAND interface circuit NDIF, and further reads or writes from the NAND interface circuit NDIF. Check if the request is being acted on.

  If there is a read or write request from the NAND interface circuit NDIF, and the operation for this request has not been performed yet, the read request from the NOR interface circuit NRIF is given priority to postpone the read or write request from the NAND interface circuit NDIF. To allow.

  When an operation for a read or write request from the NAND interface circuit NDIF is being executed, the operation being executed is temporarily interrupted, and a read request is preferentially permitted from the NOR interface circuit NRIF.

  When a read / write request is input from the NAND interface circuit NDIF to the access arbitration circuit, the access arbitration circuit checks whether there is a read / write request from the NOR interface circuit NRIF, and further reads / writes from the NOR interface circuit NRIF. Check if the request is being acted on.

  When an operation for a read or write request from the NOR interface circuit NRIF is being executed, the read / write request is permitted from the NAND interface circuit NDIF after the operation is completed.

  When there is no read or write request from the NOR interface circuit NRIF and no operation is performed for this request, the read and write request is permitted from the NAND interface circuit NDIF.

  The address conversion circuit converts the address RADD into the address MRADD for the purpose of increasing the usage rate and hit rate of the cache memories L2Cache, PL2A, and PL2B.

  The address MRADD converted by the address conversion circuit is input to the cache memory L2Cache and the prefetch control circuit PREF.

  In the cache memory L2Cache, first, a hit determination is made as to whether or not the data designated by the address MRADD exists in the cache memory L2Cache. If the data specified by the address MRADD exists in the cache memory L2Cache, an L2Cache hit occurs, and if it does not exist, an L2Cache miss occurs.

  The hit determination circuit PL2Hit in the prefetch control circuit PREF performs a hit determination as to whether or not the data specified by the address MRADD exists in either of the cache memories PLA2 and PL2B.

  If the data specified by the address MRADD exists in either one of the cache memories PL2A and PL2B, a PL2 hit occurs. Otherwise, a PL2 miss occurs.

  Further, the hit determination circuit L3Hit in the prefetch control circuit PREF performs a hit determination as to whether or not the data designated by the address MRADD exists in the data register DREG in the flash memory FLASH_CHIP.

If the data specified by the address MRADD exists in the data register DREG in the flash memory FLASH_CHIP, an L3 hit occurs. Otherwise, an L3 miss occurs.
<Description of L2Cache hit operation>
In the case of an L2Cache hit, data is directly output from the cache memory L2Cache, and is output to the information processing device CPU_CHIP from the NOR interface NOR IF through the NOR interface circuit NRIF.

  When the Wait signal becomes Low, the information processing device CPU_CHIP knows that the requested data has arrived and takes in the requested data.

That is, in the case of an L2Cache hit, there is no need to transfer data from the flash memory FLASH_CHIP to the cache memory L2Cache, data can be read directly from the cache memory L2Cache, and data transfer can be performed at high speed.
<Explanation of PL2 hit operation>
In the case of an L2Cache miss and a PL2 hit, data is directly output from either of the cache memories PL2A and PL2B, and is output from the NOR interface NOR IF to the information processing device CPU_CHIP through the NOR interface circuit NRIF. The read time at this time is equivalent to the read time from the L2Cache.

  That is, in the case of a PL2 hit, there is no need to transfer data from the flash memory FLASH_CHIP to the cache memories PL2A and PL2B, and data can be directly read from the cache memory PL2A or PL2B, and data transfer can be performed at high speed.

In this way, when the cache memory L2Cache, PL2A, and PL2B are hit, data can be directly output from the cache memory L2Cache, PL2A, PL2B, and data transfer between the information processing device CPU_CHIP and the memory module MSM can be performed at high speed. .
<L2Cache miss, PL2 miss, L3 hit operation explanation>
Next, data transfer in the case of an L2Cache miss, a PL2 miss, and an L3 hit will be described.

  When an L2Cache miss, a PL2 miss, and an L3 hit, first, when the access arbitration circuit permits a read request from the NOR interface circuit NRIF, the control circuit RWCL issues a read request for the Nth page data to the control circuit FCNT. The Nth page data in the data register DREG is transferred to the buffer circuit BUF.

  Using the time for transferring the Nth page data in the data register DREG to the buffer circuit BUF, the data currently stored in the cache memories PL2A and PL2B is transferred to the cache memory L2Cache, and the cache memory L2Cache is updated. .

  The Nth page data transferred to the buffer circuit BUF is subjected to error detection by an error detection / correction circuit ECC. If there is no error in the Nth page data transferred to the buffer circuit BUF, this Nth page data is transferred to the cache memory PL2A by the control circuit RWCL, and if there is an error, the error detection / correction circuit ECC corrects the error. Thereafter, the Nth page data is transferred to the cache memory PL2A by the control circuit RWCL. Data requested by the information processing device CPU_CHIP in the Nth page data transferred to the cache memory PL2A is output from the NOR interface NOR IF to the information processing device CPU_CHIP through the NOR interface circuit NRIF.

  Although not particularly limited, the Wait signal remains High until data is output, and the information processing device CPU_CHIP waits for the arrival of data. When the Wait signal becomes Low, the information processing device CPU_CHIP knows that the requested data has arrived and takes in the requested data.

  Further, the prefetch instruction circuit PRECT instructs the control circuit RWCL to prefetch data, the control circuit RWCL inputs a read request to the control circuit FCNT, and the next page data in the data register DREG, that is, the N + 1th data is buffered. Transfer to circuit BUF.

  The N + 1-th page data transferred to the buffer circuit BUF is detected by the error detection / correction circuit ECC at every 512B although not particularly limited. If there is no error in the (N + 1) th page data transferred to the buffer circuit BUF, this N + 1 page data is transferred to the cache memory PL2A by the control circuit RWCL, and if there is an error, the error detection / correction circuit ECC performs error correction. Thereafter, the (N + 1) th page data is transferred to the cache memory PL2B by the control circuit RWCL. When the data register DREG of the flash memory FLASH_CHIP is hit, there is no need to transfer data from the memory cell array MARY to the data register DREG, and data can be read directly from the data register DREG, and data can be transferred at high speed. it can.

  Thus, by using the data register DREG of the flash memory FLASH_CHIP as a cache memory, the hit rate can be improved by effectively increasing the capacity of the cache memory, and data transfer between the information processing device CPU_CHIP and the memory module MSM can be performed. It can be done at high speed.

Furthermore, by using the data prefetching function, the data of the next page of the data requested by the information processing device CPU_CHIP is transferred to the cache memory PL2B in advance, so that the hit rate can be improved and the data transfer speed can be increased.
<L2Cache miss, PL2 miss, L3 miss operation explanation>
A data transfer operation when an L2Cache miss causes a PL2 miss and an L3 miss will be described.

  When a read request from the NOR interface circuit NRIF is permitted by the access arbitration circuit, first, the control circuit RWCL inputs a read request for Nth page data to the control circuit FCNT. The control circuit FCNT transfers the Nth page data in the memory cell array MARY to the data register DREG. Next, the data register DREGN page data is output to the control circuit RWCL. The control circuit RWCL transfers this data to the buffer circuit BUF.

  During data transfer from the data register DREG to the buffer circuit BUF, the data currently held in the cache memories PL2A and PL2B is transferred to the cache memory L2Cache, and the cache memory L2Cache is updated.

  The Nth page data transferred to the buffer circuit BUF is detected by the error detection / correction circuit ECC at every 512B although not particularly limited. If there is no error in the Nth page data transferred to the buffer circuit BUF, this Nth page data is transferred to the cache memory PL2A by the control circuit RWCL, and if there is an error, the error detection / correction circuit ECC corrects the error. Thereafter, the Nth page data is transferred to the cache memory PL2A by the control circuit RWCL. Data requested by the information processing device CPU_CHIP in the Nth page data transferred to the cache memory PL2A is output from the NOR interface NOR IF to the information processing device CPU_CHIP through the NOR interface circuit NRIF.

  Although not particularly limited, the Wait signal remains High until data is output, and the information processing device CPU_CHIP waits for the arrival of data.

  Further, when the prefetch instruction circuit PRECT supports prefetching of data to the control circuit RWCL, the control circuit RWCL inputs a read request to the control circuit FCNT and buffers the next page data in the data register DREG, that is, the N + 1th data. Transfer to circuit BUF.

  The N + 1-th page data transferred to the buffer circuit BUF is detected by the error detection / correction circuit ECC at every 512B although not particularly limited. If there is no error in the (N + 1) th page data transferred to the buffer circuit BUF, this N + 1 page data is transferred to the cache memory PL2A by the control circuit RWCL, and if there is an error, the error detection / correction circuit ECC performs error correction. Thereafter, the (N + 1) th page data is transferred to the cache memory PL2B by the control circuit RWCL.

  Further, the data transferred to the data register DREG is held as it is, and the data register DREG is used as a cache memory.

  In addition, the prefetching function can improve the hit rate by transferring the data requested by the information processing device CPU_CHIP to the cache memory PL2B of the Nth page data and the next N + 1 page data at high speed. Data transfer can be performed.

  In this way, the data buffer DREG of the flash memory FLASH_CHIP is treated as a cache memory, and hitting this data buffer DREG eliminates the need to transfer data directly from the memory cell array MARY to the data buffer DREG, so that high-speed data transfer is possible. realizable.

  Furthermore, by using the data prefetching function, the data of the next page of the data requested by the information processing device CPU_CHIP is transferred to the cache memory PL2B in advance, so that the hit rate can be improved and the data transfer speed can be increased.

In addition, the data update from the cache memories PL2A and PL2B to the cache memory L2Cache is performed simultaneously with the data transfer from the data register DREG to the buffer circuit BUF performed at the time of L2Cache miss and PL2 miss, so the data update time to the cache memory L2Cache is reduced. It can be concealed and data transfer without waste can be realized.
<Description of read operation from NAND interface NAND IF1>
Next, an operation when the information processing device CPU_CHIP inputs a read request from the NAND interface NAND IF1 will be described.

  When the access arbitration circuit ARB permits a read request from the NAND interface circuit NDIF, first, the control circuit RWCL inputs a data read request to the control circuit FCNT. The control circuit FCNT transfers data in the memory cell array MARY to the data register DREG. Next, the data in the data register DREG is output to the control circuit RWCL. The control circuit RWCL transfers this data to the buffer circuit BUF.

  The data transferred to the buffer circuit BUF is subjected to error detection by an error detection / correction circuit ECC. If there is no error in the data transferred to the buffer circuit BUF, it is transferred to the read buffer RBUF by the control circuit RWCL. If there is an error, the error detection and correction circuit ECC corrects the error, and then the control circuit RWCL performs the read buffer RBUF. Forwarded to

Of the data transferred to the read buffer RBUF, data requested by the information processing device CPU_CHIP is output from the NAND interface NAND IF1 to the information processing device CPU_CHIP through the NAND interface circuit NDIF.
<Description of write operation from NAND interface NAND IF1>
Next, an operation when the information processing device CPU_CHIP inputs a write request from the NAND interface NAND IF1 will be described.

  When a write request, write address NWADD, and write data NWDATA are input to the NAND interface circuit NDIF, the write data NWDATA is transferred to the write buffer WBUF, and the write address NWADD is transferred to the address arbitration circuit ARB.

  The address arbitration circuit ARB transfers the write address NWADD to the address conversion circuit DSTR. The address conversion circuit DSTR performs an operation on the address NWADD, converts it to the address MNWADD, and inputs it to the cache memory L2Cache hit determination circuit PL2Hit.

  Thereafter, the cache memory L2Cache and the hit determination circuit PL2Hit use the address MNWADD to perform processing for maintaining data consistency with the cache memories L2Cache, PL2A, and PL2B. Specifically, the cache memory L2Cache checks whether the data of the address MNWADD exists, and if it exists, invalidates the data. The hit determination circuit PL2Hit checks whether or not the data of the address MNWADD exists in the cache memories PL2A and PL2B, and if it exists, invalidates the data. When the invalidation of the data in the cache memories L2Cache, PL2A, and PL2B is completed, the data in the data buffer DREG is invalidated by the hit determination circuit L3Hit.

  When the invalidation of all the cache memories is completed, the access arbitration circuit ARB permits a write request from the NAND interface circuit NDIF.

  When a write request from the NAND interface circuit NDIF is permitted in the access arbitration circuit ARB, first, the control circuit RWCL inputs a data write request and write data WData to the control circuit FCNT. The control circuit FCNT transfers the write data Wdata to the data register DREG, and further writes the data transferred to the data register DREG to the memory cell array MARY.

  The alternative processing circuit REP checks whether or not the writing to the memory cell array MARY has been successful, and if successful, ends the processing. When writing fails, writing is performed to a new alternative address prepared in advance in the flash memory FLASH_CHIP. When the replacement process is performed, the address information indicating the replacement address for the defective address and the defective address is held and managed.

  Further, the memory address management circuit MMG checks whether the write address NWADD is an address in the write number averaging processing area.

If the write address NWADD is an address in the write count averaging processing area, the sum of the write count and erase count managed by the write count averaging circuit WLV after the data WDATA is written to the memory cell array MARY. Increase one. Furthermore, when the sum of the number of times of writing and the number of times of erasing reaches the sum threshold of the number of times of writing and the number of times of erasing held by the writing number averaging circuit WLV, the writing number averaging circuit WLV concentrates on rewriting. Although there is no particular limitation, the correspondence between the physical address and the logical address is changed for each 64-page data, and the correspondence information between the physical address and the logical address is held. As described above, the number of rewrites of the memory array can be averaged by the write number averaging circuit WLV, and the reliability can be improved.
<Description of erase operation from NAND interface NAND IF1>
Next, an operation when the information processing device CPU_CHIP inputs an erasure request from the NAND interface NAND IF1 will be described.

  When the erase request and erase address NEADD are input to the NAND interface circuit NDIF, the erase request and erase address NEADD address are transferred to the arbitration circuit ARB.

  The address arbitration circuit ARB transfers the erase address NEADD to the address conversion circuit DSTR. The address conversion circuit DSTR performs an operation on the address NEADD, converts it to the address MNEADD, and inputs it to the cache memory L2Cache hit determination circuit PL2Hit.

  Thereafter, the cache memory L2Cache and the hit determination circuit PL2Hit use the address MNEADD to perform processing for maintaining data consistency with the cache memories L2Cache, PL2A, and PL2B. Specifically, the cache memory L2Cache checks whether the data of the address MNEADD exists, and if it exists, invalidates the data. The hit determination circuit PL2Hit checks whether or not the data of the address MNEADD exists in the cache memories PL2A and PL2B, and if it exists, invalidates the data. When the invalidation of the data in the cache memories L2Cache, PL2A, and PL2B is completed, the data in the data buffer DREG is invalidated by the hit determination circuit L3Hit.

  When the invalidation of all the cache memories is completed, the access arbitration circuit ARB permits the erase request from the NAND interface circuit NDIF.

  When the access arbitration circuit ARB permits the erase request from the NAND interface circuit NDIF, the control circuit RWCL first inputs the data erase request and the erase address MNEADD to the control circuit FCNT. The control circuit FCNT erases the data in the memory cell array MARY according to the erase request and the erase address MNEADD.

  Further, the memory address management circuit MMG checks whether or not the erase address NEADD is an address in the write number averaging processing area.

  If the erase address NEADD is an address in the write count averaging processing area, after the data in the memory cell array MARY is erased, the sum of the write count and erase count managed by the write count averaging circuit WLV is unified. Increase one more. Furthermore, when the sum of the number of times of writing and the number of times of erasing reaches the sum threshold of the number of times of writing and the number of times of erasing held by the writing number averaging circuit WLV, the writing number averaging circuit WLV concentrates on rewriting. Although there is no particular limitation, the correspondence between the physical address and the logical address is changed for each 64-page data, and the correspondence information between the physical address and the logical address is held. As described above, the number of rewrites of the memory array can be averaged by the write number averaging circuit WLV, and the reliability can be improved.

In FIG. 1, the error detection / correction circuit ECC, the alternative processing circuit REP, and the write count averaging circuit WLV are provided in the control circuit CT_CHIP, but of course, they are provided in the flash memory FLASH_CHIP, and error detection and error correction are performed on the flash memory FLASH_CHIP side. The address substitution process and the write count averaging process may be configured.
<Description of write operation from NOR interface NOR IF>
Next, an operation when the information processing device CPU_CHIP inputs a write request from the NOR interface NOR IF will be described.

  Although not particularly limited, when a write request, write address NORWADD, and write data NORWDATA are input to the NOR interface circuit NRIF, the write data NWDATA is transferred to the write buffer WBUF via the flash control circuit FLCT, and the write address NORWADD is NAND. The data is transferred to the arbitration circuit ARB via the interface circuit NDIF. Thereafter, the memory module MSM performs the same operation as when a write request is input to the NAND interface NAND IF1.

As described above, the write operation from the NOR interface NOR IF can be realized by passing the write address NORWADD and the write data NORWDATA from the NOR interface NOR IF to the NAND interface circuit NDIF.
<Description of erase operation from NOR interface NOR IF>
Next, an operation when the information processing device CPU_CHIP inputs a deletion request from the NOR interface NOR IF will be described.

  Although not particularly limited, when an erase request and erase address NOREADD are input to the NOR interface circuit NRIF, the erase address NOREADD is transferred to the arbitration circuit ARB via the NAND interface circuit NDIF.

  The subsequent memory module MSM performs the same operation as when an erasure request is input to the NAND interface NAND IF1 described above.

  As described above, by erasing the erase address NOREADD from the NOR interface NOR IF to the NAND interface circuit NDIF, the erase operation from the NOR interface NOR IF can be realized.

  Although not particularly limited, the clock control circuit OSC starts the clock operation to start data transfer when data transfer in the memory module MSM immediately after the power is turned on, and access to the memory module MSM from the NOR interface NOR IF and NAND interface occurs. When the data transfer is completed, the lock operation is stopped.

As described above, the clock control circuit OSC can operate and reduce power consumption only when it is necessary for data transfer.
<Effect of Example 1>
As described above, following the NOR interface and NAND interface methods, the boot program in the flash memory FLASH_CHIP is automatically transferred to the cache memory L2Cache immediately after the power is turned on. Can be launched. Further, while the information processing device CPU_CHIP is starting up, the data in the flash memory FLASH_CHIP is automatically transferred to the cache memory L2Cache, so that the memory module MSM is immediately accessed when the information processing device CPU_CHIP is started up. Therefore, high performance can be achieved. You can set the address map in the flash memory. Synchronous NOR interface and asynchronous NOR interface, address conversion method, cache area and non-cache area, cache lock area and non-cache lock area, write count averaging process area and non-write count averaging process area, write protect area The non-write protected area can be set independently, and can be freely selected by the user according to the system.
<< Cache memory >>
Since the information processing device CPU_CHIP can directly output data from the cache memories LaCache, PL2A, and PL2B built in the memory module MSM, data transfer between the information processing device CPU_CHIP and the memory module MSM can be performed at high speed. . Address conversion circuit and address conversion can be selected. Since the address conversion circuit performs address conversion so that the read address input from the information processing device CPU_CHIP is distributed to the index address of the cache memory L2Cache, the utilization rate of the cache memory L2Cache, PL2A, and PL2B is improved and hit The rate is improved and data transfer can be speeded up.
<< Read ahead >>
Furthermore, the data prefetching function transfers the data of the next page of the data currently requested by the information processing device CPU_CHIP to the cache memory in advance, thereby increasing the hit rate to the cache memory and speeding up the transfer.
<< L3 cache >>
By using the data register DREG of the flash memory FLASH_CHIP as a cache memory, the hit rate can be improved by effectively increasing the capacity of the cache memory, and the data transfer between the information processing device CPU_CHIP and the memory module MSM can be performed at high speed. Can do.
<< Cache data update >>
In addition, the data update from the cache memories PL2A and PL2B to the cache memory L2Cache is performed simultaneously with the data transfer from the data register DREG to the buffer circuit BUF performed at the time of L2Cache miss and PL2 miss, so the data update time to the cache memory L2Cache is reduced. It can be concealed and waste of data transfer time can be eliminated.
<< Error detection and correction, address substitution process >>
In the memory module MM, error detection and correction are performed when reading from the FALSH, and when writing, replacement processing is performed for defective addresses that were not written correctly, so processing can be performed at high speed. And can maintain reliability.
<< Average number of writes >>
The number of rewrites of the memory array can be averaged by the write number averaging circuit WLV, and the reliability can be further improved.
<< Wait signal >>
With the Wait signal, the information processing device CPU_CHIP can know the arrival of the requested data, and even if the data read time differs depending on the hit judgment results of the cache memory L2Cache hit judgment and hit judgment circuits PL2Hit and L3Hit Data can be imported.

In the present embodiment, an example in which the memory module MSM includes one flash memory has been described. However, the present invention is applicable even when the memory module MSM includes a plurality of flash memories. Needless to say, this is possible.
<Explanation of memory map>
2 is set in each register in the register block REG (mode setting register RModeReg, cache area setting register CAreaReg, cache lock area setting register CaLockReg, write protect area setting register WproReg, write number averaging processing area setting register WlvlReg). 3 shows an example of a memory map for the flash memory FLASH_CHIP managed by the memory address management circuit MMG based on the obtained values. In the present embodiment, although not particularly limited, a typical memory map will be described taking a memory module in which the storage area of the flash memory FLASH_CHIP is 1 Gbit + 32 Mbit (32 Mbit is an alternative area) as an example.

  Although there is no particular limitation, the flash memory FLASH_CHIP is divided into a main area MAIN and an alternative area REPAREA. The main area MAIN is divided into an area AREA-A, an area AREA-B, an area AREA-C, an area AREA-D, and an initial program area InitProg.

  The area AREA-A is managed as a non-cache area NONCAREA, a write count averaging process area WLV, and a non-write protect area NONWPRO.

  The area AREA-B is managed as a cache area CAREA, a cache lock area CALOCK, a write count averaging process area WLVL, and a non-write protect area NONWPRO.

  The area AREA-C is managed as a cache area CAREA, a non-cache lock area UNCALOCK, a non-write count averaging process area NONWLV, and a non-write protect area NONWRPRO.

  The area AREA-D is managed as a cache area CAREA, a non-cache lock area UNCALOCK, a non-write count averaging process area NONWLV, and a write protect area WPRO.

  The initial program area InitProg is managed as a cache area CAREA, a non-cache lock area UNCALOCK, a non-write count averaging process area NONWLV, and a write protect area WPRO.

  Although not particularly limited, the initial program area InitProg stores a boot program and automatic transfer area designation data.

  Although not particularly limited, the area AREA-D stores an operating system and the like.

  Although not particularly limited, the area AREA-B and the area AREA-C store application programs.

  The area AREA-A stores data such as music data, audio data, moving image data, and still image data, although not limited thereto.

  In addition, the FLASH is rewritten and the reliability is lowered, so that data written at the time of writing rarely becomes different data at the time of reading or data is not written at the time of rewriting. The replacement area REPAREA is provided to replace the defective program and data with a new area. The size of the replacement area REPAREA is not particularly limited, but may be determined so as to ensure the reliability guaranteed by the flash memory FLASH_CHIP.

Cache area CAREA, non-cache area NONCAREA, write protect area WRPRO, non-write protect area NONWRPRO, write number averaging process area WLVL and non-write number average process area NONWLVL are cache lock area CALOCK, non-cache lock area UNCALOCK, NOR By programming each register in the register block REG from the interface NOR IF, each can be set independently and can be freely selected by the user according to the system.
<Operation immediately after power-on>
Data transfer from the flash memory FLASH_CHIP to the cache memories L2Cache, PL2A, and PL2B when the power is turned on will be described.

  After the power is turned on, the flash control circuit FLCT reads data in the initial program area InitProg of the flash memory FLASH_CHIP to the circuit BUF, and checks whether there is an error in the error detection / correction circuit ECC. If there is no error, the boot program in the initial program area is transferred to the cache memory PL2A. If there is an error, the boot program is corrected, and the boot program in the initial program area is transferred to the cache memory PL2A. Next, the control circuit FLCT reads the automatic transfer area designation data from the buffer circuit BUF, sequentially reads the data in the flash memory FLASH_CHIP in the range indicated by this data to the buffer circuit BUF, and an error is detected by the error detection / correction circuit ECC. Check if it exists. If there is no error, it is transferred to the cache memory L2Cache via the cache memory PL2B, and if there is an error, it is corrected and transferred to the cache memory L2Cache via the cache memory PL2B.

In this way, by transferring necessary data to the cache memory immediately after the power is turned on, the information processing device CPU_CHIP reads this boot program from the cache memory after it starts up, quickly starts itself up, and further dynamically The random access memory DRAM_CHIP can be initialized.
<Description of read operation>
The cache memory (L2Cache, PL2A, and PL2B) holds the data in the cache area CAREA. If the cache memory (L2Cache, PL2A, and PL2B) is hit, the cache memory (L2Cache, PL2A, and PL2B) directly The data is output from the NOR interface NOR IF to the information processing device CPU_CHIP through the NOR interface circuit NRIF.

  If the cache memory (L2Cache, PL2A, and PL2B) misses, the data is transferred from the flash memory FLASH_CHIP to the cache memory (L2Cache, PL2A, and PL2B. Next, the data in the flash memory FLASH_CHIP is transferred to the cache memories L2Cache, PL2A, and PL2B. The operation to transfer to will be described.

  When the read request from NOR interface NOR IF is L2Cache miss, PL2 miss and L3 hit, or L2Cache miss, PL2 miss and L3 miss, data transfer from flash memory FLASH_CHIP to cache memory L2Cache, PL2A, PL2B Arise.

  First, data transfer when a read request from the NOR interface NOR IF results in an L2Cache miss, a PL2 miss, and an L3 hit will be described.

  If the requested data is data in the cache area, the Nth page data in the data register DREG of the flash memory FLASH_CHIP is transferred to the buffer circuit BUF.

  While the data for one page in the data register DREG is being transferred to the buffer circuit BUF, the data currently held in the cache memories PL2A and PL2B is transferred to the cache memory L2Cache, and the cache memory L2Cache is updated.

  The Nth page data transferred to the buffer circuit BUF is checked by the error detection / correction circuit ECC to check whether there is an error. If there is no error, it is directly transferred to the cache memory PL2A. If there is an error, the error-corrected data is transferred to the cache memory PL2A.

  Further, the next page data in the data register DREG, that is, the (N + 1) th data is transferred to the buffer circuit BUF by the prefetch function.

  The data of the (N + 1) th page transferred to the buffer circuit BUF is checked by the error detection / correction circuit ECC for whether there is an error. If there is no error, it is directly transferred to the cache memory PL2B. If there is an error, the error-corrected data is transferred to the cache memory PL2B.

  Next, data transfer when a read request from the NOR interface NOR IF becomes an L2Cache miss, a PL2 miss, and an L3 miss will be described.

  If the address of the read request is in the cache area, the Nth page data in the memory cell array MARY of the flash memory FLASH_CHIP is transferred to the data register DREG. Thereafter, the Nth page data in the data register DREG is transferred to the buffer circuit BUF.

  While the data in the data register DREG is being transferred to the buffer circuit BUF, the data currently held in the cache memories PL2A and PL2B is transferred to the cache memory L2Cache, and the cache memory L2Cache is updated.

  The Nth page data transferred to the buffer circuit BUF is checked by the error detection / correction circuit ECC to check whether there is an error. If there is no error, it is directly transferred to the cache memory PL2A. If there is an error, the error-corrected data is transferred to the cache memory PL2A.

  Further, the next page data in the data register DREG, that is, the (N + 1) th data is transferred to the buffer circuit BUF by the prefetch function.

  The data of the (N + 1) th page transferred to the buffer circuit BUF is checked by the error detection / correction circuit ECC for whether there is an error. If there is no error, it is directly transferred to the cache memory PL2B. If there is an error, the error-corrected data is transferred to the cache memory PL2B.

When a read request from the NOR interface NOR IF results in an L2Cache hit, data is read directly from the cache memory L2Cache. When the read request from the NOR interface NOR IF is a PL2 hit, the data is directly read from the cache memory PL2 or PL2B.
<Description of effects>
<< Cache memory >>
Data in the cache area is transferred to the cache memory (L2Cache, PL2A, PL2B), and if a read request from the information processing device CPU_CHIP hits the cache memory (L2Cache, PL2A, PL2B), the cache memory (L2Cache, PL2A, PL2B) Since data can be directly output from (), data transfer between the information processing device CPU_CHIP and the memory module MSM can be performed at high speed.
<< Read ahead >>
By using the data prefetching function, the data of the next page of the data currently requested by the information processing device CPU_CHIP is transferred to the cache memory in advance, thereby increasing the hit rate to the cache memory and speeding up the data transfer.
<< L3 cache >>
By using the data register DREG of the flash memory FLASH_CHIP as a cache memory, the hit rate can be improved by effectively increasing the capacity of the cache memory, and the data transfer between the information processing device CPU_CHIP and the memory module MSM can be performed at high speed. Can do.
<< Address substitution process >>
When writing data to the flash memory FLASH_CHIP, it is possible to perform substitution processing to the substitution processing area REPAREA for a defective address that has not been written correctly, and to maintain reliability.
<Description of register block>
FIG. 3 is an example showing a plurality of registers constituting the register block REG.

  Although not particularly limited, the register block REG includes a read mode setting register RModeReg, a cache area setting register CAreaReg, a cache lock area setting register CaLockReg, a write protect area setting register WproReg, and a write number averaging process area setting register WlvlReg.

  When changing the cache area and the non-cache area, the cache area and the non-cache area can be changed by rewriting the value of the cache area setting register CAreaReg from the NOR interface NOR IF. Although not particularly limited, immediately after the power is turned on, the entire area of the flash memory FLASH_CHIP is a cache area.

  Data in the cache area is transferred to the cache memories L2Cache, PL2A, and PL2B, and data in the non-cache area is not transferred to the cache memories L2Cache, PL2A, and PL2B.

  The cache lock area and the non-cache lock area are not particularly limited, but the cache lock area and the non-cache lock area can be changed by rewriting the value of the cache area setting register CAreaReg from the NOR interface NOR IF. . Although not particularly limited, immediately after the power is turned on, the entire area of the flash memory FLASH_CHIP is a non-cache lock area.

  Once the data in the cache lock area is transferred to the cache memory L2Cache, it can exist in the cache memory L2Cache until the cache area setting register is rewritten by a cache lock release instruction. Further, there is a possibility that data in the non-cache lock area is evicted from the cache memory L2Cache.

  When changing the write count averaging processing area and non-write count averaging process area, there is no particular limitation, but the number of writes is averaged by rewriting the value of the write count averaging process area setting register WLvlReg from the NOR interface NOR IF. The processing area and the non-write count averaging processing area can be changed. Although there is no particular limitation, immediately after the power is turned on, a half area of the flash memory FLASH_CHIP is a write frequency averaging process area.

  When the write number averaging circuit WLV determines that rewriting is concentrated on the data within the write number averaging process area, the write number average process is performed.

  The write count averaging process is not performed on the data in the non-write count averaging process area.

  When changing the write protect area and non-write protect area, there is no particular limitation, but the write protect area and non-write protect area can be changed by rewriting the value of the write protect area setting register WproReg from the NOR interface NOR IF. it can. Although not particularly limited, immediately after the power is turned on, the entire area of the flash memory FLASH_CHIP is a non-write protected area.

  Writing is not performed in the write protect area, and writing is possible in the non-write protect area.

  The NOR interface provided in the memory module MSM includes a synchronous NOR interface that operates in synchronization with the clock signal CLK, and an asynchronous NOR interface that does not synchronize with the clock signal CLK, and operates with one of the NOR interfaces. Although not particularly limited, the memory module MSM operates with an asynchronous NOR interface immediately after power-on. In addition, there is no particular limitation when changing the NOR interface provided in the memory module MSM, but by changing the value of the read mode setting register RModeReg from the NOR interface NOR IF, it is changed to a synchronous NOR interface or an asynchronous NOR interface. be able to.

  In the address conversion circuit DSTR, although not particularly limited, a plurality of address conversion methods (simple index conversion method, index bit shift conversion method, index calculation method) can be realized, and the operation is performed by any one of the address conversion methods. Although there is no particular limitation, immediately after the power is turned on, the address conversion circuit DSTR operates by the index calculation method.

  Although not particularly limited, the NOR interface and the address conversion method provided in the memory module MSM can be changed by rewriting the value of the read mode setting register RModeReg from the NOR interface NOR IF.

As described above, synchronous NOR interface and asynchronous NOR interface, address translation method, cache area and non-cache area, cache lock area and non-cache lock area, write count averaging process area and non-write count averaging process area The write protect area and the non-write protect area can be set independently, and can be freely selected by the user according to the system.
<Initial sequence at power-on>
FIG. 4 shows an initial sequence when the memory module MSM is powered on.

The control circuit CT_CHIP, the flash memory FLASH_CHIP, and the dynamic random access memory DRAM_CHIP are powered on during the T1 period (PWON), and reset during the T2 period (RESET). Data in the initial program area InitProg of FLASH_CHIP is transferred to the control circuit CT_CHIP in the next T3 period (Initload) after reset is released. During the period T4 (AutoLoad), data in the range specified by the automatic transfer area specification data in the initial program area is transferred from the flash memory FLASH_CHIP to the control circuit CT_CHIP. When the transfer of data in the range specified in the dynamic transfer area specification data is completed, the initial operation completion signal PCMP is set to High. After the period (IDLE) of T5, the memory module MSM enters an idle state and waits for a request from the information processing device CPU_CHP.
<Address translation straight>
5 to 7 show an example of address conversion between the address from the NOR interface NOR IF and the cache memory L2Cache address, which is performed by the address conversion circuit DSTR.

  First, FIG. 5 will be described. FIG. 5A shows an example of an address conversion method between the address from the NOR interface NOR IF and the cache memory L2Cache address, and FIG. 5B shows an example of the configuration of the cache memory L2Cache. .

  The configuration of the cache memory L2Cache is not particularly limited, but the capacity is 1 Mbyte, the line size is 512 bytes, the index address is from 0 to 511, and the set associative is a 4-way set associative.

  The address NRAD from the NOR interface NOR IF has 32 bits from 0 to 31, and can accommodate a maximum address space of 4 Gbytes.

  In this example, a case where the capacity of the flash memory FLASH_CHIP is 256 Mbytes will be described.

  The address Add0 of the 0th to 8th bits of the address NRAD corresponds to the line size of the cache memory L2Cache, the address Add1 of the 9th to 17th bits corresponds to the index address Index2 of the cache memory L2Cache, and is 18 to 27 bits. The eye address Add2 corresponds to the tag address Tag2 of the cache memory L2Cache.

  Next, the operation of the cache memory L2Cache when the value of the address Add1 is 511 and the value of the address ADD2 is Add2-511 will be described.

  The index address Index2 of the cache memory L2Cache is searched with the address Add1, and since it is a 4-way set associative, four types of tag addresses are selected.

  The comparison circuit COMP compares the address Add2 with the selected tag address. Since the address Add2 matches with the tag address in Add2-511, that is, hits, the data Data511 is selected from the data array.

Finally, the address Add0 is input to the selection circuit SEL, and one byte in the 512-byte data Data1 is output.
<Address conversion bit shift>
Next, FIG. 6 will be described. FIG. 6A shows an example of an address conversion method between the address from the NOR interface NOR IF and the cache memory L2Cache address, and FIG. 6B shows an example of the configuration of the cache memory L2Cache. .

  The configuration of the cache memory L2Cache is not particularly limited, but is the same as that shown in FIG.

  The address NRAD from the NOR interface NOR IF has 32 bits from 0 to 31, and can accommodate a maximum address space of 4 Gbytes.

  In this example, a case where the capacity of the flash memory FLASH_CHIP is 256 Mbytes will be described.

  The address Add0 of the 0th to 8th bits of the address NRAD corresponds to the line size Line2 of the cache memory L2Cache.

  The 9th to 11th bits and the 13th to 18th bits of the address NRAD correspond to the 0th to 2nd bits and the 3rd to 8th bits of the address Add3, respectively, and correspond to the index address Index2 of the cache memory L2Cache.

  The 12th and 19th to 27th bits of the address NRAD correspond to the 0th and 1st to 8th bits of the address Add4, respectively, and correspond to the tag address Tag2 of the cache memory L2Cache.

  Next, the operation of the cache memory L2Cache when the value of the address Add3 is 1 and the value of the address Add4 is Add5-1 will be described.

  The address Add3 searches for the index address Indx2 of the cache memory L2Cache, and since it is a 4-way set associative, four types of tag addresses are selected.

  The comparison circuit COMP compares the address Add4 with the selected tag address. Since the address Add4 matches the tag address in Add5-1, that is, hits, the data Data0 is selected from the data array.

Finally, the address Add0 is input to the selection circuit SEL, and 1 byte is output from the 512-byte data Data0.
<Address translation diffusion>
Next, FIG. 7 will be described. FIG. 7A shows an example of an address conversion method between the address from the NOR interface NOR IF and the cache memory L2Cache address, and FIG. 7B shows an example of the configuration of the cache memory L2Cache. .

  The configuration of the cache memory L2Cache is not particularly limited, but is the same as that in FIG.

  The address NRAD from the NOR interface NOR IF has 32 bits from 0 to 31, and can accommodate a maximum address space of 4 Gbytes.

  In this example, a case where the capacity of the flash memory FLASH_CHIP is 256 Mbytes will be described.

  The address Add0 of the 0th to 8th bits of the address NRAD corresponds to the line size Line2 of the cache memory L2Cache. The address Add1 of the 9th to 17th bits of the address NRAD and the address Add5 of the 18th to 26th bits are converted into an address Add6 by the address conversion circuit DSTR. The address Add6 corresponds to the index address Index2 of the cache memory L2Cache.

  The address Add2 of the 18th to 27th bits of the address NRAD corresponds to the tag address Tag2 of the cache memory L2Cache.

  The bit width of the address Add1 and the address Add5 is equal to the index address of the cache memory, and the address conversion circuit DSTR obtains the sum of the address Add1 [8: 0] and the address Add5 [8: 0], The 8th to 0th bits are converted to address Add6 [8: 0] and assigned to index address Index2.

  Since the line size, index address, and tag address vary depending on the storage capacity and configuration of the cache memory, a general description will be given.

When the storage capacity of the cache memory L2Cache is 2 ^N bytes, the line size Line2 is L bits, the index address Index2 size is I bits, and the tag address Tag2 size is (NIL) bits,
The address NRAD is divided into Add0 [L-1: 0], Add1 [I-1: 0], and Add2 [NLI-1: 0] from the lower bits.

  The address Add0 [L-1: 0] corresponds to the line size Line2 [L-1: 0] of the cache memory L2Cache, and the address Add2 [NLI-1: 0] is the tag address Tag2 [NI-1 of the cache memory L2Cache. 0]. Add1 [I-1: 0] has the same size as the index address Index2.

  If the tag address Tag2 size is equal to or larger than the size of the index address Index2, the address Add5 [I-1: 0] is assigned to the same size as the index address Index2 from the lower bits of the address Add2 [N-L-I-1: 0].

  If the tag address Tag2 size is smaller than the size of the index address Index2, the address Add2 [N-L-I-1: 0] becomes Add5 [N-L-I-1: 0].

If the tag address Tag2 size is greater than or equal to the index address Index2 size,
In the address conversion circuit DSTR, the sum of the address Add1 [I-1: 0] and the address Add5 [I-1: 0] is obtained, and the 0th bit from the (I-1) th bit of the sum is added to the address Add6 [ I-1: 0] and assigned to index address Index2 [I-1: 0].

  If the tag address Tag2 size is smaller than the size of the index address Index2, the address conversion circuit DSTR calculates the sum of the address Add1 [I-1: 0] and the address Add5 [NLI-1: 0], I-1) Bit 0 to bit 0 are converted to address Add6 [I-1: 0] and assigned to index address Index2 [I-1: 0].

  FIG. 8 illustrates the operation of the cache memory L2Cache when the value of the address Add6 is 0 and the value of the address ADD2 is Add2-0.

  The index address Indx2 of the cache memory L2Cache is searched with the address Add6, and four types of tag addresses are selected because it is a 4-way set associative.

The comparison circuit COMP compares the address Add2 with the selected tag address. Since the address Add2 matches the tag address in Add2-0, that is, hits, the data Data0 is selected from the data array.
Finally, the address Add0 is input to the selection circuit SEL, and 1 byte in the 512-byte data Data0 is output.
<Address translation effect>
FIGS. 9 and 10 are examples showing that the cache memory L2Cache is updated when the address conversion described in FIGS. 5 and 7 is performed.

  It was found that a read request input from the information processing device CPU_CHIP to the memory module MSM during execution of an application on the information processing device CPU_CHIP has characteristics.

  The first feature is that the address Add1 is generated in a distributed manner, and the address Add2 is a series of read requests that repeat a specific address range.

  The second feature is that the address Add2 is generated in a distributed manner, and the address Add1 has a series of read requests that repeat a specific address range.

  FIG. 9A shows a data update replace of the cache memory L2Cache generated by address conversion by the index calculation method shown in FIG. 7 when a read request having the first feature is input to the memory module. Yes.

  FIG. 9B shows the data update replace of the cache memory L2Cache generated by the address conversion by the simple index conversion method shown in FIG. 5 when the read request having the first feature is input to the memory module. ing.

  FIG. 10A shows a data update replace of the cache memory L2Cache generated by address conversion by the index calculation method shown in FIG. 7 when the read request having the second feature is input to the memory module. Yes.

  FIG. 10B shows a data update replace of the cache memory L2Cache caused by address conversion by the simple index conversion method shown in FIG. 5 when a read request having the second feature is input to the memory module. ing.

  As shown in FIG. 9B, in the address conversion method based on the simple index conversion method described in FIG. 5, the address Add1 is associated with the index address Index2 of the cache memory L2Cache, and the address Add2 is associated with the tag address Tag2. For this reason, when a read request having the first feature is input to the memory module, the index address Index is distributed, and therefore the index address Index is distributed, so that replacement of the cache memory L2Cache does not occur.

  As shown in FIG. 9A, in the address conversion method based on the index calculation method of FIG. 7, the address Add1 and the address Add2 are calculated, the address Add10 is generated so as to be distributed, and the address Add10 is indexed to the cache memory L2Cache. Corresponds to address Index2. For this reason, when a read request having the first feature is input to the L2 cache, the index address Index is distributed, so that the replacement of the cache memory L2Cache does not occur. That is, the cache memory L2cache can be effectively used by the address conversion method based on the index calculation method described in FIG. 7, and the hit rate is improved.

  As shown in FIG. 10B, in the address conversion method based on the simple index conversion method described in FIG. 5, the address Add1 is associated with the index address Index2 of the cache memory L2Cache, and the address Add2 is associated with the tag address Tag2. Therefore, when a read request with the second feature is input to the L2 cache, a search to a specific index address Index frequently occurs, and a mistake occurs because the tag address Tag2 is distributed. The replacement of the cache memory L2Cache frequently occurs. That is, only a part of the cache memory L2Cache can be used, and replacement of the cache memory L2Cache frequently occurs.

  As shown in FIG. 10A, in the address conversion method based on the index calculation method of FIG. 7, the address Add1 and the address Add2 are calculated, the address Add10 is generated so as to be distributed, and the address Add10 is indexed to the cache memory L2Cache. Corresponds to address Index2. For this reason, even when a read request having the second feature is input to the L2 cache, the replacement of the cache memory L2Cache does not occur because the index address Index is distributed. That is, the cache memory L2cache can be effectively used by the address conversion method based on the index calculation method described in FIG. 7, and the hit rate is increased.

  As described above, in the address conversion method based on the simple index conversion method of FIG. 5, the index can be distributed for the read request having the first feature, but for the read request having the second feature. The index cannot be distributed, and replacement of the cache memory L2Cache frequently occurs.

  In the index calculation method shown in FIG. 7, the index can be distributed and the cache memory L2cache is enabled corresponding to both the read request having the first feature and the read request having the second feature. The hit rate can be improved.

The simple index conversion method shown in FIG. 5, the index bit shift conversion method shown in FIG. 6, and the index calculation method shown in FIG. 7 are obtained by rewriting the value of the read mode setting register RModeReg from the NOR interface NOR IF. , You can choose. Thus, the address translation method can be freely selected on the user side according to the system.
<Register settings>
11A, 11B, and 11C show an example for selecting a synchronous NOR interface and an asynchronous NOR interface, selecting a burst length, and selecting an address conversion method performed by the address conversion circuit DSTR. It is a flowchart.

  The selection of the synchronous NOR interface and the asynchronous NOR interface, the selection of the burst length, and the selection of the address conversion method performed by the address conversion circuit DSTR can be selected simultaneously by writing the setting value to the read mode setting register RmodeReg.

  When selecting either the synchronous NOR interface or asynchronous NOR interface, the burst length, or the address conversion method performed by the address conversion circuit DSTR, the read mode setting register is selected from the NOR interface NOR IF. An instruction RModeSet for setting the value of RModeReg is input (Step 1), and then the set value is written to the read mode setting register RmodeReg (Step 2).

  FIG. 11 (a) is an example of selecting the NOR interface to the synchronous NOR interface, the burst length to 4, and the address translation method to the index calculation method.

  FIG. 11B shows an example in which the NOR interface is selected as the synchronous NOR interface, the burst length is set as 8, and the address conversion method is selected as the index bit shift conversion method.

  FIG. 11B shows an example of selecting the NOR interface to the asynchronous NOR interface, the burst length to 4, and the address conversion method to the simple index conversion method.

  FIG. 11D is a flowchart showing an example for reading the set value in the read mode setting register RmodeReg.

  Reading the setting value in the read mode setting register RmodeReg is not particularly limited, but when the read mode setting register read command RmodeRead is input from the NOR interface NOR IF (Step 1), the read mode setting register is read through the NOR interface NOR IF. The set value in RmodeReg is output to (Step 2).

  FIG. 12A is a flowchart showing an example for setting the ranges of the cache area and the non-cache area.

  When setting the cache area and the non-cache area, although not particularly limited, the instruction CAreaSet for setting the cache area is input from the NOR interface NOR IF (Step 1), and then the cache area is input to the cache area setting register CAreaReg. The start address value of the cache area is written (Step 2), and then the end address value of the cache area is written to the cache area setting register CAreaReg (Step 3). A cache area is between the start address value and end address value of the cache area, and the rest is a non-cache area.

  FIG. 12C is a flowchart showing an example for reading the set value in the cache area setting register CAreaReg.

  The setting value in the cache area setting register CAreaReg is not particularly limited, but when the cache area setting register CAreaReg read instruction CAreaRead is input from the NOR interface NOR IF (Step 1), the cache area setting is performed through the NOR interface NOR IF. The set value in the register CAreaReg is output to (Step 2).

  FIG. 12B is a flowchart showing an example for setting the ranges of the cache lock area and the non-cache lock area.

  When setting the cache lock area and the non-cache lock area, the command CaLOckSet for setting the cache lock area setting is input from the NOR interface NOR IF (Step 1), but not particularly limited. Next, the cache lock area setting register The start address value of the cache lock area is written to CaLockReg (Step 2), and then the end address value of the cache lock area is written to the cache lock area setting register CaLockReg (Step 3). The cache lock area is between the start address value and the end address value of the cache lock area, and the rest is the non-cache lock area. The cache lock area is preferably set in the cache area.

  FIG. 12D is a flowchart showing an example for reading the set value in the cache lock area setting register CaLockReg.

  The setting value in the cache lock area setting register CaLockReg is not particularly limited, but when the cache lock area setting register CaLockReg read instruction CaLockRead is input from the NOR interface NOR IF (Step 1), the cache is passed through the NOR interface NOR IF. The set value in the lock area setting register CaLockReg is output to (Step 2).

  FIG. 13A is a flowchart showing an example for setting the write count averaging process area and the non-write count averaging process area.

  When setting the write count averaging process area and the non-write count averaging process area, the command WlvlSet for setting the write count averaging process area is input from the NOR interface NOR IF (Step 1). Next, write the start address value of the write count averaging processing area to the write count averaging process area setting register WlvlReg (Step 2), and then write the write count averaging process area to the write count averaging process area setting register WlvlReg. Write the end address value (Step 3). The area between the start address value and the end address value of the write count averaging process area is the write count average process area, and the rest is the non-write count average process area.

  FIG. 13C is a flowchart showing an example for reading the set value in the write count averaging process area setting register WlvlReg.

  To read the setting value in the write count averaging processing area setting register WlvlReg, there is no particular limitation. However, when the write count averaging process area setting register WlvlReg read instruction WlvlRead is input from the NOR interface NOR IF (NO in Step 1) Through the interface NOR IF, the set value in the write count averaging processing area setting register WlvlReg is output to (Step 2).

  FIG. 13B is a flowchart showing an example for setting the write protect area and the non-write protect area.

  When setting the write protect area and the non-write protect area, although not particularly limited, an instruction WproSet for setting the write protect area is input from the NOR interface NOR IF (Step 1), and then the write protect area setting register WproReg Write the start address value of the write protect area (Step 2), and then write the end address value of the write protect area to the write protect area setting register WproReg (Step 3). The area between the start address value and the end address value of the write protect area is the write number averaging process area, and the other areas are non-write protect areas.

  FIG. 13D is a flowchart showing an example for reading the set value in the write protect area setting register WproReg.

  To read the setting value in the write protection area setting register WproReg, there is no particular limitation. However, when the write protection area setting register read command WproRead is input from the NOR interface NOR IF (Step 1), the write protection is performed through the NOR interface NOR IF. The set value in the area setting register WproReg is output to (Step 2).

As described above, synchronous NOR interface and asynchronous NOR interface, cache area and non-cache area, cache lock area and non-cache lock area, write count averaging process area and non-write count averaging process area, write protect area and Non-write protected areas can be set independently, and can be freely selected by the user according to the system.
<Reading flow>
FIG. 14 is a flowchart illustrating an example of a read operation of the memory module MSM when a read request is input from the NOR interface NOR IF.

  When a read request and read address RAdd are input from the NOR interface NOR IF to the memory module MSM (Step 1), a write or erase request from the NAND interface NAND IF1 is generated, and the write or erase address WorEAd matches the read address Radid. If the write or erase address WorEAdd matches the read address Radd, the memory module MSM outputs an error through the NOR interface NOR IF (Step 3).

  If the write or erase address WorEAdd does not match the read address Radd, the memory address management circuit MMG checks whether the address Radd is within the cache address range (Step 4), and if the address Radd is outside the cache address range, The memory module MSM outputs an error through the NOR interface NOR IF (Step 3).

  If the address Radd is within the cache address range, the access arbitration circuit ARB has a read / write request from the NAND interface circuit NDIF, and also performs an operation in response to a read / write request from the NAND interface circuit NDIF. Check if. If there is a read or write request from the NAND interface circuit NDIF and the operation for this request has not yet been performed, the read request from the NAND interface circuit NDIF is temporarily postponed, and then a read request from the NOR interface NOR IF is issued. Allow it preferentially (Step 4). When an operation for a read or write request from the NAND interface circuit NDIF is being executed, the operation being executed is temporarily interrupted, and a read request from the NOR interface NOR IF is preferentially permitted (Step 5).

  Next, the address conversion circuit DSTR converts the address Radd to the address MRadd (Step 6). Next, the address Mradd is input to the cache memory L2Cache and the hit determination circuits PL2Hit and L3Hit, hit determination is performed in the cache memory L2Cache (Step 7), hit determination in the hit determination circuit PL2Hit (Step 8), and hit determination circuit L3Hit Hit determination (Step 9) is performed. When the cache memory L2Cache hits, data is output from the cache memory L2Cache (Step 10) and read through the NOR interface NOR IF (Step 11). If the cache memory L2Cache misses and the hit determination circuit PL2Hit hits, data is output from either of the cache memories PL2A and PL2B (Step 12) and read through the NOR interface NOR IF (Step 11).

  When the cache memory L2Cache misses, the hit judgment circuit PL2Hit misses, and the hit judgment circuit L3Hit hits, the Nth page data in the data register DREG in the flash memory FLASH_CHIP is transferred to the buffer circuit BUF (Step 13).

  Next, error detection is performed by the error detection / correction circuit ECC while transferring the Nth page data to the buffer circuit BUF (Step 14). Next, it is checked whether there is an error detection / correction circuit ECC error (Step 15). If there is no error, the Nth page data transferred to the buffer circuit BUF is transferred to the cache memory PL2A by the control circuit RWCL. If there is an error, the error detection and correction circuit ECC corrects the error (Step 16), and then the Nth page data is transferred to the cache memory PL2A by the control circuit RWCL (Step 17).

  Data requested by the information processing device CPU_CHIP in the Nth page data transferred to the cache memory PL2A is read from the NOR interface NOR IF through the NOR interface circuit NRIF.

  Further, the prefetch instruction circuit PRECT supports prefetching of data to the control circuit RWCL, the control circuit RWCL inputs a read request to the control circuit FCNT, and buffers the next page data in the data register DREG, that is, the N + 1th data. Transfer to circuit BUF.

  Next, error detection is performed by the error detection / correction circuit ECC while transferring the (N + 1) th page data to the buffer circuit BUF (Step 19). Next, it is checked whether there is an error detection / correction circuit ECC error (Step 20). If there is no error, the (N + 1) th page data transferred to the buffer circuit BUF is transferred to the cache memory PL2B by the control circuit RWCL. If there is an error, the error detection and correction circuit ECC corrects the error (Step 12), and then the Nth page data is transferred to the cache memory PL2A by the control circuit RWCL (Step 22).

If cache memory L2Cache misses, hit decision circuit PL2Hit misses, hit decision circuit L3Hit misses,
First, the control circuit RWCL inputs a read request for Nth page data to the control circuit FCNT. The control circuit FCNT transfers the Nth page data in the memory cell array MARY to the data register DREG (Step 23). Next, the Nth page data in the data register DREG is transferred to the buffer circuit BUF (Step 13).

  Next, error detection is performed by the error detection / correction circuit ECC while transferring the Nth page data to the buffer circuit BUF (Step 14). Next, it is checked whether there is an error detection / correction circuit ECC error (Step 15). If there is no error, the Nth page data transferred to the buffer circuit BUF is transferred to the cache memory PL2A by the control circuit RWCL. If there is an error, the error detection and correction circuit ECC corrects the error (Step 16), and then the Nth page data is transferred to the cache memory PL2A by the control circuit RWCL (Step 17).

  Data requested by the information processing device CPU_CHIP in the Nth page data transferred to the cache memory PL2A is read from the NOR interface NOR IF through the NOR interface circuit NRIF.

  Further, the prefetch instruction circuit PRECT supports prefetching of data to the control circuit RWCL, the control circuit RWCL inputs a read request to the control circuit FCNT, and buffers the next page data in the data register DREG, that is, the N + 1th data. Transfer to circuit BUF.

Next, error detection is performed by the error detection / correction circuit ECC while transferring the (N + 1) th page data to the buffer circuit BUF (Step 19). Next, it is checked whether there is an error detection / correction circuit ECC error (Step 20). If there is no error, the (N + 1) th page data transferred to the buffer circuit BUF is transferred to the cache memory PL2B by the control circuit RWCL. If there is an error, the error detection and correction circuit ECC corrects the error (Step 12), and then the Nth page data is transferred to the cache memory PL2A by the control circuit RWCL (Step 22).
<Write operation>
FIG. 15 is a flowchart showing an example of access arbitration and write operation of the memory module MSM when a write request is generated from the NAND interface NAND IF1 and a read request is generated from the NOR interface.

  When the write address NWADD and the write data NWDATA are input from the NAND interface NAND IF1 (Step 1), the write address NWADD is transferred to the memory address management circuit MMG, and the write data NWDATA is transferred to the write buffer WBUF (Step 2).

  Next, the access arbitration circuit ARB checks whether or not a read request is input from the NOR interface NOR IF (Step 3). If a read request is input, the operation according to the write request from the NAND interface NAND IF1 is temporarily stopped and prioritized. Specifically, the read operation shown in FIG. 20 is performed (Step 4). When this read operation is completed, the operation returns to the operation according to the write request from the NAND interface NAND IF1, checks whether the write address NWADD exists in the cache address area (Step 5), and the address conversion circuit DSTR changes the address NWADD to the address MNWADD. (Step 6).

  The address MNWADD is compared with the tag address of the cache memory L2Cache (Step 7), and the matched tag address is invalidated (Step 8).

  Next, the access arbitration circuit ARB checks whether a read request is input from the NOR interface NOR IF (Step 9). If a read request is input, the operation according to the write request from the NAND interface NAND IF1 is temporarily stopped and prioritized. Specifically, the read operation shown in FIG. 20 is performed (Step 10). When this read operation is completed, the operation returns to the operation according to the write request from the NAND interface NAND IF1, and the write data NWDATA held in the write buffer WBUF is transferred to the data register DREG (Step 11).

  Next, the access arbitration circuit ARB checks whether a read request is input from the NOR interface NOR IF (Step 12). If a read request is input, the operation due to the write request from the NAND interface NAND IF1 is temporarily stopped and prioritized. Specifically, the read operation shown in FIG. 20 is performed (Step 13). When this read operation is completed, the operation returns to the operation according to the write request from the NAND interface NAND IF1, and the write data NWDATA held in the data register DREG is written to the memory cell array MARY (Step 14).

The alternative processing circuit REP checks whether or not the writing to the memory cell array MARY has succeeded (Step 15), and when the writing fails, prepares a new alternative address prepared in advance in the flash memory FLASH_CHIP (Step 16). ), Writing to this address (Step 14). After the write is successful, the access arbitration circuit ARB checks whether a read request is input from the NOR interface NOR IF (Step 17). If a read request is input, the operation due to the write request from the NAND interface NAND IF1 is suspended. Then, the read operation shown in FIG. 20 is preferentially performed (Step 18). When this read operation is completed, the write address NWADD is finally cleared.
<Erase operation from NAND IF1>
FIG. 16 is a flowchart showing an example of access arbitration and erase operation of the memory module MSM when an erase request is generated from the NAND interface NAND IF1 and a read request is generated from the NOR interface.

  An erase command and an erase address NEADD are input from the NAND interface NAND IF1, and the erase address NEADD is transferred to the memory address management circuit MMG (Step 1).

  Next, the access arbitration circuit ARB checks whether or not a read request is input from the NOR interface NOR IF (Step 2). If a read request is input, the operation due to the erase request from the NAND interface NAND IF1 is temporarily stopped and prioritized. Specifically, the read operation shown in FIG. 20 is performed (Step 3). When this read operation is completed, the operation returns to the operation by the erase request from the NAND interface NAND IF1, checks whether the erase address NWADD exists in the cache address area (Step 4), and the address NEADD is changed to the address MNEADD by the address conversion circuit DSTR. (Step 5).

  The address MNEADD is compared with the tag address of the cache memory L2Cache (Step 6), and the matched tag address is invalidated (Step 7).

  Next, the access arbitration circuit ARB checks whether a read request has been input from the NOR interface NOR IF (Step 8). If a read request has been input, the operation due to the erase request from the NAND interface NAND IF1 is suspended and given priority. Specifically, the read operation shown in FIG. 20 is performed (Step 9). When this read operation is completed, the operation returns to the operation according to the erase request from the NAND interface NAND IF1, and the memory cell array MARY is erased (Step 11).

  Next, the access arbitration circuit ARB checks whether a read request is input from the NOR interface NOR IF (Step 11). If a read request is input, the operation according to the write request from the NAND interface NAND IF1 is temporarily stopped and prioritized. Specifically, the read operation shown in FIG. 20 is performed (Step 12). When this read operation is completed, the operation returns to the operation according to the erase request from the NAND interface NAND IF1, and it is checked whether the address NEADD exists in the write count averaging area (Step 13). If the address NEADD is in the write count averaging area, does the sum of the write count and erase count reach the total threshold of the write count and erase count held by the write count averaging circuit WLV? (Step 14), and when the sum threshold is reached, the write number averaging circuit WLV determines that rewriting is concentrated, and performs the write number averaging process (Step 15). This write count averaging process is to change the correspondence between the physical address and the logical address for each block (64 pages) and to retain the correspondence information between the physical address and the logical address.

If the address NEADD does not exist in the write count averaging area, or after the write count averaging process is completed, the access arbitration circuit ARB checks whether a read request is input from the NOR interface NOR IF (Step 16). Is input, the operation in response to the erase request from the NAND interface NAND IF1 is temporarily stopped, and the read operation shown in FIG. 20 is preferentially performed (Step 17). When this read operation is completed, the erase address NEADD is finally cleared (Step 18).
<Read instruction from NAND IF1>
FIG. 17 is a flowchart illustrating an example of access arbitration and read operation of the memory module MSM when a read request is generated from the NAND interface NAND IF1 and further a read request is generated from the NOR interface.

When a read command and read address NRADD are input from the NAND interface NAND IF1 (Step 1),
Next, the access arbitration circuit ARB checks whether a read request is input from the NOR interface NOR IF (Step 2). If a read request is input, the operation according to the read request from the NAND interface NAND IF1 is temporarily stopped and prioritized. Specifically, the read operation shown in FIG. 20 is performed (Step 3). When this read operation is completed, the operation returns to the operation in response to the read request from the NAND interface NAND IF1, and the data read data buffer DREG is transferred from the memory cell array MARY (Step 4).

  Next, the access arbitration circuit ARB checks whether a read request is input from the NOR interface NOR IF (Step 5). If a read request is input, the operation according to the read request from the NAND interface NAND IF1 is temporarily stopped and prioritized. Specifically, the read operation shown in FIG. 20 is performed (Step 6). When this read operation is completed, the operation returns to the operation in response to the read request from the NAND interface NAND IF1, and the data held in the data buffer DREG is transferred to the buffer circuit BUF (step 7).

While the data is transferred to the buffer circuit BUF, error detection is performed by the error detection and correction circuit ECC (Step 8). Next, it is checked whether or not there is an error detection / correction circuit ECC error (Step 9). If there is no error, the data transferred to the buffer circuit BUF is transferred to the read buffer RBUF (Step 11). If there is an error, the error detection and correction circuit ECC corrects the error (Step 10) and then transfers it to the read buffer RBUF (Step 11). Finally, the data held in the read buffer RBUF is read to the NOR interface NOR IF (Step 12).
<L2Cache configuration for cache lock>
FIG. 18 shows an example of the configuration of the cache memory L2Cache necessary for performing the cache lock operation.

  Address Add6, Address Add2, and Address Add0 are equivalent to the addresses described in FIG.

  Although the configuration of the cache memory L2Cache is not particularly limited, it is composed of an address array AddressArray and a data array DataArray, the capacity of the data array DataArray is 256 Mbytes, the line size is 512 bytes, and the index address Index2 is from 0 to 511, The set associative is a 4-way set associative. The address array AddressArray is composed of a tag address Tag2, a valid bit vld, a dirty bit dt, and a cache lock flag lck, and the data array DataArray holds 512 bytes of data for one index address.

  The value of the cache lock flag lck of the tag address existing within the cache lock address range is 1, and the value of the cache lock flag lck of the tag address existing outside the cache lock address range is 0.

  Data whose cache lock flag lck is 1 is data that is not subject to data update, and will not be evicted from the cache memory L2Cache unless the cache lock flag lck becomes 0.

Data whose cache lock flag lck is 0 is data to be updated, and may be evicted from the cache memory L2Cache.
<Release cache lock flag>
FIG. 21 is a flowchart illustrating an example of cache lock release. When a cache lock release command is written to the cache lock area setting register CaLockReg from the NOR interface NOR IF (Step 1), the cache memory L2Cache sets all its cache lock flags lck to 0 (Low) (Step 2) and sets the cache lock area The cache lock range address set in the register CaLockReg is invalidated (Step 3), and finally the cache lock release completion signal indicating that the cache memory L2Cache cache lock release is completed is set to High (Step 4). Through the above procedure, the fact that the address range for performing the cache lock has become invalid is input to the memory address management circuit MMG.
<Read operation of cache lock word>
FIG. 20 is a flowchart for explaining an example of the operation of the cache memories L2Cache, PL2A, and PL2B when the cache lock is set.

  When a read request and an address RADD are input from the NOR interface NOR IF to the memory module MSM (Step 1), the memory address management circuit MMG checks whether the address RADD is within an address range for performing cache lock (Step 2). If the address RADD is out of the address range for performing the cache lock, the process proceeds to Step 26. Details of the operation from Step 26 are shown in FIG.

  If the address RADD is within the address range where the cache lock is performed, hit determination is performed in the cache memory L2Cache (Step 3).

  If the cache memory L2Cache is hit, check whether the cache lock flag corresponding to the hit tag address is High (Step 4). If the cache lock flag is High, output data from the cache memory L2Cache. (Step 24). If the cache lock flag is low, the cache lock flag is set to high (Step 5), and data is output from the cache memory L2Cache (Step 24).

  If there is a miss in the cache memory L2Cache, a hit determination is performed on the cache memories PL2A and PL2B (Step 6). If a hit occurs, the data in the cache memories PL2A and PL2B is transferred to the cache memory L2Cache and updated (Step 12). When updating the data, the data for which the cache lock flag is Low is updated by the LRU method. Next, the cache lock flag is set to High (Step 13), the cache memories PL2A and PL2B are invalidated (Step 14), and data is output from the cache memories PL2A and PL2B (Step 24).

  If there is a miss in the cache memories PL2A and PL2B, check whether the cache memories PL2A and PL2B are valid (Step 7). If they are valid, transfer the data currently in the cache memories PL2A and PL2B to the cache memory L2Cache. And update (Step 8). When updating the data, the data for which the cache lock flag is Low is updated by the LRU method.

  Next, the cache lock flag is set to High (Step 9), and the cache memories PL2A and PL2B are invalidated (Step 10). Next, the requested data is transferred from the flash memory FLASH_CHIP to the cache memory PL2A (Step 11), and the data in the cache memory PL2A is transferred to the cache memory L2Cache and updated (Step 15).

When updating the data, the data for which the cache lock flag is Low is updated by the LRU method. Next, the cache lock flag is set to High (Step 16), the cache memory PL2A is invalidated (Step 17), and data is output from the cache memory PL2A (Step 24). At the same time, the data of the next page is transferred from the flash memory FLASH_CHIP to the cache memory PL2B by the prefetch function (Step 18), and then it is checked whether it is within the address range for performing the cache lock (Step 19). If it is within the address range where the cache lock is performed, the data in the cache memory PL2B is transferred to the cache memory L2Cache and updated (Step 20). When updating the data, the data for which the cache lock flag is Low is updated by the LRU method. Next, the cache lock flag is set to High (Step 21), and the cache memory PL2B is invalidated (Step 22). If it is out of the address range for performing the cache lock, the cache memory PL2B is validated (Step 23).
<Cache lock read operation>
FIG. 21 shows an example of the operation of the cache memories L2Cache, PL2A, and PL2B when the cache lock is set and the read request input to the memory module MSM from the NOR interface NOR IF and the address RADD are outside the address range for performing the cache lock. It is a flowchart explaining about.

  If the address RADD is out of the address range where cache lock is performed (Step 25), hit determination is performed in the cache memory L2Cache (Step 26).

  When the cache memory L2Cache is hit, it is checked whether the cache lock flag corresponding to the hit tag address is Low (Step 27). If the cache lock flag is Low, data is output from the cache memory L2Cache. (Step 41). If the cache lock flag is high, an error is output (Step 28).

  If the cache memory L2Cache is missed, a hit determination is performed on the cache memories PL2A and PL2B (Step 29). If a hit occurs, data is output from the cache memory PL2A or PL2B (Step 41).

  If there is a miss in the cache memories PL2A and PL2B, check whether the cache memories PL2A and PL2B are valid (Step 30). If they are valid, the data currently in the cache memories PL2A and PL2B is transferred to the cache memory L2Cache. And update (Step 31). When updating the data, the data for which the cache lock flag is Low is updated by the LRU method.

  Next, the cache memories PL2A and PL2B are invalidated (Step 32). Next, the request data is transferred from the flash memory FLASH_CHIP to the cache memory PL2A (Step 33), and the data in the cache memory PL2A is validated (Step 34). Next, data is output from the cache memory PL2A (Step 41).

  At the same time as Step 41, the data of the next page is transferred from the flash memory FLASH_CHIP to the cache memory PL2B by the prefetch function (Step 35), and then it is checked whether it is within the address range for performing the cache lock (Step 36). If it is within the address range for performing the cache lock, the data of the cache memory PL2B is transferred to the cache memory L2Cache and updated (Step 37). When updating the data, the data for which the cache lock flag is Low is updated by the LRU method. Next, the cache lock flag is set to High (Step 38), and the cache memory PL2B is invalidated (Step 39). If it is out of the address range for performing the cache lock, the cache memory PL2B is validated (Step 40).

<FLASH with multiple memory banks>
FIG. 22 shows a second embodiment in which a flash memory FLASH_CHIP 22 having a plurality of memory banks is applied to the present invention.

  2 shows a memory system including an information processing device CPU_CHIP, a memory module MSM22, and a dynamic random access memory DRAM_CHIP.

  The memory module MSM22 includes a flash memory FLASH_CHIP22 and a control circuit CT_CHIP.

  The information processing device CPU_CHIP, the control circuit CT_CHIP, and the dynamic random access memory DRAM_CHIP are the same as those shown in FIG.

  The control circuit CT_CHIP includes a NOR interface circuit NRIF that receives read and write requests from the NOR interface (NOR IF), a NAND interface circuit NDIF that receives read and write requests from the NAND interface (NAND IF), a register block REG, and an address conversion circuit It comprises DSTR, cache memory L2Cache, PL2A, PL2B, prefetch control circuit PREF, flash control circuit FLCT, buffer circuit BFBK, and flash error control circuit FLSP.

  NOR interface (NOR IF), NOR interface circuit NRIF, NAND interface (NAND IF), NAND interface circuit NDIF, SDRAM interface (SDRAM_IF), register block REG, address conversion circuit DSTR, cache memory L2Cache, PL2A, PL2B, prefetch The control circuit PREF, the flash control circuit FLCTP, the flash control circuit FLCT, the buffer circuit BFBK, and the flash error control circuit FLSP are the same as those shown in FIG.

  The flash memory FLASH_CHIP 22 includes a control circuit FCNT22, data buffers DREG0 to DREG3, and memory banks BANK0 to BANK3.

  Although not particularly limited, regarding data transfer between the data buffer and the memory bank, data transfer between the memory bank BANK0 and the data buffer DREG0, data transfer between the memory bank BANK1 and the data buffer DREG1, and between the memory bank BANK2 and the data buffer DREG2. Data transfer and data transfer between the memory bank BANK3 and the data buffer DREG3 can be performed independently.

  Although not particularly limited, the storage capacity of one memory bank is 64 Mbytes, and the total storage capacity of the four memory banks is 256 Mbytes.

  Although not particularly limited, the data size of one data buffer is 2 kbytes, and the total data size of the four data buffers is 8 kbytes.

  The control circuit FCNT22 is a circuit that controls data transfer between the data buffers DREG0 to DREG3 and the memory banks BANK0 to BANK3 according to read and write commands from the control circuit CT_CHIP.

  The flash memory FLASH_CHIP 22 can operate with either an AND interface or a NAND interface. Here, the operation of the flash memory FLASH_CHIP 22 will be described by taking a NAND interface as an example.

  The control circuit FCNT22 is a circuit that controls data transfer between the data buffers DREG0 to DREG3 and the memory banks BANK0 to BANK3 according to read and write commands from the NAND interface NAND IF3 of the control circuit CT_CHIP.

  When a read request and a read address are input to the control circuit FCNT22 from the control circuit CT_CHIP through the NAND interface NAND IF22, the data in the memory bank designated by the read address is a data buffer corresponding to data transfer from this memory bank. Forwarded to Next, the data is transferred to the control circuit CT_CHIP through the NAND interface NAND IF3.

  With the read address, you can specify all banks at once, specify two banks, or specify each one independently, so for example when reading data from the data buffer DREG0, By performing data transfer from the memory bank BANK1 to the data buffer DREG1 in the background, the data transfer time from the memory bank to the data buffer is concealed, and the data transfer speed can be increased.

  Further, since the data transferred to the data buffer is held as it is, it can be used as an 8 Kbyte L3 cache, and the data transfer can be further speeded up.

  Thus, the present invention can be realized even when the flash memory FLASH_CHIP 22 having a plurality of memory banks is applied.

  Prior to the present application, the inventors of the present application examined the reliability of a mobile phone and a memory module in which a static random access memory SRAM and a flash memory used therein are mounted in one package.

  Soft error is a phenomenon in which the data stored in the memory array is destroyed when alpha rays emitted from radioactive materials such as uranium in the semiconductor encapsulant are incident on the memory array of the static random access memory SRAM. This is a factor that degrades the reliability of the static random access memory SRAM. In addition, since the area increases as the storage capacity of the static random access memory SRAM increases, the probability that α rays enter the static random access memory SRAM increases, and the reliability is further deteriorated.

  Volatile memory such as dynamic random access memory DRAM and static random access memory SRAM degrades reliability due to alpha rays, but non-volatile memory such as flash memory is not affected by alpha rays due to its memory array structure. I found out.

  Accordingly, one of the objects of the present invention is to provide a memory system including a highly reliable ROM and RAM.

  FIG. 23 shows a third embodiment of the present invention. This is an embodiment showing a memory system including an information processing device CPU_CHIP23, a memory module MSM23, and a dynamic random access memory DRAM_CHIP.

  The memory module MSM23 includes a flash memory FLASH_CHIP and a control circuit CT_CHIP23.

  The information processing device CPU_CHIP, the flash memory FLASH_CHIP, and the dynamic random access memory DRAM_CHIP are respectively equivalent to those shown in FIG.

  The control circuit CT_CHIP23 includes a NOR interface circuit NRIF that receives read and write requests from the NOR interface (NOR IF), a NAND interface circuit NDIF that receives read and write requests from the NAND interface (NAND IF), a register block REG, and an address conversion circuit It comprises a DSTR, a parity check circuit PRCH, a cache memory L2CacheP, PL2AP, PL2BP, a prefetch control circuit PREF, a flash control circuit FLCTP, a buffer circuit BFBK, and a flash error control circuit FLSP.

  NOR interface (NOR IF), NOR interface circuit NRIF, NAND interface (NAND IF), NAND interface circuit NDIF, SDRAM interface (SDRAM_IF), register block REG, address conversion circuit DSTR, prefetch control circuit PREF, flash control circuit FLCTP, The buffer circuit BFBK and the flash error control circuit FLSP are the same as those shown in FIG.

  The parity check circuit PRCH is a circuit that performs a parity check based on the data read from the cache memory L2CacheP and the parity data.

  The parity check includes an even parity check and an odd parity check, and the parity check circuit PRCH can perform both parity checks. Here, an even parity check will be described as an example.

  The cache memories L2CacheP, PL2AP, and PL2BP are cache memories having parity data, and other configurations and operations are the same as those described in FIG.

The flash control circuit FLCTP is a control circuit having a parity data generation circuit, and other configurations and operations are the same as those described in FIG.
<Description of L2CacheP operation>
An example of the operation when reading data from the cache memory L2Cahce will be described.

  When the cache memory L2Cache is hit, the data and parity data are directly read from the cache memory L2CahceP, and the parity check is performed by the parity check circuit PRCH.

  Although there is no particular limitation, in the even parity check, it is checked whether the number of 8-bit data and the corresponding parity bit High is an even number, and if it is an even number, the data is read correctly. In the case of an odd number, it is determined that an error has occurred in the read data.

  If the parity check circuit PRCH determines that the data has been read correctly, the data is output from the NOR interface NOR IF to the information processing device CPU_CHIP through the NOR interface circuit NRIF.

  When it is determined that the data in the cache memory L2Cache is destroyed due to a soft error and the read data has an error, the flash control circuit FLCTP reads the base data of the data in which the error occurred from the flash memory FLASH_CHIP and flashes it. Transfer to error control circuit FLSP.

  The prefetch control circuit PREF transfers the data held in the cache memories PL2AP and PL2PB to the cache memory L2CacheP while the data transfer to the flash control circuit FLSP is occurring in the data buffer DREG in the flash memory FLASH_CHIP, Update the cache memory L2Cache. In this update, the parity data is updated simultaneously with the data.

  The flash error control circuit FLSP performs error detection and correction on the data transferred from the flash memory FLASH_CHIP. If there is no error in the circuit ECC, this data is transferred to the cache memory PL2AP. If there is an error, the error is corrected. Then, transfer to the cache memory PL2AP. In addition, the flash error control circuit FLSP generates 1-bit parity data for 8-bit data, and transfers the parity data to the cache memory at the same time. Transfer to PL2AP. Although there is no particular limitation, in the case of even parity, if there are an odd number of high bits among 8-bit data, the parity data becomes high and the high bits are even. Also, if there is an even number of high bits among the 8-bit data, the parity data becomes low and the high bits are even.

  The data transferred to the cache memory PL2AP is subjected to a parity check by the parity check circuit PRCH. Although there is no particular limitation, in the even parity check, it is checked whether the number of 8-bit data and the corresponding parity bit High is an even number, and if it is an even number, the data is read correctly. In the case of an odd number, it is determined that an error has occurred in the read data.

  If the parity check circuit PRCH determines that the data has been read correctly, the data is output from the NOR interface NOR IF to the information processing device CPU_CHIP through the NOR interface circuit NRIF.

  If it is determined that an error has occurred in the read data, the data is read from the flash memory again.

  As described above, when it is determined that the data in the cache memory L2Cache is destroyed due to the soft error and the data read by the parity check circuit PRCH has an error, the data is read out from the flash memory FLASH_CHIP to Reliability deterioration can be prevented.

<DRAM in MCP>
FIG. 24 shows another embodiment to which the present invention is applied. 2 shows a memory system composed of an information processing device CPU_CHIP and a memory module MSM24.

  The memory module MSM24 includes a flash memory FLASH_CHIP, a control circuit CT_CHIP, and a dynamic random access memory DRAM_CHIP.

  Although not particularly limited, a typical flash memory used as the flash memory FLASH_CHIP is a large-capacity flash memory equipped with a NAND interface, and in this embodiment, a large-capacity flash memory equipped with an AND interface is applied. This is an example.

  There are various types of dynamic random access memory DRAM_CHIP, such as EDO (Extended Data Out), SDRAM (Synchronous DRAM), and DDR (Double Data Rate) due to differences in internal configuration and interface. Any DRAM can be used for the memory module MSM24. In the present embodiment, an example of SDRAM will be described.

  The control circuit CT_CHIP is equipped with a NOR interface NOR IF and a NAND interface NAND IF, and controls data transfer between the flash memory FLASH_CHIP and the information processing CPU_CHIP, which is shown in FIG. Is equivalent to

  The dynamic random access memory DRAM_CHIP is mounted on the memory module MSM24, and is configured to directly transfer data with the information processing device CPU_CHIP through the SDRAM interface SDRAM IF. Therefore, the NOR interface, the NAND interface, and the SDRAM interface The memory module MSM24 equipped with can implement the present invention shown in FIG.

  Thus, by incorporating the dynamic random access memory DRAM_CHIP in the memory module, the apparatus can be reduced in size and the present invention can be realized.

<Hard disk>
FIG. 25 shows a fifth embodiment to which the present invention is applied.

2 shows a memory system including an information processing device CPU_CHIP, a memory module MSM25, and a dynamic random access memory DRAM_CHIP.
The memory module MSM25 includes a hard disk HDisk and a control circuit CT_CHIP25.

  The information processing device CPU_CHIP and the dynamic random access memory DRAM_CHIP are equivalent to those shown in FIG.

  The present embodiment is an example in which a hard disk HDisk is applied instead of a flash memory.

  The hard disk HDisk is a memory that can realize a larger capacity and lower cost than the flash memory FLASH_CHIP. Interfaces for reading data from the hard disk HDisk include IDE, ATA, and UltraATA. In this embodiment, UltraATA is taken as an example, but it goes without saying that IDE, ATA, etc. can be applied.

  When it comes to data read units, address management methods, and error detection and correction methods, the flash memory takes over the data read units, address management methods, and error detection and correction methods that were originally realized on hard disks. A hard disk HDisk can be used instead of the flash memory.

  The control circuit CT_CHIP25 is a NOR interface circuit NRIF that receives read and write requests from the NOR interface (NOR IF), a NAND interface circuit NDIF that receives read and write requests from the NAND interface (NAND IF), a register block REG, and an address conversion circuit It comprises DSTR, cache memory L2Cache, PL2A, PL2B, prefetch control circuit PREF, hard disk control circuit FLCT25, buffer circuit BFBK, and flash error control circuit FLSP.

  NOR interface (NOR IF), NOR interface circuit NRIF, NAND interface (NAND IF), NAND interface circuit NDIF, SDRAM interface (SDRAM_IF), register block REG, address conversion circuit DSTR, cache memory L2Cache, PL2A and PL2B, prefetch control The circuit PREF, the buffer circuit BFBK, and the flash error control circuit FLSP have the same configuration and operation as those shown in FIG.

  The hard disk control circuit FLCT25 includes a clock control circuit OSC, a memory address management circuit MMG, an access arbitration circuit ARB, and a control circuit HRWCL.

  The configuration and operation of the clock control circuit OSC, the memory address management circuit MMG, and the access arbitration circuit ARB are the same as those shown in FIG. The control circuit HRWCL is a control circuit equipped with an UltraATA interface for reading data from the U hard disk HDisk to the control circuit RWCL shown in FIG. 1, and the operation after reading the data from the hard disk HDisk is shown in FIG. This is equivalent to the control circuit RWCL shown. Therefore, it can be seen that the present invention can be realized by applying the hard disk HDisk.

  As described above, a large capacity and low cost memory system can be realized by using the hard disk HDisk.

  FIG. 26 shows a sixth embodiment of the present invention. FIG. 26A is a top view, and FIG. 26B is a cross-sectional view of a portion along the line A-A ′ shown in the top view.

In the multichip module according to the present embodiment, CHIPM1 and CHIPM2 are mounted on a substrate (for example, a printed circuit board made of a glass epoxy substrate) PCB mounted on a device by a ball grid array (BGA). CHIPM1 is a nonvolatile memory, and CHIPM2 is a DRAM.

  With this multichip module, the memory module MSM shown in FIG. 1 and the memory module MSM22 shown in FIG. 22 can be integrated in one sealing body.

  The bonding pads on CHIPM1 and the substrate PCB are connected by bonding wires (PATH2), and the bonding pads on CHIPM2 and the substrate PCB are connected by bonding wires (PATH1). CHIPM1 and CHIPM2 are connected by a bonding wire (PATH3).

  The upper surface of the substrate PCB on which the chip is mounted is resin-molded to protect each chip and connection wiring. Further, a metal, ceramic, or resin cover (COVER) may be used from above.

  In this embodiment, since the bare chip is directly mounted on the printed circuit board PCB, a memory module with a small mounting area can be configured. Further, since each chip can be stacked, the wiring length between the chip and the substrate PCB can be shortened, and the mounting area can be reduced. By unifying the wiring between chips and the wiring between each chip and the substrate by a bonding wire method, a memory module can be manufactured with a small number of processes.

  Furthermore, by directly connecting the chips with bonding wires, the number of bonding pads and bonding wires on the substrate can be reduced, and the memory module can be manufactured with a small number of processes. When a resin cover is used, a stronger memory module can be configured. When a ceramic or metal cover is used, a memory module excellent in heat dissipation and shielding effect in addition to strength can be configured.

  FIG. 27 shows a sixth embodiment of the present invention. FIG. 27A is a top view, and FIG. 27B is a cross-sectional view of a portion along the line A-A ′ shown in the top view.

  In the multichip module of the present embodiment, CHIPM1, CHIPM2, and CHIPM3 are mounted on a board (for example, a printed circuit board made of a glass epoxy board) PCB that is mounted on a device by a ball grid array (BGA). CHIPM1 is a nonvolatile memory, and CHIP2M is a DRAM. The CHIP3M is an information processing apparatus including a central processing unit CPU, a NOR controller NRC, and a DRAM controller SDC, or a control circuit that controls data transfer of CHIP1M and CHIP2M.

  With this multichip module, the memory module MSM24 shown in FIG. 24 can be integrated in one sealing body.

  The bonding pads on CHIPM1 and the substrate PCB are connected by bonding wires (PATH2), and the bonding pads on CHIPM2 and the substrate PCB are connected by bonding wires (PATH1). CHIPM1 and CHIPM2 are connected by a bonding wire (PATH3). A ball grid array is used for mounting and wiring of CHIP3M.

  In this mounting method, since three chips can be stacked, the mounting area can be kept small. In addition, bonding between the CHIPM3 and the substrate is not required, and the number of bonding wires can be reduced, so that the number of assembly steps can be reduced and a more reliable multichip module can be realized.

  FIG. 27 shows an eighth embodiment of a multichip module according to the present invention. FIG. 27A is a top view, and FIG. 27B is a cross-sectional view of a portion along the line A-A ′ shown in the top view.

  FIG. 28 shows a seventh embodiment of a multichip module according to the present invention. FIG. 28A is a top view, and FIG. 28B is a cross-sectional view of a portion along the line A-A ′ shown in the top view.

  In the memory module of the present embodiment, CHIPM1, CHIPM2, CHIPM3, and CHIPM4 are mounted on a board (for example, a printed circuit board made of a glass epoxy board) PCB that is mounted on a device by a ball grid array (BGA). CHIPM1 is a nonvolatile memory, and CHIPM3 is a DRAM. CHIPM2 is a control circuit that controls data transfer between CHIPM1 and CHIPM2, and CHIPM4 is an information processing device that includes a central processing unit CPU, a NOR controller NRC, and a DRAM controller SDC.

  In this mounting method, the memory system shown in FIG. 1, the memory system module shown in FIG. 22, the memory system shown in FIG. 23, and the memory system shown in FIG. 24 can be integrated into one sealing body.

  The bonding pad on CHIPM1 and PCB is connected by bonding wire (PATH2), the bonding pad on CHIPM2 and PCB is connected by bonding wire (PATH4), and the bonding pad on CHIPM3 and PCB is bonding wire (PATH1). Connected with.

  CHIPM1 and CHIPM3 are connected by a bonding wire (PATH3), and CHIPM2 and CHIPM3 are connected by a bonding wire (PATH5).

  Ball grid array (BGA) is used for mounting and wiring of CHIPM4.

  In this mounting method, since the bare chip is directly mounted on the printed circuit board PCB, a memory module having a small mounting area can be configured. Further, since the chips can be arranged close to each other, the interchip wiring length can be shortened.

  By directly connecting the chips with bonding wires, the number of bonding pads and bonding wires on the substrate can be reduced, and the memory module can be manufactured with a small number of processes.

  Further, since bonding between the CHIPM 4 and the substrate is not required, and the number of bonding wires can be reduced, the number of assembling steps can be reduced, and a more reliable multichip module can be realized.

  FIG. 29 shows a ninth embodiment of the memory system according to the present invention. FIG. 29A is a top view, and FIG. 29B is a cross-sectional view of a portion along the line A-A ′ shown in the top view.

  In the memory module of the present embodiment, CHIPM1, CHIPM2, and CHIPM3 are mounted on a board (for example, a printed circuit board made of a glass epoxy board) PCB that is mounted on a device by a ball grid array (BGA). CHIPM1 is a nonvolatile memory, and CHIPM2 and CHIPM3 are DRAMs. By unifying the wiring between chips and the wiring between each chip and the substrate by a bonding wire method, a memory module can be manufactured with a small number of processes. In this mounting method, the module MSM24 shown in FIG. 24 can be integrated in one sealing body.

  Bonding pads on CHIPM1 and PCB are connected by bonding wires (PATH2), bonding pads on CHIPM2 and PCB are connected by bonding wires (PATH1), and bonding pads on CHIPM3 and PCB are bonding wires (PATH3). Connected with.

  In this embodiment, since the bare chip is directly mounted on the printed circuit board PCB, a memory module with a small mounting area can be configured. Further, since the chips can be arranged close to each other, the interchip wiring length can be shortened.

  By unifying the wiring between each chip and the substrate by the bonding wire method, the memory module can be manufactured with a small number of processes.

  FIG. 30 shows a ninth embodiment of the memory system according to the present invention. FIG. 30A is a top view, and FIG. 30B is a cross-sectional view of a portion along the line A-A ′ shown in the top view.

  In the memory module of the present embodiment, CHIPM1, CHIPM2, CHIPM3, and CHIPM4 are mounted on a board (for example, a printed circuit board made of a glass epoxy board) PCB that is mounted on a device by a ball grid array (BGA). CHIPM1 is a nonvolatile memory, and CHIPM2 and CHIPM3 are DRAMs. The CHIPM 4 is an information processing apparatus including a central processing unit CPU, a NOR controller NRC, and a DRAM controller SDC.

  In this mounting method, the memory system shown in FIG. 1, the memory system shown in FIG. 22, the memory system shown in FIG. 23, and the memory system shown in FIG. 24 can be integrated into one sealed body.

  Bonding pads on CHIPM1 and PCB are connected by bonding wires (PATH2), bonding pads on CHIPM2 and PCB are connected by bonding wires (PATH1), and bonding pads on CHIPM3 and PCB are bonding wires (PATH3). Connected with. Ball grid array (BGA) is used for mounting and wiring of CHIPM4.

  In this embodiment, since the bare chip is directly mounted on the printed circuit board PCB, a memory module having a small mounting area can be configured. Further, since the chips can be arranged close to each other, the interchip wiring length can be shortened. Bonding between the CHIPM 4 and the substrate is not necessary, and the number of bonding wires can be reduced, so that the number of assembly steps can be reduced and a more reliable multichip module can be realized.

  FIG. 31 shows a tenth embodiment of a cellular phone using a memory module according to the present invention. Mobile phone includes antenna ANT, radio block RF, baseband block BB, audio codec block SP, speaker SK, microphone MK, processor CPU, dynamic random access memory DRAM, liquid crystal display LCD, keyboard KEY and memory module MSM of the present invention Consists of.

  The operation during a call will be described.

  The sound received through the antenna ANT is amplified by the radio block RF and input to the baseband block BB. The baseband block BB converts an audio analog signal into a digital signal, performs error correction and decoding processing, and outputs it to the audio codec block SP. When the audio codec block converts the digital signal into an analog signal and outputs it to the speaker SK, the other party's voice can be heard from the speaker.

  An operation when a series of operations of accessing a homepage on the Internet from a mobile phone, downloading music data, listening to it, and storing the music data downloaded last will be described.

  The memory module MSM stores basic programs, application programs (email, Web browser, music playback program, operation playback program, game program, etc.), music data, still image data, video data, and the like.

  When the activation of the Web browser is instructed from the keyboard, the Web browser program stored in the FLASH in the memory module MSM is transferred to the cache memory in the same memory module. When the transfer to the cache is completed, the processor CPU executes the Web browser program in the DRAM, and the Web browser is displayed on the liquid crystal display LCD. When the user accesses a desired homepage and instructs the keyboard KEY to download the favorite music data, the music data is received through the antenna ANT, amplified by the radio block RF, and input to the baseband block BB. The baseband block BB converts music data that is an analog signal into a digital signal, and performs error correction and decoding processing. The music data converted into a digital signal is once held in the DRAM, and finally transferred to and stored in the FLASH of the memory module MSM.

  Next, when activation of the music playback program is instructed from the keyboard KEY, the music playback program stored in the FLASH in the memory module MSM is transferred to the cache memory in the same memory module. When the transfer to the cache memory is completed, the processor CPU executes the sound reproduction program in the cache memory, and the music reproduction program is displayed on the liquid crystal display LCD.

  When the instruction to listen to the music data downloaded to the FLASH is given from the keyboard KEY, the processor CPU executes the music playback program, processes the music data stored in the FLASH, and finally listens to the music from the speaker SK. Come.

  At this time, since the memory module of the present invention uses a large-capacity cache memory, the Web browser and the music playback program are held in the cache memory, and both programs are simultaneously executed by the CPU. Furthermore, an e-mail program can be started, and the e-mail program and mail can be sent and received simultaneously.

  Even if the Web browser is stopped, it is retained in the cache memory in the memory module, so it can be started immediately upon restart.

  When a power-off instruction is input from the keyboard, the memory module operates only the cache memory, holds a minimum amount of data, and extremely reduces power consumption.

  As described above, by using the memory module according to the present invention, a large amount of mail, music playback, application programs, music data, still image data, moving image data, and the like can be stored, and a plurality of programs can be simultaneously executed.

  FIG. 32 shows a twelfth embodiment of a cellular phone using a memory system according to the present invention. Cellular phone includes antenna ANT, radio block RF, baseband block BB, audio codec block SP, speaker SK, microphone MK, processor CPU, liquid crystal display LCD, keyboard KEY and processor CPU, dynamic random access memory DRAM, The memory system SLP of the present invention in which the memory module MSM is integrated in one sealing body is configured.

  By using the memory system SL of the present invention, the number of parts can be reduced, so that the cost can be reduced, the reliability of the mobile phone is improved, the mounting area of the parts constituting the mobile phone can be reduced, and the mobile phone can be reduced in size. Can be made.

  As described above, the main effects obtained by the invention disclosed in this specification are as follows.

  First, by automatically transferring the boot program from the FLASH to the cache memory when the power is turned on, the portable device can read the boot program of the cache memory and quickly start up.

  Secondly, by automatically transferring a program required at the time of power-on from the FLASH to the cache memory, the portable device can be immediately accessed when the portable device is started up, so that the performance of the portable device can be improved.

  Thirdly, in the memory module to which the memory system according to the present invention is applied, the FLASH data is transferred and held in the cache memory, and the portable device can directly access the cache memory, thereby realizing high-speed data transfer.

  Fourth, the memory module to which the memory system according to the present invention is applied has a data pre-read function, and the data to be used next is transferred to the cache memory in advance to improve the hit rate to the cache memory. Data transfer can be speeded up.

  Fifth, in the memory module to which the memory system according to the present invention is applied, the data register in the flash memory can be used as a cache memory, and the hit rate is improved by effectively increasing the capacity of the cache memory. Data transfer can be performed at high speed.

  Sixth, in the memory module to which the memory system according to the present invention is applied, the hit rate is improved and the data transfer is performed at high speed by performing address conversion, distributing the index address of the cache memory, and increasing the utilization rate of the cache memory. Can be

  Seventh, since data can be read from the cache memory even when writing to the flash memory is being performed, the speed of the portable device can be increased.

  Eighth, synchronous and asynchronous interfaces, address conversion methods, cache areas and non-cache areas, cache lock areas and non-cache lock areas, write count averaging processing areas and non-write count averaging processing areas, write protect areas, and Non-write protected areas can be set independently, and can be freely selected by the user according to the system.

  Ninth, in this memory module, when reading from FALSH, error detection and correction are performed, and when writing, replacement processing is performed for defective addresses that were not written correctly. Can be made fast and reliable.

  Tenth, when reading data from the cache memory inside this memory module, error detection is performed, and in the case of an error, data is read from the flash memory, so that processing can be performed at high speed and reliability can be maintained. it can.

  Eleventh, since the write averaging of the flash memory is performed inside the present memory module, the processing can be performed at high speed and the reliability can be maintained.

  12th: Write the boot program and automatic transfer area specification data to the FLASH initial program area through the NOR interface, NAND interface and AND interface, which are general interfaces, and change the boot method and data transfer area immediately after power-on. Therefore, it is possible to flexibly respond to the demands of portable devices and to achieve high functionality.

  13thly, a system memory module with a small mounting area can be provided by mounting a plurality of semiconductor chips on one sealing body.

1 is a configuration diagram of a memory system to which the present invention is applied. Explanatory drawing which shows an example of the address map of the memory system to which this invention is applied. Explanatory drawing which shows an example of the register block of the memory system to which this invention is applied. The figure which shows an example of the operation | movement at the time of power activation of the memory system to which this invention is applied. The figure which shows an example of the address translation and cache memory of the memory system to which this invention is applied. The figure which shows an example of the address translation and cache memory of the memory system to which this invention is applied. The figure which shows an example of the address conversion of the memory system to which this invention is applied. The figure which shows an example of the cache memory of the memory system to which this invention is applied. The figure which shows an example of the data update of the cache memory of the memory system to which this invention is applied. The figure which shows an example of the data update of the cache memory of the memory system to which this invention is applied. The figure which shows an example of the setting method to the register block of the memory system to which this invention is applied. The figure which shows an example of the setting method to the register block of the memory system to which this invention is applied. The figure which shows an example of the setting method to the register block of the memory system to which this invention is applied. 5 is a flowchart showing an example of a data read operation flow of the memory system to which the present invention is applied. 5 is a flowchart showing an example of a data write operation flow of the memory system to which the present invention is applied. 5 is a flowchart showing an example of a data erasing operation flow of the memory system to which the present invention is applied. 6 is a flowchart showing an example of a read operation flow of a memory system to which the present invention is applied. The figure which shows an example of the cache memory of the memory system to which this invention is applied. The figure which shows an example of the cache lock release method of the memory system to which this invention is applied. 5 is a flowchart showing an example of a data read operation flow of the memory system to which the present invention is applied. 5 is a flowchart showing an example of a data read operation flow of the memory system to which the present invention is applied. 1 is a configuration diagram of a memory system to which the present invention is applied. 1 is a configuration diagram of a memory system to which the present invention is applied. 1 is a configuration diagram of a memory system to which the present invention is applied. 1 is a configuration diagram of a memory system to which the present invention is applied. The figure which shows an example of the mounting form of the memory system by this invention. The figure which shows an example of the mounting form of the memory system by this invention. The figure which shows an example of the mounting form of the memory system by this invention. The figure which shows an example of the mounting form of the memory system by this invention. The figure which shows an example of the mounting form of the memory system by this invention. The block diagram which shows the structural example of the mobile telephone using the memory system by this invention. The block diagram which shows the structural example of the mobile telephone using the memory system by this invention. The block diagram which shows the example of a conventional memory structure utilized for the mobile telephone.

Explanation of symbols

CPU_CHIP… Information processing device, CPU… Information processing device, MSM… Memory module, NRC… NOR flash controller, NDC… NAND flash controller, SDC… DRAM controller, NOR IF… NOR interface, NAND IF1, NAND_IF2… NAND interface, SDRAM IF ... SDRAM interface, NRIF ... NOR interface circuit, NDIF ... NAND interface circuit, CT_CHIP ... control circuit, REG ... register block
DSTR ... Address conversion circuit, L2Cache ... Cache memory, PL2A ... Cache memory, PL2B ... Cache memory, PREF ... Prefetch control circuit, PL2Hit ... Hit decision circuit, L3Hit ... Hit decision circuit, PRECT ... Prefetch instruction circuit, FLCT ... Flash control circuit , OSC ... clock control circuit, MMG ... memory address management circuit, ARB ... access arbitration circuit, RWCL ... control circuit, FLSP ... flash error control circuit, ECC ... error detection and correction circuit, BUF ... buffer circuit, REF ... alternative processing circuit, WLV: Write number averaging circuit,
FLASH_CHIP ... Flash memory, FCNT ... Control circuit, DREG ... Data buffer, MARY ... Memory cell array, DRAM_CHIP ... Dynamic random access memory, CLK ... Clock signal, Wait ... Wait signal, PCMP ... Initial operation complete signal, MSM22 ... Memory module, FLASH_CHIP22 ... flash memory, FCNT22 ... control circuit, DREG0, 1, 2, 3 ... data buffer, BANK0, 1, 2, 3 ... memory van, NAND IF22 ... NAND interface, MSM23 ... memory module, CT_CHIP23 ... control circuit,
FLCTP ... Flash control circuit, L2CacheP, PL2AP, PL2BP ... Cache memory, MSM24 ... Memory module, MSM25 ... Memory module, FLCT25 ... Flash control circuit, CT_CHIP25 ... Control circuit, HRWCL ... Control circuit, HDisk ... Hard disk, MAIN ... Main area, REPAREA ... Alternative area, NONCAREA ... Non-cache area, CAREA ... Cache area, WLVL ... Writing times averaging process area, NONWLVL ... Non-writing times averaging process area, CALOCK ... Cache lock area, UNCALOCK ... Non-cache lock area, WPRO ... Write protect area, NONWPRO ... Non-write protect area, WPRO ... Write protect area, NONWPRO ... Non-write protect area, InitProg ... Initial program area, AREA-A ... Main area area, AREA-B ... Main area area, AREA- C: Main area area, AREA-D: Main area area, RModeReg: Read mode Setting register, CAreaReg ... Cache area setting register, CaLockReg ... Cache lock area setting register, WproReg ... Write protect area setting register, WlvlReg ... Write count averaging processing area setting register, PWON ... Power-on period, RESET ... Reset period, InitLoad ... Initial load period, AutoLoad ... Initial program transfer period, IDLE ... Idle period, NRAD ... Address signal from NOR interface, Tag2 ... Tag address, Index2 ... Index address, Line2 ... Line size, vld ... Data valid bit signal, dt ... Dirty Bit signal, lck ... cash lock bit signal,
LRU ... Cache data update order specification signal, AddressArray ... Cache tag address array, DataArray ... Cache data array, COMP ... Comparison circuit, SEL ... Selection circuit, CHIPM1, CHIPM2, CHIP3M, CHIP4M ... Semiconductor chip, PCB ... Printed circuit board , COVER ... Module sealing cover, PATH1 to PATH5 ... Bonding wiring, ANT ... Antenna, RF ... Wireless block, BB ... Baseband block, SP ... Audio codec block, SK ... Speaker, MK ... Microphone, CPU ... Processor, DRAM ... Dynamic random access memory, LCD ... liquid crystal display, KEY ... keyboard, MSM ... memory module, SLP ... module with CPU and memory module MSM and dynamic random access memory DRAM integrated in a single sealed body, PRC ... information Processing unit, MCM ... Memory module, CPU ... Central processing unit, SRC ... Memo Re-controller,
NOR FLASH… NOR flash memory, SRAM… static random access memory.

Claims (82)

A memory module including a non-volatile memory, a cache memory, and a control circuit that performs access between the non-volatile memory and the cache memory,
A memory module comprising: a first nonvolatile memory interface for accessing a cache memory from outside the memory module; and a second nonvolatile memory interface for accessing the nonvolatile memory. In claim 1,
Immediately after the power is turned on, data in a predetermined address area of the nonvolatile memory is transferred to a cache memory. In claim 1,
Read access from the first non-volatile memory interface to the non-volatile memory is performed via the cache memory, and access from the second non-volatile memory interface is not performed via the cache memory. A memory module characterized by accessing the memory. In claim 1,
A data transfer between the non-volatile memory and the cache memory is performed by an access from the first non-volatile memory interface. In claim 1,
The data transfer from the non-volatile memory to the cache memory and the data transfer from the non-volatile memory to the second non-volatile memory interface transfer error-corrected data. In claim 1,
An address replacement process is performed for data transfer to the non-volatile memory. In claim 1,
A memory module, wherein the nonvolatile memory holds a boot program. In claim 1,
A memory module, wherein transfer range data indicating a range of data transferred at an initial stage when operating power is turned on from the nonvolatile memory to the cache memory is held in the nonvolatile memory. In claim 1,
The memory module, wherein the nonvolatile memory and the cache memory have a memory capacity of 1/100 or less of the nonvolatile memory. In claim 2,
The memory module, wherein the non-volatile memory holds transfer range data indicating a range of a predetermined address area of the non-volatile memory. In claim 1,
Read access to the cache memory from the first non-volatile memory interface, access to the non-volatile memory from the second non-volatile memory interface, and access to the dynamic random access memory from the dynamic random access memory interface Is a memory system that can be performed simultaneously. In claim 1,
First priority is given to data transfer from the flash memory to the cache memory by read access from the first nonvolatile interface of the memory module, and the flash memory and second nonvolatile by access from the second nonvolatile interface. A memory module in which data transfer between the two-way interfaces has a second priority and data transfer by a write access from the first nonvolatile interface has a third priority. In claim 1,
The memory module, wherein the cache memory is composed of a static random memory. In claim 1,
The memory module, wherein the cache memory comprises a nonvolatile random access memory. In claim 1,
The memory module, wherein the nonvolatile memory is a NAND flash memory. In claim 1,
The memory module, wherein the nonvolatile memory is an AND flash memory. In claim 1,
The memory module, wherein the nonvolatile memory is a hard disk. In claim 1,
The memory module, wherein the first nonvolatile memory interface is a NOR flash memory interface, and the second nonvolatile memory interface is a NAND flash memory interface. In claim 1,
The memory module, wherein the first nonvolatile memory interface is a NOR flash memory interface, and the second nonvolatile memory interface is an AND flash memory interface. In claim 1,
An error check is performed for data transfer from the cache memory. In claim 5,
An error check is performed for data transfer from the cache memory. In claim 21,
A memory module, wherein when an error is found by the error check, data is transferred from the nonvolatile memory to a previous cache memory. In claim 1,
The memory module, wherein the control circuit includes an address conversion circuit, and the address conversion circuit converts an address input from the first nonvolatile memory interface and uses it for data retrieval of the cache memory. In claim 23,
A memory module capable of programming an address conversion method by the address conversion circuit. In claim 1,
The non-volatile memory includes an error detection / correction circuit and an address substitution processing circuit. In claim 1,
The memory module of the nonvolatile memory has a NAND configuration. In claim 1,
2. A memory module according to claim 1, wherein a configuration of a memory array of the nonvolatile memory is an AND configuration. A memory module including a nonvolatile memory, a cache memory, a control circuit that performs access between the nonvolatile memory and the cache memory, and a dynamic random access memory,
A first nonvolatile memory interface for accessing the cache memory from the outside of the memory module; a second nonvolatile memory interface for accessing the nonvolatile memory; and a dynamic for accessing the dynamic random access memory. A memory module comprising a random access memory interface. In claim 28,
Immediately after the power is turned on, data in a predetermined address area of the nonvolatile memory is transferred to a cache memory. In claim 28,
Read access from the first non-volatile memory interface to the non-volatile memory is performed via the cache memory, and access from the second non-volatile memory interface is not performed via the cache memory. A memory module, wherein access from the dynamic random access memory interface accesses the dynamic random access memory without going through the cache memory. In claim 28,
Data transfer between the non-volatile memory and the cache memory is performed according to a command from the first non-volatile memory interface. In claim 28,
The data transfer from the non-volatile memory to the cache memory and the data transfer from the non-volatile memory to the second non-volatile memory interface transfer error-corrected data. In claim 28,
An address substitution process is performed for data transfer from the second nonvolatile memory interface to the nonvolatile memory. In claim 28,
A memory module, wherein the nonvolatile memory holds a boot program. In claim 28,
A memory module, wherein transfer range data indicating a range of data transferred at an initial stage when operating power is turned on from the nonvolatile memory to the cache memory is held in the nonvolatile memory. In claim 28,
The memory module, wherein the nonvolatile memory and the cache memory have a memory capacity of 1/100 or less of the nonvolatile memory. In claim 29,
The memory module, wherein the non-volatile memory holds transfer range data indicating a range of a predetermined address area of the non-volatile memory. In claim 28,
Data transfer by read access from the first non-volatile interface of the memory module has first priority, data transfer by access from the second non-volatile interface has second priority, and by write access from the first non-volatile interface A memory module that prioritizes data transfer. In claim 28,
The memory module, wherein the cache memory comprises a static random access memory. In claim 28,
The memory module, wherein the cache memory is composed of a nonvolatile random access memory. In claim 28,
The memory module, wherein the nonvolatile memory is a NAND flash memory. In claim 28,
The memory module, wherein the nonvolatile memory is an AND flash memory. In claim 28,
The memory module, wherein the nonvolatile memory is a hard disk. In claim 28,
The memory module, wherein the first nonvolatile memory interface is a NOR flash memory interface, and the second nonvolatile memory interface is a NAND flash memory interface. In claim 28,
The memory module, wherein the first nonvolatile memory interface is a NOR flash memory interface, and the second nonvolatile memory interface is an AND flash memory interface. In claim 28,
An error check is performed for data transfer from the cache memory. In claim 46,
A memory module, wherein when an error is found by the error check, data is transferred from the nonvolatile memory to a previous cache memory. In claim 28,
The memory module, wherein the control circuit includes an address conversion circuit, and the address conversion circuit converts an address input from the first nonvolatile memory interface and uses it for data retrieval of the cache memory. In claim 28,
A memory module capable of programming an address conversion method by the address conversion circuit.   A non-volatile memory, a cache memory, a memory module including a control circuit for accessing between the non-volatile memory and the cache memory, a dynamic random access memory, and an information processing device, and the information processing device Performs data transfer with the cache memory via a first non-volatile memory interface, performs data transfer with the non-volatile memory via a second non-volatile memory interface, and sets the dynamic random access memory interface A memory system for transferring data to and from a dynamic random access memory. In claim 50,
In the initialization period immediately after power-on, the information processing apparatus reads a boot program from a cache memory in the memory module via a first nonvolatile memory interface. In claim 50,
Read access from the first non-volatile memory interface to the non-volatile memory is performed via the cache memory, and access from the second non-volatile memory interface is not performed via the cache memory. A memory system, wherein access from the dynamic random access memory interface accesses the dynamic random access memory without going through the cache memory. In claim 50,
A memory system, wherein read access to the cache memory from the first nonvolatile memory interface and access to the nonvolatile memory from the second nonvolatile memory interface can be performed simultaneously. In claim 50,
Read access to the cache memory from the first nonvolatile memory interface, access to the nonvolatile memory from the second nonvolatile memory interface, and access to the dynamic random access memory from the dynamic random access memory interface Is a memory system that can be performed simultaneously. A non-volatile memory and a cache system including a cache memory,
The non-volatile memory is provided with a data buffer, and the data buffer is used as a cache memory. In claim 55,
A memory module, wherein a size of a data buffer of the nonvolatile memory is larger than a line size of the cache memory. In claim 55,
A cache system for simultaneously searching the cache memory and the data buffer of the nonvolatile memory.   A cache system including a cache memory and a nonvolatile memory, wherein the data transfer from the nonvolatile memory to the cache memory transfers data for a plurality of pages. In claim 58,
The cache system, wherein the plurality of page data transferred from the non-volatile memory to the cache memory transfers Nth page data and N + 1th page data. A non-volatile memory and a cache system including a cache memory,
The cache system is used for data retrieval of the cache memory after address conversion. In claim 60,
A memory module capable of programming an address conversion method by the address conversion. The storage capacity of the cache memory is 2 ^N bytes, the line size address is Line [L-1: 0], the index address is Index [I-1: 0], and the tag address is Tag [NIL-1: 0] When represented by
When the address input to the cache memory is ADD [N-1: 0], ADD [L-1: 0] is made to correspond to Line [L-1: 0], and ADD [N-1: I + L] To Tag [NIL-1: 0], ADD [I + L-1: L] to address INDX0 [I-1: 0], and ADD [I + I + L-1: I + L ] Corresponding to the address INDX1 [I-1: 0], and adding INDX0 [I-1: 0] and INDX1 [I-1: 0] results in SUM [I-1: 0] as Index [I-1 : 0].   An information processing apparatus equipped with a cache memory, wherein the cache memory is a cache memory that retrieves data using an address converted by the address conversion method according to claim 62. Information processing apparatus.   A memory module equipped with a cache memory, wherein the cache memory is a cache memory that searches for data using an address converted by the address conversion method according to claim 62. Memory module. In claim 60,
61. A memory module according to claim 60, wherein said address conversion method by address conversion is the address conversion method according to claim 60.   A cache system including an information processing device, a cache memory, and a nonvolatile memory, wherein the information processing device is equipped with a cache memory, and the nonvolatile memory is equipped with a buffer. The cache memory is a level 1 cache memory, the cache memory is a level 2 cache memory, and the buffer of the nonvolatile memory is a level 3 cache memory.   A cache system including a non-volatile memory and a cache memory, wherein the non-volatile memory has a cache area, and the transfer from the non-volatile memory to the cache memory is performed by transferring data in the cache area. A characteristic cache system. In claim 67,
A cache system capable of programming a cache area of the nonvolatile memory.   A cache system including a non-volatile memory and a cache memory, wherein the non-volatile memory has a cache lock area, and the data transferred from the cache lock area of the non-volatile memory to the cache memory is stored in the cache system. A cache system that is not subject to data update in memory. In claim 69,
A cache system capable of programming a cache lock area of the nonvolatile memory. In claim 69,
A cache system capable of releasing a cache lock area of the nonvolatile memory.   A memory module including a non-volatile memory and a cache memory, wherein the non-volatile memory has a write protect area, and the write protect area of the non-volatile memory prohibits writing. In claim 72,
A memory module, wherein the write protect area of the non-volatile memory is programmable.   A memory module including a non-volatile memory and a cache memory, wherein the non-volatile memory has a write count averaging processing area, and the write count averaging process area of the non-volatile memory performs a write count averaging process. A memory module. In claim 74,
The memory module, wherein the write frequency averaging processing area of the nonvolatile memory is programmable. In claim 1,
The nonvolatile memory is formed on a first semiconductor chip, the control circuit is formed on a second semiconductor chip including a cache memory memory, and the first and second semiconductor chips are mounted on a circuit board and sealed. A memory system, characterized by being a multi-chip memory module. In claim 28,
The non-volatile memory is formed in a first semiconductor chip, the control circuit is formed in a second semiconductor chip including a cache memory memory, the dynamic random access memory is formed in a third semiconductor chip, and the first to third A memory system, wherein the semiconductor chip is a multi-chip memory module mounted on a circuit board and sealed. In claim 50,
The non-volatile memory includes a first semiconductor chip, the control circuit includes a cache memory memory, the second semiconductor chip, the dynamic random access memory to a third semiconductor chip, and the information processing apparatus to a fourth semiconductor chip. A memory system, characterized in that each of the first to fourth semiconductor chips is a multichip memory module mounted on a circuit board and sealed.   An information device comprising an information processing device, a storage device, and an output device, wherein the storage device is the memory system according to claim 1.   An information device comprising an information processing device, a storage device, and an output device, wherein the storage device is the memory system according to claim 17.   An information device comprising an information processing device, a storage device, and an output device, wherein the information processing device and the storage device are the memory system according to claim 28.   45. An information device comprising an information processing device, a storage device, and an output device, wherein the information processing device and the storage device are the memory system according to claim 43.

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