JP2006318192A - Electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide electronic equipment allowing suppression of floating even when using a low consumption type constant voltage regulator to compensate proper circuit operation. <P>SOLUTION: A CPU 8 outputs a control signal EN (an 'H' level) before starting access to a next SRAM after completion of access to an SRAM. According thereto, a transistor 17 turns on, a power source node Nd is electrically connected to a ground voltage GND, so that a discharge is performed. Accordingly, the floating generated in the power source node Nd is adjusted by an adjustment circuit 15. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic apparatus including a constant voltage regulator that supplies a voltage to a load circuit such as an internal memory.

  For electronic devices such as mobile phones, there is a standby power supply that can temporarily supply power even when the main power supply cannot be used. For example, when the main power source cannot be used due to a power failure or the like, a method is adopted in which data stored in a memory or the like is not lost by switching to a standby power source. In this regard, a technology has been proposed in which the data stored in the memory is saved to another location when the power to be supplied is stopped due to a power failure or the like because the power of the standby power is also limited (patent) References 1 and 2).

On the other hand, improvement in power consumption of a power source of an electronic device such as a mobile phone is also an important problem. Especially in mobile phones, etc., there is a limit to the space used for the main power supply and standby power supply, etc., so low power consumption devices are required. The lifespan has been improved.
JP 2004-334575 A JP 2005-12596 A

  However, a device with low power consumption may be difficult to operate at high speed because of a circuit configuration with low voltage operation or low current consumption.

FIG. 3 is a conceptual diagram illustrating a power supply system for driving a memory or the like.
Referring to FIG. 3, in this example, for example, a backup SRAM 5 (memory) is shown as a load circuit. A constant voltage regulator 10 that stably supplies a voltage to the memory is provided. The main power supply V0 and the standby power supply V1 are provided independently, and the switch SW receives the control signal CN and the switching between the main power supply V0 and the standby power supply V1 is controlled. Further, the system power supply 20 receives the main power supply V0 and supplies necessary voltages to the respective circuits. Here, a case where a voltage (2.85 V) for driving the memory which is the backup SRAM 5 is supplied to the constant voltage regulator 10 is shown. It is assumed that the constant voltage regulator 10 is designed to receive a voltage of 2.85V, step down to a constant voltage of 1.8V. The capacitors C0 to C2 are each provided as a noise canceller.

FIG. 4 is a circuit configuration diagram of the constant voltage regulator 10.
Referring to FIG. 4, constant voltage regulator 10 includes a transistor TR1, a comparator CP, and resistors R0 and R1. As an example, the transistor TR1 is a P-type field effect transistor.

  The source side of the transistor TR1 receives a high voltage (2.85 V) from the system power supply 20. The drain side is connected to a power supply node Nd to which a constant voltage is supplied. The gate side is connected to the output node of comparator CP. The comparator CP compares the reference voltage Vref with a voltage based on resistance division of the constant voltage by the resistors R0 and R1, and outputs a gate voltage to the gate of the transistor TR1 according to the comparison result.

  Here, in this constant voltage regulator 10, it is assumed that a low power consumption type constant voltage regulator is used, and its operation will be described. In this example, it is assumed that the device operates with an operating current of about 1 μA.

  Consider a case where power is supplied to the backup SRAM 5 in the case of such a low power consumption type constant voltage regulator of about 1 μA.

  When access to the memory that is the backup SRAM is started, a drive current is required, and the voltage level of the power supply node Nd that is the SRAM input voltage drops. Along with this, the constant voltage regulator 10 starts supplying current and restores the voltage. However, since the constant voltage regulator 10 has a response speed for starting and stopping the current supply, the SRAM input voltage (voltage Vout) is changed. When going to restoration, there arises a problem that the voltage rises to the vicinity of 1.9V exceeding the specified 1.8V.

  FIG. 5 is a diagram for explaining the operation when accessing the backup SRAM 5 when the SRAM input voltage is 1.8V and 1.9V.

  As shown in FIG. 5, when the memory access is started while the SRAM input voltage is in the vicinity of about 1.9 V, the degree of delay in the current supply start timing of the constant voltage regulator 10 increases as shown in FIG.

FIG. 6 is a diagram for explaining the current supply start delay time.
As shown in FIG. 6, it is shown that the delay time is longer at 1.9V than at 1.8V.

  FIG. 7 is a diagram for explaining changes in the output voltage Vout and the gate voltage G of the constant voltage regulator 10.

  As shown in FIGS. 7A and 7B, for example, the gate voltage G does not take much time from 2.15V to 2.0V, but in the case of 2.85V to 2.0V. Because it takes longer time. This is affected by the parasitic capacitance between the source and the gate.

  Specifically, the current supply start timing of the constant voltage regulator is about 120 μS and cannot catch up with the voltage drop, so the SRAM input voltage falls below the lower limit (1.295 V), and data cannot be read into the CPU. There is a possibility.

  The present invention has been made to solve the above-described problems, and suppresses floating even when a low-consumption type constant voltage regulator is used, thereby compensating for appropriate circuit operation. The purpose is to provide.

  The electronic device according to the present invention is connected to a memory and a system power supply to receive a high voltage, and controls to stably supply a driving voltage for driving the memory by stepping down the voltage. And a constant voltage regulator. The constant voltage regulator is a low power consumption type low voltage regulator in which an operating current is reduced in order to reduce power consumption. An adjustment circuit for adjusting the rise of the voltage supplied to the power supply node when the constant voltage regulator is controlled, and accessing the memory and adjusting the voltage of the power supply node to the adjustment circuit before accessing the memory And a control circuit for instructing to do so.

  Preferably, the field effect transistor whose source side is connected to the system power supply and whose drain side is connected to the power supply node, and the gate voltage of the field effect transistor is controlled based on the comparison between the voltage supplied to the power supply node and the reference voltage Comparator.

  Preferably, the adjustment circuit includes a switch element that electrically couples between the power supply node and the fixed voltage in response to a control signal from the control circuit.

  The electronic apparatus according to the present invention includes a control circuit that instructs the adjustment circuit to adjust the voltage of the power supply node before accessing the memory. Therefore, it is possible to adjust the rise of the voltage supplied to the power supply node, and it is possible to compensate for an appropriate circuit operation by suppressing an operation delay caused by the rise.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

FIG. 1 is a diagram illustrating a power supply system according to an embodiment of the present invention.
Referring to FIG. 1, the power supply system according to the embodiment of the present invention is different from the power supply system described in FIG. 3 in that adjustment circuit 15 is further provided. Since the other points are the same as those described in FIG. 3, detailed description thereof will not be repeated.

  Specifically, the adjustment circuit 15 includes a resistor 16 and a transistor 17. The source side of the transistor 17 is connected to the power supply node Nd via the resistor 16. The drain side is connected to the ground (fixed) voltage GND. The gate side receives the control signal EN from the CPU 7.

  The adjustment circuit 15 operates in response to an input of a control signal EN (“H” level) from the CPU 7. Specifically, transistor 17 is turned on and power supply node Nd and ground voltage GND are electrically coupled via resistor 16. Therefore, for example, even when the above-described 1.9V or the like is raised at power supply node Nd, it is discharged by inputting control signal EN to adjustment circuit 15 to lower power supply node Nd to a desired voltage level. It becomes possible.

  FIG. 2 is a timing chart when the CPU 7 accesses the backup SRAM 5.

  Referring to FIG. 2, for example, at time T1, CPU 7 is assumed to access. That is, it is assumed that the CPU 7 is executing an access command. Here, the case where the memory which is the backup SRAM 5 is accessed during the period from the time T1 to the time T3 (the period when the command AS is “H” level) is shown.

  Then, an SRAM current flows as a drive current with access to the backup SRAM.

  Along with this, the output voltage Vout of the constant voltage regulator 10 drops from 1.8V. Control is performed so that the regulator supply current flows and the output voltage of the regulator becomes an intended value at time T2 60 μs after the voltage starts to drop. Here, 60 μs is due to a delay in response speed with respect to the start of current supply of the constant voltage regulator.

  At time T3, access to the backup SRAM 5 is completed, but thereafter, the output voltage of the regulator rises to 1.9V due to a delay in response speed to the stop of the constant voltage regulator. Up to this point, the configuration is the same as the conventional configuration.

  Next, at time T5, after the access to the backup SRAM 5 is completed, the CPU 7 outputs the control signal EN (“H” level) before accessing the backup SRAM next time. Accordingly, power supply node Nd is electrically coupled to ground voltage GND and discharged at time T6. Specifically, the adjustment circuit current flows and the output voltage Vout of the constant voltage regulator 10 drops to the expected 1.8V. As a result, even when the backup SRAM 5 is accessed next time by the CPU 7, the regulator output voltage Vout is adjusted to the expected value of 1.8 V, so that even when the backup SRAM 5 is accessed, the conventional configuration will be described. As described above, since the reading operation to the CPU is possible without falling below the lower limit value, it is possible to compensate for an appropriate circuit operation. Note that the same procedure can be used when the next backup SRAM is accessed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure explaining the power supply system according to embodiment of this invention. 6 is a timing chart when the CPU 7 accesses the backup SRAM 5. FIG. It is a conceptual diagram explaining the power supply system for driving a memory etc. FIG. 1 is a circuit configuration diagram of a constant voltage regulator 10. FIG. It is a figure explaining the operation | movement at the time of access with respect to backup SRAM5 when SRAM input voltage is 1.8V and 1.9V. It is a figure explaining electric current supply start delay time. 4 is a diagram for explaining changes in an output voltage Vout and a gate voltage G of the constant voltage regulator 10. FIG.

Explanation of symbols

  5 Backup SRAM, 7 CPU, 10 constant voltage regulator, 15 adjustment circuit, 16 resistor, 17 transistor, 20 system power supply.

Claims (3)

Memory,
A constant voltage regulator that is connected to a system power supply, receives a high voltage supply, and controls the power supply node to stably supply a drive voltage for driving the memory by reducing the voltage;
The constant voltage regulator is a low power consumption type low voltage regulator in which an operating current is reduced in order to reduce power consumption,
An adjustment circuit for adjusting the rise of the voltage supplied to the power supply node accompanying the control of the constant voltage regulator;
An electronic device further comprising: a control circuit that accesses the memory and instructs the adjustment circuit to adjust a voltage of the power supply node before accessing the memory. A field effect transistor having a source side connected to the system power supply and a drain side connected to the power supply node;
The electronic apparatus according to claim 1, further comprising: a comparator that controls a gate voltage of the field effect transistor based on a comparison between a voltage supplied to the power supply node and a reference voltage.   The electronic device according to claim 1, wherein the adjustment circuit includes a switch element that electrically couples the power supply node and a fixed voltage in response to a control signal from the control circuit.

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