JP2006311176A - Clock detection circuit, signal processing circuit using the same, and information terminal device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock detection circuit capable of discriminating whether a clock signal is inputted or not by the small number of elements. <P>SOLUTION: In the clock detection circuit 100, one end of a first capacitor C1 is grounded. Power supply voltage Vdd is applied to the source of a first transistor M1 and the drain of the first transistor M1 is connected to the other end of the first capacitor C1. A clock signal CLK is inputted to the gate of the first transistor M1 via an inverter 12. A first resistor R1 is connected between the other end of the first capacitor C1 and ground potential. The first transistor M1 is repeatedly turned on and off in accordance with the clock signal CLK, the first capacitor C1 is charged with electricity and first voltage Vc1 is increased. When the first voltage Vc1 exceeds the threshold voltage of a comparator, a clock detection signal CLKDET is turned to a high level. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock signal detection technique.

Various digital signal processing circuits are built in electronic devices such as mobile phones and PDAs (Personal Digital Assistants), and each signal processing circuit performs signal processing necessary for the operation of the electronic devices. In order to extend battery life, these electronic devices
During the non-operation time, the current path of the signal processing circuit used inside may be interrupted to save power. In this case, in order to shift each signal processing circuit to the power saving state, an enable signal is sent to each signal processing circuit, and a standby mode for reducing current consumption based on the enable signal and an operation mode for performing a normal operation are provided. Switch.

In recent years, a small-sized information terminal such as a mobile phone is mainly a foldable type in which a first casing including a liquid crystal panel and a second casing including an operation unit are connected. FIG. 10 is a diagram schematically showing such a foldable mobile phone. The first housing 210 and the second housing 220 are connected via a connecting portion 230 having a hinge structure.
FIG. 11 shows an internal circuit block diagram of the mobile phone 200. A CPU 222 and a clock signal generation circuit 224 are mounted on the second housing 220. The clock signal generation circuit 224 generates a clock signal CLK and supplies it to each digital circuit. The CPU 222 performs various arithmetic processes necessary for communication and image processing.
The liquid crystal driver 214 mounted on the first housing 210 drives the liquid crystal panel 212 in a matrix based on the input image data, and displays necessary data on the liquid crystal panel 212.

  Since the connecting portion 230 between the first housing 210 and the second housing 220 has a movable structure, it is difficult to lay many signal lines. Therefore, a signal transmission circuit 240 is mounted on the mobile phone 200. The signal transmission circuit 240 is a signal processing circuit for efficiently transferring data between the first housing 210 and the second housing 220 using a low voltage differential signal LVDS (Low Voltage Differential Signal) or the like. A first unit (receiver) 240a is mounted on the first casing 210, and a second unit (transmitter) 240b is mounted on the second casing 220, respectively. For example, image data processed by the CPU 222 is input to the second unit 240 b of the signal transmission circuit 240. The second unit 240b transfers the image data to the first unit 240a. The first unit 240 a receives the image data transmitted from the second unit 240 b and sends it to the liquid crystal driver 214. The liquid crystal driver 214 drives the liquid crystal panel 212 based on the image data.

While the user does not operate the mobile phone 200, the backlight of the liquid crystal panel 212 is turned off, and other signal processing circuits are set in a standby state to shift to the power saving mode. In the power saving mode, since the liquid crystal panel 212 is turned off, it is not necessary to transmit and receive data between the first casing 210 and the second casing 220. Therefore, it is desirable that the signal transmission circuit 240 is in a standby state to reduce current consumption while the user is not operating. Here, since the common clock signal CLK is input to the liquid crystal driver 214 and other signal processing circuits, if the operation and non-operation states can be switched depending on the presence or absence of the clock signal CLK, the signal transmission circuit 240 is Since it is not necessary to input an enable signal for switching between operation and non-operation, signal lines can be reduced. Patent Document 1 discloses a clock detection circuit that detects the presence or absence of an input clock signal.
JP-A-11-220369

Since the clock detection circuit described in Patent Document 1 requires a logic gate such as a flip-flop to detect a clock signal, in the signal transmission circuit 240 mounted on an electronic device that is required to be downsized, such as the mobile phone 200. However, it was necessary to further reduce the number of elements.
The present invention has been made in view of these problems, and provides a clock detection circuit capable of determining whether a clock signal is input with a small number of elements. Another object of the present invention is to provide a signal processing circuit capable of switching between an operation state and a non-operation state by a clock signal without using an enable signal.

  One embodiment of the present invention relates to a clock detection circuit that detects a clock signal input from the outside. The clock detection circuit includes a first capacitor having one end grounded, a first transistor provided between the other end of the first capacitor and a fixed potential, and a clock signal input to a control terminal, and the other end of the first capacitor. And a first resistor provided between the ground potential and a voltage at the other end of the first capacitor as a detection result.

  According to this aspect, the first transistor is repeatedly turned on and off while the clock signal is input, the first capacitor is charged during the on period, and the first capacitor is discharged by the first resistor during the off period. As a result, since the voltage of the first capacitor rises while the clock signal is input, the presence or absence of the clock signal can be determined based on the voltage of the first capacitor.

The clock detection circuit may further include a second resistor provided on a current path from the first transistor to the first capacitor.
By providing the second resistor, the charging speed of the first capacitor can be controlled, and the charging and discharging speeds at the high level and low level of the clock signal can be adjusted to optimum values. Further, by providing the second resistor, the current flowing from the fixed potential to the ground through the first transistor and the first resistor can be suppressed while the first transistor is on, and the current consumption of the clock detection circuit can be suppressed. Can be reduced.

The clock detection circuit may further include a Schmitt buffer connected to the other end of the first capacitor, and may output the output of the Schmitt buffer as a detection result.
By providing the Schmitt buffer, even if the voltage at the other end of the first capacitor fluctuates near the threshold voltage of the Schmitt buffer, the output of the Schmitt buffer, that is, the output of the clock detection circuit can be maintained at a constant value. it can.

  Another aspect of the present invention is also a clock detection circuit for detecting a clock signal input from the outside. The clock detection circuit includes a first capacitor having one end grounded, a clock signal input to the control terminal, one end connected to the other end of the first capacitor, and the other end of the first transistor fixed. A second transistor that is provided between the potentials and has a control terminal provided with an inverted signal of the clock signal; and a second capacitor provided between the connection point of the first transistor and the second transistor and the ground potential. The voltage at the other end of the first capacitor is output as a detection result.

  The first transistor and the second transistor are alternately turned on and off, and the second capacitor is charged while the second transistor is on, and the charge charged in the second capacitor is charged to the first capacitor while the first transistor is on. Transferred. As a result, the voltage of the first capacitor rises while the clock signal is input. By providing the first transistor and the second transistor, even when the clock signal is stopped at either the high level or the low level, the voltage of the first capacitor decreases, so that the presence or absence of the clock signal can be detected. it can.

The clock detection circuit may further include a second resistor provided on a current path from the first transistor to the first capacitor.
By providing the second resistor, the charge transfer rate from the second capacitor to the first capacitor can be adjusted. Since the voltage of the first capacitor is determined by the discharge rate by the first resistor and the charge rate through the second resistor, by appropriately selecting the resistance values of the first and second resistors, The voltage fluctuation of the first capacitor can be kept constant.

The clock detection circuit may further include a Schmitt buffer connected to the other end of the first capacitor, and may output the output of the Schmitt buffer as a detection result.
By providing the Schmitt buffer, even if the voltage at the other end of the first capacitor fluctuates near the threshold voltage of the Schmitt buffer, the output of the Schmitt buffer, that is, the output of the clock detection circuit can be maintained at a constant value. it can.

  Yet another embodiment of the present invention is a signal processing circuit. This signal processing circuit is a signal processing circuit that performs data processing based on a clock signal input from the outside, and includes the above-described clock detection circuit that detects the clock signal, and no clock signal is input by the clock detection circuit. While the state is determined, the circuit operation is stopped.

  According to this aspect, there is no need to separately input an enable signal, so that the number of circuit terminals and the number of wirings can be reduced.

Still another embodiment of the present invention relates to an information terminal device in which first and second housings are connected via a connecting portion. The information terminal device includes a clock signal generation circuit mounted on the first housing and first and second units mounted on the first and second housings, respectively, and signals between the first and second units. A signal transmission circuit for performing transmission / reception of. The first unit of the signal processing circuit includes the above-described clock detection circuit. When the clock detection circuit detects the stop of the clock signal output from the clock signal generation circuit, data transmission / reception between the first and second units is performed. To enter power saving mode. The signal transmission circuit may stop the first unit after stopping the second unit when the clock detection circuit detects the stop of the clock signal.
According to this aspect, the signal transmission circuit can be stopped by stopping the clock signal of the clock signal generation circuit in a period in which transmission / reception of the signal is unnecessary, so that it is not necessary to separately input an enable signal. The number of terminals and the number of wirings can be reduced.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the present invention, a clock detection circuit that determines whether or not a clock signal is input can be configured with a small number of elements.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a clock detection circuit 100 according to the first embodiment. FIG. 2 is a diagram showing a configuration of a signal processing circuit on which the clock detection circuit of FIG. 1 is mounted. The signal processing circuit in FIG. 2 is, for example, the signal transmission circuit 240 in FIG. The second unit 240 b of the signal transmission circuit 240 includes the clock detection circuit 100 and the transmission unit 242. In addition, the first unit 240a includes a receiving unit 244. The transmission unit 242 transmits data DATA input from the outside to the reception unit 244. The clock signal CLK is input to the transmission unit 242, and the transmission unit 242 transmits a signal based on the clock signal CLK.

  A clock signal CLK is input to the clock detection circuit 100. The clock detection circuit 100 determines whether or not the clock signal CLK is input, and notifies the transmission unit 242 of it. When the input of the clock signal CLK is stopped, the transmission unit 242 causes the first unit 240a to transition to the low power consumption mode, and then the transmission unit 242 itself also transitions to the low power consumption mode.

The clock detection circuit 100 of FIG. 1 includes a comparator 10, a first resistor R1, a first capacitor C1, a first transistor M1, and an inverter 12.
The clock detection circuit 100 detects a clock signal CLK input from the outside, and outputs a clock detection signal CLKDET that becomes a high level when a clock is input.

  One end of the first capacitor C1 is grounded. The first transistor M1 is provided between the other end of the first capacitor C1 and the power supply voltage Vdd that is a fixed potential. The first transistor M1 is a P-channel MOSFET having a source connected to the power supply voltage Vdd and a drain connected to the first capacitor C1. The clock signal CLK is inverted by the inverter 12 and input to the gate which is the control terminal of the first transistor M1. The first transistor M1 is turned on when the clock signal CLK is at a high level and turned off when the clock signal CLK is at a low level.

  The first resistor R1 is connected in parallel with the first capacitor C1, and is provided between the other end of the first capacitor C1 and the ground potential. The first resistor R1 functions as a discharge circuit that discharges the electric charge stored in the first capacitor C1.

  The voltage at the other end of the first capacitor C1 (hereinafter also simply referred to as the first voltage Vc1) is input to the comparator 10. The comparator 10 compares the first voltage Vc1 at the other end of the first capacitor C1 with the threshold voltage Vth, and outputs a high level clock detection signal CLKDET when it is higher than the threshold voltage Vth. The comparator 10 may be configured using two stages of inverters connected in series, or a voltage comparator.

The operation of the clock detection circuit 100 configured as described above will be described.
FIG. 3 is a time waveform diagram showing an operation state of the clock detection circuit 100 of FIG. FIG. 3 shows, from above, the clock signal CLK, the first voltage Vc1 of the first capacitor C1, and the clock detection signal CLKDET that is the output of the comparator 10.
When the clock signal CLK is input at time T0, the gate of the first transistor M1 alternately repeats high level and low level, and the first transistor M1 is controlled to be turned on / off according to the clock signal CLK.
When the clock signal CLK goes high at time T0 and the first transistor M1 is turned on, the first voltage Vc1 of the first capacitor C1 rises to the power supply voltage Vdd.

When the clock signal CLK becomes low level at time T1, the first transistor M1 is turned off. When the first transistor M1 is turned off, the electric charge stored in the first capacitor C1 is discharged through the first resistor R1. At this time, the first voltage Vc1 decreases according to the CR time constant of the first resistor R1 and the first capacitor C1.
When the clock signal CLK becomes high level again at time T2, the first transistor M1 is turned on, the first capacitor C1 is charged by the power supply voltage Vdd, and the first voltage Vc1 rises to near the power supply voltage Vdd.

  The comparator 10 compares the first voltage Vc1 with the threshold voltage Vth, and outputs a high level when Vc1> Vth. As a result, the clock detection signal CLKDET, which is the output of the comparator 10, becomes high after time T0.

  When the clock signal CLK is stopped and fixed at a low level, the first transistor M1 is kept off, so that the charge stored in the first capacitor C1 is discharged through the first resistor R1. The first voltage Vc1 gradually decreases, and the clock detection signal CLKDET becomes a low level when it falls below the threshold voltage of the comparator 10.

  As described above, according to the clock detection circuit 100 according to the present embodiment, the first capacitor C1 is charged based on the clock signal CLK, and the first voltage Vc1 appearing in the first capacitor C1 is compared with the threshold voltage. By outputting, it is possible to detect whether the clock signal CLK is input.

FIG. 4 is a circuit diagram showing a modification of the clock detection circuit 100 of FIG. In the subsequent drawings, the same or equivalent components as those already described are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
The clock detection circuit 100 of FIG. 4 further includes a second resistor R2 in addition to the components of the clock detection circuit 100 of FIG. The second resistor R2 has one end connected to the first capacitor C1 and the other end connected to the drain of the first transistor M1. That is, the second resistor R2 is provided on the current path from the first transistor M1 to the first capacitor C1. The second resistor R2 may be provided between the source of the first transistor M1 and the power supply voltage Vdd.

  In the modification of FIG. 4, a Schmitt buffer 16 having hysteresis is used as a comparator that compares the first voltage Vc1 appearing in the first capacitor C1 with the threshold voltage. The Schmitt buffer 16 compares the first threshold voltage Vth1 with the first voltage Vc1 when the output is at a low level, and the second threshold voltage lower than the first threshold voltage Vth1 when the output is at a high level. The value voltage Vth2 is compared with the first voltage Vc1.

The operation of the clock detection circuit 100 of FIG. 4 configured as described above will be described. FIG. 5 is a time waveform diagram showing an operation state of the clock detection circuit 100 of FIG. FIG. 5 shows, from above, the clock signal CLK, the first voltage Vc1 of the first capacitor C1, and the clock detection signal CLKDET that is the output of the Schmitt buffer 16.
At time T0, the clock signal CLK becomes high level, and the first transistor M1 is turned on. When the first transistor M1 is turned on, the first capacitor C1 is charged via the first transistor M1 and the second resistor R2. In this charging period, the first voltage Vc1 increases according to the CR time constant of the first capacitor C1 and the second resistor R2.

  When the clock signal CLK becomes low level at time T1, the first transistor M1 is turned off. Since the first capacitor C1 is discharged through the first resistor R1 during a period from time T1 to time T2 when the clock signal CLK becomes high level next, the first voltage Vc1 is the first capacitor C1, the first It decreases according to the CR time constant of the resistor R1. When the clock signal CLK goes high again at time T2, the first voltage Vc1 rises. Thus, every time the clock signal CLK repeats high level and low level, the first voltage Vc1 of the first capacitor C1 rises. When the first voltage Vc1 exceeds the first threshold voltage Vth1 at time T3, the clock detection signal CLKDET that is the output of the Schmitt buffer 16 becomes high level. Even if the first voltage Vc1 falls below the first threshold voltage Vth1 due to the subsequent discharge, the voltage does not decrease to the second threshold voltage Vth2, so that the clock detection signal CLKDET remains stable at a high level.

Here, the fluctuation range at the time of discharging the first voltage Vc1 for each clock is given by ΔVc1 = Vpre × {1−exp (−Toff / C1 · R1)}. Here, Vpre represents the first voltage Vc1 immediately before the start of discharge, and Toff represents the off time of the first transistor M1. The hysteresis width Vhys = Vth1−Vth2 of the Schmitt buffer 16 may be set larger than the fluctuation width ΔVc1. The hysteresis width Vhys may be set higher than the maximum value of the fluctuation width ΔVc1, and for example, when Vpre = 4 V, Toff = 350 ns, C1 = 30 pF, and R1 = 1 MΩ, the hysteresis width Vhys may be set to about 50 mV.
By setting the hysteresis width Vhys to be larger than the fluctuation width ΔVc1 of the first voltage Vc1, it is possible to prevent the clock detection signal CLKDET from chattering in the process in which the first voltage Vc1 is repeatedly charged and discharged and is stable. In addition, the clock signal CLK can be detected.

  Further, according to this modification, the following effects can be obtained by providing the second resistor R2 as compared with the clock detection circuit 100 of FIG. In the clock detection circuit 100 of FIG. 1, the discharge time by the first resistor R1 varies as the frequency of the input clock signal CLK changes or the duty ratio changes. As a result, the fluctuation range of the first voltage Vc1 for each clock changes according to the frequency. On the other hand, in the clock detection circuit 100 of FIG. 4, as shown in FIG. 5, the first voltage Vc1 rises while the first transistor M1 is on and falls when the first transistor M1 is off. Here, since the charging time Tch and the discharging time Tdis are inversely proportional to the frequency of the clock signal CLK, the rising width and falling width of the first voltage Vc1 within one cycle both change according to the frequency of the clock signal CLK. To do. Therefore, even when the frequency of the clock signal CLK varies, the variation of the first voltage Vc1 within one cycle can be adjusted by the resistance values of the first resistor R1 and the second resistor R2, so that the Schmitt buffer 16 The hysteresis width Vhys can be set small, and the design can be easily performed.

  Also, by providing the second resistor R2, the current flowing from the power supply voltage Vdd to the ground through the first transistor M1 and the first resistor R1 while the first transistor M1 is on can be suppressed, and the clock Current consumption of the detection circuit 100 can be reduced.

(Second Embodiment)
In the clock detection circuit 100 according to the first embodiment, when the clock signal CLK stops at a high level, the first voltage Vc1 continues to be charged with the power supply voltage Vdd, so that a high level continues to be output as the clock detection signal CLKDET. . Therefore, it is impossible to detect the presence or absence of the input of the clock signal CLK that may stop at a high level.
In the second embodiment described below, a clock detection circuit 100 that can detect the presence / absence of an input even when the clock signal CLK stops at either a low level or a high level will be described.

FIG. 6 is a circuit diagram showing a configuration of the clock detection circuit 110 according to the second exemplary embodiment.
The clock detection circuit 110 according to the present embodiment includes a Schmitt buffer 16, a first resistor R1, a first capacitor C1, a second capacitor C2, a first transistor M1, a second transistor M2, an inverter 12, and an inverter 14.

One end of the first capacitor C1 is grounded. The first transistor M1 is a P-channel MOS transistor, the drain is connected to the other end of the first capacitor C1, and the clock signal CLK is input to the gate which is the control terminal via the inverter 14 and the inverter 12. . The first transistor M1 is turned off when the clock signal CLK is at a high level, and turned on when the clock signal CLK is at a low level.
The first resistor R1 is connected in parallel with the first capacitor C1, and is provided between the other end of the first capacitor C1 and the ground potential. The first resistor R1 functions as a discharge circuit that discharges the electric charge stored in the first capacitor C1.

The second capacitor C2 is connected between the source of the first transistor M1 and the ground potential. Hereinafter, the voltage of the second capacitor C2 is referred to as a second voltage Vc2. The second transistor M2 is a P-channel MOS transistor, the drain of which is connected to the source of the first transistor M1, and the power supply voltage Vdd is applied to the source. The clock signal CLK is inverted and input via the inverter 14 to the gate which is the control terminal of the second transistor M2. The second transistor M2 is turned on when the clock signal CLK is at a high level and turned off when the clock signal CLK is at a low level.
That is, a signal having an inverted logic value is input to the gates of the first transistor M1 and the second transistor M2, and is configured to be alternately turned on and off in accordance with the clock signal CLK.

  The first voltage Vc1 appearing on the first capacitor C1 is input to the Schmitt buffer 16. The Schmitt buffer 16 compares the first threshold voltage Vth1 with the first voltage Vc1 when the output is at a low level, and the second threshold voltage lower than the first threshold voltage Vth1 when the output is at a high level. The value voltage Vth2 is compared with the first voltage Vc1, and a high level clock detection signal CLKDET is output when Vc1> Vth. The Schmitt buffer 16 may be replaced with a hysteresis comparator.

The operation of the clock detection circuit 110 configured as described above will be described.
FIG. 7 is a time waveform diagram showing an operation state of the clock detection circuit 110 of FIG. FIG. 7 shows the clock signal CLK, the second voltage Vc2 of the second capacitor C2, the first voltage Vc1 of the first capacitor C1, and the clock detection signal CLKDET that is the output of the Schmitt buffer 16 from the top.
When the clock signal CLK is input at time T0, the gates of the first transistor M1 and the second transistor M2 repeatedly alternate between high level and low level, and one of the first transistor M1 and the second transistor M2 is turned on. On and off is controlled according to the clock signal CLK while maintaining a complementary relationship in which the other is off.
When the clock signal CLK goes high at time T0 and the second transistor M2 is turned on, the second capacitor C2 is charged, and the second voltage Vc2 rises to the power supply voltage Vdd.

  When the clock signal CLK becomes low level at time T1, the second transistor M2 is turned off and the first transistor M1 is turned on. At this time, the electric charge stored in the second capacitor C2 is transferred to the first capacitor C1 via the first transistor M1, so that the first voltage Vc1 rises. Thereafter, while the first transistor M1 is on, the charges stored in the first capacitor C1 and the second capacitor C2 are discharged through the first resistor R1, so that the first voltage Vc1 and the second voltage Vc2 are respectively It decreases according to the time constant.

  When the clock signal CLK becomes high level again at time T2, the second transistor M2 is turned on, the second capacitor C2 is charged, and the second voltage Vc2 rises to the power supply voltage Vdd. From time T2 to time T3, the first transistor M1 is off, the charge stored in the first capacitor C1 is discharged through the first resistor R1, and the first voltage Vc1 decreases according to the CR time constant. Keep doing.

In the clock detection circuit 110 of FIG. 6, the first voltage Vc1 of the first capacitor C1 gradually increases as the first transistor M1 and the second transistor M2 are alternately turned on and off. When the first voltage Vc1 reaches the threshold voltage Vth1 of the Schmitt buffer 16 at time T3, the clock detection signal CLKDET becomes high level.
As in the first embodiment, the hysteresis width Vhys of the Schmitt buffer 16 is set to be smaller than the fluctuation width of the first voltage Vc1, so that even if the first voltage Vc1 decreases due to discharge by the first resistor R1, The clock detection signal CLKDET does not chatter and keeps the high level stably.

  When the clock signal CLK is stopped in a low level state, the second transistor M2 is turned off and the first transistor M1 is turned on. At this time, since the charging path for the first capacitor C1 and the second capacitor C2 is blocked by the second transistor M2, the charge stored in each capacitor is discharged by the first resistor R1, and the first voltage Vc1, Both the two voltages Vc2 decrease. As a result, when the first voltage Vc1 falls below the threshold voltage Vth2 of the Schmitt buffer 16, the clock detection signal CLKDET becomes low level, and it is determined that the clock signal CLK is in a non-input state.

  When the clock signal CLK is stopped in a high level state, the second transistor M2 is turned on and the first transistor M1 is turned off. At this time, since the first transistor M1 serving as a charge transfer path from the first capacitor C1 to the second capacitor C2 is cut off, the charge stored in the first capacitor C1 is discharged by the first resistor R1, 1 voltage Vc1 decreases. As a result, when the first voltage Vc1 falls below the threshold voltage Vth2 of the Schmitt buffer 16, the clock detection signal CLKDET becomes low level, and it is determined that the clock signal CLK is in a non-input state.

  As described above, according to the clock detection circuit 110 of FIG. 6, it is possible to determine whether or not there is an input even when the clock signal CLK is stopped at either the high level or the low level.

  FIG. 8 is a circuit diagram showing a modification of the clock detection circuit 110 of FIG. The clock detection circuit 110 of FIG. 8 further includes a second resistor R2 provided on the current path from the first transistor M1 to the first capacitor C1 in addition to the clock detection circuit 110 of FIG. The second resistor R2 may be provided on either the drain or source side of the first transistor M1.

FIG. 9 is a time waveform diagram showing an operation state of the clock detection circuit 110 of FIG. FIG. 9 shows, from above, the clock signal CLK, the second voltage Vc2 of the second capacitor C2, the first voltage Vc1 of the first capacitor C1, and the clock detection signal CLKDET that is the output of the Schmitt buffer 16.
When the clock signal CLK is input at time T0, the gates of the first transistor M1 and the second transistor M2 repeatedly alternate between high level and low level, and one of the first transistor M1 and the second transistor M2 is turned on. On and off is controlled according to the clock signal CLK while maintaining a complementary relationship in which the other is off.
When the clock signal CLK goes high at time T0 and the second transistor M2 is turned on, the second capacitor C2 is charged, and the second voltage Vc2 rises to the power supply voltage Vdd.

  When the clock signal CLK becomes low level at time T1, the second transistor M2 is turned off and the first transistor M1 is turned on. At this time, the electric charge stored in the second capacitor C2 is transferred to the first capacitor C1 via the first transistor M1 and the second resistor R2. Since the second resistor R2 is provided in the charge transfer path from the second capacitor C2 to the first capacitor C1, the first voltage Vc1 rises with a time constant. During this time, the second capacitor C2 loses its charge with a time constant because the charge is lost.

  When the clock signal CLK becomes high level again at time T2, the second transistor M2 is turned on, the second capacitor C2 is charged, and the second voltage Vc2 rises to the power supply voltage Vdd. From time T2 to time T3, the first transistor M1 is off, the charge stored in the first capacitor C1 is discharged through the first resistor R1, and the first voltage Vc1 decreases according to the CR time constant. To do.

In the clock detection circuit 110 of FIG. 8, the first voltage Vc1 of the first capacitor C1 gradually increases as the first transistor M1 and the second transistor M2 are alternately turned on and off. When the first voltage Vc1 reaches the threshold voltage Vth1 of the Schmitt buffer 16 at time T4, the clock detection signal CLKDET becomes high level.
Thus, according to the clock detection circuit 110 of FIG. 8, it is possible to suitably detect the presence or absence of the input of the clock signal CLK. As with the clock detection circuit 110 in FIG. 6, the clock signal CLK may be stopped at either the high level or the low level.

Next, an effect obtained by providing the second resistor R2 in the clock detection circuit 110 of FIG. 8 will be described.
In the clock detection circuit 110 of FIG. 6, as shown in FIG. 7, the first voltage Vc1 is discharged over almost one cycle of the clock signal CLK. Therefore, when the frequency of the clock signal CLK changes, the discharge time changes, so the amount of change in the first voltage Vc1 within one cycle changes according to the frequency. As described above, since the hysteresis width Vhys of the Schmitt buffer 16 is set based on the fluctuation range of the first voltage Vc1, it is necessary to set the hysteresis width Vhys to a large value in advance for applications in which the frequency varies. And design becomes difficult.

  On the other hand, in the clock detection circuit 110 of FIG. 8, as shown in FIG. 9, the first voltage Vc1 rises while the first transistor M1 is on and falls when the first transistor M1 is off. Here, since the charging time Tch and the discharging time Tdis are inversely proportional to the frequency of the clock signal CLK, the rising width and falling width of the first voltage Vc1 within one cycle both change according to the frequency of the clock signal CLK. To do. Therefore, even when the frequency of the clock signal CLK fluctuates, the amount of change in the first voltage Vc1 within one cycle can be adjusted by the resistance values of the first resistor R1 and the second resistor R2. The hysteresis width Vhys can be set small, and the design can be easily performed.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, the first transistor M1 and the second transistor M2 are both P-channel MOS transistors. However, both of them may be N-channel MOS transistors, or a combination of P-channel and N-channel may be used. Also good. Which type of transistor is used may be determined according to a semiconductor manufacturing process to be employed.

  In addition to the signal processing circuit shown in FIG. 2, the clock detection circuit according to this embodiment can be used for various signal processing circuits that operate based on a clock signal.

1 is a circuit diagram showing a configuration of a clock detection circuit according to a first embodiment. FIG. It is a figure which shows the structure of the signal processing circuit in which the clock detection circuit of FIG. 1 is mounted. FIG. 2 is a time waveform diagram illustrating an operation state of the clock detection circuit of FIG. 1. FIG. 6 is a circuit diagram showing a modification of the clock detection circuit of FIG. 1. FIG. 5 is a time waveform diagram showing an operation state of the clock detection circuit of FIG. 4. It is a circuit diagram which shows the structure of the clock detection circuit which concerns on 2nd Embodiment. FIG. 7 is a time waveform diagram illustrating an operation state of the clock detection circuit of FIG. 6. FIG. 7 is a circuit diagram illustrating a modification of the clock detection circuit of FIG. 6. FIG. 9 is a time waveform diagram illustrating an operation state of the clock detection circuit of FIG. 8. It is a figure which shows a folding type mobile phone typically. It is a figure which shows the internal circuit block diagram of the mobile telephone of FIG.

Explanation of symbols

  100 clock detection circuit, 110 clock detection circuit, 10 comparator, 12 inverter, 14 inverter, 16 Schmitt buffer, R1 first resistor, R2 second resistor, C1 first capacitor, C2 second capacitor, M1 first transistor, M2 first transistor 2 transistors, 200 mobile phone, 210 first housing, 212 liquid crystal panel, 214 liquid crystal driver, 220 second housing, 222 CPU, 224 clock signal generation circuit, 230 coupling unit, 240 signal transmission circuit, 240a first unit, 240b Second unit, Vc1 first voltage, Vc2 second voltage, CLK clock signal, CLKDET clock detection signal.

Claims (9)

A clock detection circuit for detecting a clock signal input from the outside,
A first capacitor having one end grounded;
A first transistor provided between the other end of the first capacitor and a fixed potential and having the control signal input to the clock signal;
A first resistor provided between the other end of the first capacitor and a ground potential;
And a voltage at the other end of the first capacitor is output as a detection result.   The clock detection circuit according to claim 1, further comprising a second resistor provided on a current path from the first transistor to the first capacitor.   The clock detection circuit according to claim 1, further comprising a Schmitt buffer connected to the other end of the first capacitor, and outputting an output of the Schmitt buffer as a detection result. A clock detection circuit for detecting a clock signal input from the outside,
A first capacitor having one end grounded;
A first transistor having the control signal input to the clock signal and having one end connected to the other end of the first capacitor;
A second transistor provided between the other end of the first transistor and a fixed potential, and having an inverted signal of the clock signal input to a control terminal thereof;
A connection point between the first transistor and the second transistor and a second capacitor provided between a ground potential;
And a voltage at the other end of the first capacitor is output as a detection result.   The clock detection circuit according to claim 4, further comprising a second resistor provided on a current path from the first transistor to the first capacitor.   6. The clock detection circuit according to claim 4, further comprising a Schmitt buffer connected to the other end of the first capacitor, and outputting an output of the Schmitt buffer as a detection result. A signal processing circuit that performs data processing based on an externally input clock signal,
The clock detection circuit according to claim 1, wherein the clock signal is detected, and the circuit operation is stopped while the clock detection circuit determines that the clock signal is in a non-input state. Signal processing circuit. An information terminal device in which the first and second housings are connected via a connecting part,
A clock signal generation circuit mounted in the first housing;
A signal transmission circuit including first and second units mounted on the first and second housings, respectively, for transmitting and receiving signals between the first and second units;
With
The first unit of the signal processing circuit includes the clock detection circuit according to any one of claims 1 to 6, and when the clock detection circuit detects a stop of the clock signal output from the clock signal generation circuit, An information terminal device, wherein transmission / reception of data between the first and second units is stopped and a transition is made to a power saving mode.   9. The information terminal device according to claim 8, wherein when the clock detection circuit detects the stop of the clock signal, the signal transmission circuit stops the first unit after stopping the second unit. .

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