JP2006309539A - Memory controller, flash memory system and control method of flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flash memory system with high access efficiency to flash memory. <P>SOLUTION: The memory controller for controlling access to a flash memory 11 comprises address registers 23a and 23b for retaining physical addresses on the flash memory 11. In accessing to the flash memory 11, address data based on a physical address retained in the address register 23a is given to the flash memory 11, and a physical address for next access to the flash memory 1 is set in the address register 23b. After the physical address retained in the address register 23a is given to the flash memory 11, the physical address retained in the address register 23b is transferred to the address register 23a and retained therein. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory controller, a flash memory system, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory. Data stored in the flash memory is required to be retained even when power is not supplied.

  A NAND flash memory is a type of flash memory that is particularly frequently used in the above memory system. Each of the plurality of memory cells included in the NAND flash memory receives a logical value “0” from an erased state in which data indicating a logical value “1” is stored, independently of the other memory cells. It is possible to change to a writing state in which the indicated data is stored.

  In contrast, when at least one of the plurality of memory cells must change from a written state to an erased state, each memory cell cannot change independently of the other memory cells. At this time, in a predetermined number of memory cells called blocks, all the memory cells must be simultaneously erased. This batch erase operation is generally called “block erase”. A block that has been subjected to block erase is referred to as an erased block.

  Due to the above features, data cannot be overwritten in the NAND flash memory. In order to rewrite the stored data in the memory cell, after block data including new data is written to the erased block, block erasure for the block storing the old data must be performed.

  The rewritten data is written in a block different from the previously stored block. Therefore, the correspondence between the logical block address specified by the address signal supplied from the host system and the physical block address indicating the actual block address in the flash memory is the same every time data is rewritten in the flash memory. Dynamically adjusted by the controller. For example, the correspondence between logical block addresses and physical block addresses is described in an address conversion table provided in the controller.

For example, in Patent Document 1, a logical block address is converted into a physical block address using an address conversion table. This physical block address is set in the physical block address portion of the physical address register. An initial value is appropriately set in the word address portion of the physical address register. The physical address register supplies the address data held in the physical block address part and the word address part to the flash memory, and increments the value held in the word address part every time the address data is supplied. Yes.
JP-A-9-161491

  However, in Patent Document 1, every time the physical block to be accessed changes, a new physical block address is set in the physical block address portion of the physical address register, and a new initial value is set in the word address portion. Therefore, when a plurality of blocks are continuously accessed, the physical address register resetting process is performed each time, resulting in a problem that the processing efficiency is lowered.

  Therefore, an object of the present invention is to provide a memory controller, a flash memory system including the memory controller, and a flash memory control method capable of improving processing efficiency when continuously accessing a plurality of blocks.

In order to achieve the above object, a memory controller according to the first aspect of the present invention provides:
A memory controller that controls access from a host system to a flash memory having a plurality of physical blocks of multiple pages in a storage area,
Physical block detection means for sequentially detecting the physical blocks to be accessed from logical addresses sequentially given from the host system;
A first address register for holding address data to be given to the memory controller;
A second address register for holding address data to be given to the memory controller;
First address setting means for setting and holding address data corresponding to the physical block detected by the physical block detection means in the first address register;
The physical block to be accessed next to the physical block indicated by the address data held in the first address register is obtained from the detection result of the physical block detecting means, and the address data corresponding to the obtained physical block Second address setting means for setting and holding in the second address register;
Address data supply means for supplying the address data held in the first address register to the flash memory to execute the access;
In response to the address data held in the first address register being supplied to the flash memory, the address data held in the second address register at that time is set in the first address register. Address data changing means to be held,
In response to the address data held in the second address register being held in the first address register, the physical block of the physical block indicated by the address data held in the first address register at that time Next, third address setting means for obtaining a physical block to be accessed from the detection result of the physical block detecting means, and setting and holding address data corresponding to the obtained physical block in the second address register When,
It is characterized by providing.

The first address register includes a main register that holds a part that specifies the physical block of the address data, and a sub-register that holds a part that specifies the page of the address data.
The second address register includes a main register that holds a part that specifies a physical block of the address data, and a sub-register that holds a part that specifies the page of the address data.
The first address setting means includes first initial value setting means for setting an initial value of a sub-register of the first address register,
The second address setting means includes second initial value setting means for setting an initial value of a sub-register of the second address register,
The third address setting means comprises third initial value setting means for setting an initial value of a sub-register of the second address register;
Update means for updating a value held in a sub-register of the first address register may be provided.

  In this case, the updating means may subtract or add one by one to the value held in the subregister of the first address register.

  In addition, in response to the address data held in the second address register being set in the first address register, new address data can be set in the second address register. As a result, in response to the setting of new address data in the second address register, there is provided flag setting means for indicating that new address data cannot be set in the second address register. May be.

  In order to achieve the above object, a flash memory system according to the second aspect of the present invention, a memory controller according to the first aspect of the present invention, and a flash memory are provided.

In order to achieve the above object, a flash memory control method according to a third aspect of the present invention includes:
A flash memory control method for controlling access from a host system to a flash memory having a plurality of physical blocks of multiple pages in a storage area,
Physical block detection processing for sequentially detecting the physical blocks to be accessed from logical addresses sequentially given from the host system;
A first address setting process for setting and holding address data corresponding to a physical block detected by the physical block detection process in a first address register for holding address data to be given to the memory controller;
The physical block to be accessed is obtained from the detection result of the physical block detection process next to the physical block indicated by the address data held in the first address register, and the address data to be given to the memory controller is held. A second address setting process for setting and holding address data corresponding to the obtained physical block in the second address register for;
Address data supply processing for supplying the address data held in the first address register to the flash memory and executing the access;
Responding to the address data held in the first address register being supplied to the flash memory, the address data held in the second address register at that time is stored in the first address register. Address data change processing to be set and retained,
In response to the address data held in the second address register being held in the first address register, the physical block of the physical block indicated by the address data held in the first address register at that time Next, a third address setting process for obtaining a physical block to be accessed from the detection result of the physical block detection process, and setting and holding address data corresponding to the obtained physical block in the second address register When,
It is characterized by performing.

The first address register includes a main register that holds a part that specifies the physical block of the address data, and a sub-register that holds a part that specifies the page of the address data.
The second address register includes a main register that holds a part that specifies a physical block of the address data, and a sub-register that holds a part that specifies the page of the address data.
The first address setting process includes a first initial value setting process for setting an initial value of a sub-register of the first address register,
The second address setting means includes a second initial value setting process for setting an initial value of a sub-register of the second address register;
The third address setting means includes a third initial value setting process for setting an initial value of a sub-register of the second address register;
Update processing for updating the value held in the sub-register of the first address register may be performed.

  In this case, in the update process, the value held in the sub-register of the first address register may be subtracted or added one by one.

  In addition, in response to the address data held in the second address register being set in the first address register, new address data can be set in the second address register. As a result, in response to the setting of new address data in the second address register, a flag setting process is performed to indicate that new address data cannot be set in the second address register. May be.

  According to the present invention, the address data corresponding to the block being accessed is held in the first address register, and the address data of the next block to be accessed is held in the second address register. When the access destination block is switched, the address data held in the second address register is transferred to the first address register. Thereby, it is possible to suppress a decrease in processing efficiency when the access destination block is switched.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram showing a flash memory system 10 according to an embodiment of the present invention.
As shown in FIG. 1, the flash memory system 10 includes a flash memory 11 and a memory controller 20 that controls the flash memory 11. The flash memory system 10 is usually built in various information processing apparatuses that are host systems 30 such as personal computers and digital still cameras that process various information such as characters, sounds, and image information.
The details of the flash memory 11 and the memory controller 20 and the operation of the flash memory system 10 will be described below.
[Description of flash memory 11]
In the flash memory system 10, a flash memory 11 in which data is stored is composed of a NAND flash memory. The NAND flash memory is a non-volatile memory developed for use as a storage device (as an alternative to a hard disk). This NAND flash memory cannot perform random access, and writing and reading are performed in units of pages and erasing is performed in units of blocks. Since data cannot be overwritten, data is written into the erased area when data is written.

  Since NAND flash memory has such characteristics, normally, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data (rewriting is performed). A process of erasing the block in which the previous data) has been written is performed.

  When such data rewriting is performed, the data after rewriting is written in a block different from that before rewriting, so the correspondence between the logical address given from the host system 30 side and the physical address in the flash memory 11 The relationship changes dynamically every time data is rewritten. Accordingly, when accessing the flash memory 11, an address conversion table showing the correspondence between logical addresses and physical addresses is usually created, and the flash memory 11 is accessed using this address conversion table.

FIG. 2 is an explanatory diagram showing the relationship between blocks and pages.
The configuration of the block and page differs depending on the specifications of the flash memory 11, but in a general flash memory, as shown in FIG. 2A, one block is configured with 32 pages (P0 to P31), A page is composed of a user area of 512 bytes and a redundant area of 16 bytes. As the storage capacity increases, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. What is being provided is also provided.

  Here, the user area is mainly an area where data supplied from the host system 30 is stored, and the redundant area is stored with additional data such as error correction code, corresponding logical address information and block status. Area. The error correction code is additional data for detecting and correcting an error included in the data stored in the user area, and is generated by an ECC block described later.

  The corresponding logical address information is written when data is stored in a physical block, and indicates information related to the logical address of the data stored in the physical block. If no data is stored in the physical block, the corresponding logical address information is not written, so whether the corresponding logical address information is written or not is the erased block. Can be judged. That is, if the corresponding logical address information is not written, it is determined that the block is an erased block.

  The block status is a flag indicating whether or not the physical block is a bad block (a physical block in which data cannot be normally written). When the physical block is determined to be a bad block, Is set with a flag indicating that it is a bad block.

Next, the circuit configuration of the flash memory 11 will be described.
A general NAND flash memory includes a register for holding write data or read data and a memory cell array for storing data. The memory cell array includes a plurality of memory cell groups in which a plurality of memory cells are connected in series, and a specific memory cell in the memory cell group is selected by a word line. Data copying (copying from register to memory cell or copying from memory cell to register) is performed between the memory cell selected by the word line and the register.

  A memory cell constituting the memory cell array is composed of a MOS transistor having two gates. Here, the upper gate is called a control gate, and the lower gate is called a floating gate. By injecting charges (electrons) into the floating gate and discharging charges (electrons) from the floating gate, Write and erase data.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When injecting electrons into the floating gate, a high voltage is applied so that the control gate is at the high potential side. When electrons are injected from the floating gate, a high voltage at which the control gate is at the low potential side is applied. Applied to discharge electrons. The state in which electrons are injected into the floating gate (write state) corresponds to data having a logical value “0”, and the state in which electrons are discharged from the floating gate (erased state) has a logical value “1”. Corresponds to data.

[Description of Memory Controller 20]
The memory controller 20 includes a host interface block 21, a microprocessor 22, a flash memory interface block 23, an ECC (Error Collection Code) block 24, a buffer 25, a ROM (Read Only Memory) 26, and an SRAM (SRAM). Static Randam Access Memory) 27, and these elements are integrated on one semiconductor chip. The function of each element will be described below.

The microprocessor 22 is a unit that operates based on a program stored in the ROM 26 and controls the entire operation of the memory controller 20, and uses the storage area of the SRAM 27 as a work area.
A conversion table indicating the correspondence between the logical address (address given to the flash memory system 10) and the physical address (address in the flash memory 11) is created in the storage area of the SRAM 27 by the microprocessor 22.

  The host interface block 21 has a function of relaying commands and logical addresses obtained from the host system 30 via the external bus 31 and giving them to the microprocessor 22 and giving data given from the host system 30 to the buffer 25. The host interface block 21 has a function of transferring a signal supplied from the microprocessor 22 and data held in the buffer 25 to the host system 30.

  The buffer 25 is a functional block for holding data read from the flash memory 11 via the internal bus 12 and data to be written to the flash memory 11. Data read from the flash memory 11 is held in the buffer 25 until it is output to the host system 30. Data to be written to the flash memory 11 is held in the buffer 25 until the data write operation of the flash memory 11 is ready.

  The ECC block 24 is a functional block for generating an error correction code added to the write data to the flash memory 11. In addition, the ECC block 24 detects and corrects errors included in the read data based on the error correction code read together with the data from the flash memory 11.

FIG. 3 is a diagram for explaining the configuration of the flash memory interface block 23 in FIG.
The flash memory interface block 23 is provided with an address register 23a, an address register 23b, an empty flag register 23c, a control block 23d, and a data transfer unit (transfer unit) 23e.

  The address register 23a and the address register 23b hold physical addresses in the flash memory 11 as address data. The address data held in the address register 23 a and the address register 23 b is set by the microprocessor 22.

  The data transfer unit 23 e transfers write data held in the buffer 25 to the flash memory 11 and transfers data read from the flash memory 11 to the buffer 25.

Next, the operation of the flash memory system 10 of FIG. 1 will be described.
The host system 30 gives a command or a logical address for accessing the flash memory 11 to the flash memory system 10. Commands and logical addresses are given to the microprocessor 22 via the host interface block 21. When data is written to the flash memory 11, the data is given from the host system 30 and given to the buffer 25 via the host interface block 21.

The microprocessor 22 decodes the command and converts the logical address into a physical address using the address conversion table of the SRAM 27. Then, the physical address is set in the address register 23 a of the flash memory interface block 23. That is, the physical block corresponding to the block indicated by the logical address is detected by the conversion table, and the address data indicating the detected physical block is set in the address register 23a.
When continuously accessing a plurality of blocks of the flash memory 11, the microprocessor 22 sets and holds the physical address corresponding to the next block to be accessed in the address register 23b.

  When the access to the block corresponding to the physical address held in the address register 23a is completed, the physical address held in the address register 23b is transferred to the address register 23a. Thereafter, address data newly generated based on the physical address held in the address register 23 a is supplied to the flash memory 11.

  The transfer of the physical address from the address register 23b to the address register 23a is controlled by the control block 23d. The control block 23d sets empty information in the empty flag register 23c when the physical address held in the address register 23b is transferred to the address register 23a. This empty information is information indicating that a new physical address can be set in the address register 23b.

  When the microprocessor 22 detects that empty information is set in the empty flag register 23c, the microprocessor 22 sets a new physical address in the address register 23b. Thereafter, the microprocessor 22 releases the vacancy information set in the vacancy flag register 23c.

  Note that the control block 23d preferably confirms that empty information is not set in the empty flag register 23c before the physical address held in the address register 23b is transferred to the address register 23a. This is because when empty information is set in the empty flag register 23c, it indicates that the physical address corresponding to the next access destination block is not set in the address register 23b.

  FIG. 4 is an explanatory diagram of the efficiency of the access processing, and includes the case where there is only one address register (FIG. 4A) and two address registers (address register 23a and address register 23b) according to the present invention. (FIG. 4B).

  When there is only one address register (FIG. 4A), an address conversion process for obtaining a physical address corresponding to the first accessed block is executed (address conversion a). The obtained physical address is set in the address register (register setting a). When a physical address is set in the address register, access to the flash memory 11 is started based on the set physical address (address output a). If this access is a read process for n pages, address data indicating the page to be read is sequentially output for n pages.

  When the access to the first block is completed, an address conversion process for obtaining a physical address corresponding to the block to be accessed second is executed (address conversion b). The obtained physical address is set in the address register (register setting b). When a physical address is set in the address register, access to the flash memory 11 is started based on the set physical address (address output b). If this access is a read process for m pages, address data indicating the page to be read is sequentially output for m pages.

  When the access to the second block is completed, an address conversion process for obtaining a physical address corresponding to the third accessed block is executed (address conversion c). The obtained physical address is set in the address register (register setting c). When a physical address is set in the address register, access to the flash memory 11 is started as described above.

  When two address registers 23a and 23b are provided as shown in FIG. 3 (FIG. 4B), an address conversion process for obtaining a physical address corresponding to the block to be accessed first is executed (address conversion). a). The obtained physical address is set in the address register 23a (register setting a). Subsequently, an address conversion process for obtaining a physical address corresponding to the second accessed block is executed (address conversion b). The obtained physical address is set in the address register 23b (register setting b).

  When the physical address corresponding to the block to be accessed first is set in the address register 23a and the physical address corresponding to the block to be accessed second is set in the address register 23b, the physical address based on the physical address set in the address register 23a is set. Thus, access to the flash memory 11 is started (address output a). If this access is a read process for n pages, address data indicating the page to be read is sequentially output for n pages.

  Note that the address conversion processing (address conversion b) for obtaining the physical address corresponding to the second accessed block and the setting of the physical address in the address register 23b (register setting b) are the physical address set in the address register 23a. It may be executed after starting the access to the flash memory 11 based on the above (address output a).

  When the access to the first block is completed, the physical address set in the address register 23b is transferred to the address register 23a, and the physical address newly stored in the address register 23a (the physical address corresponding to the second block to be accessed) is subsequently transferred. Access to the flash memory 11 is started based on (address) (address output b). If this access is a read process for m pages, address data indicating the page to be read is sequentially output for m pages.

  After the physical address set in the address register 23b is transferred to the address register 23a, an address conversion process for obtaining a physical address corresponding to the block to be accessed third is executed in parallel with the access to the flash memory 11 ( Address translation c). The obtained physical address is set in the address register 23b (register setting c).

  When the access to the second block is completed, the physical address set in the address register 23b is transferred to the address register 23a, and the physical address newly held in the address register 23a (corresponding to the third block to be accessed). Access to the flash memory 11 is started based on the physical address.

  When the two address registers 23a and 23b are provided as described above, the physical address corresponding to the next block to be accessed can be held in advance in one of the address registers 23b. When these blocks are switched, it is possible to continue the access by simply performing the transfer process between the address registers.

  Each of the address registers 23a and 23b may be composed of a main register and a sub register. For example, a physical block address indicating an access destination block is set in the main register, and the page number of the first page accessing the sub register and the number of pages accessed are set.

FIG. 5 is an explanatory diagram of read processing when the address registers 23a and 23b are composed of a main register and a sub register.
In the read process, a read command is supplied to the flash memory 11, and then the address data generated based on the physical address held in the main register of the address register 23a and the page number held in the sub register. (Address a) is supplied. The flash memory 11 outputs data a in response to the supplied read command and address data. The page number and the number of pages held in the subregister are updated every time address data is supplied to the flash memory 11. In this update, the page number is incremented by 1 and the number of pages is decremented by 1.

  When reading data for n pages, n is set as the number of pages to access the sub-register, and the read command and address data are sequentially supplied until the number of pages held in the sub-register becomes zero. In response, data is output from the flash memory 11. After supplying a read command and address data for reading nth page data from the first page, the physical address, page number, and number of pages held in the address register 23b are transferred to the address register 23a.

  After the physical address, page number, and number of pages held in the address register 23b are transferred to the address register 23a, a read command and address data are sequentially supplied in the same manner as described above. Is output.

  On the other hand, when the physical address, page number, and number of pages held in the address register 23b are transferred to the address register 23a, the control block 23d sets empty information in the empty flag register 23c. When the microprocessor 22 detects that empty information is set in the empty flag register 23c, the microprocessor 22 sets a new physical address, page number, and number of pages in the address register 23b. After setting a new physical address, page number, and number of pages in the address register 23b, the microprocessor 22 cancels the empty information set in the empty flag register 23c. In this manner, a new physical address, page number, and number of pages are set in the address register 23b in parallel with the access to the flash memory 11.

  As described above, since the flash memory system 10 of the present embodiment includes the two address registers 23a and 23b, the physical address corresponding to the block to be accessed next is held in advance in one address register 23b. Therefore, when the access destination block is switched, the access can be continued only by performing the transfer process between the address registers, and the access efficiency can be improved.

1 is a configuration diagram of a flash memory system according to an embodiment of the present invention. It is explanatory drawing which shows the relationship between a block and a page. It is a figure explaining the structure of the flash memory interface block in FIG. It is explanatory drawing of the efficiency of an access process. It is explanatory drawing of the reading process at the time of comprising an address register with a main register and a sub register.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Flash memory system 11 Flash memory 20 Memory controller 21 Host interface block 22 Microprocessor 23 Flash memory interface block 23a Address register 23b Address register 23c Empty flag register 23d Control block 23e Transfer part 24 ECC block 25 Buffer 26 ROM
63 SRAM

Claims (9)

A memory controller that controls access from a host system to a flash memory having a plurality of physical blocks of multiple pages in a storage area,
Physical block detection means for sequentially detecting the physical blocks to be accessed from logical addresses sequentially given from the host system;
A first address register for holding address data to be given to the memory controller;
A second address register for holding address data to be given to the memory controller;
First address setting means for setting and holding address data corresponding to the physical block detected by the physical block detection means in the first address register;
The physical block to be accessed next to the physical block indicated by the address data held in the first address register is obtained from the detection result of the physical block detecting means, and the address data corresponding to the obtained physical block Second address setting means for setting and holding in the second address register;
Address data supply means for supplying the address data held in the first address register to the flash memory to execute the access;
In response to the address data held in the first address register being supplied to the flash memory, the address data held in the second address register at that time is set in the first address register. Address data changing means to be held,
In response to the address data held in the second address register being held in the first address register, the physical block indicated by the address data held in the first address register at that time Next, third address setting means for obtaining a physical block to be accessed from the detection result of the physical block detecting means, and setting and holding address data corresponding to the obtained physical block in the second address register When,
A memory controller comprising: The first address register includes a main register that holds a part that specifies the physical block of the address data, and a sub-register that holds a part that specifies the page of the address data,
The second address register includes a main register that holds a part that specifies a physical block of the address data, and a sub-register that holds a part that specifies the page of the address data.
The first address setting means includes first initial value setting means for setting an initial value of a sub-register of the first address register,
The second address setting means includes second initial value setting means for setting an initial value of a sub-register of the second address register,
The third address setting means comprises third initial value setting means for setting an initial value of a sub-register of the second address register;
2. The memory controller according to claim 1, further comprising updating means for updating a value held in a sub-register of the first address register.   3. The memory controller according to claim 2, wherein the updating unit performs subtraction or addition by one on a value held in a sub-register of the first address register.   In response to the address data held in the second address register being set in the first address register, it indicates that new address data can be set in the second address register; As a result, in response to the setting of new address data in the second address register, there is provided flag setting means for indicating that new address data cannot be set in the second address register. The memory controller according to claim 1, wherein the memory controller is a memory controller.   A flash memory system comprising the memory controller according to any one of claims 1 to 4 and a flash memory. A flash memory control method for controlling access from a host system to a flash memory having a plurality of physical blocks of multiple pages in a storage area,
Physical block detection processing for sequentially detecting the physical blocks to be accessed from logical addresses sequentially given from the host system;
A first address setting process for setting and holding address data corresponding to a physical block detected by the physical block detection process in a first address register for holding address data to be given to the memory controller;
The physical block to be accessed is obtained from the detection result of the physical block detection process next to the physical block indicated by the address data held in the first address register, and holds the address data to be given to the memory controller. A second address setting process for setting and holding address data corresponding to the obtained physical block in a second address register for;
Address data supply processing for supplying the address data held in the first address register to the flash memory and executing the access;
Responding to the address data held in the first address register being supplied to the flash memory, the address data held in the second address register at that time is stored in the first address register. Address data change processing to be set and retained,
In response to the address data held in the second address register being held in the first address register, the physical block indicated by the address data held in the first address register at that time Next, a third address setting process for obtaining a physical block to be accessed from the detection result of the physical block detection process, and setting and holding address data corresponding to the obtained physical block in the second address register When,
And a flash memory control method. The first address register includes a main register that holds a part that specifies the physical block of the address data, and a sub-register that holds a part that specifies the page of the address data,
The second address register includes a main register that holds a part that specifies a physical block of the address data, and a sub-register that holds a part that specifies the page of the address data.
The first address setting process includes a first initial value setting process for setting an initial value of a sub-register of the first address register,
The second address setting means includes a second initial value setting process for setting an initial value of a sub-register of the second address register;
The third address setting means includes a third initial value setting process for setting an initial value of a sub-register of the second address register;
The flash memory control method according to claim 6, wherein an update process for updating a value held in a sub-register of the first address register is performed.   8. The flash memory control method according to claim 7, wherein the update processing subtracts or adds one by one to a value held in a sub-register of the first address register.   In response to the address data held in the second address register being set in the first address register, it indicates that new address data can be set in the second address register; As a result, in response to the setting of new address data in the second address register, flag setting processing indicating that new address data cannot be set in the second address register is performed. 9. The flash memory control method according to claim 6, wherein

Images