JP2006302132A - Signal processor, reconfigurable logic circuit device and reconfigurable sequential circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor which dynamically configures hardware and reconfigures the hardware according to an interruption request. <P>SOLUTION: The signal processor is provided with: a logic circuit part starting part 7 which generates a starting signal S8 for starting a logic circuit part being reconfigurable hardware from an interruption source; a reconfiguration data control part 6 constituted of a memory part 61 for definition which is a memory of bank configuration storing configuration data for determining configuration of a logic circuit part 5 being the reconfigurable hardware and in which output of the selected bank memory always acts on the logic circuit part as logic circuit part data; and the logic circuit part 5 for changing configuration of the hardware according to the contents of the logical circuit part data and a reconfiguration trigger signal S7. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a circuit device related to a logic circuit section, and more particularly to a reconfigurable embedded signal processing device and a reconfigurable logic circuit capable of changing the configuration of a logic circuit by providing definition data. Circuits related to logic circuit units, such as a dynamic reconfigurable logic circuit device that can change the configuration of a logic circuit in units of clocks, and a sequential circuit that can control the operation of other circuits in a digital circuit It relates to the device.

A conventional signal processing apparatus is shown in FIGS.
The conventional signal processing apparatus is a hardware having a small circuit scale and can execute image processing and an auxiliary accelerator function. In FIG. 19, image data that cannot be processed at the requested speed is sent from the arithmetic unit 120 to the non-real-time path 124 via the arithmetic unit I / F 122 and processed, and then designated via the arithmetic unit I / F. To the address of the storage device.
If necessary, the transferred data is further processed by the arithmetic unit, or repeatedly processed by the non-real time path, or transferred to the real time path 123 and finally sent to the output device 126. Image data that can be processed at the required speed is sent directly to the real-time path 123 via the arithmetic unit I / F.
The image data sent to the real-time path is output to the output device 126 via the output device I / F 125. In FIG. 20, the arithmetic unit I / F 122 includes an input buffer 221 and a path determination unit 222.
The non-real time path 124 includes a reconfiguration data control unit 6, a logic circuit unit 5, a work memory 241, and an output buffer 242. Image data to which a path is determined by the arithmetic device 120 and necessary header information is added is sent to the arithmetic device I / F 122. The arithmetic device I / F stores the image data in the input buffer 221, and the path determination unit 222 determines the data transmission direction based on real-time or non-real-time identification written in the header information.
The header information is sent to the reconfiguration data control unit, and the reconfiguration data control unit loads the processing contents to be operated next written in the header information into the logic circuit unit. The input buffer 221 sends data to be processed through the non-real time path 124 to the logic circuit unit 5. The logic circuit unit performs arithmetic processing using the work memory 241, sends the result to the output buffer 242, and the output buffer transfers the memory address written in the header (see, for example, Patent Document 1). The logic circuit unit of the conventional example is configured by a dynamically programmable rewritable FPGA (Field Programmable Gate Array) element. Thus, the conventional signal processing apparatus executes the logic circuit unit after analyzing the header information. is there. Furthermore, it is used in fields that do not require real time.

Further, as shown in FIG. 21, the conventional reconfigurable logic circuit device includes a logic circuit unit 13 in which the connection relation of internal logic elements is specified according to definition data, and definition data to be given to this logic circuit unit. And a definition memory unit 12 that stores the definition data, and the definition memory unit selectively loads the definition data from one of the two volatile memories and the volatile memory into the logic circuit unit. Means. Thus, since the volatile memory is provided as a set as the definition memory, the definition data to be loaded into the logic circuit unit can be changed only by switching the selection of the volatile memory by the selection control means ( Patent Document 2).
As described above, the conventional reconfigurable logic circuit device has a plurality of definition data, and changes the function of the logic circuit unit 13 by switching and reading the data.
A conventional reconfigurable sequential circuit is shown in FIG.
A memory 100 capable of repeatedly performing sequential reading, a state storage means 300 in which content corresponding to final content sequentially read from the memory 100 is set as a current state, an externally input transition condition, The transition condition storage means 200 is configured to cause the memory 100 to sequentially read in accordance with the setting contents of the state storage means 300 (see Patent Document 3).
Thus, the conventional reconfigurable sequential circuit configures the state transition circuit by a combinational circuit that is not affected by the complexity of the state transition condition.
JP-A-11-147335 (FIGS. 2 and 4) Japanese Patent Laid-Open No. 5-63551 (FIG. 1) Japanese Patent Laid-Open No. 14-169687 (FIG. 1)

However, since the signal processing device of Patent Document 1 is activated after analyzing the contents of the header information, there is a problem that latency from a processing request in the logic circuit unit to a start increases. Therefore, it has the problem that it can be used only in fields that do not require real-time performance.
In addition, since the FPGA is used as the logic circuit unit, the read of the memory storing the reconfiguration data and the change of the elements constituting the logic circuit unit are sequentially performed. Has a problem that it takes several milliseconds or more. This means that in a signal processing device that operates at a system clock level of MHz or higher, hardware reconfiguration cannot be performed dynamically at the system clock level, and the operation of the signal processing device stops for reconfiguration. There is also the problem of end up.
Further, there is a further problem that the system level of the signal processing device becomes large, such as analysis processing of header information and use of FPGA.

In the reconfigurable logic circuit device disclosed in Patent Document 2, since the definition data of the logic circuit unit having a size larger than at least the output port of the memory is stored in the memory, the memory read circuit is read into the selection controller. A definition data holding circuit is required. In particular, since the data in the logic circuit section is large, the definition data holding circuit is a factor that increases the circuit scale. In order to change the function, the definition data must be read once from the memory. Therefore, there is a problem that the dynamic definition data cannot be switched in units of clocks.
Furthermore, since the definition data is switched by the CPU, there is a problem that the CPU is necessarily required in the apparatus.
Further, in the reconfigurable sequential circuit of Patent Document 3, only the state transition can be reconfigured. Therefore, the output signal is a state, and it is necessary to interpret the state in the receiving circuit. This has the problem that redesign occurs even if a circuit controlled by a sequential circuit is provided by IP.
Further, when the IP is not redesigned, some state interpretation circuit is required, so that there is a problem that a separate circuit is required. At the same time, there was a problem that it could not cope with the increase or decrease of the input signal.
In addition, in order to search the state after the transition from the input signal, the input signal is sequentially used as the address of the read memory, and the memory read time unnecessary for the state transition is added, and the state and the input signal The memory procedure is determined by the number of combinations, and a large amount of memory capacity is required.

The first invention of the present invention has been made in view of such problems, and by dynamically configuring the hardware and reconfiguring the hardware in response to an interrupt request, the operation can be performed. An object of the present invention is to provide a signal processing apparatus that minimizes the latency.
According to the second aspect of the present invention, definition data can be changed in units of clocks, management of definition data is facilitated by an index or the like, and its own circuit change is determined based on a calculation result of a logic circuit unit, and the LSI is realized. An object of the present invention is to provide a reconfigurable logic circuit device capable of suppressing the circuit scale so as to be optimal.
It is an object of the third invention of the present invention to provide a reconfigurable sequential circuit capable of suppressing the memory capacity without requiring circuit redesign.

In order to achieve the above object, a signal processing device having a reconfigurable circuit device includes a CPU, a memory, an I / O device group, and an interrupt controller, and is accessed from the CPU. Inputs n interrupt sources generated by a group of possible I / O devices, generates a logic circuit unit activation signal from a certain interrupt source, and requests an interrupt request from the logic circuit unit ACK signal and other interrupt sources to the interrupt controller An index register set by the CPU that holds a bank number of a bank memory used as logic circuit unit data and generates a reconfiguration trigger signal when the bank number is changed; A bank-structured memory that stores configuration data that determines the configuration of the logic circuit, and the output of the selected bank memory is A reconfigurable data control unit that is configured by a definition memory unit that always acts on the logic circuit unit as logic circuit unit data and is accessible from the CPU, and is arithmetically processed by the logic circuit unit activation signal that is accessible from the CPU And a logic circuit unit that outputs a logic circuit unit ACK signal after completion of arithmetic processing and changes the hardware configuration in accordance with the contents of the logic circuit unit data and the reconfiguration trigger signal.
According to a second aspect of the present invention, in the signal processing device according to the first aspect, the logic circuit unit activation unit generates a logic circuit unit activation signal from an interrupt source that is accessible from the CPU and receives a request. Generates the encoded data of the state and a reconfiguration data selection signal that is a signal for changing the contents of the index register, and the logic circuit unit ACK signal and other interrupt sources that are not accepting requests from the interrupt controller to the interrupt controller An interrupt request is generated, and the index register is set by the CPU or a reconfiguration data selection signal.
According to a third aspect of the present invention, there is provided the signal processing device according to the second aspect, wherein the logic circuit unit is implemented by using the reconfiguration data selection signal and the logic circuit unit data in the logic circuit unit. An allocation control unit for controlling allocation of basic elements is provided.
According to a fourth aspect of the present invention, in the signal processing device according to the third aspect of the present invention, a hardware sequencer including an FSM (Finite State Machine) is used instead of the CPU, the interrupt controller, and the memory. Yes.

According to a fifth aspect of the present invention, there is provided a reconfigurable logic circuit device including a definition memory and a logic circuit unit capable of changing a circuit configuration according to the contents of the definition memory. And a logic circuit unit in which the definition data of one PE is smaller than the output port width of the memory, and N sets of definition data can be stored in one-to-one correspondence with each PE in an array of elements N It is characterized by comprising a definition memory section composed of definition array memories prepared for the number of PEs.
According to a sixth aspect of the present invention, there is provided a wiring unit in which the PE reconstructs wiring between a plurality of inputs entering the PE and an output to the arithmetic unit according to the contents of the definition array memory. It is characterized by comprising a calculation unit that changes the processing of calculation in accordance with the contents of the definition array memory.
The invention described in claim 7 is characterized by comprising an index register for outputting an address for selecting the definition array memory.
According to an eighth aspect of the present invention, the definition array memory is a two-dimensional array in which data can be specified from rows and columns, the index register is composed of a row selection unit and a column selection unit, and the row selection unit and the column selection unit It is characterized by comprising with PE which changes a structure by the content of.
The invention described in claim 9 is characterized in that the setting value of the index register is changed by the operation result of the logic circuit section.

The invention according to claim 10 can cope with increase / decrease of the circuit in the sequential circuit that includes the reconfigurable circuit device and generates the output signal from the state generated by the internal circuit using the input signal as a transition condition. A memory control unit that includes an input signal having a bit width and generates a state from the control signal, and a state interpretation that generates a state interpretation signal that stores the association between the operation in the state and the input signal using the state as an address A memory and a memory composed of an output generation memory having a bit width capable of accommodating an increase / decrease in a circuit by storing an output signal corresponding to the state by using the state as an address, from the state interpretation signal and the input signal; A state control unit that generates a control signal for the memory control unit is provided.
The invention according to claim 11 is characterized in that encoded data is stored in the output generation memory, and a decoder is provided in a subsequent stage of the output generation memory.
According to a twelfth aspect of the present invention, the state control unit includes a lookup table.
The invention described in claim 13 is characterized in that the reconfigurable sequential circuit is used as a control unit of a reconfigurable data path for executing arithmetic processing.

According to the first aspect of the present invention, since the logic circuit unit can be activated with a minimum latency for an interrupt request of an arbitrary system, the real-time property of the system can be improved. Further, since the logic circuit section data of the selected bank can always be output, the hardware reconfiguration can be made very short.
According to the second aspect of the present invention, in addition to the effect of the first aspect, hardware processing for an arbitrary interrupt request can be shared by one logic circuit unit. Since the number of active circuits can also be reduced, power consumption can be reduced.
According to the third aspect of the invention, in addition to the effects of the first and second aspects, the logic circuit unit can be activated with a minimum latency for an arbitrary interrupt request of an arbitrary system. , The real-time nature of the system can be improved. Since arbitrary interrupt requests can be duplicated, the latency of switching processing in multiple interrupts can be suppressed, which can contribute to further improvement of real-time performance.
According to the fourth aspect of the invention, in addition to the effects of the first, second, and third aspects, since the components having a large number of gates such as a memory and a CPU are not used, the number of gates of the entire signal processing device can be reduced. Thus, the LSI can be reduced in size.
According to the fifth aspect of the present invention, the definition data can be changed in a very short time of changing the address by dividing the memory and making the definition data for each PE as small as a word unit. It becomes like this. Further, reading of the memory for holding data and holding of the read data can be eliminated, and the circuit size can be suppressed.
Since the circuit can be changed by rewriting the address of the definition address memory, it is possible to easily implement a state machine, particularly a state machine using a C language switch statement.
According to the invention described in claim 6, the configuration data of the wiring between the PEs and the wiring in the PE can be managed in common. Furthermore, the degree of freedom for changing the wiring in the PE can be increased.
According to the invention described in claim 7, management of the definition array memory can be facilitated.
According to the eighth aspect of the present invention, the PE configuration can be changed according to the contents of the row selection unit and the column selection unit, and a PE suitable for the application can be prepared.
According to the ninth aspect of the present invention, since the contents of the index register can be changed by the operation result of the logic circuit unit, the circuit configuration can be changed according to the environment. Further, processing equivalent to software can be performed without a CPU, and an LSI can be created without mounting a CPU or memory. Therefore, the die area of the LSI can be reduced.
According to the tenth aspect of the present invention, since the control signal and the output signal can be generated separately from the state interpretation memory and the output generation memory using the state as an index, it can be adapted to the input signal and output signal of an arbitrary circuit. become able to. Since state transition control and output generation can be performed independently, different outputs can be obtained with the same state transition, and conversely, different state transitions can be taken with the same output.
Furthermore, the number of changes for reconfiguration can be reduced. Since state interpretation and output generation can be considered for a state, creation of an arbitrary state transition can be simplified.
According to the eleventh aspect of the present invention, the memory capacity of the output generation memory can be compressed, and a sequential circuit having a smaller circuit scale can be obtained.
According to the invention described in claim 12, the circuit configuration of the state control unit can be changed, and the operation of the control signal of the memory control unit can be changed.
According to the thirteenth aspect of the present invention, both the sequential circuit for performing control and the data path for performing computation can be reconfigured, and high processing capability and software flexibility can be achieved. By applying to the ASIC, the control unit and the data path of the ASIC can be reconfigured according to the application, so that one ASIC can be a hardware platform that can be used for a plurality of applications.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the signal processing apparatus according to the first embodiment of the present invention.
In FIG. 1, the I / O device group 3 connected to the bus S4 generates n interrupt sources S1 that are input to the logic circuit unit activation unit 7 that activates reconfigurable hardware. The logic circuit unit activation unit 7 generates a logic circuit unit activation signal S8 for activating the logic circuit unit 5 using one of the interrupt sources. Since the logic circuit unit 5, which is reconfigurable hardware, returns the logic circuit unit ACK S9 after the processing is completed, this signal is used as a new interrupt source and used as an unprocessed n-1 interrupt source. In addition, n interrupt requests S5 to be input to the interrupt controller 4 are generated.
The interrupt source that generates the start signal S8 for starting the reconfigurable hardware (logic circuit unit) can be selected arbitrarily, but it has the highest priority and is a periodic interrupt that requires the most real-time capability. High effect can be obtained. The interrupt controller 4 inputs the interrupt S2 to the CPU 1, and the CPU 1 returns an interrupt ACK S3 after the processing is completed. The reconfiguration data control unit 6 includes a definition memory unit (reconfiguration data storage unit) 61 including a memory in which logic circuit unit data S6 is held.
The memory of the definition memory unit 61 has a bank configuration, and new logic circuit unit data S6 is output each time the bank is switched. For this bank switching, the index register 62 is used as a reconfiguration data selection register. The index register 62 is set by the CPU 1, and when the set value is changed, a reconfiguration trigger signal S7 for instructing the reconfiguration of the logic circuit unit 5 is generated. In the logic circuit unit 5, when the reconfiguration trigger signal S7 is generated, the logic circuit unit data S6 is operated to reconfigure the hardware.
The difference between the present invention and Patent Document 1 is that the logic circuit unit activation unit 7 is added and the logic circuit unit data S6 is always output.

Next, Example 2 will be described with reference to the drawings.
FIG. 2 is a block diagram illustrating the configuration of the signal processing apparatus according to the second embodiment.
An operation point different from that of the first embodiment will be described. In FIG. 2, in the logic circuit unit activation unit 7, n interrupt sources S1 are arbitrated based on, for example, priority, and one interrupt source is selected. Using this selected interrupt source, the logic circuit unit activation signal S8 is generated. At the same time, a reconfiguration data selection signal S10 indicating which interrupt source has been selected is generated. The reconfiguration data selection signal S10 rewrites the data held in the index register 62, whereby the bank of the definition memory unit 61 is changed, and the reconfiguration of the logic circuit unit 5 is executed in synchronization with the interrupt.
This embodiment is different from the previous embodiment in that the reconfiguration data selection signal S10 is generated by the logic circuit section activation unit 7 of the first embodiment and is changed so as to act on the index register 62.

Next, Example 3 will be described with reference to the drawings.
FIG. 3 is a block diagram illustrating the configuration of the signal processing apparatus according to the third embodiment.
Operations different from those in the first and second embodiments will be described. In FIG. 3, the logic circuit unit 5 causes the logic circuit unit data S <b> 6 to act by using the reconfiguration trigger signal S <b> 7 as a trigger to perform hardware reconfiguration.
In this reconfigured state, when there are unused basic elements, the allocation control unit 51 manages which reconfiguration data selection signal S10 and the basic elements are used. Here, when a new interrupt source occurs, a reconfiguration trigger signal S7 is generated, and the logic circuit section data S6 is also updated. The allocation control unit 51 controls the masking of the reconstruction trigger signal S7 to the basic element being used so that only the part that has not been used can be reconfigured. Then, the reconfigured basic element and the reconfiguration data selection signal S10 are newly managed as a pair.
This embodiment is different from the first and second embodiments in a portion including an allocation control unit 51 that controls allocation of basic elements for realizing the logic circuit unit 5.

Next, Example 4 will be described with reference to the drawings.
FIG. 4 is a block diagram showing the configuration of the signal processing apparatus according to the fourth embodiment.
Operations different from those of the first, second, and third embodiments will be described. In FIG. 4, the hardware sequencer 8 is a control sequence that is described as a program in the CPU and is realized by hardware using an FSM (Finite State Machine). The FSM is, for example, each sequence called a state transition table expressed in a table format, and switching of the sequence is performed in synchronization with the interrupt request S5.
The main arithmetic processing of the interrupt processing is performed by the logic circuit unit 5, and processing such as communication with the host is performed using the I / O device group 3 by operating the bus.
This embodiment is different from the first, second, and third embodiments in that a hardware sequencer 8 is provided instead of the CPU and the memory.
As mentioned above, Example 1- Example 4 is description regarding 1st invention applicable to Claims 1-4.

Next, Example 5 will be described with reference to the drawings. (Hereinafter, Examples 5 to 8 are portions related to the second invention corresponding to claims 5 to 8).
FIG. 5 is a block diagram of the reconfigurable logic circuit device according to the fifth embodiment.
In FIG. 5, the reconfigurable logic circuit device 11 includes a definition memory 12 and a logic circuit unit 13. The definition memory 12 is a memory that stores data in which the circuit configuration of the logic circuit unit 13 is defined. The output of the definition memory unit 12 is operated to change the circuit configuration of the logic circuit unit 13. The logic circuit unit 13 is composed of one or more PEs (processor elements), and each PE is interconnected.
In addition, input / output signals are also interconnected with the PE. In FIG. 5, inputs are connected to PE1 31 and PE2 32, and outputs are connected to PE3 33 and PE4 34. After the circuit configuration is defined, the logic circuit unit 13 is equivalent to a dedicated circuit, performs an operation using an input signal, and transfers the result as an output signal outside the reconfigurable logic circuit device 11.

Reconfiguration of the interconnected wiring and the arithmetic circuit is performed inside the PE, and the connection between the PEs is fixed. The definition memory unit 12 includes four memories, that is, a definition array memory 1 21 to a definition array memory 424 corresponding to the PE one-to-one. Each definition array memory stores N sets of data for changing the internal configuration of the PE in the form of an array. The PE is divided into a plurality of pieces, and each definition data is held to be equal to or smaller than the memory output port width.
Accordingly, by fixing the control signal to the definition array memory, the memory output can be held, and a complicated circuit such as the selection control unit disclosed in Patent Document 2 can be eliminated. In the conventional example, the volatile memory corresponds to the definition data of the entire logic circuit unit. However, the definition array memory of this embodiment is merely a definition memory for PE, and the entire output of the definition memory unit 12 is. Becomes the definition data of the logic circuit section 13. In this example, there are four PEs and four definition array memories corresponding thereto, but the number is not limited to this.
The implementation of the definition array memory may be a two-dimensional array. The definition array memory may be a non-volatile memory or a volatile memory. In the case of a volatile memory, a process for writing data into the definition array memory after power-on is required.
This embodiment is different from Patent Document 2 in that the definition memory is divided, the logic circuit section is composed of PE, and the selection control section is excluded.

FIG. 6 is a detailed block diagram of the configurable logic circuit device according to the fifth embodiment shown in FIG. FIG. 6 shows details of PE1 shown in FIG. 5. The operation of the embodiment 5 will be described with reference to FIG.
The logic circuit unit 13 that performs the operation is connected to 14 registers 14 as input / output data. PE1 31 creates one calculation result from three inputs, and inputs it to PE3 33 and PE4 34. The PE1 has an ALU1 18 and an ALU2 19 as arithmetic units for executing operations. The input of ALU1 is connected to SW1 15 and SW2 16, and SW1 and SW2 connected to the register 14 determine the register to be input using the data in the definition array memory 121 of the definition memory unit 12. .

FIG. 7 shows two types of opcodes. FIG. 7A shows the operation code of the fifth embodiment. ALU1 and ALU2 perform four operations according to the operation code. This opcode is also part of the definition array memory. ALU2 has the output of ALU1 and the output of SW3 17 as inputs. The array memory for definition of PE1 31 is composed of 12 bits SW1, SW2 and SW3 and 4 bits ALU1 and ALU2 for a total of 16 bits.
In a 16-bit port output memory as in this embodiment, the memory itself has a data holding function, and therefore it is not necessary to have a data holding function after the memory. Therefore, in this embodiment, which has four PEs and each PE has the same structure, 64-bit definition data is required.
In the conventional example, it is necessary to output 64-bit data from one memory, and a memory having a 16-bit or 32-bit width output port requires an external holding function such as a flip-flop. In this embodiment, since the data in the definition array memory can be switched by switching the address, switching can be performed in units of clocks. Furthermore, since the definition array memory is associated with each PE, it is possible to perform data switching control in units of PEs. As a result, 64 bits can be supported. In this way, the same operation as that of the fifth embodiment is executed using the operation code of FIG.
FIG. 7B shows an operation code that can execute an operation different from that in the fifth embodiment (this will be described later).

Next, Example 6 will be described with reference to the drawings.
FIG. 8 is a block diagram of a reconfigurable logic circuit device showing the configuration of the sixth embodiment.
Since all PEs have the same configuration, PE1 31 will be described as a representative example. In FIG. 8, a wiring unit 1 311 selects an input to the calculation unit 1 312 and the wiring unit 2 314 from a plurality of inputs based on the data in the definition array memory. Some inputs of the wiring section 1 311 are not used for calculation at a certain point in time, and this redundancy increases the degree of freedom of input. The calculations of the calculation unit 1 312 and the calculation unit 2 313 are also determined based on the data in the definition array memory. The outputs of the calculation unit 1 and the calculation unit 2 are connected to the wiring unit 2 314, and the output is selected based on the data in the definition array memory. In this example, there are two arithmetic units. However, the number of arithmetic units is not limited to two, and complex arithmetic operations can be handled by providing many arithmetic units. The same applies to the wiring part. This embodiment is different from the previous embodiment in the configuration of PE composed of a wiring unit and a calculation unit.

Next, Example 7 will be described with reference to the drawings.
FIG. 9 is a block diagram of a reconfigurable logic circuit device showing the configuration of the seventh embodiment.
In FIG. 9, the index register 20 is arranged before the input of the definition array memory unit 12 (definition array memories 21 to 24). The index register 20 can be read and written from an external CPU or the like, and the data in the definition array memories 21 to 24 in the definition memory unit 12 can be changed by changing the index register 20.
This embodiment is different from the previous embodiment in that the index register 20 is added.

Next, a modification of the seventh embodiment will be described with reference to the drawings.
FIG. 9B is a block diagram of a reconfigurable logic circuit device showing a configuration of a modified example of the seventh embodiment.
In FIG. 9B, the index register 20 includes a column selection unit 20a and a row selection unit 20b. Further, the definition array memory unit 120 is configured in a two-dimensional array, and addresses are designated by the outputs of the column selection unit 20a and the row selection unit 20b of the index register 20. This two-dimensional array is a definition two-dimensional array memory unit 120 (definition two-dimensional array memories 121 to 124). Similar to the fifth embodiment, the PE (FIG. 5) is reconfigured with the contents of the row selection unit 20b. Further, the PE configuration is changed according to the contents of the column selection unit 20a. For example, when the row selection unit is 1 bit, 0 and 1 can be taken as values.
In the case of 0, ALU1 and ALU2 in FIG. 6 are reconfigured to execute the opcode in FIG. In this case, the same calculation as in the fifth embodiment can be performed.
Next, in the case of 1, ALU1 and ALU2 in FIG. 6 are reconfigured to execute the opcode in FIG. 7B. In this case, an operation different from that in the fifth embodiment can be executed. This is equivalent to preparing different PEs according to the contents of the column selection unit 20a, and allows the PEs to be specified according to the application. This embodiment is different from the seventh embodiment in the configuration of the index register 20, the definition array memory unit 120, and the PE (FIG. 5).

Next, Example 8 will be described with reference to the drawings.
FIG. 10 is a block diagram of a reconfigurable logic circuit device showing the configuration of the eighth embodiment.
In FIG. 10, index registers 20 are arranged in all stages of inputs of the definition array memory 1 21 to the definition array memory 4 24.
The index register 20 is connected to an output that is a calculation result of the logic circuit unit 13, and changes the value of the index register 20 using the calculation result. With this configuration, the logic circuit unit 13 calculates a change condition of the logic circuit unit and changes the index register 20, so that circuit reconfiguration that can be said to be adjustment of the logic circuit unit 13 can be executed.
Further, the circuit can be reconfigured only by the reconfigurable logic circuit device 11. For example, it is possible to provide a device in which a difference in the external environment is calculated by the logic circuit unit 13 and the logic circuit unit 13 can be changed so as to suit the environment, and the circuit does not need to be readjusted even if the environment changes. Become.
The index register 20 can be read and written from an external CPU or the like, and can be changed from the CPU. This embodiment is different from the previous embodiment in that the index register 20 and the index register 20 can be changed based on the calculation result of the logic circuit section 13.

Next, Example 9 will be described with reference to the drawings.
Examples 9 to 12 are parts corresponding to the third invention.
FIG. 11 is a block diagram of a reconfigurable sequential circuit according to the ninth embodiment of the present invention.
In FIG. 11, the reconfigurable sequential circuit 41 includes a memory 42 and a state control unit 301. The memory 42 includes a state interpretation memory 101, an output generation memory 102, and a memory control unit 103. The input signal S11 as a transition condition is a signal having an n1 bit width, and this bit width has a certain margin so as to be able to cope with an increase or decrease in circuits attached to the outside. The input signal S11 is input to the state control unit 301.
The state control unit 301 also receives a state interpretation signal S15 that is an output of the state interpretation memory 101, and generates a control signal S14 for controlling the memory control unit 103 based on these two signals. The memory control unit 103 operates according to the control signal, and generates the state S13. The state S13 acts as an address of the state interpretation memory 101 and the output generation memory 102. The state interpretation memory 101 generates a state interpretation signal S15, and the output generation memory 102 generates an n2-bit output signal S12. The output signal S12 is also a signal having a sufficient number of bits so as to cope with the increase or decrease of the external circuit.

If there is no branching in this state transition,
-Transition to the next state (go)
-Hold the state until a certain transition condition is met (wait)
・ Transition to a certain state (jump)
Control may be performed. Furthermore, when branching is necessary,
A sequential circuit that takes an arbitrary state can be obtained by adding to the control (if-else-) a transition to state A in a certain transition state and transition to state B otherwise. In addition, this makes it possible to use a fixed state circuit as the logic of state transition, which conventionally forms a combinational circuit individually, and makes it possible to realize the reconfigurable sequential circuit of the present invention.
The present invention is different from Patent Document 3 in that the state interpretation memory 101 and the output generation memory 102 are provided, and the state interpretation memory 101 is provided with a state register function.

  FIG. 12 is a block diagram of a circuit using the reconfigurable sequential circuit shown in FIG. FIG. 12 shows an example in which the CPU 4 and two external circuits, the circuit 12 and the circuit 23 are connected, and both the input signal and the output signal are 4-bit signals. In either case, one bit is not used, but when the number of circuits increases, it is possible to deal with this unused signal. Therefore, it is possible to cope with the increase / decrease of the external circuit by providing a margin for the bit width of the input / output signal for the physical signal line. The logical correspondence will be described below.

FIG. 13 is a diagram showing the contents of the state interpretation memory 101.
In FIG. 13, the state S13 is used as an address, and the content of the address indicated by the state S13 is output as the state interpretation signal S15.
(1) When the state is 0,
The wait S21 is the contents of the state interpretation memory. The state holds 0 until the input signal 1 S21 becomes true, and when the input signal 1 S21 becomes true, the state transitions to 1 which is the next state.
(2) Similarly, when the state is 1, the state transition is controlled by the state of the input signal 2 S22 in wait S22.
(3) When the state is 2,
In wait S23, the state transition is controlled by the state of the input signal 3 S23.
When the state is 3,
At jump 0, the state transitions to 0 unconditionally. A new state can be reconfigured by changing the contents of the state interpretation memory. Furthermore, using an input signal for the transition state is a logical correspondence.

Next, FIG. 14 shows the contents of the output generation memory 102.
Although the state is also used as an address in FIG. 14, the output is an output signal in this state.
(1) When in state 0,
In the case of all 0, the output signals 1 to 4 S31 to S34 are all 0 signals.
In state 1,
In make S31, the output signal 1 is 1 and the others are 0.
(2) In state 2,
In make S32, the output signal 2 is 1 and the others are 0.
(3) In state 3,
In make S33, the output signal 3 becomes 1, and the others become 0.
The output signal can be reconfigured by changing the contents of the output generation memory. The logical correspondence is that the output signal can be associated with the state. Furthermore, since the state interpretation memory 101 and the output generation memory 102 are independent, the degree of freedom of reconfiguration is increased by generating different output signals in the same state.

The operation waveform at this time is shown in FIG.
This figure is described in positive logic (true when 1). When the input signal 1 S21 is 0, the state is maintained as 0, and the output signals 1 to 4 S31 to S34 are all 0. When the input signal 1 becomes 1 at a certain time, the state transitions to 1. At the same time, the output signal 1 S31 becomes 1. In this state, the input signal 2 S22 is observed. When the input signal 2 S22 is 0, the current state 1 is held, and when it becomes 1, the state transitions to 2, and at the same time, the output signal 2 S32 becomes 1, and other signals including the output signal 1 Becomes 0. Similarly, when the state is 2, the input signal 3 S23 is observed, the same state is maintained until S23 becomes 1, and when it becomes 1, the state 3 is transited. State 3 immediately transitions to state 0.
The input signal 1 21 is an activation signal generated by the CPU 4, and the reconfigurable sequential circuit 41 waits for this activation signal. After the activation signal is generated, the state changes to 1, and the output signal 1 S31 is generated to activate the circuit 144. When the processing in the circuit 1 is completed, the input signal 2 S22 is generated in the circuit 1.
The input signal 2 is an acknowledge signal of the circuit 1, the state transitions to 2 in synchronization with this signal, and the output signal 2 S32 is generated.
The output signal 2 activates the circuit 2 45, and the input signal 3 S 23, which is an acknowledge signal, is generated in the circuit 2 after the processing is completed.
When S23 is generated, the state changes to 3, and an output signal 3 S33 is generated to indicate to the CPU that the processing in the circuits 1 and 2 has been completed. In this example, the input signal 4 S24 and the output signal 4 S34 are not used, but it is possible to connect an external circuit to this signal and change the contents of the state interpretation memory 101 and the output generation memory 102. It becomes the reconstruction of.

Since the state can be controlled by the output and input signal of the state interpretation memory 101 in this way, the state transition can be reconfigured by changing the state interpretation memory 101.
Furthermore, the output can be reconfigured by changing the output generation memory 102. That is, the sequential circuit 41 can be reconfigured.

Next, Example 10 will be described with reference to the drawings.
FIG. 16 is a diagram illustrating the configuration of the tenth embodiment.
The m-bit output generation memory 102 stores encoded data. A decoder 104 is provided after the output generation memory 102 to generate an output signal S12 having an n2 bit width. At this time, m <n2, so that the capacity of the output generation memory can be suppressed.
This embodiment is different from the previous embodiment in that the output generation memory 102 and the decoder 104 are provided, and the encoded data is stored in the output generation memory 102.
As described above, since the decoder 104 is provided at the subsequent stage of the output generation memory 102, the capacity of the output generation memory 102 can be suppressed, so that the circuit area can be reduced.

Next, Example 11 will be described with reference to the drawings.
FIG. 17 is a diagram showing the configuration of the eleventh embodiment. The state control unit 301 is configured with a lookup table 3011. The input signal S11 and the state interpretation signal S15 are input, and the look-up table 3011 generates an output signal S12 corresponding to the input. Thereby, the logic of the state control unit 301 can be changed, and control other than the state control described in the ninth embodiment can be performed.
This embodiment is different from the ninth and tenth embodiments in that the state control unit 301 includes a lookup table 3011.
Thus, since the state control unit 301 is configured by the lookup table 3011, any state transition can be performed.

Next, Example 12 will be described with reference to the drawings.
FIG. 18 is a diagram showing the configuration of the twelfth embodiment. The reconfigurable sequential circuit 41 is connected to the reconfigurable data path 50. The output signal S12 that is the output of the reconfigurable sequential circuit 41 becomes the input of the reconfigurable data path 50, and the output of the reconfigurable data path 50 becomes the input signal S11 of the reconfigurable sequential circuit 41. The data path 50 is a circuit that performs an operation, and the reconfigurable sequential circuit 41 controls both the operation and reconfiguration of the data path 50. By controlling the sequence of the sequential circuit 41, it is possible to perform complex operations while reconfiguring the data path 50.
This embodiment is different from the previous embodiments 9, 10 and 11 in that the reconfigurable data path 50 and the reconfigurable sequential circuit 41 are combined.
In this way, both the sequential circuit 41 as the control unit and the data path 50 as the calculation part are configured to be reconfigurable, so that the hardware can have software flexibility, so there is no CPU. Can enable autonomous operation.

Since the logic circuit unit can realize hardware in software, it can be applied to general digital signal processing other than embedded.
In addition, since the circuit can be adapted to the environmental change by calculating and determining the environmental change, it can be widely applied to sensor processing in general outdoors.

1 is a block diagram of a signal processing apparatus showing a first embodiment of the present invention. It is a block diagram of the signal processing apparatus which shows Example 2 of this invention. It is a block diagram of the signal processing apparatus which shows Example 3 of this invention. It is a block diagram of the signal processing apparatus which shows Example 4 of this invention. It is a block diagram of the reconfigurable logic circuit device which shows Example 5 of this invention. FIG. 6 is a detailed block diagram of the reconfigurable logic circuit device shown in FIG. 5. It is a figure which shows two types of opcodes of ALU1 and ALU2 of the re-recoverable logic circuit device shown in FIG. It is a block diagram of the reconfigurable logic circuit device which shows Example 6 of this invention. It is a block diagram of the reconfigurable logic circuit device which shows Example 7 (a) and modification (b) of this invention. It is a block diagram of the reconfigurable logic circuit device which shows Example 8 of this invention. It is a block diagram of the configurable sequential circuit which shows Example 9 of this invention. It is a block diagram of a reconfigurable sequential circuit using the circuit shown in FIG. It is a figure which shows the example of a memory map of the state interpretation memory of the reconfigurable sequential circuit shown in FIG. It is a figure which shows the example of a memory map of the output creation memory of the reconfigurable sequential tree circuit shown in FIG. It is a figure which shows the example of an operation waveform of the reconfigurable sequential circuit shown in FIG. It is a block diagram of the reconfigurable sequential circuit which shows Example 10 of this invention. It is a block diagram of the reconfigurable sequential circuit which shows Example 11 of this invention. It is a block diagram of the reconfigurable sequential circuit which shows Example 12 of this invention. It is a block diagram of the conventional signal processing apparatus. FIG. 20 is a detailed view of the apparatus shown in FIG. 19. It is a block diagram of a conventional reconfigurable logic circuit device. It is a block diagram of the conventional reconfigurable sequential circuit.

Explanation of symbols

1 CPU
2 Memory 3 I / O device group 4 Interrupt controller 5, 13 Logic circuit (reconfigurable hardware)
51 Allocation control unit 6 Reconfiguration data control unit 61, 12, 120 Definition memory unit (reconfiguration data storage unit)
62, 20 Index register (Reconfiguration data selection register)
7 Logic circuit unit start-up unit 8 Hardware sequencer 11 Reconfigurable logic circuit device 14 Register 15 SW1
16 SW2
17 SW3
18 ALU1
19 ALU2
20a column selection unit 20b row selection unit 21-24, 121-124 array memory for definition 31 PE1
32 PE2
33 PE3
34 PE4
41 reconfigurable sequential circuit 42 memory 43 CPU
44 Circuit 1
45 Circuit 2
50 Reconfigurable Data Bus 101 State Interpretation Memory 102 Output Generation Memory 103 Memory Control Unit 104 Decoder 301 State Control Unit 311 Wiring Unit 1
312 Calculation unit 1
313 Calculation unit 2
314 Wiring part 2
3011 Look-up table S1 Interrupt source S2 Interrupt S3 Interrupt ACK
S4 Bus S5 Interrupt request S6 Logic circuit section data S7 Reconfiguration trigger signal S8 Logic circuit section start signal S9 Logic circuit section ACK
S10 Reconfiguration data selection signal S21 Input signal 1
S22 Input signal 2
S23 Input signal 3
S24 Input signal 4
S31 Output signal 1
S32 Output signal 2
S33 Output signal 3
S34 Output signal 4

Claims (13)

A CPU, a memory, an I / O device group, and an interrupt controller. The n interrupt sources generated by the I / O device group accessible from the CPU are input, and a logic circuit unit start signal is output from an interrupt source. In a signal processing device including a logic circuit unit activation unit that generates and generates an interrupt request from the logic circuit unit ACK signal and other interrupt sources to the interrupt controller,
In addition, the bank number of the bank memory used as reconfigurable hardware data is held, and when the bank number is changed, the index register set by the CPU that generates a reconfiguration trigger signal and the configuration of the reconfigurable hardware A memory having a bank configuration for storing configuration data to be determined. The output of the selected bank memory is configured by a definition memory unit that always acts on the logic circuit unit as reconfigurable hardware data, and can be accessed from the CPU. A configuration data controller;
Accessible from the CPU, starts arithmetic processing in response to the logic circuit section start signal, outputs a logic circuit section ACK signal after the arithmetic processing ends, and performs hardware according to the contents of the reconfigurable hardware data and the reconfiguration trigger signal And a logic circuit unit for changing the configuration of the signal processing apparatus.   The logic circuit unit activation unit generates a logic circuit unit activation signal from an interrupt source that is accessible from the CPU and accepts a request, and a reconfiguration data selection signal that is a signal for changing the encoded data in this state and the contents of the index register Generating an interrupt request to the interrupt controller from the logic circuit unit ACK signal and another interrupt source that has not received the request, and the index register is set by the CPU or the reconfiguration data selection signal. The signal processing apparatus according to claim 1, wherein the signal processing apparatus is configured to be set.   3. The allocation control unit that controls allocation of basic elements for realizing a logic circuit unit using the reconfiguration data selection signal and logic circuit unit data in the logic circuit unit. Signal processing equipment.   4. A signal processing apparatus according to claim 3, wherein said signal processing apparatus is constituted by a hardware sequencer made of FSM (Finite State Machine) instead of said CPU, interrupt controller and memory.   In a reconfigurable logic circuit device comprising a definition memory and a logic circuit unit whose circuit configuration can be changed according to the contents of the definition memory, data for defining one PE that is composed of a plurality of processor elements (PE) Including a logic circuit unit that is smaller than the output port width of the memory, each of the PEs can store N sets of definition data in a one-to-one correspondence, and an array of elements N is provided for the number of PEs. A reconfigurable logic circuit device comprising a definition memory unit composed of a memory.   The PE calculates the wiring between the plurality of inputs entering the PE and the output to the arithmetic unit according to the contents of the definition array memory, and calculates the wiring according to the contents of the definition array memory. 6. The reconfigurable logic circuit device according to claim 5, wherein the reconfigurable logic circuit device is configured by an arithmetic unit that changes the processing of (5).   7. The reconfigurable logic circuit device according to claim 5, further comprising an index register that outputs an address for selecting the definition array memory.   The definition array memory is a two-dimensional array in which data can be specified from rows and columns, the index register is composed of a row selection unit and a column selection unit, and the configuration is changed depending on the contents of the row selection unit and the column selection unit. 8. The reconfigurable logic circuit device according to claim 5, wherein the reconfigurable logic circuit device is formed of PE.   8. The reconfigurable logic circuit device according to claim 7, wherein the setting value of the index register is changed based on an operation result of the logic circuit unit. In a sequential circuit that includes a reconfigurable circuit device and generates an output signal from a state generated by an internal circuit using an input signal as a transition condition,
A memory control unit that has an input signal having a bit width that can correspond to the increase or decrease of the circuit, generates a state from the control signal, and stores the association between the operation in the state and the input signal using the state as an address A state interpretation memory that generates an interpretation signal; and a memory that includes an output generation memory having a bit width that can be used to increase or decrease a circuit by storing an output signal corresponding to the state by using the state as an address, A reconfigurable sequential circuit comprising: a state control unit that generates a control signal for the memory control unit from a state interpretation signal and an input signal.   11. The reconfigurable sequential circuit according to claim 10, wherein the output generation memory stores encoded data, and a decoder is provided at a subsequent stage of the output generation memory.   12. The reconfigurable sequential circuit according to claim 10, wherein the state control unit is configured by a look-up table.   The reconfigurable sequential circuit according to any one of claims 10 to 12, wherein the reconfigurable sequential circuit is used as a control unit of a reconfigurable data path that executes arithmetic processing.

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