JP2006345157A - Coding equipment, decoding equipment, coding method, decoding method and these programs - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide coding equipment capable of shortening a processing time at a time when a plurality of picture data are coded on the basis of a predetermined reference relationship. <P>SOLUTION: In a processable MB searching circuit 130, micro-block MBs processable in parallel among a plurality of picture data are specified on the basis of the reference relationship among a plurality of the picture data. A plurality of the micro-block MBs are processed in parallel by processors 111 and 112. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an encoding device that encodes image data, an encoding method, and a program thereof, and a decoding device that decodes image data, a decoding method, and a program thereof.

  In recent years, image data has been handled as digital data. At that time, MPEG (compressed by orthogonal transformation such as discrete cosine transformation and motion compensation is used for the purpose of efficient transmission and storage of information, and using redundancy unique to image information. Moving Picture Experts Group) H.264 / AVC (Advanced Video Coding) and other encoding devices and decoding devices that are compliant with systems such as broadcast stations and information reception in general households are becoming widespread.

  By the way, in the above-described encoding device and decoding device, there is a demand to reduce the processing time in the field of real-time communication and the like.

The present invention has been made in view of such circumstances, and provides an encoding apparatus, an encoding method, and a program thereof that can reduce processing time when encoding a plurality of picture data based on a predetermined reference relationship. The purpose is to do.
It is another object of the present invention to provide a decoding device, a decoding method, and a program thereof that can shorten the processing time when decoding a plurality of picture data encoded based on a predetermined reference relationship.

  In order to solve the above-described problems of the prior art and achieve the above-described object, an encoding apparatus according to a first aspect of the present invention provides an encoding for encoding a plurality of picture data based on a predetermined reference relationship. An apparatus for detecting data that can be encoded in the plurality of picture data based on the reference relationship of the plurality of picture data, and based on a detection result of the detection means, And a plurality of processing circuits that perform encoding processing of a plurality of picture data in parallel.

  The decoding device according to the present invention is a decoding device that decodes a plurality of picture data based on a predetermined reference relationship, and includes a plurality of pieces of picture data based on the reference relationship of the plurality of picture data. Detection means for detecting data that can be decoded, and a plurality of processing circuits that perform decoding processing of the plurality of picture data in parallel based on the detection result of the detection means.

  Also, the encoding method of the present invention is an encoding method for encoding a plurality of picture data based on a predetermined reference relationship, wherein the plurality of picture data is based on the reference relationship of the plurality of picture data. A first step of detecting data that can be encoded in the picture data, and a second step of performing parallel processing on the encoding processing of the plurality of picture data based on the detection result of the first step; Have

  The decoding method of the present invention is a decoding method for decoding a plurality of picture data based on a predetermined reference relationship, and includes a plurality of pieces of picture data based on the reference relationship of the plurality of picture data. A first step of detecting data that can be decoded, and a second step of parallelly decoding the plurality of picture data based on the detection result of the first step.

  The program of the present invention is a program executed by a computer that encodes a plurality of picture data based on a predetermined reference relation, and the plurality of picture data is based on the reference relation of the plurality of picture data. A first procedure for detecting data that can be encoded in picture data; and a second procedure for performing parallel processing on the encoding processing of the plurality of picture data based on the detection result of the first procedure; Is executed by the computer.

  The program of the present invention is a program executed by a computer that decodes a plurality of picture data based on a predetermined reference relationship, and the plurality of pictures is based on the reference relationship of the plurality of picture data. A first procedure for detecting data that can be decoded in the data, and a second procedure for performing parallel decoding processing on the plurality of picture data based on a detection result of the first procedure. To run.

According to the present invention, it is possible to provide an encoding device, an encoding method, and a program thereof that can shorten the processing time when encoding a plurality of picture data based on a predetermined reference relationship.
Furthermore, according to the present invention, it is possible to provide a decoding device, a decoding method, and a program thereof that can shorten the processing time when decoding a plurality of picture data encoded based on a predetermined reference relationship.

Hereinafter, an encoding apparatus according to an embodiment of the present invention will be described.
<First Embodiment>
First, the relationship between the component of this embodiment and the component of this invention is demonstrated.
The processable MB search circuit 130 shown in FIG. 1 is an example of the detection means of the present invention.
Moreover, the processors 111 and 112 of this embodiment are examples of the processing circuit of this invention.
Further, the macro block MB of the present embodiment is an example of the block data of the present invention.

Hereinafter, the image processing apparatus 1 of the present embodiment will be described.
FIG. 1 is a conceptual diagram of an image processing apparatus 1 according to the present embodiment.
As shown in FIG. 1, the image processing apparatus 1 includes, for example, a multiprocessor 110, an entropy code / arithmetic encoding circuit 121, an entropy decoding / arithmetic decoding circuit 122, a processable MB search circuit 130, a bit stream memory 140, a work memory. 150 and a frame memory 160.
As shown in FIG. 1, the multiprocessor 110 is connected to an entropy code / arithmetic encoding circuit 121, an entropy decoding / arithmetic decoding circuit 122, and a processable MB search circuit 130 via a control bus 115.
The multiprocessor 110 is connected to the bit stream memory 140, the work memory 150, and the frame memory 160 via the image data bus 135.
The entropy code / arithmetic encoding circuit 121, the entropy decoding / arithmetic decoding circuit 122, the processable MB search circuit 130, the bit stream memory 140, the work memory 150, and the frame memory 160 are connected via an image data bus 135. ing.

  In the present embodiment, the processing of the multiprocessor 110 is performed based on a program (an example of the program of the present invention) stored in a memory (not shown).

The entropy code / arithmetic encoding circuit 121 shown in FIG. 1 performs entropy encoding or arithmetic encoding on the picture data encoded by the multiprocessor 110 and writes the result to the bitstream memory 140.
The entropy decoding / arithmetic decoding circuit 122 performs entropy decoding or arithmetic decoding on the picture data input from the bit stream memory 140 via the image data bus 135 when the multiprocessor 110 performs decoding processing, and the control bus. The data is output to the multiprocessor 110 via 115.

Further, the entropy code / arithmetic encoding circuit 121, the entropy decoding / arithmetic decoding circuit 122, the processable MB search circuit 130, and the like are configured by, for example, CMOS (Complementary Metal-Oxide Semiconductor) gates.
The work memory 150 is, for example, an SRAM (Static RAM).
The bit stream memory 140 and the work memory 150 are, for example, DDR-SDRAM.

[Multiprocessor 110]
The multiprocessor 110 performs encoding processing and decoding processing in units of macroblocks MB.
In the present embodiment, the multiprocessor 110 uses, for example, H.264 as an encoding method. H.264 / AVC, MPEG, etc. are adopted.
Note that the picture data of this embodiment may be either frame data or field data.

<Encoding process>
FIG. 2 is a functional block diagram of the encoding process performed by the multiprocessor 110 shown in FIG.
In the encoding process, the multiprocessor 110 performs the operation unit 24, the orthogonal transform unit 25, the quantization unit 26, the inverse quantization unit 29, the inverse orthogonal transform unit 30, the deblock filter 31, the addition unit 33, the intra unit illustrated in FIG. The functions of the prediction unit 41 and the motion prediction / compensation unit 42 are realized.

The calculation unit 24 generates image data S24 indicating a difference between the picture data T_PIC to be encoded and the predicted image data input from the intra prediction unit 41 or the motion prediction / compensation unit 42, and supplies this to the orthogonal transform unit 25. Output.
The orthogonal transform unit 25 generates image data (for example, DCT coefficient) S25 indicating transform coefficients by performing orthogonal transform such as discrete cosine transform (DCT) or Karhunen-Loeve transform on the image data S24. The data is output to the quantization unit 26.

The quantization unit 26 quantizes the image data S25 (transformation coefficient before quantization) to generate image data S26 indicating the transform coefficient after quantization, which is generated by the entropy code / arithmetic coding circuit 121 shown in FIG. And to the inverse quantization unit 29 shown in FIG.
The inverse quantization unit 29 performs an inverse quantization process corresponding to the quantization of the quantization unit 26 on the image data S <b> 26, generates data obtained thereby, and outputs this to the inverse orthogonal transform unit 30.
The inverse orthogonal transform unit 30 outputs the image data generated by performing the inverse transform of the orthogonal transform in the orthogonal transform unit 25 to the data input from the inverse quantization unit 29 to the adding unit 33.

The adding unit 33 adds (decodes) the image data input (decoded) from the inverse orthogonal transform unit 30 and the predicted image data PI input from the intra prediction unit 41 or the motion prediction / compensation unit 42 to be referred (reconstructed). Picture data is generated and output to the deblocking filter 31.
The deblock filter 31 writes the image data from which the block distortion of the reference picture data is removed to the work memory 150 as reference picture data R_PIC.

The intra prediction unit 41 determines the intra prediction mode and the block size of the prediction block that minimize the residual in the macroblock MB to be intra-coded.
The intra prediction unit 41 uses 4 × 4 and 16 × 16 pixels as the block size.
The intra prediction unit 41 outputs predicted image data PI based on intra prediction to the calculation unit 24 and the addition unit 33 when intra prediction is selected.

The motion prediction / compensation unit 42 performs motion prediction from an image that has already been encoded, locally decoded, and recorded in the work memory 150, and determines a motion vector that minimizes the residual and a block size for motion compensation. .
The motion prediction / compensation unit 42 uses 16 × 16, 16 × 8, 8 × 16, 8 × 8, 8 × 4, 4 × 8, and 4 × 4 pixels as block sizes.
When the inter prediction is selected, the motion prediction / compensation unit 42 outputs the predicted image data PI based on the inter prediction to the calculation unit 24 and the addition unit 33.

Based on the search result of the processable MB search circuit 130, the multiprocessor 110 performs a parallel process between a plurality of picture data and performs the encoding process shown in FIG.
Further, the multiprocessor 110 performs the encoding process shown in FIG. 2 in parallel between a plurality of macroblocks MB in the picture data based on the search result of the processable MB search circuit 130.

[Processable MB search circuit 130 (when encoding)]
FIG. 3 is a flowchart for explaining the processing of the processable MB search circuit 130 shown in FIG. 1 when the multiprocessor 110 is encoded.
Step ST11:
In the processable MB search circuit 130, the current (encoding target) macroblock MB is unencoded, and the left and top (macroblocks MB_A, MB_B, MB_C shown in FIG. 4) of the current macroblock MB are encoded. It is determined whether or not the condition of being completed is satisfied. If it is determined that the condition is satisfied, the process proceeds to step ST12, and if not, the process proceeds to step ST14.

Step ST12:
As shown in FIG. 5, the processable MB search circuit 130 determines whether or not the condition that the macroblock MB in the search area (reference area) in the reference picture of the current macroblock MB has been encoded is satisfied. If it is determined that the condition is satisfied, the process proceeds to step ST13. If not, the process proceeds to step ST14.

Step ST13:
The processable MB search circuit 130 registers the current macroblock MB in the encoding processable macroblock list EPML.

Step ST14:
The processable MB search circuit 130 selects an unselected macroblock MB as the current macroblock MB as the current macroblock MB.
Specifically, the processable MB search circuit 130 increments the address of the selected macroblock MB.
Step ST15:
The processable MB search circuit 130 proceeds to step ST16 when determining that the process of step ST11 has been completed for all macroblocks MB in one picture data, and otherwise proceeds to step ST11.
Step ST16:
The processable MB search circuit 130 proceeds to step ST18 when determining that the processing of steps ST11 to ST15 has been completed for the three picture data continuously encoded by the multiprocessor 110, and proceeds to step ST17 otherwise. .

Step ST17:
The processable MB search circuit 130 resets the address of the selected macroblock MB to “0”.
Step ST18:
The processable MB search circuit 130 ends the process when it determines that the encoding process has been completed for the three picture data encoded in parallel by the multiprocessor 110, and returns to step ST11 otherwise.

Hereinafter, an operation example of the encoding process of the image processing apparatus 1 illustrated in FIG. 1 will be described.
FIG. 6 is a flowchart for explaining an operation example of the encoding process of the image processing apparatus 1 shown in FIG.
Step ST21:
The processor 111 shown in FIG. 1 activates the entropy code / arithmetic coding circuit 121.
As a result, the entropy code / arithmetic encoding circuit 121 can start the process of performing entropy encoding or arithmetic encoding on the picture data encoded by the multiprocessor 110 in step ST25 and writing the picture data in the bit stream memory 140. It becomes a state.
Step ST22:
The processor 111 activates the processable MB search circuit 130 shown in FIG.
As a result, the processable MB search circuit 130 performs the process shown in FIG. 3 and generates an encoding processable MB list EPML.

Step ST23:
The processor (parent processor) 111 activates the processor (child processor) 112.
Thereby, the processor 112 performs the process shown in FIG.
Step ST24:
The processor 111 inquires the processable MB search circuit 130 for a macroblock MB that can be encoded.
The processable MB search circuit 130, based on the inquiry from the processor 111, in the macroblock MB allocated to the processor 111 based on the encoding processable macroblock list EPML generated by the procedure shown in FIG. It is determined whether there is a macroblock MB that can be encoded. If it is determined that there is a macroblock MB that can be encoded, the processor 111 is notified of the macroblock MB.
Upon receiving notification that there is a processable macroblock MB, the processor 111 proceeds to step ST25, otherwise proceeds to step ST26.

Step ST25:
The processor 111 performs encoding processing of the macro block MB to be processed.
Specifically, the processor 111 performs an encoding process on the processing target macroblock MB according to the functional block shown in FIG. 2, and the result is entropy encoded via the work memory 150 and the frame memory 160 shown in FIG. / Output to arithmetic coding circuit 121.
Step ST26:
For example, when the processor 111 determines that the encoding process has ended based on the determination result of the host system such as a system management thread executed by the multiprocessor 110, the processor 111 ends the process. Otherwise, the process returns to step ST24.

FIG. 7 is a flowchart for explaining the encoding process executed by the processor 112 activated by the processor 111 in step ST23 shown in FIG.
Step ST31:
The processor 112 inquires the processable MB search circuit 130 about a macroblock MB that can be encoded.
The processable MB search circuit 130, based on the inquiry from the processor 112, in the macroblock MB allocated to the processor 112 based on the encoding processable macroblock list EPML generated by the procedure shown in FIG. It is determined whether there is a macroblock MB that can be encoded. If it is determined that there is a macroblock MB that can be encoded, the processor 112 is notified of the macroblock MB.
Upon receiving notification that there is a macroblock MB that can be encoded, the processor 112 proceeds to step ST32, otherwise proceeds to step ST33.

Step ST32:
The processor 112 performs an encoding process on the processing target macroblock MB.
Specifically, the processor 112 performs encoding processing on the macro block MB to be processed according to the functional block shown in FIG. 2, and the result is entropy encoded via the work memory 150 and the frame memory 160 shown in FIG. / Output to arithmetic coding circuit 121.
Step ST33:
When determining that the encoding process has ended, the processor 112 ends the process, and otherwise returns to step ST31.

FIG. 8 is a diagram for explaining a processing flow in the processors 111 and 112 and the entropy code / arithmetic coding circuit 121 when the image processing apparatus 1 shown in FIG. 1 performs the coding process.
As shown in FIG. 8, in the period X1, the processor 111 performs the upper half encoding process of the I1 picture data.
Next, in the period X2, the lower half encoding process of the I1 picture data by the processor 111 and the upper half encoding process of the P2 picture data by the processor 112 are performed in parallel.
Next, in the period X3, the encoding process for the upper half of the B3 picture data by the processor 111 and the encoding process for the lower half of the P2 picture data by the processor 112 are performed in parallel. In parallel with this, the entropy code / arithmetic coding circuit 121 performs entropy coding or arithmetic coding processing of the I1 picture data.
Next, in the period X4, the lower half encoding process of the B3 picture data by the processor 111 and the upper half encoding process of the B4 picture data by the processor 112 are performed in parallel. In parallel with this, the entropy code / arithmetic coding circuit 121 performs entropy coding or arithmetic coding processing of the P2 picture data.
Note that the encoding processing of the processors 111 and 112 shown in FIG. 8 is performed according to the functional blocks shown in FIG.

  By the way, in the example shown in FIG. 8, the processor 111 executes encoding processing of the upper half and the lower half of the I1 picture data, the upper half and the lower half of the B3 picture data, and the upper half and the lower half of the P5 picture data, The case where the processor 112 executes the encoding process of the upper half and the lower half of the P2 picture data, the upper half and the lower half of the B4 picture data, and the upper half and the lower half of the B6 picture data is illustrated. The processing of the macro block MB may be executed by any of the processors 111 and 112 as long as parallel processing is possible based on the reference relationship.

<Decryption process>
[Multiprocessor 110 (during decoding)]
FIG. 9 is a functional block diagram of a decoding process performed by the multiprocessor 110 shown in FIG.
The multiprocessor 110 implements functions such as the inverse quantization unit 83, the inverse orthogonal transform unit 84, the addition unit 85, the intra prediction unit 89, and the motion prediction / compensation unit 90 illustrated in FIG. 9 in the decoding process.

The inverse quantization unit 83 inversely quantizes the image data S82 after lossless decoding input from the entropy decoding / arithmetic decoding circuit 122 by an inverse quantization method corresponding to the quantization unit 26 illustrated in FIG. This is generated and output to the inverse orthogonal transform unit 84.
The inverse orthogonal transform unit 84 performs the orthogonal inverse transform corresponding to the orthogonal transform of the orthogonal transform unit 25 shown in FIG. 2 on the image data S83 input from the inverse quantization unit 83 to generate the image data S84, and adds this. To the unit 85.
The adding unit 85 adds the predicted image input from the intra prediction unit 89 or the motion prediction / compensation unit 90 and the image data S84 input from the inverse orthogonal transform unit 84 to generate image data S85, which is generated as work memory. 150 and the frame memory 160 are written.

When the block data to be decoded in the image data S85 read from the work memory 150 is subjected to intra prediction encoding, the intra prediction unit 89 generates predicted image data by decoding the block data using the intra method. This is output to the adder 85.
When the block data to be decoded in the image data S85 read from the work memory 150 has been subjected to inter prediction encoding, the motion prediction / compensation unit 90 decodes the block data using the inter method and predicts image data. Is output to the adder 85.

[Processable MB search circuit 130 (in decoding)]
FIG. 10 is a flowchart for explaining the processing of the processable MB search circuit 130 shown in FIG.
Step ST41:
In the processable MB search circuit 130, the current (decoding target) macroblock MB has not been decoded, and the screen left and top (macroblocks MB_A, MB_B, MB_C shown in FIG. 4) of the current macroblock MB have been decoded. If it is determined whether or not the above condition is satisfied, the process proceeds to step ST42. If not, the process proceeds to step ST45.

Step ST42:
The processable MB search circuit 130 determines whether or not the current macroblock MB is intra-encoded, and if it is determined that it is intra-encoded, the process proceeds to step ST44; otherwise (inter-encoded). In step ST43).
Step ST43:
The processable MB search circuit 130 indicates, for example, the motion vector MV in the reference image data based on the motion vector MV of the current macroblock MB input from the entropy decoding / arithmetic decoding circuit 122 shown in FIGS. It is determined whether or not the indicated macroblock MB has already been decoded. If it is determined that the macroblock MB has been decoded, the process proceeds to step ST44, and if not, the process proceeds to step ST45.

Step ST44:
The processable MB search circuit 130 registers the current macroblock MB in the decoding processable macroblock list DPML.
Step ST45:
The processable MB search circuit 130 selects an unselected macroblock MB as the current macroblock MB as the current macroblock MB.
Specifically, the processable MB search circuit 130 increments the address of the selected macroblock MB.
Step ST46:
The processable MB search circuit 130 proceeds to step ST47 when determining that the process of step ST41 has been completed for all macroblocks MB in one picture data, and otherwise proceeds to step ST41.
Step ST47:
The processable MB search circuit 130 proceeds to step ST48 when determining that the processing of steps ST41 to ST46 has been completed for the three picture data successively decoded by the multiprocessor 110, and proceeds to step ST49 otherwise.

Step ST48:
The processable MB search circuit 130 resets the address of the selected macroblock MB to “0”.
Step ST49:
The processable MB search circuit 130 ends the process when it determines that the decoding process has been completed for the three picture data continuously decoded by the multiprocessor 110, and returns to step ST41 otherwise.

Hereinafter, an operation example of the decoding process of the image processing apparatus 1 illustrated in FIG. 1 will be described.
FIG. 11 is a flowchart for explaining an operation example of the decoding process of the image processing apparatus 1 shown in FIG.
Step ST61:
The processor 111 shown in FIG. 1 activates the entropy code / arithmetic decoding circuit 122.
Thus, the entropy decoding / arithmetic decoding circuit 122 performs entropy decoding or arithmetic decoding on the picture data input from the bit stream memory 140 via the image data bus 135 when the multiprocessor 110 performs decoding processing, and performs control processing. The data is output to the multiprocessor 110 via the bus 115.
Step ST62:
The processor 111 activates the processable MB search circuit 130 shown in FIG.
As a result, the processable MB search circuit 130 performs the process shown in FIG. 10 and generates a decoding processable MB list DPML.

Step ST63:
The processor (parent processor) 111 activates the processor (child processor) 112.
Thereby, the processor 112 performs the process shown in FIG.
Step ST64:
The processor 111 inquires the processable MB search circuit 130 for a macroblock MB that can be decoded.
The processable MB search circuit 130 decodes the macroblock MB assigned to the processor 111 based on the decoding processable macroblock list DPML generated by the procedure shown in FIG. 10 based on the inquiry from the processor 111. It is determined whether there is a processable macroblock MB. If it is determined that there is a macroblock MB that can be decoded, the processor 111 is notified of the macroblock MB.
Upon receiving notification that there is a macroblock MB that can be decoded, the processor 111 proceeds to step ST65, and otherwise proceeds to step ST66.

Step ST65:
The processor 111 performs a decoding process on the decoding target macroblock MB.
Specifically, the processor 111 performs the decoding process on the decoding target macroblock MB input from the entropy decoding / arithmetic decoding circuit 122 according to the functional block shown in FIG. 150 and the frame memory 160 are written.
Step ST66:
For example, when the processor 111 determines that the decoding process has ended based on the determination result of the host system such as a system management thread executed by the multiprocessor 110, the processor 111 ends the process. Otherwise, the process returns to step ST64.

FIG. 12 is a flowchart for explaining the decoding process executed by the processor 112 activated by the processor 111 in step ST63 shown in FIG.
Step ST71:
The processor 112 inquires the processable MB search circuit 130 for a macroblock MB that can be decoded.
Based on the inquiry from the processor 112, the processable MB search circuit 130 decodes the macroblock MB assigned to the processor 112 based on the decoding processable macroblock list DPML generated by the procedure shown in FIG. It is determined whether there is a processable macroblock MB. If it is determined that there is a macroblock MB that can be decoded, the processor 112 is notified of the macroblock MB.
Upon receiving notification that there is a macroblock MB that can be decoded, the processor 112 proceeds to step ST72, otherwise proceeds to step ST73.

Step ST72:
The processor 112 performs an encoding process on the decoding target macroblock MB.
Specifically, the processor 112 performs an encoding process on the decoding target macroblock MB input from the entropy decoding / arithmetic decoding circuit 122 in accordance with the functional blocks shown in FIG. Write to the memory 150 or the frame memory 160.
Step ST73:
If processor 112 determines that the decoding process has ended, it ends the process, and if not, it returns to step ST71.

FIG. 13 is a diagram for explaining the flow of processing in the entropy decoding / arithmetic decoding circuit 122 and the processors 111 and 112 when the image processing apparatus 1 shown in FIG. 1 performs decoding processing.
As shown in FIG. 13, in the period X11, the entropy decoding / arithmetic decoding circuit 122 performs entropy or arithmetic decoding processing on the upper half of the I1 picture data.
Next, in the period X12, the processor 111 performs the decoding process on the upper half of the I1 picture data input from the entropy decoding / arithmetic decoding circuit 122 according to the functional block shown in FIG. At the same time, the entropy decoding / arithmetic decoding circuit 122 performs decoding processing of P2 picture data.
Next, in the period X13, the decoding process for the lower half of the I1 picture data by the processor 111 and the decoding process for the upper half of the P2 picture data by the processor 112 are performed in parallel. In parallel with this, the B3 picture data is decoded by the entropy decoding / arithmetic decoding circuit 122.
Next, in the period X14, the decoding process for the upper half of the B3 picture data by the processor 111 and the decoding process for the lower half of the P2 picture data by the processor 112 are performed in parallel. At the same time, the entropy decoding / arithmetic decoding circuit 122 performs decoding processing of B4 picture data.
Note that the decoding processing of the processors 111 and 112 shown in FIG. 13 is performed according to the functional blocks shown in FIG.
That is, in the decoding process, the processors 111 and 112 perform the decoding process of the I, P, and B picture data as shown in FIG. Run in parallel based on.

  By the way, in the example shown in FIG. 13, the processor 111 executes decoding processing of the upper half and the lower half of the I1 picture data, the upper half and the lower half of the B3 picture data, and the upper half and the lower half of the P5 picture data. 112 illustrates the case where the decoding process is performed on the upper half and the lower half of the P2 picture data, the upper half and the lower half of the B4 picture data, and the upper half and the lower half of the B6 picture data. The processing of the block MB may be executed by any of the processors 111 and 112 as long as parallel processing is possible based on the reference relationship.

As described above, in the image processing apparatus 1, the processors 111 and 112 perform encoding processing of a plurality of picture data in parallel. Therefore, according to the image processing apparatus 1, the processing time of the encoding process can be shortened.
In the image processing apparatus 1, the processors 111 and 112 perform a decoding process on a plurality of picture data in parallel. Therefore, according to the image processing apparatus 1, the processing time of the decoding process can be shortened.

  Incidentally, as described above, in the image processing apparatus 1, the By performing H.264 / AVC encoding or decoding processing, for example, HD (High Definition) image encoding or decoding processing can be executed by software using low-speed and inexpensive processors 111 and 112 having an operating frequency of about 200 MHz. Become.

Second Embodiment
FIG. 15 is a configuration diagram of the image processing apparatus 101 of the present embodiment.
As shown in FIG. 15, the image processing apparatus 101 is the same as the image processing apparatus shown in FIG. 1 except for the configuration of the multiprocessor 110a and the processing content of the processable MB search circuit 130a.

As illustrated in FIG. 15, the multiprocessor 110 a includes processors 1111, 1112, 1113 and processors 1121, 1122, 1123.
In the present embodiment, the processors 1111, 1112, and 1113 perform the processing of the processor 111 described in the first embodiment.
At this time, the processors 1111, 1112, and 1113 perform encoding processing and decoding processing of one picture data in parallel as shown in FIG.
That is, in the image processing apparatus 101, in addition to performing encoding processing and decoding processing in parallel between a plurality of picture data, parallel processing is also performed in one picture data.
The processors 1121, 1122, and 1123 perform the processing of the processor 112 described in the first embodiment.
At this time, the processors 1121, 1122, and 1123 perform encoding processing and decoding processing of one picture data in parallel as shown in FIG.

Here, as shown in FIG. 16, for example, the processor 1111 performs encoding processing sequentially from the left to the right in the figure for the macroblock MB on the line in the vertical direction V1 in the picture data.
In parallel with the processing of the processor 1111, the processor 1112 performs the encoding process of the current macroblock MB on the line in the vertical direction V <b> 2 in which the macroblock MB adjacent on the upper side has already been encoded by the processor 1111. .
In parallel with the processing of the processors 1111 and 1112, the processor 1113 encodes the current macroblock MB on the line in the vertical direction V3 in which the macroblock MB adjacent to the upper side has already been encoded by the processor 1112. I do.

  The processors 1111, 1112, and 1113 also perform the decoding process in the same manner as the encoding process described above.

  The processors 1121, 1122, and 1123 also perform encoding and decoding processes in the same manner as the processors 1111, 1112, and 1113 described above.

  According to the present embodiment, since the processing of the macroblock MB in the picture data is parallelized, the processing time can be further reduced as compared with the first embodiment.

<Third Embodiment>
FIG. 17 is a configuration diagram of the image processing apparatus 201 of the present embodiment.
As shown in FIG. 17, the image processing apparatus 201 has a configuration in which the entropy code / arithmetic encoding circuit 121 is removed from the image processing apparatus 1 shown in FIG. 1.
The image processing apparatus 201 is the same as the image processing apparatus 1 of the first embodiment except that only the decoding process is performed without performing the encoding process.

FIG. 18 is a timing chart showing the flow of processing when the three-picture simultaneous decoding process is performed by the image processing apparatus 201 shown in FIG.
The entropy decoding / arithmetic decoding circuit 122 decodes one frame (one picture) at a time in synchronization with the synchronization signal for each picture. After the first I picture is decoded by the entropy decoding / arithmetic decoding circuit 122, the multiprocessor 110 starts decoding.
As shown in FIG. 18, the multiprocessor 110 performs decoding processing of up to three pictures in parallel.
Each processor in the multiprocessor 110 does not always perform the decoding process, and a wait occurs during a period in which the processable MB search circuit 130 cannot find a processable macroblock MB.
Each processor does not necessarily determine which picture is to be decoded in advance, but can decode a processable macroblock MB regardless of the picture data to which it belongs according to the notification from the processable MB search circuit 130. Yes.
FIG. 14 is a diagram showing a spatial image of the 3-picture simultaneous decoding process. Regarding the processing timing, it is not always necessary to synchronize with a synchronization signal in units of pictures. In addition to paralleling between pictures (simultaneous decoding of multiple pictures) as shown in FIG. 14, parallel processing within a picture (simultaneous decoding of multiple MBs within the same picture) is also performed.

<Fourth embodiment>
FIG. 19 is a configuration diagram of the image processing apparatus 301 of the present embodiment.
As shown in FIG. 19, the image processing apparatus 301 includes, for example, a multiprocessor 110, a bit stream memory 140, a work memory 150, and a frame memory 160, which are connected via an image data bus 135.

In the image processing apparatus 301, the multiprocessor 110 includes, for example, three processors 111, 112, and 113, and a plurality of different picture data (picture data) are encoded or decoded in parallel as shown in FIG. Let it be processed.
Note that the number of processors included in the multiprocessor 110 may be four or more.

<Fifth Embodiment>
FIG. 21 is a configuration diagram of the image processing apparatus 401 of the present embodiment.
As shown in FIG. 21, the image processing apparatus 401 includes, for example, a multiprocessor 110, an entropy decoding / arithmetic decoding circuit 1221, 1222, 1223, a processable MB search circuit 130, a bit stream memory 140, a work memory 150, and a frame memory 160. Have
In FIG. 21, the structure which attached | subjected the same code | symbol as 1st Embodiment is the same as what was demonstrated in 1st Embodiment.

The entropy decoding / arithmetic decoding circuits 1221, 1222, 1223, for example, realize entropy decoding or arithmetic decoding of picture data (picture data) read from the bit stream memory 140 by parallel processing, as shown in FIG.
For example, the parallel processing may be performed by specifying data that can be processed in parallel by the processable MB search circuit 130 and notifying the data to the entropy decoding / arithmetic decoding circuits 1221, 1222, and 1223.
Note that the multiprocessor 110 decodes each picture data in parallel as shown in FIG. 22 as in the first embodiment.

The present invention is not limited to the embodiment described above.
For example, in the above-described embodiment, the case where each component is realized by a circuit is illustrated. However, for example, a processing circuit such as a CPU (Central Processing Unit) executes a program for all or part of the above-described component. May be realized.
Further, in the above-described embodiment, the case where the processes are parallelized by a plurality of processors has been exemplified. However, the parallel processing in the present invention includes a case where threads are processed in parallel by time sharing or the like by one processor.

FIG. 1 is a configuration diagram of an image processing apparatus according to a first embodiment of the present invention. FIG. 2 is a functional block diagram of the encoding process executed by the multiprocessor shown in FIG. FIG. 3 is a flowchart for explaining processing at the time of encoding of the processable MB search circuit shown in FIG. FIG. 4 is a diagram for explaining the reference relationship of macroblocks in the same picture data. FIG. 5 is a diagram for explaining an encoding process by the multiprocessor shown in FIG. FIG. 6 is a flowchart for explaining an encoding process by the multiprocessor (processor 111) shown in FIG. FIG. 7 is a diagram for explaining the encoding process by the processor 112 shown in FIG. FIG. 8 is a flowchart for explaining an encoding process by the multiprocessor shown in FIG. FIG. 9 is a functional block diagram of decoding processing executed by the multiprocessor shown in FIG. FIG. 10 is a flowchart for explaining processing at the time of decoding of the processable MB search circuit shown in FIG. FIG. 11 is a diagram for explaining decoding processing by the multiprocessor shown in FIG. FIG. 12 is a flowchart for explaining decoding processing by the multiprocessor (processor 111) shown in FIG. FIG. 13 is a diagram for explaining decoding processing by the multiprocessor shown in FIG. FIG. 14 is a diagram for explaining decoding processing by the multiprocessor shown in FIG. FIG. 15 is a configuration diagram of an image processing apparatus according to the second embodiment of the present invention. FIG. 16 is a diagram for explaining the operation of the image processing apparatus shown in FIG. FIG. 17 is a configuration diagram of an image processing apparatus according to the third embodiment of the present invention. FIG. 18 is a diagram for explaining the operation of the image processing apparatus shown in FIG. FIG. 19 is a configuration diagram of an image processing apparatus according to the fourth embodiment of the present invention. FIG. 20 is a diagram for explaining the operation of the image processing apparatus shown in FIG. FIG. 21 is a configuration diagram of an image processing apparatus according to the fifth embodiment of the present invention. FIG. 22 is a diagram for explaining the operation of the image processing apparatus shown in FIG.

Explanation of symbols

24 ... Calculation unit, 25 ... Orthogonal transformation unit, 26 ... Quantization unit, 27 ... Lossless encoding unit, 28 ... Buffer, 29 ... Dequantization unit, 30 ... Inverse orthogonal transformation unit, 33 ... Addition unit, 41 ... Intra Prediction unit 42 ... motion prediction / compensation unit 83 ... inverse quantization unit 84 84 inverse orthogonal transform unit 85 ... addition unit 110 ... multiprocessor 111, 112, 113, 1111, 1112, 1113, 1121, 1122 , 1123 ... processor, 121 ... entropy code / arithmetic encoding circuit, 122 ... entropy decoding / arithmetic decoding circuit, 130 ... processable MB search circuit, 140 ... bit stream memory, 150 ... work memory, 160 ... frame memory

Claims (12)

An encoding device that encodes a plurality of picture data based on a predetermined reference relationship,
Detecting means for detecting data that can be encoded in the plurality of picture data based on the reference relationship of the plurality of picture data;
And a plurality of processing circuits that perform the encoding processing of the plurality of picture data in parallel based on a detection result of the detection unit. The processing circuit performs the encoding process in units of a plurality of block data constituting the picture data,
The encoding device according to claim 1, wherein the detection unit detects the block data that can be encoded in the plurality of picture data. The detection means is a reference used for encoding the block data to be detected after the encoding processing of the other block data at a predetermined position with respect to the block data to be detected in the picture data is completed. The determination according to claim 2, wherein encoding of the block data to be detected is possible on the condition that encoding of block data in the reference target area in the target picture data has been completed. Encoding device. The detecting means detects the block data that can be encoded based further on a reference relationship between a plurality of block data in the picture data,
The encoding device according to claim 2, wherein the processing circuit processes a plurality of the block data belonging to the same picture data in parallel based on a detection result of the detection means. A decoding device that decodes a plurality of picture data based on a predetermined reference relationship,
Detecting means for detecting data capable of decoding processing in the plurality of picture data based on the reference relationship of the plurality of picture data;
A decoding apparatus comprising: a plurality of processing circuits that perform decoding processing of the plurality of picture data in parallel based on a detection result of the detection unit. The processing circuit performs the decoding process in units of a plurality of block data constituting the picture data,
The decoding device according to claim 5, wherein the detection means detects the block data that can be decoded in the plurality of picture data. The detection means ends the decoding process of the other block data at a predetermined position with respect to the block data to be detected in the picture data, and the reference target used for decoding the block data to be detected The decoding device according to claim 6, wherein it is determined that decoding processing of the block data to be detected is possible on condition that decoding of block data has been completed. The detection means detects the block data that can be decoded based on a reference relationship between a plurality of block data in the picture data,
The decoding apparatus according to claim 6, wherein the processing circuit processes a plurality of the block data belonging to the same picture data in parallel based on a detection result of the detection means. An encoding method for encoding a plurality of picture data based on a predetermined reference relationship,
A first step of detecting data that can be encoded in the plurality of picture data based on the reference relationship of the plurality of picture data;
And a second step of performing parallel processing on the encoding processing of the plurality of picture data based on the detection result of the first step. A decoding method for decoding a plurality of picture data based on a predetermined reference relationship,
A first step of detecting data that can be decoded in the plurality of picture data based on the reference relationship of the plurality of picture data;
A decoding method comprising: a second step of performing parallel processing on decoding processing of the plurality of picture data based on the detection result of the first step. A program executed by a computer that encodes a plurality of picture data based on a predetermined reference relationship,
A first procedure for detecting data that can be encoded in the plurality of picture data based on the reference relationship of the plurality of picture data;
A program for causing the computer to execute a second procedure for performing parallel processing on encoding processing of the plurality of picture data based on the detection result of the first procedure. A program executed by a computer that decodes a plurality of picture data based on a predetermined reference relationship,
A first procedure for detecting data capable of decoding processing in the plurality of picture data based on the reference relationship of the plurality of picture data;
A program for causing the computer to execute a second procedure for performing parallel processing on decoding processing of the plurality of picture data based on a detection result of the first procedure.

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