JP2006344306A - Shift register - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a shift register for preventing variations in the threshold voltage of a transistor. <P>SOLUTION: When a control signal VFR is high and a control signal /VFR is low, transistors Q2, Q5, Q12 are biased positively and transistors Q3, Q6, Q11 are biased negatively. Conversely, when the control signal VFR is low and the control signal /VFR is high, the transistors Q2, Q5, Q12 are biased negatively and the transistors Q3, Q6, Q11 are biased positively. Thus, by alternating high/low in the levels of the control signals VFR, /VFR at each frame, a threshold voltage Vth can be shifted up and down alternately regarding respective transistors Q2, Q5, Q12, Q3, Q6, Q11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a shift register, and more particularly to a shift register for sequentially driving a plurality of gate lines included in a liquid crystal display device.

  In a shift register constituted by a thin film transistor using amorphous silicon (hereinafter referred to as “a-Si TFT”), when the a-Si TFT is continuously biased (ie, DC), There is a problem that the threshold voltage shifts relatively large. Conventional shift registers for solving such problems are disclosed in, for example, Patent Documents 1 to 4 below.

JP 2002-175695 A JP-A-8-263027 JP 2004-246358 A JP 2002-197885 A

  The conventional shift register disclosed in Patent Document 1 controls the gate bias level, thereby reducing the voltage stress applied to the gate and reducing the increase in the threshold voltage of the transistor.

  The conventional shift register disclosed in Patent Document 2 lowers the gate bias of the transistor at the start of use, detects a change in the threshold voltage of the transistor, and supplies a power supply voltage corresponding to the change. It corresponds to the fluctuation of the threshold voltage.

  The conventional shift register disclosed in Patent Document 3 suppresses a rise in threshold voltage by applying a periodically changing voltage as a power supply voltage and changing a gate bias.

  In the conventional shift register disclosed in Patent Document 4, an increase in threshold voltage is reduced within this period by providing an integrated voltage adjustment operation period.

  However, according to the conventional shift registers disclosed in Patent Documents 1 to 3, the gate bias level can be reduced, but since a constant bias is applied, the threshold voltage increases as time passes. There is a problem of causing malfunction of the circuit.

  In particular, the conventional shift register disclosed in Patent Document 2 has a problem in that a circuit for detecting fluctuations in threshold voltage must be provided outside the apparatus. Further, according to the conventional shift register disclosed in Patent Document 3, since the power supply voltage is periodically changed, there is a problem that power consumption increases.

  Further, according to the conventional shift register disclosed in Patent Document 4, since the display cannot be performed within the integrated voltage adjustment operation period, there is a problem that the integrated voltage adjustment operation period cannot be made long.

  The present invention has been made to solve such a problem, and a shift capable of preventing fluctuations in the threshold voltage of a transistor by a method different from the conventional shift register disclosed in Patent Documents 1 to 4 above. The purpose is to obtain a register.

  A shift register according to the present invention is a shift register in which a plurality of unit shift registers are connected in cascade and operates in synchronization with a plurality of clock signals having different phases, each of the plurality of unit shift registers including an output terminal , Connected between the output terminal and the clock input terminal, connected between the output pull-up driving unit for charging the output terminal, the output terminal, and a terminal to which the first control signal is input, A first output pull-down driver for discharging the output terminal; the output terminal; and a terminal to which a second control signal complementary to the first control signal is input; And a second output pull-down driving unit that discharges.

  The shift register according to the present invention can prevent the threshold voltage of the transistor from fluctuating.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the element which attached | subjected the same code | symbol in different drawing shall show the same or equivalent element.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing the overall configuration of a shift register according to the present invention. In order to simplify the drawing, FIG. 1 shows an example in which four unit shift registers SR1 to SR4 are cascaded in this order. The entire configuration of the shift register shown in FIG. 1 is common to Embodiments 2 to 4 described later. The shift register SR1 has a terminal to which the clock signal CLK is input, a terminal to which the start signal IN is input, a terminal to which the output signal G2 of the subsequent unit shift register SR2 is input, and a terminal to which the power supply voltage VDD is input. A terminal to which the ground voltage VSS is input, a terminal to which the control signal VFR is input, a terminal to which a control signal / VFR complementary to the control signal VFR is input, and a terminal to which the output signal G1 is output. is doing. Note that the power supply voltage VDD and the ground voltage VSS are set for convenience of explanation, and each level of the power supply voltage VDD and the ground voltage VSS is a display element driven by output signals G1 to G4 of the shift register. It is set according to the characteristics (not shown). The same applies to the clock signal CLK, the start signal IN, and the control signals VFR and / VFR.

  Similarly, the shift registers SR2 and SR3 have a terminal to which the clock signal CLK is input, a terminal to which the output signals G1 and G2 of the preceding unit shift registers SR1 and SR2 are input, and the subsequent unit shift registers SR3 and SR4. A terminal to which output signals G3 and G4 are input, a terminal to which power supply voltage VDD is input, a terminal to which ground voltage VSS is input, a terminal to which control signal VFR is input, and a control signal / VFR are input. And a terminal from which output signals G2 and G3 are output.

  Similarly, the shift register SR4 receives a terminal to which the clock signal CLK is input, a terminal to which the output signal G3 of the previous unit shift register SR3 is input, and an output signal G5 of the subsequent dummy unit shift register SR5. A terminal to which the power supply voltage VDD is input, a terminal to which the ground voltage VSS is input, a terminal to which the control signal VFR is input, a terminal to which the control signal / VFR is input, and an output signal G4 is output. Terminal.

  The clock signal C1 is input to the odd-numbered unit shift registers SR1 and SR3, and the clock signal C2 having a phase opposite to that of the clock signal C1 is input to the even-numbered unit shift registers SR2 and SR4.

  FIG. 2 is a timing chart showing operation waveforms of the shift register shown in FIG. 1 and 2, the unit shift register SR1 outputs the output signal G1 when the clock signal C1 is input after the start signal IN is input. The output signal G1 is input to the unit shift register SR2.

  The unit shift register SR2 outputs the output signal G2 when the clock signal C2 is input after the output signal G1 is input. The output signal G2 is input to the unit shift registers SR1 and SR3. In response to the input of the output signal G2, the unit shift register SR1 does not output the output signal G1 even if the clock signal C1 is input thereafter.

  Similarly, the unit shift register SR3 outputs the output signal G3 when the clock signal C1 is input after the output signal G2 is input. The output signal G3 is input to the unit shift registers SR2 and SR4. In response to the input of the output signal G3, the unit shift register SR2 does not output the output signal G2 even if the clock signal C2 is input thereafter.

  Similarly, the unit shift register SR4 outputs the output signal G4 when the clock signal C2 is input after the output signal G4 is input. The output signal G4 is input to the unit shift registers SR3 and SR5. In response to the input of the output signal G4, the unit shift register SR3 does not output the output signal G3 even if the clock signal C1 is input thereafter.

  In this manner, the output signals G1 to G4 are sequentially output from the four unit shift registers SR1 to SR4 in synchronization with the two-phase clock signals C1 and C2.

  Although FIGS. 1 and 2 show a shift register that operates in synchronization with the two-phase clock signals C1 and C2, the shift register can be driven using three-phase or more clock signals. FIG. 3 is a block diagram showing another overall configuration of the shift register according to the present invention, and shows a shift register that operates in synchronization with three-phase clock signals C1 to C3. The clock signal C3 is input to the unit shift registers SR1 and SR4, the clock signal C1 is input to the unit shift register SR2, and the clock signal C2 is input to the unit shift register SR3.

  FIG. 4 is a timing chart showing operation waveforms of the shift register shown in FIG. 3 and 4, the unit shift register SR1 outputs the output signal G1 when the clock signal C3 is input after the start signal IN is input. The output signal G1 is input to the unit shift register SR2. The unit shift register SR2 outputs the output signal G2 when the clock signal C1 is input after the output signal G1 is input. The output signal G2 is input to the unit shift register SR3. Similarly, the unit shift register SR3 outputs the output signal G3, and thereafter, the unit shift-registered SR4 outputs the output signal G4. In this manner, the output signals G1 to G4 are sequentially output from the four unit shift registers SR1 to SR4 in synchronization with the three-phase clock signals C1 to C3.

  FIG. 5 is a circuit diagram showing a configuration of unit shift register SR (respective shift registers SR1 to SR4) according to the first embodiment of the present invention. The transistors Q1 to Q12 are all N-type a-Si TFTs. The drain electrode of the transistor Q1 is connected to the terminal N4 to which the clock signal CLK is input, the source electrode is connected to the output terminal N3 that outputs the output signal Gn, and the gate electrode is connected to the node N9. Yes. The transistor Q1 functions as an output pull-up driving unit for charging the output terminal N3.

  The drain electrode of the transistor Q2 is connected to the output terminal N3, the source electrode is connected to a terminal to which the control signal / VFR is input, and the gate electrode is connected to the node N10. The drain electrode of the transistor Q3 is connected to the output terminal N3, the source electrode is connected to a terminal to which the control signal VFR is input, and the gate electrode is connected to the node N11. The transistors Q2 and Q3 function as an output pull-down driving unit for discharging the output terminal N3.

  The drain electrode of the transistor Q4 is connected to the terminal N1 to which the power supply voltage VDD is input, the source electrode is connected to the node N9, and the output signal Gn-1 (or the start signal IN) is input to the gate electrode. Connected to the terminal N6. The transistor Q4 functions as a part of the pull-up driving unit for activating the output pull-up driving unit (transistor Q1) in response to the output signal Gn-1.

  The drain electrode of the transistor Q5 is connected to the node N9, the source electrode is connected to a terminal to which the control signal / VFR is input, and the gate electrode is connected to the node N10. The drain electrode of the transistor Q6 is connected to the node N9, the source electrode is connected to a terminal to which the control signal VFR is input, and the gate electrode is connected to the node N11. The transistors Q5 and Q6 function as another part of the pull-up driving unit.

  The drain electrode of the transistor Q7 is connected to the terminal N7 to which the control signal VFR is input, the source electrode is connected to the node N10, and the gate electrode is connected to the terminal N5 to which the output signal Gn + 1 is input. Yes. The drain electrode of the transistor Q9 is connected to the terminal N8 to which the control signal / VFR is input, the source electrode is connected to the node N11, and the gate electrode is connected to the terminal N5. The transistors Q7 and Q9 function as a pull-down drive unit for activating the output pull-down drive unit (transistors Q2 and Q3) in response to the output signal Gn + 1.

  The drain electrode of the transistor Q8 is connected to the node N10, the source electrode is connected to the terminal N2 to which the ground voltage VSS is input, and the gate electrode is connected to the terminal N6. The drain electrode of the transistor Q10 is connected to the node N11, the source electrode is connected to the terminal N2, and the gate electrode is connected to the terminal N6.

  The drain electrode of the transistor Q11 is connected to the node N10, the source electrode is connected to a terminal to which the control signal VFR is input, and the gate electrode is connected to the node N11. The drain electrode of the transistor Q12 is connected to the node N11, the source electrode is connected to a terminal to which the control signal / VFR is input, and the gate electrode is connected to the node N10. Transistors Q11 and Q12 constitute a flip-flop circuit and are arranged mainly for the purpose of avoiding the influence of noise on the low level side of nodes N10 and N11. If there is no problem of an increase in low level due to noise or leakage current, the transistors Q11 and Q12 may be omitted.

  FIG. 6 is a timing chart showing operation waveforms of the unit shift register SR shown in FIG. The voltage VA shown in FIG. 6 is a high level voltage of the control signals VFR and / VFR shown in FIG. The voltage VA is an arbitrary voltage at which the transistors Q2, Q5, and Q12 are turned on. For simplicity of explanation, the voltage VA is a voltage at which the transistors Q7 and Q9 in the on state can operate in the non-saturated region. Further, Vth shown in FIG. 6 is a threshold voltage of the transistors Q1 to Q12. 5 and 6, it is assumed that the control signal VFR is at the high level and the control signal / VFR is at the low level (for example, the ground voltage VSS).

  5 and 6, in the initial state, the potential of node N10 is set to voltage VA, and the potential of node N11 is set to ground voltage VSS. Since the potential of the node N10 is set to the voltage VA, the transistor Q5 is turned on, and the potential of the node N9 is set to the ground voltage VSS. Further, since the potential of the node N10 is set to the voltage VA, the transistor Q2 is turned on, and the potential of the node N3 is set to the ground voltage VSS.

  When the output signal Gn-1 of the previous unit shift register SR becomes high level (power supply voltage VDD) at time t0, the transistor Q8 is turned on, so that the potential of the node N10 becomes the ground voltage VSS. As a result, the transistor Q5 is turned off. Further, when the transistor Q4 is turned on, the potential of the node N9 becomes VDD-Vth. As a result, the transistor Q1 is turned on.

  When the output signal Gn-1 of the preceding unit shift register SR becomes low level (ground voltage VSS) at time t1, the transistors Q4 and Q8 are turned off, but the potential of the node N9 (VDD-Vth) and the potential of the node N10 (ground) The voltage VSS) is held by parasitic capacitances (not shown) of the respective nodes N9 and N10.

  When the clock signal CLK becomes high level (power supply voltage VDD) at time t2, since the transistor Q1 is turned on, the potential of the output terminal N3 (output signal Gn) rises. Further, since the transistor Q1 is turned on, the clock signal CLK is capacitively coupled to the node N9 by a capacitance (not shown) between the node N9 and the channel of the transistor Q1, and as a result, the potential of the clock signal CLK is reduced. As the voltage rises, the potential at the node N9 also rises. Since the capacitance value between the gate electrode and the channel of the transistor Q1 is sufficiently larger than the parasitic capacitance value of the node N9, the potential of the node N9 rises by almost the amount of change (VDD) in the potential of the clock signal CLK. −Vth.

  The potential (2VDD−Vth) of the node N9 satisfies the condition for operating the transistor Q1 in the non-saturation region. Therefore, a voltage drop corresponding to the threshold voltage Vth of the transistor Q1 does not occur, and the potential of the output terminal N3 becomes the power supply voltage VDD which is the same as the high level of the clock signal CLK.

  When the clock signal CLK becomes low level (ground voltage VSS) at time t3, the transistor Q1 is turned on, so that the potential of the output terminal N3 also decreases as the potential of the clock signal CLK decreases, and the potential of the output terminal N3 is equal to the ground voltage. It becomes VSS. Further, the potential of the node N9 that is capacitively coupled to the clock signal CLK drops by the amount of change (VDD) of the potential of the clock signal CLK and becomes VDD-Vth.

  When the output signal Gn + 1 of the subsequent unit shift register SR becomes high level (power supply voltage VDD) at time t4, the transistor Q7 is turned on, so that the potential of the node N10 becomes the voltage VA. As a result, when the transistor Q5 is turned on, the potential of the node N9 becomes the ground voltage VSS. At this time, the transistor Q9 is also turned on, but since the potential of the control signal / VFR is the ground voltage VSS, the potential of the node N11 remains at the ground voltage VSS.

  The output signal Gn + 1 of the subsequent unit shift register SR becomes low level (ground voltage VSS) at time t5.

  After time t4, the unit shift register SR is in a non-selected state. In the non-selected state, the voltage VA is continuously applied to the gate electrodes of the transistors Q2, Q5, and Q12, and the ground voltage VSS is applied to the source electrodes of the transistors Q2, Q5, and Q12. Therefore, the transistors Q2, Q5, and Q12 are in a positive bias state. When the positive bias state continues for a long time, the threshold voltages Vth of the transistors Q2, Q5, and Q12 shift.

  By the way, the transistors Q3, Q6, and Q11 are paired with the transistors Q2, Q5, and Q12, respectively, and are biased complementary to the bias of the transistors Q2, Q5, and Q12. That is, when the control signal VFR is at a high level and the control signal / VFR is at a low level, the transistors Q2, Q5, and Q12 are positively biased, and the transistors Q3, Q6, and Q11 are negatively biased. Conversely, when the control signal VFR is at a low level and the control signal / VFR is at a high level, the transistors Q2, Q5, and Q12 are negatively biased, and the transistors Q3, Q6, and Q11 are positively biased.

  Therefore, as shown in the timing chart of FIG. 7, the high and low levels of the control signals VFR, / VFR are alternated every frame, so that the transistors Q2, Q5, Q12, Q3, Q6, Q11 are related. The threshold voltage Vth can be shifted alternately in the upward direction and in the downward direction. As a result, if the shift amount in the upward direction and the shift amount in the downward direction are equal to each other, as a result, the threshold voltage Vth does not vary from the initial value.

  Here, the cycle of alternating high / low levels of the control signals VFR, / VFR is not limited to one frame, but may be every one frame or less, or every two frames or more. As the alternating cycle is shortened, the power consumption of the circuit driving the control signals VFR, / VFR increases. In addition, the longer the alternating period, the more complicated the configuration of the external drive circuit for generating a pulse having a long pulse length.

  FIG. 8 is a circuit diagram showing a modification of the configuration of the unit shift register SR shown in FIG. The drain electrode of the transistor Q4 is connected not to the terminal N1 to which the power supply voltage VDD is input but to the terminal N6 to which the output signal Gn-1 (or the start signal IN) is input. Since the transistor Q4 operates in the saturation region, the potential of the node N9 is determined by the gate voltage of the transistor Q4. Since the high level of the output signal Gn-1 is the power supply voltage VDD, even when the drain electrode of the transistor Q4 is connected to the terminal N6 instead of the terminal N1, the potential of the node N9 is the same as that of the circuit shown in FIG. Value can be set.

  According to the unit shift register SR shown in FIG. 8, since the wiring for connecting the terminal N1 and the drain electrode of the transistor Q4 can be omitted, compared with the unit shift register SR shown in FIG. The area occupied by the circuit can be reduced.

Embodiment 2. FIG.
FIG. 9 is a circuit diagram showing a configuration of the unit shift register SR according to the second embodiment of the present invention. The source electrode of the transistor Q2 is connected to a terminal to which a control signal / VFR ′ is input, and the source electrode of the transistor Q3 is connected to a terminal to which a control signal VFR ′ is input. The source electrode of the transistor Q5 is connected to the terminal N8 ′ to which the control signal / VFR ′ is input, and the source electrode of the transistor Q6 is connected to the terminal N7 ′ to which the control signal VFR ′ is input. The source electrode of the transistor Q11 is connected to a terminal to which a control signal VFR ′ is input, and the source electrode of the transistor Q12 is connected to a terminal to which a control signal / VFR ′ is input. Other configurations of the unit shift register SR according to the second embodiment are the same as those shown in FIG.

  FIG. 10 is a timing chart showing the alternating timing of the control signals VFR, / VFR, VFR ′, / VFR ′, corresponding to FIG. As shown in FIG. 10, the high level voltage value VB of the control signals VFR ′ and / VFR ′ is set higher than the high level voltage value VA of the control signals VFR and / VFR.

  That is, the high level voltage value VB of the control signal / VFR ′ input to each source electrode of the transistors Q2, Q5, and Q12 is output from the transistor Q9 in response to the output signal Gn + 1 of the unit shift register SR in the subsequent stage. Similarly, the high level voltage value VB of the control signal VFR ′ input to the source electrodes of the transistors Q3, Q6, and Q11 is higher than the high level voltage value VA, and the output signal Gn + 1 of the subsequent unit shift register SR. In response to the high level voltage value VA output from the transistor Q7. In other words, for each of the transistors Q2, Q5, Q12, Q3, Q6, and Q11, the bias voltage value VB when the negative bias is made is set higher than the bias voltage value VA when the positive bias is made. .

  Normally, for an N-type a-Si TFT, the shift amount of the threshold voltage Vth due to the positive bias is greater than the shift amount of the threshold voltage Vth due to the negative bias. large. Since the shift amount of the threshold voltage Vth depends on the magnitude of the bias voltage, according to the unit shift register SR according to the second embodiment, the bias voltage value VB when the negative bias is applied is expressed by the positive bias. By setting it higher than the bias voltage value VA at the time of being made, the shift amount in the increasing direction and the shift amount in the decreasing direction of the threshold voltage Vth can be made equal to each other.

Embodiment 3 FIG.
FIG. 11 is a circuit diagram showing a configuration of a unit shift register SR according to the third embodiment of the present invention. The transistor Q13 is an N-type a-Si TFT. The gate electrode of the transistor Q7 is connected to the terminal N7 to which the control signal VFR is input, and the gate electrode of the transistor Q9 is connected to the terminal N8 to which the control signal / VFR is input. The gate electrodes of the transistors Q8 and Q10 are connected to the node N9. The drain electrode of the transistor Q13 is connected to the node N9, the source electrode is connected to the terminal N2 to which the ground voltage VSS is input, and the gate electrode is connected to the terminal N5 to which the output signal Gn + 1 is input. Yes. Other configurations of the unit shift register SR according to the third embodiment are the same as those shown in FIG.

  FIG. 12 is a timing chart showing operation waveforms of the unit shift register SR shown in FIG. 11 and 12, it is assumed that the control signal VFR is at a high level and the control signal / VFR is at a low level.

  In the initial state, the potential of the node N10 is set to the voltage VA-Vth, and the potential of the node N11 is set to the ground voltage VSS. Since the potential of the node N10 is set to the voltage VA-Vth, the transistor Q5 is turned on, and the potential of the node N9 is set to the ground voltage VSS. Further, since the potential of the node N10 is set to the voltage VA-Vth, the transistor Q2 is turned on, and the potential of the node N3 is set to the ground voltage VSS.

  When the output signal Gn-1 of the previous unit shift register SR becomes high level (power supply voltage VDD) at time t0, the transistor Q4 is turned on. At this time, the transistor Q5 is also turned on, but by making the on-resistance of the transistor Q4 sufficiently smaller than the on-resistance of the transistor Q5, the potential of the node N9 rises to VDD−Vth. As a result, the transistor Q1 is turned on. Further, when the transistor Q8 is turned on, the potential of the node N10 becomes the ground voltage VSS.

  When the output signal Gn-1 of the previous unit shift register SR becomes low level (ground voltage VSS) at time t1, the transistor Q4 is turned off, but the potential (VDD-Vth) of the node N9 is equal to the parasitic capacitance (not shown) of the node N9. Not). Further, since the transistor Q8 is turned on, the potential of the node N10 is maintained at the ground voltage VSS.

  When the clock signal CLK becomes high level (power supply voltage VDD) at time t2, since the transistor Q1 is turned on, the potential of the output terminal N3 (output signal Gn) rises. Further, since the transistor Q1 is turned on, the clock signal CLK is capacitively coupled to the node N9 by a capacitance (not shown) between the node N9 and the channel of the transistor Q1, and as a result, the potential of the clock signal CLK is reduced. As the voltage rises, the potential at the node N9 also rises. Since the capacitance value between the gate electrode and the channel of the transistor Q1 is sufficiently larger than the parasitic capacitance value of the node N9, the potential of the node N9 rises by almost the amount of change (VDD) in the potential of the clock signal CLK. −Vth.

  The potential (2VDD−Vth) of the node N9 satisfies the condition for operating the transistor Q1 in the non-saturation region. Therefore, a voltage drop corresponding to the threshold voltage Vth of the transistor Q1 does not occur, and the potential of the output terminal N3 becomes the power supply voltage VDD which is the same as the high level of the clock signal CLK.

  When the clock signal CLK becomes low level (ground voltage VSS) at time t3, the transistor Q1 is turned on, so that the potential of the output terminal N3 also decreases as the potential of the clock signal CLK decreases, and the potential of the output terminal N3 is equal to the ground voltage. It becomes VSS. Further, the potential of the node N9 that is capacitively coupled to the clock signal CLK drops by the amount of change (VDD) of the potential of the clock signal CLK and becomes VDD-Vth.

  When the output signal Gn + 1 of the subsequent unit shift register SR becomes high level (power supply voltage VDD) at time t4, the transistor Q13 is turned on, so that the potential of the node N9 becomes the ground voltage VSS. As a result, the transistor Q8 is turned off, so that the potential of the node N10 becomes VA-Vth. At this time, the potential of the node N11 remains at the ground voltage VSS.

  The output signal Gn + 1 of the subsequent unit shift register SR becomes low level (ground voltage VSS) at time t5.

  After time t4, the unit shift register SR is in a non-selected state. In the non-selected state, the voltage VA-Vth is continuously applied to the gate electrodes of the transistors Q2, Q5, and Q12, and the ground voltage VSS is applied to the source electrodes of the transistors Q2, Q5, and Q12. Therefore, the transistors Q2, Q5, and Q12 are in a positive bias state. When the positive bias state continues for a long time, the threshold voltages Vth of the transistors Q2, Q5, and Q12 shift.

  By the way, the transistors Q3, Q6, and Q11 are paired with the transistors Q2, Q5, and Q12, respectively, and are biased complementary to the bias of the transistors Q2, Q5, and Q12. That is, when the control signal VFR is at a high level and the control signal / VFR is at a low level, the transistors Q2, Q5, and Q12 are positively biased, and the transistors Q3, Q6, and Q11 are negatively biased. Conversely, when the control signal VFR is at a low level and the control signal / VFR is at a high level, the transistors Q2, Q5, and Q12 are negatively biased, and the transistors Q3, Q6, and Q11 are positively biased.

  Therefore, as shown in the timing chart of FIG. 7, by alternating the high / low levels of the control signals VFR, / VFR for each frame, the transistors Q2, Q5, Q12, Q3, Q6, Q11 are related. The threshold voltage Vth can be shifted alternately in the upward direction and in the downward direction. As a result, if the shift amount in the upward direction and the shift amount in the downward direction are equal to each other, as a result, the threshold voltage Vth does not vary from the initial value.

  According to the unit shift register SR according to the third embodiment, the high level voltage VA-Vth at the node N10 or the node N11 is supplied from the transistor Q7 or the transistor Q9 that is always turned on. Therefore, even if a leakage current occurs in the transistors Q8 and Q11 or the transistors Q10 and Q12 in the non-selected state, the node N10 or the node N11 is maintained at the high level voltage VA−Vth as compared with the configuration illustrated in FIG. It becomes easy.

  On the other hand, according to the configuration shown in FIG. 11, when the transistor Q8 is turned on, a through current flows from the terminal N7 through the transistors Q7 and Q8 to the terminal N2, and when the transistor Q10 is turned on, the terminal N8 is passed through the transistors Q9 and Q10. Through current flows through the terminal N2. On the other hand, according to the configuration shown in FIG. 5, the transistor Q7 and the transistor Q8 are not turned on at the same time, and the transistor Q9 and the transistor Q10 are not turned on at the same time. There is an advantage that power consumption is small.

  FIG. 13 is a circuit diagram showing a modification of the configuration of the unit shift register SR shown in FIG. The drain electrode of the transistor Q4 is connected not to the terminal N1 to which the power supply voltage VDD is input but to the terminal N6 to which the output signal Gn-1 (or the start signal IN) is input. Since the transistor Q4 operates in the saturation region, the potential of the node N9 is determined by the gate voltage of the transistor Q4. Since the high level of the output signal Gn-1 is the power supply voltage VDD, even when the drain electrode of the transistor Q4 is connected to the terminal N6 instead of the terminal N1, the potential of the node N9 is the same as that of the circuit shown in FIG. Value can be set.

  According to the unit shift register SR shown in FIG. 13, since the wiring for connecting the terminal N1 and the drain electrode of the transistor Q4 can be omitted, compared with the unit shift register SR shown in FIG. The area occupied by the circuit can be reduced.

Embodiment 4 FIG.
FIG. 14 is a circuit diagram showing a configuration of a unit shift register SR according to the fourth embodiment of the present invention. The source electrode of the transistor Q2 is connected to a terminal to which a control signal / VFR ′ is input, and the source electrode of the transistor Q3 is connected to a terminal to which a control signal VFR ′ is input. The source electrode of the transistor Q5 is connected to the terminal N8 ′ to which the control signal / VFR ′ is input, and the source electrode of the transistor Q6 is connected to the terminal N7 ′ to which the control signal VFR ′ is input. The source electrode of the transistor Q11 is connected to a terminal to which a control signal VFR ′ is input, and the source electrode of the transistor Q12 is connected to a terminal to which a control signal / VFR ′ is input. Other configurations of the unit shift register SR according to the fourth embodiment are the same as those shown in FIG.

  As shown in FIG. 10, the high level voltage value VB of the control signals VFR ′ and / VFR ′ is set higher than the high level voltage value VA of the control signals VFR and / VFR.

  That is, the high level voltage value VB of the control signal / VFR ′ input to each source electrode of the transistors Q2, Q5, and Q12 is output from the transistor Q9 in response to the output signal Gn + 1 of the unit shift register SR in the subsequent stage. Similarly, the high-level voltage value VB of the control signal VFR ′ input to the source electrodes of the transistors Q3, Q6, and Q11 is higher than the high-level voltage value VA. In response to the high level voltage value VA output from the transistor Q7. In other words, for each of the transistors Q2, Q5, Q12, Q3, Q6, and Q11, the bias voltage value VB when the negative bias is made is set higher than the bias voltage value VA when the positive bias is made. .

  Normally, for an N-type a-Si TFT, the shift amount of the threshold voltage Vth due to the positive bias is greater than the shift amount of the threshold voltage Vth due to the negative bias. large. Since the shift amount of the threshold voltage Vth depends on the magnitude of the bias voltage, according to the unit shift register SR according to the fourth embodiment, the bias voltage value VB when the negative bias is applied is expressed by the positive bias. By setting it higher than the bias voltage value VA at the time of being made, the shift amount in the increasing direction and the shift amount in the decreasing direction of the threshold voltage Vth can be made equal to each other.

It is a block diagram which shows the whole structure of the shift register which concerns on this invention. 2 is a timing chart showing operation waveforms of the shift register shown in FIG. 1. It is a block diagram which shows the other whole structure of the shift register which concerns on this invention. 4 is a timing chart showing operation waveforms of the shift register shown in FIG. 3. 1 is a circuit diagram illustrating a configuration of a unit shift register according to a first embodiment of the present invention. 6 is a timing chart showing operation waveforms of the unit shift register shown in FIG. 5. It is a timing chart which shows the alternating timing of a control signal. FIG. 6 is a circuit diagram illustrating a modification of the configuration of the unit shift register illustrated in FIG. 5. It is a circuit diagram which shows the structure of the unit shift register which concerns on Embodiment 2 of this invention. FIG. 8 is a timing chart showing alternating timing of control signals in correspondence with FIG. 7. FIG. It is a circuit diagram which shows the structure of the unit shift register which concerns on Embodiment 3 of this invention. 12 is a timing chart showing operation waveforms of the unit shift register shown in FIG. FIG. 12 is a circuit diagram illustrating a modification of the configuration of the unit shift register illustrated in FIG. 11. It is a circuit diagram which shows the structure of the unit shift register which concerns on Embodiment 4 of this invention.

Explanation of symbols

Q1-Q13 transistor, N3 output terminal, N4 terminal, VFR, / VFR, VFR ′, / VFR ′ control signals.

Claims (9)

A plurality of unit shift registers are cascaded and operate in synchronization with a plurality of clock signals having different phases,
Each of the plurality of unit shift registers is
An output terminal;
An output pull-up driver connected between the output terminal and the clock input terminal and charging the output terminal;
A first output pull-down driver connected between the output terminal and a terminal to which a first control signal is input, and discharging the output terminal;
A shift having a second output pull-down driver connected between the output terminal and a terminal to which a second control signal complementary to the first control signal is input, and discharges the output terminal. register. Each of the plurality of unit shift registers is
A pull-up driver that activates the output pull-up driver in response to the output signal of the unit shift register of the previous stage;
2. The shift register according to claim 1, further comprising a pull-down driver that activates the first or second output pull-down driver in response to an output signal of a subsequent unit shift register. The pull-down driver is
A first pull-down driver that applies a voltage corresponding to the voltage of the first control signal to the second output pull-down driver in response to the output signal of the unit shift register at the subsequent stage;
A second pull-down driver that applies a voltage corresponding to the voltage of the second control signal to the first output pull-down driver in response to the output signal of the unit shift register at the subsequent stage. Item 3. The shift register according to Item 2. The first output pull-down driver is
A first electrode connected to the output terminal;
A second electrode connected to a terminal to which the first control signal is input;
A first transistor including a control electrode connected to an output node of the second pull-down driver,
The second output pull-down driver is
A first electrode connected to the output terminal;
A second electrode connected to a terminal to which the second control signal is input;
The shift register according to claim 3, further comprising: a second transistor including a control electrode connected to an output node of the first pull-down driver. The high level voltage value of the first control signal input to the second electrode of the first transistor is output from the first pull-down driving unit in response to the output signal of the unit shift register at the subsequent stage. Higher than the high level voltage value of the voltage
The high level voltage value of the second control signal input to the second electrode of the second transistor is output from the second pull-down driving unit in response to the output signal of the unit shift register at the subsequent stage. The shift register according to claim 4, wherein the shift register is higher than a high level voltage value of the voltage to be applied. The pull-up drive unit is
A first electrode connected to the output pull-up driver;
A control electrode connected to a terminal to which the output signal of the preceding unit shift register is input;
A third transistor including the control electrode or a second electrode connected to a power supply terminal to which a power supply potential is input;
A first electrode connected to the output pull-up driver;
A second electrode connected to a terminal to which the first control signal is input;
A fourth transistor including a control electrode connected to the output node of the second pull-down driver;
A first electrode connected to the output pull-up driver;
A second electrode connected to a terminal to which the second control signal is input;
The shift register according to claim 3, further comprising: a fifth transistor including a control electrode connected to an output node of the first pull-down driver. The high level voltage value of the first control signal input to the second electrode of the fourth transistor is output from the first pull-down driver in response to the output signal of the unit shift register at the subsequent stage. Higher than the high level voltage value of the voltage
The high level voltage value of the second control signal input to the second electrode of the fifth transistor is output from the second pull-down driving unit in response to the output signal of the unit shift register at the subsequent stage. The shift register according to claim 6, wherein the shift register is higher than a high level voltage value of the voltage to be applied. A first electrode connected to an output node of the first pull-down driver;
A second electrode connected to a terminal to which the first control signal is input;
A sixth transistor including a control electrode connected to the output node of the second pull-down driver;
A first electrode connected to an output node of the second pull-down driver;
A second electrode connected to a terminal to which the second control signal is input;
The shift register according to claim 3, further comprising a seventh transistor including a control electrode connected to an output node of the first pull-down driver. The high level voltage value of the first control signal input to the second electrode of the sixth transistor is output from the first pull-down driving unit in response to the output signal of the unit shift register at the subsequent stage. Higher than the high level voltage value of the voltage
The high-level voltage value of the second control signal input to the second electrode of the seventh transistor is output from the second pull-down driver in response to the output signal of the subsequent unit shift register. The shift register according to claim 8, wherein the shift register is higher than a high-level voltage value of the voltage.

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