JP2006344153A - Information processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing system that can cause a peripheral device processor to take over part of the work of a host processor. <P>SOLUTION: The information processing system 10 includes a main CPU 20, an accelerator 40, and a peripheral device 60 having a local CPU 30. The main CPU 20 determines whether or not to request the local CPU to control the accelerator, and if determining to make the request to the local CPU 30, instructs the local CPU 30 on control command content to be given to the accelerator 40. The local CPU 30 gives to the accelerator 40 a control command to the accelerator 40 stored in a predetermined memory 50 according to the instruction from the main CPU 20. The accelerator 40 executes processing corresponding to the given control command. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing system.

  In an information processing system that includes a main CPU, an accelerator, and peripheral devices, the operations of the main CPU and peripheral devices are determined when the system is built. There is no replacement.

  Here, when the peripheral device processor is in an idle state, if a part of the operation of the host processor is taken over by the peripheral device processor, the processing capacity of the entire system can be improved.

  However, when the peripheral device processor does not have the same function as the host processor, or when the interface to the accelerator is different, it is difficult to transfer part of the host processor's work to the peripheral device processor. there were.

  The present invention has been made in view of the problems as described above, and an object of the present invention is to provide an information processing system capable of taking over a part of the work of a host processor by a processor for a peripheral device. Objective.

(1) The present invention
An information processing system including a peripheral device having a main CPU, an accelerator providing a given function, and a local CPU,
The main CPU includes accelerator control processing means,
Accelerator control processing means
Determining means for determining whether to request the local CPU to control the accelerator;
If it is determined not to request to the local CPU, the control command for the accelerator stored in the given memory is given to the accelerator by itself.
If it is determined to request the local CPU, the control command content to be given to the accelerator is instructed to the local CPU,
The local CPU gives a control command for the accelerator stored in a given memory to the accelerator based on an instruction from the main CPU,
The accelerator includes a control command execution unit that executes processing corresponding to a given control command (moves from the host or the peripheral device through the same interface).

  The determination means can be realized, for example, by the main CPU executing a program of a predetermined determination algorithm.

For a given memory,
The local CPU is for controlling peripheral devices (peripherals) and does not have the same function as the main CPU.

  The accelerator control command is defined by an API (application interface).

  When receiving an accelerator control command defined by an API (application interface), the accelerator control command execution unit functions as a driver that analyzes and executes the control command. The accelerator control command execution unit operates with the same interface for the main CPU and the local CPU (that is, the same processing is performed regardless of whether the accelerator control command is issued by the main CPU or the local CPU). It is configured).

  According to the present invention, since the processing can be distributed when the slave processor is idle or when the processing of the main CPU is busy, the processing speed of the system can be improved in the business using the accelerator.

(2) The information processing system of the present invention
A memory that is accessible from the main CPU and the local CPU and that stores a control command for an accelerator;
The main CPU is
If it is determined that the request is made to the local CPU, the address on the memory where the control command to be given to the accelerator is stored is instructed to the local CPU,
The local CPU reads a control command from an address on the memory instructed by a main CPU, and gives a control command to the accelerator.

  According to the present invention, when it is determined that the main CPU requests the local CPU, the processing is simple because it is only necessary to indicate the address where the control command is stored.

(3) The information processing system of the present invention
The determination means includes
It includes means for determining whether or not an accelerator control request can be made based on a processing schedule or processing content of the main CPU.

  For example, an accelerator control request may be made to the local CPU when a process with a high calculation load is included in the process schedule or process contents of the main CPU.

(4) The information processing system of the present invention
The determination means includes
It includes means for inquiring an accelerator control request to the local CPU device, and determining whether or not an accelerator control request can be made based on a response result to the inquiry.

(5) The information processing system of the present invention
The determination means includes
It includes means for determining whether or not an accelerator control request can be made based on the usage status of the peripheral device.

  The usage status of the peripheral device may be determined based on, for example, whether or not the main CPU is using the peripheral device.

In addition, in the area that can be referred to by the main CPU, there is a register indicating whether the operation status of the peripheral device or the processing request can be accepted,
The local CPU updates the register based on its operating status,
The determination means of the main CPU is:
Whether or not a processing request can be made may be determined based on the register.

  For example, it may be configured to have a flag register indicating whether or not the peripheral device can process, and the main CPU refers to the flag register.

(6) The information processing system of the present invention
A first bus connected to at least a main CPU, peripheral devices, an accelerator, and a memory;
A second bus connected to at least the peripheral device, the accelerator, and the memory;
When the main CPU controls the accelerator, use the first bus,
The second bus is used when the local CPU controls the accelerator.

  In this way, the use of the buses of the main CPU and the local CPU does not compete with each other, so that smooth distributed processing can be performed.

1. Integrated Circuit Device Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  In the following, a network is connected to a server that manages various image data, a 3D image is generated from the image data in real time and displayed on a monitor (first function), numerical information is detected from the image data, and this is detected. A system capable of performing a calculation based on the above and superimposing the calculation result into a 3D image (second function), and encrypting the generated display image data and storing it in a server (third A system capable of functioning will be described as an example.

  FIG. 1 is a diagram for explaining the information processing system according to the present embodiment.

  The information processing system 10 according to the present embodiment includes a main CPU 20, an accelerator (here, an image processing accelerator 40, an encryption processing accelerator 42, a compression / decompression processing accelerator 44, etc.), peripheral devices (here, a network controller 60, an HDD controller 62). USB controller 64, graphic controller 66, other controller 68, etc.).

  The information processing system 10 according to the present embodiment includes an IOP (I / O-Processor) / bus bridge circuit 30. The IOP (I / O-Processor) / bus bridge circuit 30 is a combination of the IOP (I / O-Processor) and the bus bridge circuit in one block. There is no. Here, the IOP (I / O-Processor) is a local CPU originally described in the peripheral devices 60, 62, 64, 66 as IOP (I / O-Processor), and is independently described. , 62, 64, 66 may be a local CPU.

  The information processing system 10 according to the present embodiment may include a memory 50 accessible from the main CPU 20 and the IOP (local memory) 30.

  The information processing system 10 according to the present embodiment includes a main CPU 20, peripheral devices 60, 62, 64, 66, 68, accelerators 40, 42, 44, and a main bus (first bus) 70 connected to the memory 50. Peripheral devices 60, 62, 64, 66, 68, accelerators 40, 42, 44, and an I / O bus (second bus) connected to the memory may be included.

  The image processing accelerator 40 performs a digital image conversion process.

  The encryption processing accelerator 42 performs encryption processing of personal information, content data, and the like.

  The compression / decompression processing accelerator 44 performs file compression / decompression processing.

  The network controller 60 is an Eathernet or wireless LAN controller.

  The HDD controller 62 is an ATA, S-ATA, or MT controller.

  The USB controller 64 is a USB / UART controller.

  The graphic controller 66 is a controller for graphic control and monitor output.

  The other controller 68 is, for example, a controller for GPIO, keyboard, or mause.

  The main CPU 20 of the present embodiment includes accelerator control processing means. The accelerator control processing means controls the accelerator (here, the image processing accelerator 40, the encryption processing accelerator 42, the compression / decompression processing accelerator 44, etc.) by the main CPU 20 itself, or a peripheral device (here, the local CPU of the peripheral device). When the main CPU 20 determines that the IOP / bus bridge circuit 30) is to perform control, and the main CPU 20 determines to control the accelerator itself, the control command for the accelerator stored in the given memory 50 is transmitted to the accelerator itself. Is issued to the peripheral device, the processing for operating the accelerator is performed, and if it is determined that the peripheral device is to perform the processing, the control device content to be issued to the accelerator is instructed to the peripheral device.

  The accelerators 40, 42, and 44 include a control command execution unit that executes processing corresponding to the received control command (moves from the host or the peripheral device through the same interface).

  Here, the determination means can be realized in software by the main CPU executing a determination processing program stored in the memory 50, for example.

  Peripheral devices 60, 62, 64, 66, 68 include a local CPU (here, IOP / bus bridge circuit 30) for controlling the operation of the peripheral device, and the local CPU 30 is based on an instruction from main CPU 20, When a control command is given to the accelerators 40, 42, 44 stored in a given memory 50, the accelerator 40, 42, 44 executes the process instructed by the control command.

  Control commands for the accelerators 40, 42, and 44 may be stored in the memory 50 accessible from the main CPU 20 and the local CPU 30. The main CPU 20 may instruct the peripheral device (here, IOP / bus bridge circuit 30 which is a local CPU) the contents of the control command issued to the accelerator by the address of the control command on the memory 50. . The local CPU (here, the IOP / bus bridge circuit 30) may read a control command from an address on the memory instructed by the main CPU 20 and issue a control command to the accelerators 40, 42, and 44. .

  Further, the determination means may inquire of the processing request to the peripheral device (here, the IOP / bus bridge circuit 30 which is the local CPU), and determine whether the processing request is possible based on the response result.

  The determination means may determine whether or not a processing request is possible based on the usage status of the peripheral device (here, the IOP / bus bridge circuit 30 which is a local CPU).

  Further, an area (in this case, for example, the memory 50) that can be referred to by the main CPU has a register that indicates whether the peripheral devices 60, 62, 64, 66, and 68 are operating or whether processing requests can be accepted. Here, the IOP / bus bridge circuit 30) updates the register based on the operating status of the peripheral devices 60, 62, 64, 66, and 68, and the main CPU 20 determines whether or not a processing request is possible based on the register. Also good.

  When the main CPU 20 controls the accelerators 40, 42, and 44, the main bus (first bus) is used, and the local CPU (here, the IOP / bus bridge circuit 30) controls the accelerators 40, 42, and 44. When performing this, an I / O bus (second bus) may be used.

  FIG. 2 is a diagram for explaining an information processing system of a comparative example.

  The information processing system 10 ′ of the comparative example includes a main CPU 20 ′ accelerator (here, image processing accelerator 40 ′, encryption processing accelerator 42 ′, compression / decompression processing accelerator 44 ′, etc.), peripheral devices (here, network controller 60 ′, HDD controller 62 ′, USB controller 64 ′, graphic controller 66 ′, other controller 68 ′, etc.).

  The information processing system 10 'according to the comparative example includes an IOP (I / O-Processor) / bus bridge circuit 30'. The IOP (I / O-Processor) / bus bridge circuit 30 'is a configuration in which the IOP (I / O-Processor) and the bus bridge circuit are combined into one block and are described as separate blocks. There is no difference. Here, the IOP (I / O-Processor) is a local CPU that originally exists in the peripheral devices 60 ′, 62 ′, 64 ′, 66 ′ and is described independently as an IOP (I / O-Processor). It may be a local CPU existing in the peripheral devices 60 ′, 62 ′, 64 ′, 66 ′.

  In the information processing system 10 ′ of the comparative example, the accelerators 40 ′, 42 ′, and 44 ′ are connected only to the main bus (first bus).

  The comparative information processing system 10 ′ includes a memory 50 ′ that is accessible from the main CPU 20 but not accessible from the IOP (local CPU) 30 ′.

  In contrast, in the present embodiment, when the IOP (local CPU) 30 executes processing, the accelerators 40, 42, and 44 and the main memory 50 are provided with IOs so that the main bus (first bus) 70 is not used. Interfaces 41, 43, 45 and 54 from the bus (second bus) 80 are provided. Therefore, the only memory in the main memory 50 that can be used as it is by the IOP (local memory) 30 is that the main CPU 20 only receives a storage destination designation (a format that does not require the data itself to be transferred). The command list (API executed by the accelerator) can be transferred.

  The accelerators 40 ', 42', and 44 'in FIG. 2 originally have APIs, but usually there is driver level software, and the code defined by the API issued by the host program is used for HW control of the accelerator. Dropping and running. For this reason, in the comparative example, when the CPU that executes the API is changed to other than the main CPU, for example, when the CPU is changed to the IOP (local CPU) 30 ′, the driver is changed to the changing CPU (here, the IOP (local CPU) 30 ′). Must be installed. On the other hand, in the present embodiment, even if there is no driver, a batch of codes describing processing is handled as data (see FIG. 14), so the IOP (local CPU) 30 is simply connected to the command port of the accelerator, for example. A series of processes can be executed by writing data.

  That is, in terms of the combination of the above API and driver, the accelerators 40, 42, and 44 have a driver function from the beginning, and if the API code is written as data, the subsequent processing can be completed within the accelerator. Configure as you can.

  FIG. 3 is a diagram for explaining an example of processing in which the main CPU requests the local CPU to control the accelerator.

  Here, the host CPU 120, the memory 150, the peripheral device 160, and the accelerator 140 are connected to the system bus 170, and the peripheral device 160 and the accelerator 140 are configured to be able to exchange without going through the system bus. The peripheral device 160 includes a local CPU 130 and a local memory 132 for controlling peripheral devices.

  The main CPU determines whether or not to request the local CPU to control the accelerator. If the main CPU determines to request the local CPU, the main CPU instructs the local CPU on the contents of the control command to be given to the accelerator. For example, when the main CPU has numerical calculation processing, the control of the accelerator may be requested to the local CPU.

  The main CPU transfers a command for a series of processing of the accelerator and necessary data or designation information of an area having data to the local memory, and requests control of the accelerator (see S1). For example, if a command and necessary data or designation information of an area with data can be placed in a memory accessible from both the main CPU and the local CPU, an address on the memory may be designated for the local CPU. Good.

The local CPU 130 gives a control command for the accelerator stored in a given memory to the accelerator based on an instruction from the main CPU. Here, the local CPU gives an instruction to the accelerator from the command transferred to the local memory 132 and the necessary data or data area instruction information (see S2).

  The accelerator executes processing corresponding to the given control command. Then, the processing end signal and the processing result are returned to the local CPU (see S3).

  When all the commands have been executed, the local CPU 130 returns the end and the processing result or the storage area information of the processing result to the CPU (see S4).

  4 and 5 are diagrams for explaining the processing flow of the main CPU.

  FIG. 4 is a flowchart when the main CPU controls the graphic accelerator and the encryption processing accelerator.

  First, block data is read (step S10).

  Next, an image processing accelerator control process is performed (step S20). In this example, the main CPU determines that the image processing accelerator is to be controlled by itself. Processing for operating the image processing accelerator by issuing a control command for the image processing accelerator stored in the memory to the image processing accelerator. To do. Details of the processing of the image processing accelerator will be described with reference to FIG.

  Next, as a process for realizing the first function, image display of image data after image processing is performed (step S50). The graphic display on the IO bus executes the image display. The specific processing contents of the image display will be described with reference to FIG.

  Next, as a process for realizing the second function, an encryption process (step S30) is first performed. In this example, it is determined that the main CPU controls the encryption processing accelerator by itself, and the encryption processing accelerator is issued by issuing a control command for the encryption processing accelerator stored in the memory to the encryption processing accelerator. Perform processing to operate. Details of the processing of the encryption processing accelerator will be described with reference to FIG.

  Next, data transmission processing (step S40) is performed. Details of the data transmission process will be described with reference to FIG.

  FIG. 5 is a flowchart when the main CPU instructs the local CPU to control the graphic accelerator and the encryption processing accelerator.

  In FIG. 5, numerical calculation is performed and the load on the main CPU becomes heavy, and the setting is to instruct the IOP (local CPU) to control the graphic accelerator and the encryption processing accelerator (steps S120 and S130).

  In general, there are various types of numerical calculations, such as for weather analysis, structural analysis of buildings, destruction simulation of buildings, etc., and since it must be executed by a program, it is not possible to request numerical calculations from the IOP (local CPU) It is.

  First, block data is read (step S110).

  Here, since the processing in steps S150 to S170 is performed, numerical calculation is performed and the load on the main CPU becomes heavy, so that it is determined that the accelerator is controlled by the peripheral device.

  Therefore, first, an image processing accelerator control process is performed (step S120). In this example, it is determined that the peripheral device is to be controlled by the image processing accelerator, and the control command to be issued to the image processing accelerator is instructed to the peripheral device (here, IOP (local CPU)). The contents of the control command can be instructed by, for example, instructing the address of the memory storing the control command for the image processing accelerator.

  The IOP (local CPU) performs processing for operating the image processing accelerator by issuing a control command for the image processing accelerator stored in a given memory based on an instruction from the main CPU. Details of the processing of the image processing accelerator will be described with reference to FIG.

  Next, as a process for realizing the second function, an encryption process (step S130) is first performed. In this example, it is determined that the peripheral processing device is to be controlled by the encryption processing accelerator, and the control command to be issued to the encryption processing accelerator is instructed to the peripheral device (here, IOP (local CPU)). The contents of the control command can be instructed by, for example, instructing the address of the memory storing the control command for the image processing accelerator.

  The IOP (local CPU) performs a process for operating the encryption processing accelerator by issuing a control command to the encryption processing accelerator stored in a given memory based on an instruction from the main CPU. Details of the processing of the encryption processing accelerator will be described with reference to FIG.

  Next, data transmission processing (step S140) is performed. Details of the data transmission process will be described with reference to FIG.

  Further, in FIG. 5, the processes of steps S150 to S160 are performed to realize the superimpose (third function), and the processes of steps S170 to S180 are performed to generate data for image display (first function). I do.

  First, numerical data extraction processing is performed (step S150). The specific contents of the numerical data extraction process are shown in FIG. This is performed by the main CPU because it is executed by a program.

  Next, numerical calculation processing is performed (step S160). The specific contents of the numerical calculation process are shown in FIG. This is performed by the main CPU because it is executed by a program.

  Next, image composition processing is performed (step S170). Image composition is executed by the graphic controller on the IO bus. The specific processing contents of the image display will be described with reference to FIG.

  Next, as a process for realizing the first function, image display of image data after image processing is performed (step S180). The graphic display on the IO bus executes the image display. The specific processing contents of the image display will be described with reference to FIG.

  FIG. 6 is a flowchart for explaining block data read processing.

  First, the channel of the network controller is specified, and data transfer from the server is requested to the IOP (step S210).

  Until the data is completed, the IOP controls the network controller, reads the data from the server, and stores it in the main memory (step S220).

  When the data is finished, the IOP interrupts the main CPU (step S240).

  The CPU performs a data transfer end process (step S250).

  FIG. 7 is a flowchart for explaining the processing of the image processing accelerator.

  The image processing accelerator performs processing such as an instruction to the DMAC, an instruction to the geometry engine, an instruction to the rendering engine, and an instruction to the pixel engine.

  First, a 3D image generation instruction command is set (step S310). Here, processing instructions are given to the geometry engine, rendering engine, and pixel engine.

  Next, the storage destination of the original data is designated (step S320).

  Next, the storage destination of the processing data is designated (step S330).

  Next, an end condition is designated (step S340). The designation of the end condition may be performed according to the data size, or may be performed according to a time limit or the like.

  Next, a process start instruction is given (step S350).

  The viewpoint information is transmitted until the end condition is satisfied (step S360). Here, the viewpoint information is input to the geometry engine. The viewpoint information is information instructed by operating a mouse or the like while viewing an image, for example.

  When the termination condition is satisfied, the CPU performs termination processing (steps S370 and S380).

  FIG. 8 is a flowchart for explaining the encryption process.

  The encryption process is performed using a key input at the start of the process. It is assumed that data is encrypted in block units.

  First, key information is set (step S410).

  Next, the DMAC is set (designation of data input area and data output area) (step S420).

  Next, an instruction for permission to start encryption processing is given (step S430).

  Next, the DMAC is activated (step S440).

  When the encryption processing accelerator performs encryption processing for all data in units of blocks, the CPU performs end processing (steps S450 and S470).

  FIG. 9 is a flowchart for explaining the data transmission process.

  First, the channel of the network controller is designated, and data transfer to the server is instructed (step S510).

  Until the data is completed, the IOP controls the network controller and reads the data from the main memory and transfers it to the server (steps S520 and S530). When the data is finished, the CPU is interrupted (step S540).

  The CPU performs a data transfer end process (step S550).

  FIG. 10 is a flowchart for explaining the numerical data extraction process.

  The following processing is repeated until the data is completed.

  First, the original data is read (step S610).

  Next, numerical data is detected (step S620).

  The time stamp and numerical value of the data are written in a predetermined memory area (step S630).

  FIG. 11 is a flowchart for explaining the numerical calculation process.

  The following processing is repeated until the extraction data is completed.

  First, a set of extracted data is read (step S710).

  Next, calculation is performed based on the data (step S720).

  Next, the calculation result is stored in the memory together with the time stamp to be associated (step S730).

  FIG. 12 is a flowchart for explaining image composition / image display processing.

  This processing is executed by the graphic controller connected to the IO bus. Data is automatically thrown from the graphic accelerator, and numerical data is written by the CPU.

  The following processing is repeated until the processing is completed.

  First, image data is fetched from the graphic accelerator (step S810).

  Next, numerical data is taken in (step S820).

  If the time stamps match, the numerical data is imposed on the image (steps S830 and S840).

  The image data is stored in the frame memory (step S850).

  FIG. 13 is a flowchart for explaining the image display processing.

  First, DMAC setting is performed (step S910).

Next, a transfer start instruction is issued (step S920).
Then, data transfer processing of the frame memory is performed until the data is finished (steps S930 and S940).

  When the process ends, an end interrupt is issued to the CPU (step S940).

  FIG. 14 shows an example of an API (control command) on the main memory.

  The main memory 200 is accessible from the main CPU and the local CPU (here, IOP), and stores control commands for the accelerator.

  A command storage area 210 starting from address 220 (0000_1000_0000_1000) stores a control command (API) to be given to the image processing accelerator as shown at 230.

  When the main CPU determines that the peripheral device is to control the accelerator, the main CPU instructs the peripheral device with a control command content to be issued to the accelerator by the address of the control command on the memory, and The local CPU reads the control command from the address on the memory instructed from the main CPU, and issues the control command to the accelerator.

  When no numerical calculation load is applied, the command group is executed by the main CPU. When there is an instruction for numerical calculation, the main CPU transmits the command storage address to be processed to the local CPU (here IOP) in order to leave the instruction by the command to the local CPU (here IOP). Here, the start address 220 of the command storage area is transmitted.

  In response to a start instruction from the local CPU (here, IOP) and the main CPU, the command is read from the address.

  The first data 240 is a code for identifying a control partner. Bits 31 to 0 of 8000 (see 242) indicate that the control partner is an image processing accelerator.

  The local CPU (here IOP) reads the command from the next address, and if bits 63 to 48 (see 244) are not "CCCC", it operates by writing the data as it is to the command port of the image processing accelerator. The mode can be set (created in advance so that it can be set).

  When the local CPU (here IOP) detects "CCCC" (see 250), if the target is currently executing a command, it continues to write the next code (see 260) in the command port. This data is updated sequentially. In this state, it waits for an end interrupt from the image processing accelerator.

  After the end interrupt is generated, the next command area data is read (see 270). Since there is “CCCC” again, it is recognized that the additional processing is in the image processing accelerator, and the next code (see 280) is read.

  Then, the local CPU (here, IOP) writes the data from (l) to (p) to the command port of the image processing accelerator.

  Next, when (q) is read and the end of the command is recognized, the end interrupt from the image processing accelerator is recognized, the main CPU is interrupted, and the end is notified.

  When executed only by the main CPU, switching of tasks to be processed in parallel is complicated, but according to the present invention, the main CPU can recognize only the end interrupt by leaving the processing to the local CPU. This has the effect of reducing the processing overhead associated with task switching.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

The figure for demonstrating the information processing system of this Embodiment. The figure for demonstrating the information processing system of a comparative example. The figure for demonstrating an example of the process from which main CPU requests the control of an accelerator to local CPU. FIG. 5 is a flowchart when the main CPU controls the graphic accelerator and the encryption processing accelerator. FIG. 6 is a flowchart when the main CPU instructs the local CPU to control the graphic accelerator and the encryption processing accelerator. FIG. 5 is a flowchart for explaining block data read processing. The flowchart figure for demonstrating the process of an image processing accelerator. The flowchart figure for demonstrating an encryption process. The flowchart figure for demonstrating a data transmission process. The flowchart for demonstrating numerical data extraction processing. The flowchart for demonstrating number calculation processing. FIG. 6 is a flowchart for explaining image composition / image display processing. The flowchart for demonstrating about an image display process. It is an example of API (control command) on the main memory.

Explanation of symbols

10, information processing system, 20 main CPU, 30 IOP / bus bridge circuit, 40 image processing accelerator, 42 encryption processing accelerator, 44 compression / decompression processing accelerator, 50 memory, 60 network controller, 62 HDD controller, 64 USB controller, 66 graphic controller, 68 other controller, 70 main bus (first bus) 80 I / O bus (second bus), 90 local memory

Claims (6)

An information processing system including a peripheral device having a main CPU, an accelerator providing a given function, and a local CPU,
The main CPU includes accelerator control processing means,
Accelerator control processing means
Determining means for determining whether to request the local CPU to control the accelerator;
If it is determined not to request to the local CPU, the control command for the accelerator stored in the given memory is given to the accelerator by itself.
If it is determined to request the local CPU, the control command content to be given to the accelerator is instructed to the local CPU,
The local CPU gives a control command for the accelerator stored in a given memory to the accelerator based on an instruction from the main CPU,
The accelerator includes a control command execution unit that executes processing corresponding to a given control command. In claim 1,
A memory that is accessible from the main CPU and the local CPU and that stores a control command for an accelerator;
The main CPU is
If it is determined that the request is made to the local CPU, the address on the memory where the control command to be given to the accelerator is stored is instructed to the local CPU,
The information processing system, wherein the local CPU reads a control command from an address on the memory instructed by a main CPU and gives a control command to an accelerator. In any one of Claims 1 thru | or 2.
The determination means includes
An information processing system comprising means for determining whether or not an accelerator control request can be made based on a processing schedule or processing content of a main CPU. In any one of Claims 1 thru | or 3,
The determination means includes
An information processing system comprising means for inquiring an accelerator control request to a local CPU device and determining whether or not an accelerator control request can be made based on a response result to the inquiry. In any one of Claims 1 thru | or 4,
The determination means includes
An information processing system comprising means for determining whether or not an accelerator control request can be made based on a usage status of a peripheral device. In any one of Claims 1 thru | or 5,
A first bus connected to at least a main CPU, peripheral devices, an accelerator, and a memory;
A second bus connected to at least the peripheral device, the accelerator, and the memory;
When the main CPU controls the accelerator, use the first bus,
An information processing system using a second bus when a local CPU controls an accelerator.

Images