JP2006237944A - Image sensor with reduced noise - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image sensor capable of reducing shot noise. <P>SOLUTION: The image sensor having a plurality of photoelectric converting elements PD arranged in an array is provided with: a storage capacitance Cint which accumulates electric charges generated by the photoelectric converting elements PD; a reset transistor RST resetting the storage capacitance to a reset potential; first and second sample holding transistors SH1 and SH2 transferring the voltage of the storage capacitance; and a circuit which reads the held voltage out to a vertical bus line VB. The read circuit accumulates electric charges in the storage capacitance by the first sample holding transistor and then accumulates electric charges in the storage capacitance by the second sample holding transistor as well after resetting the storage capacitance. An output circuit synthesizes a first accumulation voltage with a second accumulation voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image sensor, and more particularly, to an image sensor in which an S / N ratio of a detection signal is increased by an image sensor using infrared rays.

  In the image sensor, a photoelectric conversion element is arranged in a two-dimensional array, an electric charge converted according to incident light or incident infrared light by the photoelectric conversion element is accumulated in a storage capacitor, and a readout circuit that outputs a voltage of the storage capacitor is provided. Provided in each photoelectric conversion element. Patent Document 1 describes a correlated double sampling circuit for removing noise in a CMOS image sensor.

  Since incident light is accompanied by photon fluctuations, the detection voltage includes shot noise due to grating fluctuations if the integration period differs even for images of the same luminance. In particular, when using infrared rays, shot noise generated from the photoelectric conversion element due to fluctuations in the amount of incident light is an important problem. This shot noise is different from the noise which is a problem in the above-mentioned Patent Document 1.

By sufficiently extending the integration period for accumulating the photoelectrically converted charge in the storage capacitor, the influence of fluctuations in the amount of incident light can be reduced and shot noise can be reduced. In addition, the amount of generated charge corresponding to the amount of incident light is affected by fluctuations. However, there is a relationship of Q = CV between the storage capacitor C and the detection voltage V with respect to the charge amount Q. Since the fluctuation of the generated charge amount Q is proportional to the half of the charge amount Q (Q ^1/2 ), the fluctuation of the detection voltage V is −1 of the storage capacitor C from the relationship V = Q / C. / Proportional to square (C ^-1/2 ). Therefore, after the configuration in which the integration period is extended to the maximum frame rate, increasing the capacitance value C of the storage capacitor leads to a reduction in shot noise.
Japanese Patent Laid-Open No. 2003-234963

  However, increasing the capacitance value of the storage capacitor in the readout circuit of each pixel is limited due to chip area limitations. In order to reduce noise, a frame integration method has been proposed in which the output from the readout circuit of each pixel is integrated by an external circuit. However, this method complicates the external circuit and integrates the detection signals acquired in a plurality of frames, and is not suitable for capturing moving images.

  Accordingly, an object of the present invention is to provide an image sensor capable of reducing shot noise.

In order to achieve the above object, according to a first aspect of the present invention, in an image sensor in which a plurality of photoelectric conversion elements are arranged in an array,
A storage capacitor for storing charges generated by the photoelectric conversion element; a reset transistor for resetting the storage capacitor to a reset potential; first and second sample and hold transistors for transferring a voltage of the storage capacitor; and the sample Read comprising a first and second source follower transistor to which the voltage transferred by the hold transistor is supplied to the gate, and a selection transistor for outputting the source of the first and second source follower transistor to the vertical bus line A circuit is provided corresponding to the photoelectric conversion element. In the frame period, the readout circuit stores charge in the storage capacitor after resetting the storage capacitor, and transfers the voltage of the storage capacitor to the gate of the first source follower transistor by the first sample and hold transistor. The integration operation of 1 and again, after resetting the storage capacitor, the charge is stored in the storage capacitor, and the second sample and hold transistor transfers the voltage of the storage capacitor to the gate of the second source follower transistor. Integral operation is performed. Then, the output circuit combines the first source voltage of the first source follower transistor and the second source voltage of the second source follower transistor.

According to the above image sensor, the readout circuit performs the integration operation twice in one frame period, and holds the voltages detected by the integration operations as the first and second source voltages. In the subsequent pixel detection signal output operation, the output circuit combines the first and second source voltages. The first integration period and the second integration period have random fluctuations that are independent of each other. Therefore, the sum of values obtained by squaring the fluctuation (noise) of the first source voltage in the first integration operation and the fluctuation (noise) of the second source voltage in the second integration operation is the combined output. Is equal to the square of. As a result, the fluctuation (noise) of the combined output is reduced to 1 / (2 ^1/2 ) times. Therefore, the shot noise of the detection signal can be reduced without increasing the capacitance value of the storage capacitor of the readout circuit.

  The shot noise of the detection signal can be reduced and the SN ratio can be increased.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 1 is a circuit diagram of a general infrared image sensor. In the image sensor, photoelectric conversion elements such as photodiodes PD are arranged in a two-dimensional array, and each photoelectric conversion element PD is provided with a readout circuit. The readout circuit will be described with respect to the pixel PX11. The storage capacitor Cint, the reset transistor RST that resets the node N1 of the storage capacitor Cint to the reset potential VR, and the charge photoelectrically converted by the photoelectric conversion element PD are transmitted to the storage capacitor Cint. The sample-and-hold transistor SH that samples and holds the voltage of the transfer gate transistor IN, the node N1 generated by the charge accumulation by the storage capacitor Cint at the gate of the source follower transistor SF, and the source voltage of the source follower transistor SF to the vertical bus line VB1. It is comprised with the selection transistor SL to output.

  The row selection shift register 10 sequentially selects the row selection lines R1 and R2, and outputs the source voltage of the source follower transistor SF in the readout circuit of each pixel to the respective vertical bus lines VB1 and VB2 via the selection transistor SL. . The bus line selection shift register 20 sequentially selects the vertical bus line selection transistors BSL1 and BSL2, and inputs the source voltage of each pixel output to the vertical bus line to the output circuit AMP having an amplification function.

  In the conventional infrared image sensor, the reset transistor RST is turned on by the reset signal φRST to reset the node N1 to the reset potential VR, and then the transfer gate transistor IN is set by the integration signal φIN. Conduction is performed, and the integration capacitor Cint is charged or discharged by the charge generated by the photodiode PD. The voltage at the node N1 generated after this integration period is then sampled and held at the gate electrode of the source follower transistor SF via the sample hold transistor SH. When the integration operation and the sample hold operation are finished, an operation of outputting the detection voltage of each pixel to the outside is performed. That is, the selection transistor SL is made conductive by driving the row selection line R1, the source voltage of the source follower transistor is output to the vertical bus lines BV1 and BV2, and the vertical bus lines are sequentially selected by the shift register 20 and output. The signal is input to the circuit AMP and amplified.

  The read operation by the selection transistor SL, the vertical bus line selection transistor BSL, and the output circuit AMP is performed during the integration operation by the integration signal φIN in the subsequent frame period.

  As described above, in the conventional infrared image sensor, the storage capacitor Cint is charged or discharged by the charge generated by the photoelectric conversion element within one frame period. Therefore, the integration period is one frame period at the longest, and in order to further reduce noise due to charge fluctuations under the longest integration period, as described above, the detection voltage is inversely proportional to the 1/2 power of the storage capacity. Therefore, it is necessary to increase the capacitance value of the storage capacitor Cint. However, the increase in the capacitance value of the storage capacitor is limited due to restrictions such as chip area.

  FIG. 2 is a circuit diagram of the infrared image sensor in the present embodiment. In FIG. 2, among the pixels PX11 to PX22 in 2 rows and 2 columns, the photoelectric conversion element PD and its readout circuit are shown in the pixel PX11. As shown in the pixel PX11, in the image sensor of the present embodiment, the configurations of the storage capacitor Cint, the reset transistor RST, and the transfer gate transistor IN during the integration operation are the same as those in FIG. However, unlike FIG. 1, two systems of sample and hold circuits each including a sample and hold transistor SH and a source follower transistor SF are provided for each pixel.

  In other words, the first sample and hold circuit is composed of the sample and hold transistor SH1 and the source follower transistor SF1 connected to the node N1, and the second sample hall circuit is the sample and hold transistor SH2 and the source that are connected to the node N1. It is composed of a follower transistor SF2. The source of the first source follower transistor SF1 is connected to the first vertical bus line VB11 via the selection transistor SL1, and the source of the second source follower transistor SF2 is connected to the second vertical bus line via the selection transistor SL2. Connected to line VB12.

  The selection transistors SL1 and SL2 may be provided between the source follower transistors SF1 and SF2 and the power supply Vcc. In that case, the two selection transistors SL1 and SL2 may be a common selection transistor.

  The row selection shift register 10 sequentially drives the row selection lines R1 and R2 to simultaneously turn on the selection transistors SL1 and SL2 of the pixels in each row, and the source voltage of the source follower transistor is changed to the first and second vertical buses. Output to lines VB11, VB12, VB21, VB22. The bus line selection shift register 20 sequentially drives the vertical bus selection signals φBSL11 to φBSL22 to sequentially turn on the vertical bus selection transistors BSL11 to BSL22, and sets the source voltages of the vertical bus lines VB11, VB12, VB21, and VB22. The signals are sequentially output to the horizontal bus lines HB1 and HB2. The horizontal bus lines HB1 and HB2 are provided with current sources CS1 and CS2, respectively. When the selection transistor SL and the vertical bus selection transistor BSL are turned on, the source follower transistor SF and the current source of the selected pixel cause An amplifier circuit is configured.

  Further, the horizontal bus lines HB1 and HB2 are connected to an output circuit AMP which is an amplifier circuit in the subsequent stage, and this output circuit amplifies the detection signal of each pixel and outputs it as an output signal Vout.

  FIG. 3 is a circuit diagram showing a specific example of the output circuit in the present embodiment. 3, the circuit of the pixel PX11, the vertical bus lines VB11 and VB12, and the horizontal bus lines HB1 and HB2 are the same as those in FIG. The output circuit AMP is an inverting amplifier circuit composed of a P-type load transistor P1 and an N-type driving transistor Q2. Two horizontal bus lines HB1 and HB2 are connected to input switches SW1 and SW2 at the gate of the transistor Q2. Are connected sequentially.

  FIG. 4 is an operation waveform diagram of the infrared image sensor in the present embodiment. The operation of the image sensor will be described with reference to this figure. FIG. 4 shows two frame periods FM1 and FM2 corresponding to the frame rate. In brief, first, in the first half of the frame period FM1, a reset operation RT1, an integration operation INT1, and a sample and hold operation SH1 by the first sample and hold circuit are performed in all pixels. Further, in the second half of the frame period FM1, the reset operation RT2, the integration operation INT2, and the sample and hold operation SH2 by the second sample and hold circuit are performed on all the pixels. Then, in the first half of the frame FM2, the two detection voltages sampled and held in each pixel are combined by the output circuit AMP.

  In the first half of the frame period FM1, the reset signal φRST becomes H level, the reset transistor RST becomes conductive, and the node N1 of the storage capacitor Cint is reset to the reset potential VR. This is the reset operation RT1. As a result, the node N1 rises to the reset potential VR. Next, the integration signal φIN becomes H level, the transfer gate transistor IN becomes conductive, the charge generated by the photodiode PD as a photoelectric conversion element discharges the storage capacitor Cint, and the potential of the node N1 decreases. This is the integration operation INT1. By this integration operation INT1, the potential of the node N1 is lowered by the voltage dV1 corresponding to the incident light intensity. Then, the first sample and hold signal φSH1 becomes H level, the first sample and hold transistor SH1 becomes conductive, and the potential of the node N1 (VR−dV1) is sampled to the gate G1 of the first source follower transistor SF1. When the first sample hold transistor SH1 is turned off, the sampled detection voltage is held in the gate G1. The above is the sample and hold operation SH1.

  Next, in the second half of the frame period FM1, the same operation as described above is performed by the second sample and hold circuit SH2. That is, the reset transistor RST is turned on to reset the node N1 (RT2), the transfer gate transistor IN is turned on to discharge the storage capacitor Cint (INT2), and finally the second sample hold transistor SH2 is turned on. The potential of the node N1 (VR-dV2) is sampled and held by the gate G2 of the second source follower transistor SF2 (SH2). As a result, the two detection voltages for the incident light in the frame period FM1 are held in the gates G1 and G2, respectively.

  Next, in the first half of the frame period FM2, two detection voltages (VR-dV1, VR-dV2) sampled and held in all pixels in the frame period FM1 are output through the vertical bus line VB and the horizontal bus line HB. It is input to AMP, amplified and output. More precisely, the above output operation is performed before the first sample and hold operation SH1 in the frame period FM2 starts.

  Specifically, the row selection shift register 10 drives the row selection line R1 to make both the first and second selection transistors SL1 and SL2 conductive, and the first and second source follower transistors SF1 and SF2 are connected. The source is connected to the first and second vertical bus lines VB11 to VB22. Then, the bus line selection shift register 20 sequentially drives the vertical bus selection signals φBSL11 to φBSL22 to sequentially turn on the vertical bus selection transistors BSL11 to BSL22. As a result, the first and second vertical bus lines VB11 and VB12 in each column are connected to the first and second horizontal bus lines HB1 and HB2. In synchronization with this, in the output circuit AMP, the switches SW1 and SW2 are sequentially turned on, and two detection voltages are added to the gate of the transistor Q2, which is the input of the output circuit, and synthesized.

  FIG. 5 is a waveform diagram showing input signals and output signals of the horizontal bus line and the output circuit. FIG. 5 shows how two detection voltages of one pixel are combined. The vertical bus selection signal φBSL11 becomes H level in the period t1, and the vertical bus selection signal φBSL12 becomes H level in the period t2 which is shifted in time from that. When the vertical bus selection signal φBSL11 becomes H level, the first source follower transistor SF1 drives the first horizontal bus line HB1, and the first source voltage is output. Similarly, when the vertical bus selection signal φBSL12 becomes H level, the second source follower transistor SF2 drives the second horizontal bus line HB2, and the second source voltage is output.

  When the response characteristic of the first-stage amplifier circuit using the source follower transistor is adjusted to make the response speed slightly slower than the horizontal scanning speed of the bus line selection shift register 20, the signal HB1 of the first and second horizontal bus lines is set. , HB2 signal waveforms VHB1 and VHB2 are as shown in FIG. That is, when the vertical bus selection transistor BSL11 is turned on, the source follower transistor SF1 drives the first horizontal bus line HB1, but the response characteristic is slow, so that the level VHB1 of the first horizontal bus line HB1 reaches its peak value. As a result, the selection transistor BSL11 becomes non-conductive. Thereafter, the level VHB1 of the first horizontal bus line HB1 is lowered by the current source CS1. When the vertical bus selection transistor BSL12 continues to be conductive, the source follower transistor SF2 drives the second horizontal bus line HB2, resulting in a similar waveform VHB2.

  Note that the input switches SW1 and SW2 of the output circuit AMP are, for example, that the input switch SW1 is conductive during the periods t1 and t2, and the input switch SW2 is conductive during the period t2 and the subsequent period. VHB1 and VHB2 are transmitted to the gate of the transistor Q2.

  The signal waveforms VHB1 and VHB2 of both horizontal bus lines are adjusted so that the peak values are shifted and overlap with the half-wave value PEAK / 2 of the respective peak values PEAK. As a result, the combined signal SV obtained by combining both signals becomes equal to the peak value PEAK of both signals VHB1 and VHB2 at point A. Since the frame period FM1 is a short period, it is assumed that infrared light having the same light intensity is incident in the first half and the second half. When the synthesized signal SV is input to the gate of the transistor Q1 of the output circuit AMP, the output voltage Vout becomes a signal waveform having a peak value that is lowered by dV from the power supply Vcc level as shown in FIG. . The drop voltage dV at this peak is a detection signal corresponding to the incident light intensity.

  Therefore, the fluctuation (noise) of the detection voltage will be described. In the present embodiment, two integration operations are performed in one frame period, and two detection voltages dV1 and dV2 are acquired. The two integration operations have random fluctuations that are not related to each other. Further, the two detection voltages dV1 and dV2 are output as two horizontal bus signals VHB1 and VHB2, respectively.

  At point A, the peak value SVp of the combined signal SV is equal to the sum of half (Vp / 2) of the peak values Vp of the horizontal bus signals VHB1 and VHB2 corresponding to the two detection voltages dV1 and dV2. That is, SVp = Vp / 2 + Vp / 2. Therefore, if the peak values are equal (Vp of VHB1 = Vp of VHB2) as described above, the peak value of the composite signal SV is the same as the peak values of the two detection signals VHB1 and VHB2.

  Therefore, the relationship between the fluctuation (noise n) SVn of the combined voltage SV and the fluctuations VHB1n and VHB2n of the two detection voltages VHB1 and VHB2 is as follows. The fluctuations of the two detection voltages VHB1 and VHB2 at the point A are ½ of the original fluctuations VHB1n and VHB2n. Since the two detection voltages VHB1 and VHB2 have random fluctuations that are not related to each other, the fluctuations are averaged and have the following relationship.

(SVn) ² = (VHB1n / 2) ² + (VHB2n / 2) ²
From the above relationship, the fluctuation SVn of the composite voltage is as follows.

SVn = {(VHB1n / 2) ² + (VHB2n / 2) ² } ^1/2
Therefore, if VHB1n = VHB2n = VHBn, the combined voltage fluctuation SVn is
SVn = VHBn / 2 ^1/2
Thus, the fluctuation of the combined voltage SV obtained by combining the two detection voltages is 1/2 ^1/2 times the fluctuation VHBn of the two detection voltages. This is equivalent to the noise when the storage capacitor Cint is doubled when the fluctuation of the detection voltage is inversely proportional to the 1/2 power of the storage capacitor Cint.

  As described above, by performing the integration operation twice in the readout circuit of each pixel and synthesizing the detected signals, the fluctuation (noise) of the detection signal is reduced without increasing the capacity value of the storage capacitor. Can do.

  In FIG. 5, the overlap of the two detection voltages VHB1 and VHB2 is made to coincide with each other at a ½ peak value, but it is not always necessary to have such timing, and the two horizontal bus signals VHB1 and VHB2 are not necessarily used. May be combined so that is added by some processing. For example, the peak values of the detection voltages VHB1 and VHB2 may be added.

  In FIG. 3, the first and second vertical bus lines VB11 and VB12 are connected to the output circuit AMP via the first and second horizontal bus lines HB1 and HB2. The reason for this is that if one common horizontal bus line is used, the signal of the first vertical bus line VB21 in the succeeding pixel PX12 overlaps the signal of the second vertical bus line VB12 in the pixel PX21, which causes a crosstalk problem. Because it does. By separating the horizontal bus line provided in common for a plurality of pixels into two, such a crosstalk problem can be avoided. However, when the horizontal scanning speed of the bus line selection shift register is low, one vertical bus line can be shared.

  Returning to FIG. 4, the read operation in the frame FM2 must be performed during the first-half integration operation INT2. That is, it is necessary to complete the scanning of the row selection line in a half frame period. After the readout operation is completed, the first sample hold operation SH1 is performed on all the pixels.

  The above embodiment is summarized as follows.

(Appendix 1) In an image sensor in which a plurality of photoelectric conversion elements are arranged in an array,
A storage capacitor for storing charges generated by the photoelectric conversion element; a reset transistor for resetting the storage capacitor to a reset potential; first and second sample and hold transistors for transferring a voltage of the storage capacitor; and the sample Read comprising a first and second source follower transistor to which the voltage transferred by the hold transistor is supplied to the gate, and a selection transistor for outputting the source of the first and second source follower transistor to the vertical bus line A circuit corresponding to the photoelectric conversion element,
In the frame period, the readout circuit stores charges in the storage capacitor after resetting the storage capacitor, and transfers the voltage of the storage capacitor to the gate of the first source follower transistor by the first sample and hold transistor. In the first integration operation, after the storage capacitor is reset again, charges are stored in the storage capacitor, and the voltage of the storage capacitor is transferred to the gate of the second source follower transistor by the second sample-hold transistor. A second integration operation,
And an output circuit that synthesizes a first source voltage of the first source follower transistor and a second source voltage of the second source follower transistor.

(Appendix 2) In Appendix 1,
The selection transistor includes first and second selection transistors connected to the first and second source follower transistors;
And first and second bus lines to which the first and second source voltages are output in response to conduction of the selection transistor, respectively.
The output circuit inputs the first source voltage output to the first bus line and the second source voltage output to the second bus line while shifting them by a predetermined time. An image sensor that generates output.

(Appendix 3) In Appendix 1,
A row selection line for selecting the selection transistor;
First and second vertical bus lines from which the first and second source voltages are output;
First and second vertical bus selection transistors for sequentially selecting the first and second vertical bus lines;
The output circuit inputs the first and second source voltages with a predetermined time shift through the first and second vertical bus selection transistors that are sequentially selected, and generates a composite output.

(Appendix 4) In Appendix 3,
Furthermore, first and second horizontal bus lines provided in common to the readout circuits of the respective pixels via the first and second column selection transistors,
An image sensor having an input switch for sequentially connecting the first and second horizontal bus lines to an input end of the output circuit.

(Appendix 5) In Appendix 3,
And a vertical bus selection circuit for conducting the first and second vertical bus selection transistors while shifting the predetermined time.
The first input signal when the first vertical bus selection transistor is turned on and the second input signal when the second vertical bus selection transistor is turned on have a value approximately half of the peak value. An image sensor that is made conductive by shifting for a predetermined time to the extent that it overlaps.

(Appendix 6) In Appendix 1,
The image sensor, wherein the readout circuit includes a transfer gate transistor provided between the photoelectric conversion element and a storage capacitor.

It is a circuit diagram of a general infrared image sensor. It is a circuit diagram of the infrared image sensor in this Embodiment. It is a circuit diagram which shows the specific example of the output circuit in this Embodiment. It is an operation | movement waveform diagram of the infrared image sensor in this Embodiment. It is a wave form diagram which shows an input signal and an output signal of a horizontal bus line and an output circuit.

Explanation of symbols

PX11, PX12, PX21, PX22: Pixel PD: Photoelectric conversion element Cint: Storage capacitor SH1, SH2: Sample hold transistor SF1, SF2: Source follower transistor SL1, LS2: Select transistor VB11, VB12, VB21, VB22: Vertical bus line HB1 , HB2: Horizontal bus line AMP: Output circuit

Claims (5)

In an image sensor in which multiple photoelectric conversion elements are arranged in an array,
A storage capacitor for storing charges generated by the photoelectric conversion element; a reset transistor for resetting the storage capacitor to a reset potential; first and second sample and hold transistors for transferring a voltage of the storage capacitor; and the sample Read comprising a first and second source follower transistor to which the voltage transferred by the hold transistor is supplied to the gate, and a selection transistor for outputting the source of the first and second source follower transistor to the vertical bus line A circuit corresponding to the photoelectric conversion element,
In the frame period, the readout circuit stores charges in the storage capacitor after resetting the storage capacitor, and transfers the voltage of the storage capacitor to the gate of the first source follower transistor by the first sample and hold transistor. In the first integration operation, after the storage capacitor is reset again, charges are stored in the storage capacitor, and the voltage of the storage capacitor is transferred to the gate of the second source follower transistor by the second sample-hold transistor. A second integration operation,
And an output circuit that synthesizes a first source voltage of the first source follower transistor and a second source voltage of the second source follower transistor. In claim 1,
The selection transistor includes first and second selection transistors connected to the first and second source follower transistors;
And first and second bus lines to which the first and second source voltages are output in response to conduction of the selection transistor, respectively.
The output circuit inputs the first source voltage output to the first bus line and the second source voltage output to the second bus line while shifting them by a predetermined time. An image sensor that generates output. In the claims,
A row selection line for selecting the selection transistor;
First and second vertical bus lines from which the first and second source voltages are output;
First and second vertical bus selection transistors for sequentially selecting the first and second vertical bus lines;
The output circuit inputs the first and second source voltages with a predetermined time shift through the first and second vertical bus selection transistors that are sequentially selected, and generates a composite output. In claim 3,
Furthermore, first and second horizontal bus lines provided in common to the readout circuits of the respective pixels via the first and second column selection transistors,
An image sensor having an input switch for sequentially connecting the first and second horizontal bus lines to an input end of the output circuit. In claim 3,
And a vertical bus selection circuit for conducting the first and second vertical bus selection transistors while shifting the predetermined time.
The first input signal when the first vertical bus selection transistor is turned on and the second input signal when the second vertical bus selection transistor is turned on have a value approximately half of the peak value. An image sensor that is made conductive by shifting for a predetermined time to the extent that it overlaps.

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