JP2006222329A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in a transistor separated by STI (shallow trench isolation) that a depot is formed in an edge of an active region as an interface with a separation region, the transistor has a low threshold voltage, and a leakage current generated. <P>SOLUTION: A gate electrode is formed so as to cover the edge of at least one of source and drain diffusion layers of a transistor separated by STI. The edge of the diffusion layer is covered with the gate electrode to form a transistor which has a normal threshold voltage between a subchannel transistor and the diffusion layer. During a low gate voltage, the transistor shields between the subchannel transistor and the diffusion layer to cause no current flowing between the drain and source diffusion layers. Consequently, there can be obtained a semiconductor device which has no hump characteristic. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an element isolation region having a shallow trench isolation structure.

  The capacity of semiconductor devices has been increased, and the dimensions of elements to be used have been reduced, and a shallow trench isolation (hereinafter abbreviated as STI) method has been adopted as an element isolation method. Element isolation by STI is performed by forming a trench in a silicon substrate and embedding an insulating film in the trench, so that there is no bird's beak compared to the conventional LOCOS (Local oxidation of Silicon) method and high integration is achieved. Suitable for

  However, in STI, since a trench is formed in a silicon substrate, a divot is generated at the edge of the silicon surface at the boundary between the isolation region and the active region. In this divot, since a normal insulating film is not formed, a transistor different from the original transistor characteristic is formed. These are shown in FIGS. 4A, 4B, and 5. FIG. 4A is a plan view of a conventional transistor, FIG. 4B is a cross-sectional view taken along line ab of the transistor, and FIG. 5 illustrates transistor characteristics.

  A trench formed in the silicon substrate 1 is filled with an insulator 2 and is flattened, and then a gate insulating film is formed, and a gate electrode 4 is formed on the gate insulating film. At this time, the divot 3 is formed at the edge of the active region that forms the boundary between the active region serving as the channel of the transistor and the insulator 2. 4A, the transistor includes a drain (or source) diffusion layer 5, a source (or drain) diffusion layer 6, and a gate electrode 4. In FIG.

  A channel of the transistor is formed in the active region below the gate electrode 4. A main transistor 7 is formed at the center of the active region, and a subchannel transistor 8 is formed along the edges of the active region on both sides thereof. Since a normal gate insulating film is not formed in the divot 3 region at the edge of the active region, the threshold voltage of the subchannel transistor 8 becomes a low voltage. Since the sub-channel transistor 8 has a low threshold voltage, a current flows at a gate voltage that should normally be turned off, and an off-leakage current in the semiconductor device is generated. Thus, the characteristics of the subchannel transistor adversely affect the characteristics of the original transistor.

  In FIG. 5, the characteristic of the main transistor 7 is indicated by a solid line, and the characteristic of the subchannel transistor 8 is indicated by a dotted line. The main transistor 7 formed in the central portion of the active region has original transistor characteristics. However, the subchannel transistor 8 formed at the edge portion has a low threshold voltage and a large variation, and its transistor characteristics are not constant. The reason is that the shape of the divot varies and the film quality and thickness of the gate insulating film formed in the divot portion vary, so the characteristics of the subchannel transistor 8 also vary.

  A characteristic obtained by superimposing the main transistor characteristic and the sub-channel transistor characteristic is the entire transistor characteristic. When the sub-channel transistor 8 is turned on at a low gate voltage where no current flows originally, the current starts to flow, and then the main transistor 7 is turned on to have a stepped voltage-current characteristic. This is called the hump characteristic.

  As a countermeasure against this hump characteristic, a transistor having the shape shown in FIG. 6 has been widely used (hereinafter referred to as a “hump countermeasure transistor 1”). 6 has a drain (or source) diffusion layer 5 at the center of the active region, a gate is formed in a ring shape so as to surround the diffusion layer 5, and a source (or drain) diffusion layer 6 is formed outside the gate. Although the subchannel transistor 8 is formed in the gate extraction portion, both diffusion layers are the same diffusion layer, have the same potential, and no current flows, so that the hump characteristic can be taken. However, this shape has a problem that the element area becomes large.

  The reason why the element area becomes large is that the shape of the channel portion between the source and drain of the gate must be ring-shaped, so that the size required to form one transistor is X direction / Y This is because the size of two gate L dimensions and the size of diffusion layers (source and drain regions) for three locations are necessary in both directions. 7A and 7B, the transistor widths are clearly 2 W and W, respectively. However, in the anti-hump transistor 1 shown in FIG. There is also a problem that it is not clear whether the definition of the W size is the inner circumferential dimension W1 of the ring-shaped gate channel portion, the central circumferential dimension W2, or the outer circumferential dimension W3.

  As a solution to the problem of the anti-hump transistor 1, the technique is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2002-198524). According to Patent Document 1, the transistor shown in FIG. 8 is applied to a latch MOS transistor of a sense amplifier formed in the semiconductor memory device shown in FIG. Since the paired transistors of the latch MOS transistors of the sense amplifier need to have the same transistor characteristics in terms of circuit characteristics, it is a circuit that needs to take countermeasures against the hump characteristics.

  In the transistor shown in FIG. 8, the drain diffusion layer 5 is provided in the center of the active region, the gate electrode 4 is provided on both sides thereof, and the source diffusion layer 6 is provided on the outside thereof. The two gate electrodes 4 divide the diffusion layer into source and drain regions, and the gate electrode 4 is further arranged to cover the edge of the diffusion layer 5 at the boundary with the STI. By covering the edge of the diffusion layer 5 with the gate electrode 4, the sub-channel transistor is formed between the left and right diffusion layers 6 and separated from the diffusion layer 5 to prevent the hump characteristics. Hereinafter, the anti-hump transistor disclosed in Patent Document 1 is referred to as anti-hump transistor 2.

  FIG. 9 shows two pairs of latch MOS transistors of the sense amplifier in the semiconductor memory device. The sense amplifier is disposed adjacent to the memory cell array, the paired transistors are required to have uniform transistor characteristics, and it is necessary to repeatedly form elements at the bit line pitch of the memory cells. When the bit line pitch becomes narrower as the process becomes finer, the contact arrangement width and the gate L dimension width necessary for forming the transistor elements cannot be secured, and the hump countermeasure transistor 2 cannot be accommodated within the memory cell pitch. A problem occurs.

  FIG. 10 shows an example in which transistors without hump countermeasures are arranged at a bit line repetition pitch as a conventional example. In FIG. 10, the repetition pitch for two pairs of bit lines is set to one pitch, and four latch MOS transistors for two pairs of bit lines are accommodated. The element contained in this one pitch has two transistor gate electrodes, three diffusion layer regions, and one density correction dummy gate. Therefore, it falls within the pitch of the memory cell. Here, the number shared with adjacent blocks is counted as 0.5. In addition, the roughness correction dummy gate has different etching dimensional accuracy because there is a difference in the etching amount if the pattern is rough when the gate electrode is etched. Therefore, the correction correction dummy gate is arranged to prevent variation in the etching size. Pattern.

  11 and 12 show examples in which the anti-hump transistor 2 of Patent Document 1 is applied to a latch MOS transistor of a sense amplifier. Since the anti-hump transistor 2 requires one gate electrode divided into two and requires two gate electrodes, the elements contained within the pitch are four transistor gate electrodes and four diffusion layer regions. 11 cannot fit in the pitch. As a result, the elements that are conventionally arranged in the X direction must be shifted in the Y direction as shown in FIG. 12, leading to an increase in the element area.

  Further, in the anti-hump transistor 2 of Patent Document 1, since the gate electrode is divided into two, the minimum value of the transistor W size that can be generated is the minimum W size that can be generated when the gate electrode is not divided. The size is doubled (FIG. 13). As a result, a transistor having a minimum W size (for example, W = 1 μm) in terms of circuit capability needs to be created with a double W size (W = 2 μm), which increases the device area and current. There is a connected problem. In addition, in order to suppress transistor characteristic variation and increase in current, when the transistor channel length needs to be increased, the anti-hump transistor 2 has two gate electrodes divided into two. However, if the value is increased, there is a problem that the device area is increased due to twice the influence.

JP 2002-198524 A

  As described above, the transistor using the STI structure element isolation method has a problem that the hump characteristic occurs. Since the hump characteristics vary due to the characteristics of the circuit, there are transistors that cannot accept the hump characteristics and want to make the transistor characteristics constant. For example, in a transistor constituting a pair transistor part of a DRAM sense amplifier or a current mirror current amplifier circuit, it is necessary to arrange a transistor element having a countermeasure against the occurrence of a hump characteristic. There is a problem that the element arrangement area becomes larger than that of a transistor element to which no countermeasure is taken, leading to an increase in chip size.

  In Patent Document 1, the anti-hump transistor 2 in which elements can be arranged in a smaller area than the anti-hump transistor 1 that has been subjected to the anti-hump has been invented. The repetitive pitch of the sense amplifier section has become smaller, making it difficult to arrange in a small area. In addition, in the anti-hump transistor 2, since the gate electrode of the transistor is divided into two, the minimum W size of the transistor that can be created is twice the W size when the gate electrode is not divided. Therefore, even with a transistor having a minimum W size in terms of circuit characteristics, a 2W size transistor larger than necessary is disposed, which causes a problem that current consumption increases.

  In view of the above problems, an object of the present invention is to provide a semiconductor device that includes a transistor having a smaller element area and has a countermeasure against humping and can obtain stable electrical characteristics.

  The semiconductor device of the present application has an element isolation region having a shallow trench isolation structure, and an edge of at least one of the source diffusion layer and the drain diffusion layer isolated by the element isolation region is formed in a ring shape in a ring shape It is characterized by having a transistor covered with.

  In the semiconductor device of the present application, the gate electrode covers an edge of the diffusion layer and extends further to the diffusion layer side from the edge of the diffusion layer.

  In the semiconductor device of the present application, the gate electrode covers an edge of the diffusion layer and extends from the edge of the diffusion layer to the diffusion layer side by 0.05 μm or more.

  In the semiconductor device of the present application, the gate electrode covers an edge of the diffusion layer and further covers a divot portion outside thereof.

  In the semiconductor device of the present application, the gate electrode covering the edge of the diffusion layer functions as a dummy gate for density correction.

  The semiconductor device of the present application is characterized in that wiring is performed by metal wiring from a diffusion layer surrounded by the gate electrode through a contact.

  In the semiconductor device of the present application, the transistor is used as a latching transistor.

  In the semiconductor device of the present application, the transistor is used as a sense amplifier transistor of a semiconductor memory device.

  The semiconductor device of the present application has an element isolation region having a shallow trench isolation structure, and at least one of the source diffusion layer and the drain diffusion layer separated by the element isolation region is a central portion of the diffusion layer. And a transistor having means for electrically separating the edge portion from each other.

  In the semiconductor device of the present application, the means for electrically separating is a transistor provided between a central portion and an edge portion of the diffusion layer.

  The present invention completely cuts off the subchannel path between the source and the drain by covering the edge part of the diffusion layer of either or both of the source and drain regions of the transistor with a gate electrode in a ring shape. In addition, a transistor that does not generate hump characteristics can be obtained. Further, in recent minute diffusion processes, it is necessary to arrange a density correction dummy gate in a transistor gate electrode having a predetermined interval or more for the purpose of suppressing variation in the gate size of the transistor. By doing so, the gate spacing of the transistors becomes dense, so that an effect of eliminating the need to newly arrange a coarse / dense correction dummy gate can be obtained.

  The present invention will be described in detail below with reference to the drawings.

  A first embodiment will be described with reference to FIGS. FIG. 1 is a plan view of a transistor, and FIG. 2 is a plan view for explaining a density correction dummy gate.

  In the transistor illustrated in FIG. 1A, the edge of one diffusion layer 5 in the source or drain region of the transistor is covered with a gate electrode 4 in a ring shape. In FIG. 1B, both the diffusion layer 5 and the diffusion layer 6 in both the drain and source regions are covered with the gate electrode 4. The transistor surrounding one edge of the diffusion layer in FIG. 1A is used when two transistors are formed side by side and the diffusion layer 6 having a common potential is shared. The transistor surrounding both diffusion layer edges in FIG. 1B is used when the common potential diffusion layer is not shared.

  In addition, as shown in FIG. 2A, in a recent fine diffusion process, a coarse / dense correction dummy gate 14 is arranged in a pattern of the gate electrode 4 having a predetermined interval or more in order to suppress variation in the gate size of the transistor. However, by using the gate pattern of FIG. 2B, the distance between the gate electrodes of the transistors becomes dense, so that it is not necessary to newly provide a density correction dummy gate.

  The reason why the transistor structure of the present invention does not generate hump characteristics will be described. As shown in FIGS. 1A and 1B, in the transistor, a gate electrode 4 is disposed at the center of a diffusion layer, and the diffusion layer is formed by a drain (or source) diffusion layer 5 and a source (or drain) diffusion layer 6. To be separated. The edges of the three sides of the drain diffusion layer 6 are covered with a gate electrode in a ring shape. A divot is generated at the edge of the diffusion layer separated by STI, and a subchannel transistor 8 (shown by a thick diagonal line in the figure) is formed in the divot portion. The subchannel transistor 8 has a characteristic that the transistor is turned on with a threshold voltage Vt lower than that of the main transistor.

  However, in the transistor in which the edge portion of the diffusion layer is covered with the gate electrode 4 in a ring shape, a transistor having a normal threshold voltage is formed inside the divot. Therefore, the source and drain regions of the transistor are connected via a subchannel transistor and a transistor having a normal threshold voltage. Even if the subchannel transistor is turned on at a low Vt, the source of the transistor No current flows between the drain and the drain, and the current does not flow between the source and drain of the transistor until the normal threshold voltage Vt at which the main transistor is turned on is reached. That is, in the graph of FIG. 5, the characteristics of the sub-channel transistor indicated by the dotted line are completely invisible, only the characteristics of the main transistor are visible, and no hump characteristics are generated, and stable ideal transistor characteristics are obtained. It will be a thing.

  Here, the width of the gate electrode that covers the edge of the diffusion layer for suppressing the hump characteristics is examined. The gate electrode width for forming a transistor having a normal threshold voltage inside the sub-channel transistor having a low threshold voltage generated in the divot is the minimum gate electrode width. Inside the diffusion layer, it is sufficient to completely cover the edge of the diffusion layer to form a transistor having a normal threshold voltage. To completely cover the diffusion layer, the transistor is arranged to extend to the silicon side by about 0.05 μm.

  However, the gate electrode is formed so as to cover the divot here because of the minimum pattern size of the gate electrode. Since the divot size generated at the edge of the diffusion layer is about 0.2 μm, the overlap dimension between the gate electrode and the diffusion layer covering the edge of the diffusion layer is about 0.2 to 0.3 μm, and the latch MOS of the sense amplifier In order to obtain a stable Vt, the transistor gate channel length (gate L dimension) is preferably not a Lmin dimension but a slightly large L dimension, and about 0.3 μm is necessary. Therefore, the gate width covering the edge of the diffusion layer and the transistor gate width Have the same dimensions. Further, in order to cover all the edges of the diffusion layer, the edges of the three sides are covered in a ring shape.

  Further, in the conventional anti-hump transistor 2 shown in FIG. 13, the gate of the channel portion of the transistor must be constituted by two, whereas in the present invention, the gate of the channel portion of the transistor is 1 Since it can be configured with a book, the minimum W dimension value of a transistor that can be produced can form a minimum W dimension transistor having a size half that of the conventional shape.

  In this embodiment, a transistor in which the edge portion of the diffusion layer is covered with a gate electrode in a ring shape, the subchannel transistor 8 is formed in a shape as shown by a thick hatched portion in FIG. 1 along the edge of the diffusion layer. Is done. As shown in FIG. 5, the subchannel transistor 8 has a characteristic that the transistor is turned on at a Vt lower than that of the main transistor. In the transistor in which the edge portion of the diffusion layer is covered with the gate electrode 4 in a ring shape, a transistor having a normal threshold voltage is formed between the diffusion layer and the edge, and the transistor is turned off. Are not directly connected in the subchannel transistor 8.

  For this reason, even if the sub-channel transistor is turned on at a low Vt, no current flows between the source and drain of the transistor, and the current does not flow between the source and drain of the transistor until the main transistor is turned on. It will flow. That is, in the graph of FIG. 5, when the gate voltage is low, the characteristics of the sub-channel transistor indicated by the dotted line are completely invisible, and only the characteristics of the main transistor are visible, so that stable ideal transistor characteristics are obtained. . In the transistor using the element isolation method of the STI structure, it is possible to obtain a stable transistor characteristic that is not affected by the subchannel transistor generated by the divot, that is, has no hump characteristic.

  Furthermore, the anti-hump transistor of the present application is composed of one gate and a gate electrode that covers the edge of one or both diffusion layers, so that it is half the size of the conventional anti-hump transistor. A minimum W size transistor can be formed. Therefore, when forming a transistor having a minimum W dimension in terms of circuit, the present invention is more advantageous in terms of area and current consumption than the conventional shape.

  The anti-hump transistor of the present application is composed of one gate and a gate electrode that covers the edge of one or both diffusion layers. With these structures, a transistor and a semiconductor device with a small element area can be obtained.

  A second embodiment will be described with reference to FIG. This embodiment is an embodiment in which the anti-hump transistor of the present application is used as a sense amplifier of a semiconductor memory device as a circuit that cannot accept the hump characteristics because the hump characteristics vary in terms of circuit characteristics. In a semiconductor memory device, a sense amplifier row is arranged adjacent to a memory cell array, and the sense amplifier circuit has a pair of latch MOS transistors. Since the pair of latch MOS transistors need to have the same transistor characteristics in terms of circuit characteristics, it is necessary to take a countermeasure against the hump characteristics.

  As shown in FIG. 3, four latch MOS transistors for two bits are arranged at a pitch for two bits of memory cells. The four transistors are arranged with two transistors sharing the source diffusion layer on the upper side, and two transistors sharing the source diffusion layer with the neighbor (not shown) on the lower side. One pair of latch transistors constitutes one pair, and two transistors on the right side constitute one pair of latch transistors. The bit lines BL1T, BL1N, BL2T, BL2N in the vertical direction are wired by the metal wiring 11. The bit line BL1T is connected to the upper left drain diffusion layer and the lower left gate electrode. The bit line BL1N is connected to the upper left gate electrode and the lower left drain diffusion layer. The bit line BL2T is connected to the upper right gate electrode and the lower right drain diffusion layer. The bit line BL2N is connected to the upper right drain diffusion layer and the lower right gate electrode. The metal wiring 11 is connected to the diffusion layer through a contact 9 and is connected to the gate electrode 4 through a through hole 10. In this figure, the common wiring of the source diffusion layer is not shown.

  In each transistor, the edge portion of the drain diffusion layer region connected to the bit line BLT (or BLN) is completely covered with the gate electrode 4, and the gate electrode covering the edge portion is in contact with the gate electrode 4 of the transistor channel portion. The diffusion layer region connected to the bit line BL is formed so as to be completely surrounded by the ring-shaped gate electrode 4. A divot of about 0.2 μm is generated on the silicon substrate at the edge of the diffusion layer, and a gate electrode enters the divot to form a subchannel transistor that causes hump characteristics. With the gate electrode covered in a ring shape, a transistor that is turned on at a normal Vt is provided inside the subchannel transistor, that is, between the subchannel transistor and the diffusion layer region connected to the bit line BL. Therefore, even when the subchannel transistor is turned on at a low Vt, no current flows between the source and drain of the transistor until the normal Vt is reached. In other words, the sense amplifier can be configured by transistors having stable transistor characteristics that do not generate hump characteristics.

  In the arrangement of the latch MOS transistors of the sense amplifier shown in FIG. 3, elements arranged at a repetitive pitch have two transistor gate electrodes, two gate electrodes covering the diffusion layer edge, and the distance between the gates covering the diffusion layer edge. There are one region and three diffusion layer regions. Here, suppose that the gate width covering the edge of the diffusion layer and the transistor gate width of the present invention are the same, compared with the case of the conventional anti-hump transistor 2 (FIG. 11). In FIG. 11 configured with the anti-hump transistor 2, there are four transistor gate electrodes and four diffusion layer regions. In the present invention, the number of arrangement elements for one diffusion layer region is reduced in the bit line pitch direction, and the interval region between the gates covering the edge of the diffusion layer is increased by one.

By applying specific numerical values to this, and comparing the element dimensions arranged in the bit line repetition direction of the conventional example (FIG. 11) and the embodiment of the present invention (FIG. 3),
Necessary dimension for one diffusion layer region = Contact dimension + (Dimension between contact and gate X2)
= 0.16 + (0.12 X 2) = 0.4 μm
Distance between gates covering diffusion layer edge = 0.16 μm
Required dimension for one diffusion layer region-Distance between the gates covering the edge of the diffusion layer = 0.4-0.16 = 0.24 μm.

  Therefore, in the conventional example (FIG. 11) and the embodiment of the present invention (FIG. 3), the elements can be arranged with a smaller pitch of 0.24 μm per two pairs of bit lines. Since the return pitch for two pairs of bit lines is less than 2.0 μm, a value of 0.24 μm has a great influence on the possibility of element arrangement. Conventionally, two in the bit line repeat pitch direction. However, in the present invention, two transistors can be arranged in the bit line repetition pitch direction.

  The anti-hump transistor of the present application is composed of one gate and a gate electrode that covers the edge of one or both diffusion layers. By using this anti-hump transistor as a latch MOS transistor, a semiconductor device including a latch circuit and a sense amplifier circuit that operate stably with a minimum area corresponding to the memory cell pitch even in a narrow pitch interval can be obtained.

  Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.

It is a top view of the transistor in this invention. It is a top view explaining the structure as a dummy gate for density correction in the transistor of this application. It is a top view which applied the transistor of this invention to the sense amplifier. It is the top view (A) and sectional drawing (B) of the conventional transistor. It is the conventional transistor characteristic view. It is a top view of the conventional anti-hump transistor 1. It is a top view explaining the channel width of the conventional anti-hump transistor 1. It is a top view of the conventional anti-hump transistor 2. It is a circuit diagram of a sense amplifier of a semiconductor memory device. FIG. 10 is a plan view in which the sense amplifier of FIG. 9 is configured by a conventional transistor. FIG. 10 is a plan view (part 1) in which the sense amplifier of FIG. 9 is configured by a conventional anti-hump transistor 2; FIG. 10 is a plan view (part 2) in which the sense amplifier of FIG. 9 is configured with a conventional anti-hump transistor 2; It is a top view explaining the size of the conventional anti-hump transistor 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Insulator 3 Divot 4 Gate electrode 5, 6 Diffusion layer 7 Main transistor 8 Subchannel transistor 9 Contact 10 Through hole 11 Metal wiring 14 Dummy gate for density correction

Claims (10)

  In a semiconductor device having an element isolation region having a shallow trench isolation structure, the edge of at least one of the source diffusion layer and the drain diffusion layer isolated by the element isolation region is covered with a gate electrode in a ring shape A semiconductor device including a transistor.   2. The semiconductor device according to claim 1, wherein the gate electrode covers an edge of the diffusion layer and extends further to the diffusion layer side from the edge of the diffusion layer.   The semiconductor device according to claim 2, wherein the gate electrode covers an edge of the diffusion layer and extends from the edge of the diffusion layer to the diffusion layer side by 0.05 μm or more.   The semiconductor device according to claim 2, wherein the gate electrode covers an edge of the diffusion layer and further covers a divot portion outside the gate electrode.   5. The semiconductor device according to claim 1, wherein the gate electrode covering the edge of the diffusion layer functions as a dummy gate for density correction.   6. The semiconductor device according to claim 1, wherein wiring is performed by metal wiring from a diffusion layer surrounded by the gate electrode through a contact.   7. The semiconductor device according to claim 1, wherein the transistor is used as a latching transistor.   7. The semiconductor device according to claim 1, wherein the transistor is used as a sense amplifier transistor of a semiconductor memory device.   In a semiconductor device having an element isolation region having a shallow trench isolation structure, at least one of the source diffusion layer and the drain diffusion layer isolated by the element isolation region is formed at a center portion and an edge portion of the diffusion layer. A semiconductor device comprising a transistor having means for electrically disconnecting the semiconductor device. The semiconductor device according to claim 9, wherein the means for electrically disconnecting is a transistor provided between a central portion and an edge portion of the diffusion layer.

Images