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JP2006210870A - Module with built-in component, and manufacturing method thereof - Google Patents

Module with built-in component, and manufacturing method thereof Download PDF

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Publication number
JP2006210870A
JP2006210870A JP2005183193A JP2005183193A JP2006210870A JP 2006210870 A JP2006210870 A JP 2006210870A JP 2005183193 A JP2005183193 A JP 2005183193A JP 2005183193 A JP2005183193 A JP 2005183193A JP 2006210870 A JP2006210870 A JP 2006210870A
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Prior art keywords
insulating layer
thermosetting resin
inner via
wiring boards
component
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JP2005183193A
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Japanese (ja)
Inventor
Yasuhiro Nakamura
泰啓 中村
Yoshitake Hayashi
林  祥剛
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005183193A priority Critical patent/JP2006210870A/en
Publication of JP2006210870A publication Critical patent/JP2006210870A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a module with a built-component of high connection reliability of inner via. <P>SOLUTION: A module with a built-in component 100 comprises an electric insulation layer 4 of a mixture containing inorganic filler and thermo-setting resin, and a pair of wiring boards 5 and 6 covering upper and lower surfaces of the electric insulation layer 4 respectively. A circuit component 3 embedded in the electric insulation layer 4 is jointed to at least one of the pair of wiring boards 5 and 6, and an inner via 2 solidified at the lower temperature than the thermo-setting resin of the electric insulation layer 4 electrically connects both wiring boards 5 and 6 together, which is provided to the electric insulation layer 4. A dummy via 1 which is solidified at the lower temperature than the thermo-setting resin of the electric insulation layer 4 is provided to the inner via 2 on the side opposite to the circuit component 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体等の能動部品、コンデンサ等の受動部品を電気絶縁層に内蔵した部品内蔵モジュール及びその製造方法に関する。   The present invention relates to a component built-in module in which an active component such as a semiconductor and a passive component such as a capacitor are built in an electrical insulating layer, and a method for manufacturing the same.

近年、電子機器に対する高性能化および小型化の要求に伴って、電子機器に用いられる回路基板もまた小型高密度のものが望まれている。このような要求に対して、従来のスルホール構造を有するガラス・エポキシ基板では高密度実装化への対応ができなくなりつつある。このため、高密度実装を実現する手段として、LSI間や部品間を最短距離で接続できるインナービア接続法を採用した高密度実装基板の開発が進められている。   In recent years, with the demand for higher performance and miniaturization of electronic devices, circuit boards used in electronic devices are also desired to be small and dense. In response to such a demand, a conventional glass / epoxy substrate having a through-hole structure is becoming unable to cope with high-density mounting. For this reason, as a means for realizing high-density mounting, development of a high-density mounting board adopting an inner via connection method capable of connecting LSIs and components at the shortest distance is in progress.

このようなインナービア接続法を採用した高密度実装基板として、樹脂基板およびセラミック基板が一般的である。樹脂基板は樹脂系材料によって構成されるため、熱伝導性が低い。このため、回路部品実装がより高密度になればなるほど部品から発生する熱を放熱させることは困難となる。一方、セラミック基板は、熱伝導性が高いため放熱性には優れているがコスト高となる。   Resin substrates and ceramic substrates are common as high-density mounting substrates that employ such an inner via connection method. Since the resin substrate is made of a resin material, the thermal conductivity is low. For this reason, the higher the density of circuit component mounting, the more difficult it is to dissipate heat generated from the components. On the other hand, since the ceramic substrate has high thermal conductivity, the ceramic substrate is excellent in heat dissipation but is expensive.

こうしたことから、最近、注目されているのが、無機質フィラーと熱硬化性樹脂との混合物を基板材料にした高密度実装基板である(例えば特許文献1参照)。   For these reasons, a high-density mounting substrate using a mixture of an inorganic filler and a thermosetting resin as a substrate material has recently been attracting attention (see, for example, Patent Document 1).

この高密度実装基板は、前述した樹脂基板およびセラミック基板と同様にインナービア接続ができ、高密度配線が可能であるばかりでなく、基板材料に熱伝導性の高い無機質フィラーが含まれているので、樹脂基板よりも放熱性に優れている。しかもセラミック基板のように1000℃以上の高温における製造プロセスが不要であるため、設備コストがかからない。さらに半導体等の能動部品やコンデンサ等の受動部品を基板に内蔵することができるので、より高密度、高性能化が期待できる。   This high-density mounting board can be connected to the inner vias in the same manner as the resin board and ceramic board described above, and not only enables high-density wiring, but also includes an inorganic filler with high thermal conductivity in the board material. It has better heat dissipation than the resin substrate. And since the manufacturing process in the high temperature of 1000 degreeC or more like a ceramic substrate is unnecessary, installation cost does not start. Furthermore, since active components such as semiconductors and passive components such as capacitors can be built in the substrate, higher density and higher performance can be expected.

以下図面を参照しながら、このような無機質フィラーと熱硬化性樹脂を基板材料にした高密度実装基板の構成および製造方法を説明する。   Hereinafter, a configuration and a manufacturing method of a high-density mounting substrate using such an inorganic filler and a thermosetting resin as a substrate material will be described with reference to the drawings.

図7は、従来の部品内蔵モジュール90の構成を示す断面図である。部品内蔵モジュール90は、無機フィラー及び熱硬化性樹脂を含む混合物からなる電気絶縁層94を備える。この電気絶縁層94の上下面をそれぞれ覆う2層構成の配線基板95及び96が設けられる。両配線基板95及び96のそれぞれの両面には配線パターン97が形成され、電気絶縁層94側の面にはビアランド82が形成される。   FIG. 7 is a cross-sectional view showing a configuration of a conventional component built-in module 90. The component built-in module 90 includes an electrical insulating layer 94 made of a mixture containing an inorganic filler and a thermosetting resin. Two-layer wiring boards 95 and 96 are provided to cover the upper and lower surfaces of the electrical insulating layer 94, respectively. A wiring pattern 97 is formed on both surfaces of both wiring boards 95 and 96, and a via land 82 is formed on the surface on the electric insulating layer 94 side.

配線基板95の配線パターン97には電気絶縁層94に埋め込まれた回路部品93が接合される。電気絶縁層94の熱硬化性樹脂よりも低温で硬化したインナービア92が両配線基板95、96をビアランド82により電気的に接続して電気絶縁層94に設けられる。配線基板96の表面の配線パターン97に回路部品83が接合される。   A circuit component 93 embedded in the electrical insulating layer 94 is bonded to the wiring pattern 97 of the wiring board 95. An inner via 92 cured at a lower temperature than the thermosetting resin of the electrical insulating layer 94 is provided in the electrical insulating layer 94 by electrically connecting the wiring boards 95 and 96 with via lands 82. A circuit component 83 is bonded to the wiring pattern 97 on the surface of the wiring board 96.

このように構成された部品内蔵モジュール90は、以下のようにして製造される。図8(a)〜(c)及び図9は従来の部品内蔵モジュール90の製造方法を示す断面図である。図8(a)を参照すると、まずインナービア92を形成した未硬化の電気絶縁層80を準備する。この電気絶縁層80は、未硬化のエポキシ樹脂等の熱硬化性樹脂とアルミナなどの無機質フィラーとを混合したシート状の材料で構成される。インナービア92は、レーザまたはパンチャーなどの装置によって電気絶縁層80に貫通穴を形成し、電気絶縁層
80の熱硬化性樹脂よりも低温で硬化する低温熱硬化性樹脂と銀等の導電性金属粉とを含む導電性ペーストを貫通穴に充填して形成する。
The component built-in module 90 configured as described above is manufactured as follows. 8A to 8C and FIG. 9 are cross-sectional views showing a conventional method for manufacturing the component built-in module 90. Referring to FIG. 8A, first, an uncured electrical insulating layer 80 in which an inner via 92 is formed is prepared. The electrical insulating layer 80 is made of a sheet-like material in which a thermosetting resin such as an uncured epoxy resin and an inorganic filler such as alumina are mixed. The inner via 92 is formed by forming a through hole in the electric insulating layer 80 by a device such as a laser or a puncher, and is a low temperature thermosetting resin that cures at a lower temperature than the thermosetting resin of the electric insulating layer 80 and a conductive metal such as silver. A conductive paste containing powder is formed by filling the through holes.

そして配線パターン97及びビアランド82を形成した2層構成の配線基板95を作製し、配線パターン97に回路部品93を接合するとともに、配線パターン97及びビアランド82を形成した2層構成の配線基板96を作製する。配線基板95及び96は、前述した電気絶縁層80と同等の熱硬化性樹脂と無機質フィラーとの混合材料、または既存のガラス・エポキシ基板やセラミック基板の材料で構成する。   Then, a wiring board 95 having a two-layer structure in which the wiring pattern 97 and the via land 82 are formed is manufactured, and a circuit component 93 is bonded to the wiring pattern 97 and a wiring board 96 having a two-layer structure in which the wiring pattern 97 and the via land 82 are formed. Make it. The wiring boards 95 and 96 are made of a mixed material of a thermosetting resin and an inorganic filler equivalent to the electrical insulating layer 80 described above, or a material of an existing glass / epoxy board or ceramic board.

次いで図8(c)に示すように、下金型13、配線基板95、電気絶縁層80、配線基板96及び上金型14をこの順番にプレス用治具にセットする。その後、熱プレス装置(図示せず)を用いて、電気絶縁層80の熱硬化性樹脂の硬化温度よりも低くインナービア92の硬化温度よりも高い温度で加熱した状態で両配線基板95及び96を電気絶縁層80に向けて加圧して回路部品93を電気絶縁層80に埋め込む。その後、電気絶縁層80の熱硬化性樹脂の硬化温度よりも高い温度で加熱して、熱硬化性樹脂を硬化させた図9に示す電気絶縁層94を形成する。   Next, as shown in FIG. 8C, the lower mold 13, the wiring board 95, the electrical insulating layer 80, the wiring board 96, and the upper mold 14 are set in this order on the pressing jig. Thereafter, both wiring boards 95 and 96 are heated using a hot press apparatus (not shown) at a temperature lower than the curing temperature of the thermosetting resin of the electrical insulating layer 80 and higher than the curing temperature of the inner via 92. The circuit component 93 is embedded in the electrical insulating layer 80 by applying pressure to the electrical insulating layer 80. Thereafter, the electrical insulating layer 94 shown in FIG. 9 is formed by heating at a temperature higher than the curing temperature of the thermosetting resin of the electrical insulating layer 80 to cure the thermosetting resin.

そしてプレス用治具から取り出した後、配線基板96の表面の配線パターン97に回路部品83を接合すると、前述した図7に示す構成の部品内蔵モジュール90が得られる。
特開平11−220262号公報
Then, after taking out from the pressing jig, when the circuit component 83 is joined to the wiring pattern 97 on the surface of the wiring substrate 96, the component built-in module 90 having the configuration shown in FIG. 7 is obtained.
Japanese Patent Laid-Open No. 11-220262

前述した従来の部品内蔵モジュール90の構成では、回路部品93を電気絶縁層94に埋設する際に生じるいくつかの解決すべき課題がある。以下その理由を詳述する。   In the configuration of the conventional component built-in module 90 described above, there are some problems to be solved that occur when the circuit component 93 is embedded in the electrical insulating layer 94. The reason will be described in detail below.

図8(c)及び図9で前述したように、回路部品93を未硬化の電気絶縁層80内に埋め込む際に加熱、加圧すると、電気絶縁層80が含有する未硬化の熱硬化性樹脂が軟化して流動し易くなるので回路部品93を容易に埋め込むことができる。一方、電気絶縁層80のインナービア92は、両配線基板95及び96のビアランド82で圧縮されることにより低抵抗なビア接続が得られる。   As described above with reference to FIGS. 8C and 9, when the circuit component 93 is embedded in the uncured electrical insulating layer 80 and heated and pressurized, the uncured thermosetting resin contained in the electrical insulating layer 80. Is softened and easily flows, so that the circuit component 93 can be easily embedded. On the other hand, the inner vias 92 of the electrical insulating layer 80 are compressed by the via lands 82 of both the wiring boards 95 and 96 to obtain a low resistance via connection.

しかしながら、軟化した熱硬化性樹脂は、埋め込まれる回路部品93により押されて電気絶縁層80の外側に向かって放射状に流動する。そのため図9に示すように、回路部品93の周りのインナービア92が、流動する熱硬化性樹脂により圧迫されてビアランド82との位置ずれを生じるおそれがある。それによって、インナービア92とビアランド82との接続が不十分になる。このため、インナービア92の接続抵抗が高くなり、また信頼性に悪影響を及ぼすという問題が生じる。   However, the softened thermosetting resin is pressed by the embedded circuit component 93 and flows radially toward the outside of the electrical insulating layer 80. Therefore, as shown in FIG. 9, the inner via 92 around the circuit component 93 may be pressed by the flowing thermosetting resin and may be displaced from the via land 82. Thereby, the connection between the inner via 92 and the via land 82 becomes insufficient. For this reason, the connection resistance of the inner via 92 is increased, and there is a problem that the reliability is adversely affected.

また、このような部品内蔵モジュールに用いられる半導体素子は、今後益々高周波動作になっていくことから発生ノイズの外部への影響や外乱ノイズの影響を受けて誤動作する問題が予測される。   In addition, since semiconductor elements used in such component built-in modules will be operated at higher frequencies in the future, problems of malfunction due to the influence of generated noise to the outside and disturbance noise are expected.

本発明の目的は、上記従来例の問題点を解決し得る部品内蔵モジュール及びその製造方法を提供することにある。   An object of the present invention is to provide a component built-in module that can solve the problems of the conventional example and a method for manufacturing the module.

本発明に係る部品内蔵モジュールは、無機フィラー及び熱硬化性樹脂を含む混合物からなる電気絶縁層と、電気絶縁層上下面をそれぞれ覆う一対の配線基板とを備え、一対の配線基板の少なくとも一方には電気絶縁層に埋め込まれた回路部品が接合され、電気絶縁層の熱硬化性樹脂よりも低温で硬化したインナービアが両配線基板を電気的に接続して電気絶縁層に設けられ、このインナービアに対して回路部品の反対側に電気絶縁層の熱硬化性樹脂よりも低温で硬化したインナービア位置ずれ防止体を設けたことを特徴とする。   A component built-in module according to the present invention includes an electrical insulating layer made of a mixture containing an inorganic filler and a thermosetting resin, and a pair of wiring boards that respectively cover the upper and lower surfaces of the electrical insulating layer, and at least one of the pair of wiring boards. The circuit parts embedded in the electrical insulation layer are joined, and an inner via that is cured at a lower temperature than the thermosetting resin of the electrical insulation layer is provided in the electrical insulation layer by electrically connecting both wiring boards. An inner via misalignment prevention body cured at a lower temperature than the thermosetting resin of the electrical insulating layer is provided on the opposite side of the circuit component with respect to the via.

この構成によれば、電気絶縁層の熱硬化性樹脂よりも低温で硬化したインナービアに対して回路部品の反対側に電気絶縁層の熱硬化性樹脂よりも低温で硬化したインナービア位置ずれ防止体が設けられる。このため、回路部品を電気絶縁層に埋め込む際に回路部品に押されてインナービアへ向かう熱硬化性樹脂の流動をインナービア位置ずれ防止体により抑制することができる。その結果、熱硬化性樹脂の流動によるインナービアの位置ずれを防止することができる。また、インナービア位置ずれ防止体が導電性材料で構成されているため、シールド効果を得ることができノイズの影響を防止することができる。   According to this configuration, the inner vias cured at a lower temperature than the thermosetting resin of the electrical insulating layer are prevented from being displaced on the opposite side of the circuit component to the inner vias cured at a lower temperature than the thermosetting resin of the electrical insulating layer. A body is provided. For this reason, when the circuit component is embedded in the electrical insulating layer, the flow of the thermosetting resin that is pushed by the circuit component and travels toward the inner via can be suppressed by the inner via misalignment prevention body. As a result, it is possible to prevent displacement of the inner via due to the flow of the thermosetting resin. Further, since the inner via position misalignment prevention body is made of a conductive material, a shielding effect can be obtained and the influence of noise can be prevented.

本発明に係る他の部品内蔵モジュールは、無機フィラー及び熱硬化性樹脂を含む混合物からなる電気絶縁層と、電気絶縁層上下面をそれぞれ覆う一対の配線基板とを備え、一対の配線基板の少なくとも一方には電気絶縁層に埋め込まれた回路部品が接合され、光により硬化したインナービアが両配線基板を電気的に接続して電気絶縁層に設けられ、このインナービアに対して回路部品の反対側に光により硬化したインナービア位置ずれ防止体を設けたことを特徴とする。   Another component built-in module according to the present invention includes an electrical insulating layer made of a mixture containing an inorganic filler and a thermosetting resin, and a pair of wiring boards respectively covering the upper and lower surfaces of the electrical insulating layer, and at least one of the pair of wiring boards. On one side, circuit components embedded in the electrical insulating layer are joined, and an inner via hardened by light is provided in the electrical insulating layer by electrically connecting both wiring boards. An inner via misalignment prevention body hardened by light is provided on the side.

この構成によれば、光により硬化したインナービアに対して回路部品の反対側に光により硬化したインナービア位置ずれ防止体が設けられる。回路部品を電気絶縁層に埋め込む際に回路部品に押されてインナービアへ向かう熱硬化性樹脂の流動をインナービア位置ずれ防止体により抑制することができる。その結果、熱硬化性樹脂の流動によるインナービアの位置ずれを防止することができる。   According to this configuration, the inner via misalignment prevention body cured by light is provided on the opposite side of the circuit component with respect to the inner via cured by light. When the circuit component is embedded in the electrical insulating layer, the flow of the thermosetting resin that is pushed by the circuit component toward the inner via can be suppressed by the inner via misalignment prevention body. As a result, it is possible to prevent displacement of the inner via due to the flow of the thermosetting resin.

インナービアは回路部品を囲んで複数個配置され、インナービア位置ずれ防止体は電気絶縁層の外周部に複数個配置されることが好ましい。電気絶縁層が配線基板の外周部からはみ出して厚みむらが生じることを防止できる。   It is preferable that a plurality of inner vias are disposed so as to surround the circuit components, and a plurality of inner via position misalignment prevention bodies are disposed on the outer peripheral portion of the electrical insulating layer. It is possible to prevent the electrical insulating layer from protruding from the outer peripheral portion of the wiring board and causing unevenness in thickness.

複数個のインナービア位置ずれ防止体は複数個のインナービアを囲むように配置されることが好ましい。インナービア位置ずれ防止体をインナービアに対して回路部品の反対側に配置するためである。   The plurality of inner via position shift prevention bodies are preferably arranged so as to surround the plurality of inner vias. This is because the inner via misalignment prevention body is disposed on the opposite side of the circuit component with respect to the inner via.

インナービア位置ずれ防止体はダミービアで構成されることが好ましい。インナービアと同じ工程でインナービア位置ずれ防止体を作製できるからである。   The inner via position misalignment prevention body is preferably formed of a dummy via. This is because the inner via misalignment prevention body can be manufactured in the same process as the inner via.

また、インナービア位置ずれ防止体はそれぞれが電気的に接続されていることが好ましい。インナービア位置ずれ防止体はアース接続されていることが好ましい。インナービアインナービア位置ずれ防止体のシールド効果によりモジュール内部、外部からのノイズを遮断することができるからである。   Moreover, it is preferable that the inner via position misalignment prevention bodies are electrically connected to each other. The inner via misalignment prevention body is preferably connected to the ground. This is because the noise from the inside and outside of the module can be blocked by the shielding effect of the inner via inner position deviation prevention body.

インナービア及びダミービアは、銀、銅、金及びニッケルから選ばれる少なくとも1つを含む金属粉体と、光硬化樹脂又は電気絶縁層の熱硬化樹脂よりも低温で硬化する低温熱硬化性樹脂とを含むことが好ましい。インナービアと同じ材料でインナービア位置ずれ防止体を作製できるからである。   The inner via and the dummy via include a metal powder containing at least one selected from silver, copper, gold, and nickel, and a low-temperature thermosetting resin that cures at a lower temperature than the photo-curing resin or the thermosetting resin of the electrical insulating layer. It is preferable to include. This is because an inner via misalignment prevention body can be manufactured using the same material as the inner via.

電気絶縁層は、70重量%以上95重量%以下の無機フィラーと5重量%以上30重量%以下の熱硬化性樹脂とを含むことが好ましい。電気絶縁層の線膨張係数、熱伝導度及び誘電率を容易に制御できるからである。   The electrical insulating layer preferably contains 70 wt% or more and 95 wt% or less of an inorganic filler and 5 wt% or more and 30 wt% or less of a thermosetting resin. This is because the linear expansion coefficient, thermal conductivity, and dielectric constant of the electrical insulating layer can be easily controlled.

熱硬化性樹脂は、エポキシ樹脂、フェノール樹脂及びシアネート樹脂から選ばれる少なくとも1つを含むことが好ましい。電気絶縁層の耐熱性を向上させるためである。   The thermosetting resin preferably contains at least one selected from an epoxy resin, a phenol resin, and a cyanate resin. This is to improve the heat resistance of the electrical insulating layer.

無機フィラーは、アルミナ、マグネシア、シリカ、窒化アルミニウム及び窒化珪素から選ばれる少なくとも1つを含むことが好ましい。アルミナ、窒化アルミニウムを用いると、従来のガラス・エポキシ基板よりも熱伝導度を高くすることができ、電気絶縁層に埋め込んだ回路部品からの発熱を容易に放熱することができる。特にアルミナはコストが安いという利点がある。シリカを用いると、電気絶縁層の線膨張係数がシリコン半導体に近くなり温度変化によるクラックの発生を防止できるため、半導体を直接実装するフリップチップ実装時に好ましい。またシリカを用いると、誘電率の低い電気絶縁層が得られ、比重
も軽くなるため、携帯電話等の高周波信号用基板に使用すると好ましい。窒化珪素を用いても誘電率の低い電気絶縁層が得られる。
The inorganic filler preferably contains at least one selected from alumina, magnesia, silica, aluminum nitride, and silicon nitride. When alumina or aluminum nitride is used, the thermal conductivity can be made higher than that of a conventional glass / epoxy substrate, and the heat generated from the circuit components embedded in the electrical insulating layer can be easily dissipated. In particular, alumina has the advantage of low cost. When silica is used, the coefficient of linear expansion of the electrical insulating layer is close to that of a silicon semiconductor, and cracks due to temperature changes can be prevented. Therefore, it is preferable at the time of flip chip mounting in which a semiconductor is directly mounted. Further, when silica is used, an electric insulating layer having a low dielectric constant can be obtained and the specific gravity can be reduced. Therefore, it is preferably used for a high-frequency signal substrate such as a mobile phone. Even when silicon nitride is used, an electrical insulating layer having a low dielectric constant can be obtained.

回路部品は、ベアICチップを含み、配線基板にフリップチップ実装されていることが好ましい。小型高密度な部品内蔵モジュールを構成できる。   The circuit component preferably includes a bare IC chip and is flip-chip mounted on the wiring board. A compact and high-density component built-in module can be configured.

回路部品は、抵抗、コンデンサ、及びインダクタから選ばれる少なくとも1つを含むことが好ましい。   The circuit component preferably includes at least one selected from a resistor, a capacitor, and an inductor.

本発明に係る部品内蔵モジュールの製造方法は、一対の配線基板の少なくとも一方に回路部品を接合し、上下面を各配線基板でそれぞれ覆って回路部品を埋め込むための電気絶縁層を無機フィラー及び未硬化状態の熱硬化性樹脂を含む混合物で形成し、熱硬化性樹脂よりも低温で硬化して両配線基板を電気的に接続するためのインナービアを電気絶縁層に形成し、熱硬化性樹脂よりも低温で硬化するインナービア位置ずれ防止体をインナービアに対して、埋め込まれた回路部品の反対側に位置するように電気絶縁層に形成し、両配線基板を電気絶縁層の上下側にそれぞれ配置し、電気絶縁層の熱硬化性樹脂の硬化温度よりも低くインナービア及びインナービア位置ずれ防止体の硬化温度よりも高い温度で加熱した状態で両配線基板を電気絶縁層に向けて加圧して回路部品を電気絶縁層に埋め込み、熱硬化性樹脂の硬化温度よりも高い温度で加熱することを特徴とする。   In the method for manufacturing a component built-in module according to the present invention, an electrical insulating layer for embedding a circuit component is formed by bonding a circuit component to at least one of a pair of wiring boards and covering the upper and lower surfaces with the wiring boards. An inner via is formed in the electrically insulating layer for electrically connecting the two wiring boards by curing at a lower temperature than the thermosetting resin and forming a thermosetting resin. An inner via misalignment prevention body that cures at a lower temperature than the inner via is formed on the electrical insulating layer so as to be opposite to the embedded circuit component, and both wiring boards are placed on the upper and lower sides of the electrical insulating layer. Each wiring board is electrically insulated by placing it at a temperature lower than the curing temperature of the thermosetting resin of the electrical insulation layer and higher than the curing temperature of the inner via and the inner via misalignment prevention body. Embedded circuit components electrically insulating layer is pressurized towards, characterized by heating at a temperature higher than the curing temperature of the thermosetting resin.

この構成によれば、熱硬化性樹脂よりも低温で硬化して両配線基板を電気的に接続するためのインナービアを電気絶縁層に形成し、熱硬化性樹脂よりも低温で硬化するインナービア位置ずれ防止体をインナービアに対して、埋め込まれた回路部品の反対側に位置するように電気絶縁層に形成して、そして、電気絶縁層の熱硬化性樹脂の硬化温度よりも低くインナービア及びインナービア位置ずれ防止体の硬化温度よりも高い温度で加熱した状態で両配線基板を電気絶縁層に向けて加圧して回路部品を電気絶縁層に埋め込む。このため、回路部品を電気絶縁層に埋め込む際に回路部品からインナービアへ向かう熱硬化性樹脂の流動をインナービア位置ずれ防止体により抑制することができる。その結果、熱硬化性樹脂の流動によるインナービアの位置ずれを防止することができる。また、インナービア位置ずれ防止体が導電性材料で構成されているため、シールド効果を得ることができノイズの影響を防止することができる。   According to this configuration, the inner via is formed in the electrically insulating layer for electrically connecting the two wiring boards by curing at a lower temperature than the thermosetting resin, and the inner via is cured at a lower temperature than the thermosetting resin. The misalignment prevention body is formed on the electric insulating layer so as to be located on the opposite side of the embedded circuit component with respect to the inner via, and the inner via is lower than the curing temperature of the thermosetting resin of the electric insulating layer. In addition, the circuit boards are embedded in the electrical insulation layer by pressing both wiring boards toward the electrical insulation layer while being heated at a temperature higher than the curing temperature of the inner via displacement prevention body. For this reason, when the circuit component is embedded in the electrical insulating layer, the flow of the thermosetting resin from the circuit component toward the inner via can be suppressed by the inner via position shift prevention body. As a result, it is possible to prevent displacement of the inner via due to the flow of the thermosetting resin. Further, since the inner via position misalignment prevention body is made of a conductive material, a shielding effect can be obtained and the influence of noise can be prevented.

本発明に係る他の部品内蔵モジュールの製造方法は、一対の配線基板の少なくとも一方に回路部品を接合し、上下面を各配線基板でそれぞれ覆って回路部品を埋め込むための電気絶縁層を無機フィラー及び未硬化状態の熱硬化性樹脂を含む混合物で形成し、光により硬化して両配線基板を電気的に接続するためのインナービアを電気絶縁層に形成し、光により硬化するインナービア位置ずれ防止体を、インナービアに対して、埋め込まれた回路部品の反対側に位置するように電気絶縁層に形成し、インナービア及びインナービア位置ずれ防止体に光を照射して硬化させ、両配線基板を電気絶縁層の上下側にそれぞれ配置し、両配線基板を電気絶縁層に向けて加圧して回路部品を電気絶縁層に埋め込み、熱硬化性樹脂の硬化温度よりも高い温度で加熱することを特徴とする。   In another method of manufacturing a component built-in module according to the present invention, an electrical insulating layer for embedding a circuit component by bonding a circuit component to at least one of a pair of wiring boards and covering the upper and lower surfaces with each wiring board is provided with an inorganic filler. And an inner via position which is formed by a mixture containing an uncured thermosetting resin, cured by light and electrically connected to both wiring boards, and is cured by light. The prevention body is formed on the electrical insulating layer so as to be located on the opposite side of the embedded circuit component with respect to the inner via, and the inner via and the inner via position prevention body are irradiated with light and cured, and both wirings Place the board on the upper and lower sides of the electrical insulation layer, press both wiring boards toward the electrical insulation layer, embed circuit components in the electrical insulation layer, and a temperature higher than the curing temperature of the thermosetting resin Characterized by heating.

この構成によれば、光により硬化して両配線基板を電気的に接続するためのインナービアを電気絶縁層に形成し、光により硬化するインナービア位置ずれ防止体を、インナービアに対して、埋め込まれた回路部品の反対側に位置するように電気絶縁層に形成し、インナービア及びインナービア位置ずれ防止体に光を照射して硬化させ、両配線基板を電気絶縁層に向けて加圧して回路部品を電気絶縁層に埋め込む。このため、回路部品を電気絶縁層に埋め込む際に回路部品からインナービアへ向かう熱硬化性樹脂の流動をインナービア位置ずれ防止体により抑制することができる。その結果、熱硬化性樹脂の流動によるインナービアの位置ずれを防止することができる。また、インナービア位置ずれ防止体が導電性材料で構成されているため、シールド効果を得ることができノイズの影響を防止することができる。   According to this configuration, the inner via is formed in the electrically insulating layer for being cured by light and electrically connecting both the wiring boards, and the inner via misalignment prevention body that is cured by light is formed on the inner via. It is formed on the electrical insulation layer so that it is located on the opposite side of the embedded circuit component, and the inner via and the inner via misalignment prevention body are irradiated with light and cured, and both wiring boards are pressed toward the electrical insulation layer. Then embed the circuit components in the electrical insulation layer. For this reason, when the circuit component is embedded in the electrical insulating layer, the flow of the thermosetting resin from the circuit component toward the inner via can be suppressed by the inner via position shift prevention body. As a result, it is possible to prevent displacement of the inner via due to the flow of the thermosetting resin. Further, since the inner via position misalignment prevention body is made of a conductive material, a shielding effect can be obtained and the influence of noise can be prevented.

本発明によれば、インナービアの接続信頼性および耐ノイズ性を高めた部品内蔵モジュール及びその製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the component built-in module which improved the connection reliability and noise resistance of the inner via | veer, and its manufacturing method can be provided.

図1は本実施の形態に係る部品内蔵モジュール100の断面図であり、図2は図1の断面AAに沿った平面断面図である。部品内蔵モジュール100は、電気絶縁層4を備える。電気絶縁層4は、70重量%以上95重量%以下の無機フィラー及び5重量%以上30重量%以下の熱硬化性樹脂を含む混合物からなる。   FIG. 1 is a cross-sectional view of the component built-in module 100 according to the present embodiment, and FIG. 2 is a plan cross-sectional view along the cross-section AA of FIG. The component built-in module 100 includes an electrical insulating layer 4. The electrical insulating layer 4 is made of a mixture containing 70% to 95% by weight of an inorganic filler and 5% to 30% by weight of a thermosetting resin.

この電気絶縁層4の上下面をそれぞれ覆う2層構成の配線基板5及び6が設けられる。両配線基板5及び6のそれぞれの両面には配線パターン7が形成され、電気絶縁層4側の面にはビアランド12が形成される。   Two-layer wiring boards 5 and 6 are provided to cover the upper and lower surfaces of the electrical insulating layer 4, respectively. A wiring pattern 7 is formed on both surfaces of both the wiring substrates 5 and 6, and a via land 12 is formed on the surface on the electric insulating layer 4 side.

配線基板5の配線パターン7には電気絶縁層4に埋め込まれた半導体チップ3が接合される。電気絶縁層4の熱硬化性樹脂よりも低温で硬化したインナービア2が、両配線基板5及び6をビアランド12により電気的に接続して電気絶縁層4に設けられる。このインナービア2は、半導体チップ3を囲んで複数個設けられる。   The semiconductor chip 3 embedded in the electrical insulating layer 4 is bonded to the wiring pattern 7 of the wiring substrate 5. The inner via 2 cured at a lower temperature than the thermosetting resin of the electrical insulating layer 4 is provided in the electrical insulating layer 4 by electrically connecting both the wiring boards 5 and 6 by the via land 12. A plurality of inner vias 2 are provided surrounding the semiconductor chip 3.

このインナービア2に対して半導体チップ3の反対側に、電気絶縁層4の熱硬化性樹脂よりも低温で硬化したダミービア1が、電気絶縁層4の外周部にインナービア2を囲むように複数個設けられる。   A plurality of dummy vias 1 hardened at a lower temperature than the thermosetting resin of the electrical insulating layer 4 on the opposite side of the semiconductor chip 3 with respect to the inner via 2 so as to surround the inner via 2 around the outer peripheral portion of the electrical insulating layer 4. Are provided.

無機フィラー及び熱硬化性樹脂を選択することによって、電気絶縁層4の線膨張係数、熱伝導度、及び誘電率等を容易に制御することができる。   By selecting the inorganic filler and the thermosetting resin, the linear expansion coefficient, thermal conductivity, dielectric constant, and the like of the electrical insulating layer 4 can be easily controlled.

電気絶縁層4の無機フィラーとして例えば、アルミナ、マグネシア、窒化ホウ素、窒化アルミ、窒化珪素、テフロン(登録商標)及びシリカ等を用いることができる。アルミナ、窒化ホウ素及び窒化アルミを用いると、従来のガラス・エポキシ基板よりも熱伝導度の高い基板が製作可能となり、半導体チップ3の発熱を効果的に放熱させることができる。特にアルミナを用いるとコストが安いという利点も得られる。シリカを用いると、電気絶縁層4の線膨張係数がシリコン半導体に近づき、温度変化によるクラックの発生等を防止することができるため、半導体チップを直接実装するフリップチップ実装時に好ましい。またシリカは、誘電率の低い電気絶縁層が得られ、比重も軽いため、携帯電話等の高周波用基板として好ましい。窒化珪素やテフロン(登録商標)を用いても誘電率の低い電気絶縁層が得られる。また、窒化ホウ素を用いると線膨張係数を低減できる。   As the inorganic filler of the electrical insulating layer 4, for example, alumina, magnesia, boron nitride, aluminum nitride, silicon nitride, Teflon (registered trademark), silica, and the like can be used. When alumina, boron nitride, and aluminum nitride are used, a substrate having higher thermal conductivity than a conventional glass / epoxy substrate can be manufactured, and the heat generated by the semiconductor chip 3 can be effectively dissipated. In particular, when alumina is used, there is an advantage that the cost is low. When silica is used, the coefficient of linear expansion of the electrical insulating layer 4 approaches that of a silicon semiconductor, and cracks due to temperature changes can be prevented. Therefore, it is preferable when flip chip mounting is used to directly mount a semiconductor chip. Silica is preferable as a high-frequency substrate for a mobile phone or the like because an electrical insulating layer having a low dielectric constant is obtained and its specific gravity is light. Even when silicon nitride or Teflon (registered trademark) is used, an electrically insulating layer having a low dielectric constant can be obtained. Further, when boron nitride is used, the linear expansion coefficient can be reduced.

電気絶縁層4の熱硬化性樹脂として、耐熱性の高いエポキシ樹脂やフェノール樹脂、シアネート樹脂を用いると、電気絶縁層4の耐熱性が向上する。また、誘電正接の低いフッ素樹脂、PTFE樹脂(四フッ化エチレン樹脂)、PPO樹脂(ポリフェニレンオキサイド)、PPE樹脂(ポリフェニレンエーテル)を含む樹脂、もしくはそれらの樹脂を変性させた樹脂を用いると、電気絶縁層4の高周波特性が向上する。   When an epoxy resin, phenol resin, or cyanate resin having high heat resistance is used as the thermosetting resin of the electric insulating layer 4, the heat resistance of the electric insulating layer 4 is improved. In addition, if a fluororesin having a low dielectric loss tangent, a PTFE resin (tetrafluoroethylene resin), a PPO resin (polyphenylene oxide), a resin containing PPE resin (polyphenylene ether), or a resin obtained by modifying these resins is used, The high frequency characteristics of the insulating layer 4 are improved.

電気絶縁層4は、分散剤、着色剤、カップリング剤または離型剤をさらに含んでもよい。分散剤により、熱硬化性樹脂中のフィラーを均一性よく分散させることができる。着色剤により、電気絶縁層4を着色することができるため、部品内蔵モジュールの放熱性が向上する。カップリング剤により、熱硬化性樹脂とフィラーとの接着強度を高くすることができるため、電気絶縁層4の電気絶縁性が高まる。離型剤により、金型と混合物との離型性が向上するため、生産性が向上する。   The electrical insulating layer 4 may further include a dispersant, a colorant, a coupling agent, or a release agent. The filler in the thermosetting resin can be dispersed with good uniformity by the dispersant. Since the electrical insulating layer 4 can be colored by the colorant, the heat dissipation of the component built-in module is improved. Since the coupling agent can increase the adhesive strength between the thermosetting resin and the filler, the electrical insulation of the electrical insulation layer 4 is enhanced. The mold release agent improves the mold release property between the mold and the mixture, thereby improving productivity.

両配線基板5及び6の配線パターン7は、電気伝導性を有する物質からなり、例えば、
金属箔や導電性樹脂組成物、金属板を加工したリードフレームにより構成することができる。金属箔やリードフレームを用いると、エッチング等により微細な配線パターンを容易に形成できる。また、金属箔を用いると、離型フィルムを用いた転写等により配線パターンを形成できる。特に銅箔は値段も安く、電気伝導性も高いため好ましい。
The wiring patterns 7 of both wiring boards 5 and 6 are made of a material having electrical conductivity, for example,
It can be comprised with the lead frame which processed metal foil, the conductive resin composition, and the metal plate. When a metal foil or a lead frame is used, a fine wiring pattern can be easily formed by etching or the like. When a metal foil is used, a wiring pattern can be formed by transfer using a release film. In particular, copper foil is preferable because of its low price and high electrical conductivity.

また、配線パターン7を導電性樹脂組成物により構成する場合、金、銀、銅及びニッケル等の金属粉やカ―ボン粉を用いることにより、電気抵抗が低い配線パターンを形成できる。   Moreover, when the wiring pattern 7 is comprised with a conductive resin composition, a wiring pattern with low electrical resistance can be formed by using metal powder, such as gold | metal | money, silver, copper, and nickel, or carbon powder.

さらに、これらの配線パターン7の表面にメッキ処理をする事により、耐食性や電気伝導性を向上させることができる。さらに、配線パターン7の電気絶縁層4との接触面を粗化することで、電気絶縁層4との接着性を高めることができる。   Furthermore, by plating the surface of these wiring patterns 7, the corrosion resistance and electrical conductivity can be improved. Furthermore, the adhesiveness with the electrical insulating layer 4 can be improved by roughening the contact surface of the wiring pattern 7 with the electrical insulating layer 4.

半導体チップ3は、例えばトランジスタ、IC及びLSI等の半導体素子により構成する。半導体素子は、半導体ベアーチップであってもよい。また、半導体チップ3もしくは半導体チップ3と配線パターン7との接続部の少なくとも一部を封止樹脂により封止しても良い。配線パターン7と半導体チップ3とは、例えば導電性接着剤、異方性導電フィルム(ACF)を用いたフリップチップボンディングにより接続する。また、バンプ15を形成して接続してもよい。また、電気絶縁層4によって半導体チップ3を外気から遮断することができるため、湿度による信頼性低下を防止することができる。また、電気絶縁層4の材料としてフィラーと熱効果性樹脂との混合物を用いると、セラミック基板と異なり、高温で焼成する必要がなく、半導体チップ3を内蔵することが容易である。   The semiconductor chip 3 is composed of semiconductor elements such as transistors, ICs, and LSIs, for example. The semiconductor element may be a semiconductor bare chip. Further, at least a part of the connection portion between the semiconductor chip 3 or the semiconductor chip 3 and the wiring pattern 7 may be sealed with a sealing resin. The wiring pattern 7 and the semiconductor chip 3 are connected by flip chip bonding using, for example, a conductive adhesive or an anisotropic conductive film (ACF). Further, bumps 15 may be formed and connected. Moreover, since the semiconductor chip 3 can be shielded from the outside air by the electrical insulating layer 4, it is possible to prevent a decrease in reliability due to humidity. Further, when a mixture of a filler and a thermal effect resin is used as the material of the electrical insulating layer 4, unlike the ceramic substrate, it is not necessary to fire at a high temperature, and the semiconductor chip 3 can be easily incorporated.

インナービア2は、両配線基板5及び6の配線パターン7間を接続する機能を有する導電性粉末と電気絶縁層4の熱硬化性樹脂よりも低温で硬化する低温熱硬化性樹脂との混合物で構成する。例えば、金、銀、銅又はニッケル等の金属粉末やカ―ボン粉末と低温熱硬化性樹脂との混合物を用いることができる。電気絶縁層4の熱硬化性樹脂よりも低温で硬化する低温熱硬化性樹脂としては、例えば、エポキシ樹脂、フェノール樹脂またはシアネート樹脂を用いることができる。エポキシ樹脂は、耐熱性が高いため特に好ましい。金属粉末は、金、銀、銅またはニッケルが導電性が高いため好ましく、銅は導電性が高いのみならずマイグレーションも少ないため特に好ましい。銅を銀で被覆した金属粉を用いても、マイグレーションの少なさと導電性の高さとの両方の特性を満たすことができる。   The inner via 2 is a mixture of conductive powder having a function of connecting the wiring patterns 7 of both wiring boards 5 and 6 and a low-temperature thermosetting resin that cures at a lower temperature than the thermosetting resin of the electrical insulating layer 4. Constitute. For example, a metal powder such as gold, silver, copper or nickel, or a mixture of carbon powder and a low-temperature thermosetting resin can be used. As the low-temperature thermosetting resin that cures at a lower temperature than the thermosetting resin of the electrical insulating layer 4, for example, an epoxy resin, a phenol resin, or a cyanate resin can be used. Epoxy resins are particularly preferred because of their high heat resistance. As the metal powder, gold, silver, copper, or nickel is preferable because of its high conductivity, and copper is particularly preferable because of its high conductivity and low migration. Even when metal powder in which copper is coated with silver is used, it is possible to satisfy both characteristics of low migration and high conductivity.

ダミービア1は、インナービア2と同じ材料で構成することが好ましい。このダミービア1は後述するように、半導体チップ3を電気絶縁層4に埋め込むために加熱、加圧する際に発生する電気絶縁層4の樹脂の流れによるインナービア2の位置ずれを防止する。このダミービア1の形状や大きさは、埋め込む半導体チップ3やインナービア2の配置等の種々の条件に応じて、適宜選択する。   The dummy via 1 is preferably made of the same material as the inner via 2. As will be described later, the dummy via 1 prevents the position of the inner via 2 from being displaced due to the resin flow of the electrical insulating layer 4 that occurs when the semiconductor chip 3 is embedded in the electrical insulating layer 4 and heated and pressed. The shape and size of the dummy via 1 are appropriately selected according to various conditions such as the arrangement of the embedded semiconductor chip 3 and inner via 2.

また、ダミービア1はそれぞれが電気的に接続されており、アース接続されていることが好ましい。位置ずれ防止体のシールド効果によりモジュール内部、外部からのノイズを遮断することができるからである。   The dummy vias 1 are electrically connected to each other and are preferably grounded. This is because the noise from the inside and outside of the module can be blocked by the shielding effect of the displacement prevention body.

このように構成された部品内蔵モジュール100は、以下のようにして製造する。図3(a)〜(c)並びに図4(a)及び(b)は本実施の形態に係る部品内蔵モジュール100の製造方法を示す断面図である。   The component built-in module 100 configured as described above is manufactured as follows. FIGS. 3A to 3C and FIGS. 4A and 4B are cross-sectional views illustrating a method of manufacturing the component built-in module 100 according to the present embodiment.

まず未硬化状態の電気絶縁層10を作製する。未硬化状態の電気絶縁層10の作製方法の一例は、以下の通りである。未硬化の熱硬化性樹脂や、フィラーと未硬化の熱硬化性樹脂との混合物により電気絶縁層10を作製する。最初にフィラーと未硬化の熱硬化性樹脂とを混合して攪拌することにより、電気絶縁層10をシート状に形成する。シート形状に成形する方法としては、例えばドクターブレード法等によって、フィラーと熱硬化性樹脂との混合物の層をフィルム上に作製する方法を用いることができる。電気絶縁層10は、硬化温度以下で乾燥させることによって、粘着性を低下させることができる。この熱処理
によって、板状の電気絶縁層10の粘着性が失われるため、フィルムとの剥離が容易になる。未硬化状態(Bステージ)にすることにより、電気絶縁層10の取扱いが容易となる。
First, an uncured electrical insulating layer 10 is produced. An example of a method for producing the uncured electrical insulating layer 10 is as follows. The electrical insulating layer 10 is produced from an uncured thermosetting resin or a mixture of a filler and an uncured thermosetting resin. First, the electrical insulating layer 10 is formed into a sheet by mixing and stirring the filler and the uncured thermosetting resin. As a method for forming into a sheet shape, for example, a method of forming a layer of a mixture of a filler and a thermosetting resin on a film by a doctor blade method or the like can be used. The electrical insulating layer 10 can reduce adhesiveness by drying at a curing temperature or lower. By this heat treatment, the adhesiveness of the plate-like electrical insulating layer 10 is lost, so that peeling from the film becomes easy. By making it into an uncured state (B stage), handling of the electrical insulating layer 10 becomes easy.

次に図3(a)に示すように、未硬化の電気絶縁層10にインナービアを形成する為の貫通孔8及びダミービアを形成する為の貫通孔9を作製する。これらの貫通孔8及び9は、例えばパンチング加工やドリル加工、レーザー加工によって形成することができる。   Next, as shown in FIG. 3A, the through hole 8 for forming the inner via and the through hole 9 for forming the dummy via are formed in the uncured electrical insulating layer 10. These through holes 8 and 9 can be formed by, for example, punching, drilling, or laser processing.

次に図3(b)に示すように、貫通孔8にビアペースト(導電性ペースト)を充填してインナービア2を形成する。同時に貫通孔9にビアペースト(導電性ペースト)を充填してダミービア1を形成する。貫通孔8及び9へのビアペーストの充填には、印刷や注入による方法を用いることができる。   Next, as shown in FIG. 3B, the via hole 8 is filled with via paste (conductive paste) to form the inner via 2. At the same time, via holes 9 are filled with via paste (conductive paste) to form dummy vias 1. For filling the through holes 8 and 9 with the via paste, printing or injection methods can be used.

次に図3(c)に示すように、未硬化状態の電気絶縁層10の上下面側に配線基板6及び5をそれぞれ位置合わせして重ねる。そして図4(a)に示すように、電気絶縁層10の熱硬化性樹脂の硬化温度よりも低くインナービア2及びダミービア1の硬化温度よりも高い温度で加熱して、電気絶縁層10は未硬化のままインナービア2及びダミービア1を硬化させた状態で、両配線基板6及び5を電気絶縁層10に向けて加圧して半導体チップ3を電気絶縁層10に埋め込む。   Next, as shown in FIG. 3C, the wiring boards 6 and 5 are respectively aligned and stacked on the upper and lower surfaces of the uncured electrical insulating layer 10. Then, as shown in FIG. 4A, heating is performed at a temperature lower than the curing temperature of the thermosetting resin of the electrical insulating layer 10 and higher than the curing temperature of the inner via 2 and the dummy via 1, so that the electrical insulating layer 10 is not yet formed. In a state where the inner via 2 and the dummy via 1 are cured while being cured, both the wiring boards 6 and 5 are pressed toward the electrical insulating layer 10 to embed the semiconductor chip 3 in the electrical insulating layer 10.

半導体チップ3を電気絶縁層10に埋め込む際に半導体チップ3に押されてインナービア2へ向かう未硬化の熱硬化性樹脂の流動を、上下配線基板6及び5のビアランド12により圧縮されるダミービア1が抑制する。   When the semiconductor chip 3 is embedded in the electrical insulating layer 10, the dummy via 1 that is compressed by the via lands 12 of the upper and lower wiring boards 6 and 5 is pressed by the semiconductor chip 3 and the flow of the uncured thermosetting resin toward the inner via 2. Suppresses.

このように、加圧前に電気絶縁層10の熱硬化性樹脂が硬化しない程度に加熱してペースト状のインナービア2及びダミービア1を硬化させておくことで、電気絶縁層10の外周部に配置されて硬化したダミービア1が壁となり、加熱、加圧する際に発生する電気絶縁層10の樹脂の流れを抑制する。このため、インナービア2がビアランド12に対して位置ずれしにくくなり、インナービアの高い接続信頼性を確保することができる。   In this way, the paste-like inner via 2 and dummy via 1 are cured by heating to the extent that the thermosetting resin of the electrical insulating layer 10 is not cured before pressing, so that the outer peripheral portion of the electrical insulating layer 10 is cured. The dummy via 1 disposed and cured serves as a wall, and suppresses the resin flow of the electrical insulating layer 10 that occurs when heating and pressurizing. For this reason, the inner via 2 is less likely to be displaced with respect to the via land 12, and high connection reliability of the inner via can be ensured.

次に電気絶縁層10の熱硬化性樹脂の硬化温度よりも高い温度で加熱すると、図4(b)に示すように、熱硬化性樹脂が硬化した電気絶縁層4を形成できる。このようにして部品内蔵モジュール100を完成させることができる。   Next, by heating at a temperature higher than the curing temperature of the thermosetting resin of the electric insulating layer 10, as shown in FIG. 4B, the electric insulating layer 4 in which the thermosetting resin is cured can be formed. In this way, the component built-in module 100 can be completed.

図5は、第1変形例に係る部品内蔵モジュールの製造方法を示す断面図であり、前述した図3(c)に対応する。図5に示すように、半導体チップ3を埋め込むためのキャビティ11を未硬化の電気絶縁層10Aに形成してもよい。このキャビティ11により、半導体チップ3を電気絶縁層10Aに埋め込む際の体積分に相当する樹脂の流れを抑制することができる。   FIG. 5 is a cross-sectional view illustrating the method for manufacturing the component built-in module according to the first modification, and corresponds to FIG. 3C described above. As shown in FIG. 5, a cavity 11 for embedding the semiconductor chip 3 may be formed in the uncured electrical insulating layer 10A. The cavity 11 can suppress the flow of resin corresponding to the volume of the semiconductor chip 3 when it is embedded in the electrical insulating layer 10A.

図6(a)は第2変形例に係る部品内蔵モジュールの平面図であり、(b)は第3変形例に係る部品内蔵モジュールの平面図である。部品内蔵モジュール100を多面取りモジュール200に多数個同時に作成する場合は、図6(a)に示すように各部品内蔵モジュール100のそれぞれの外周部に沿ってダミービア1を設けてもよい。また、図6(b)に示すように多面取りモジュール200の外周部に沿ってダミービア1を設けてもよい。   FIG. 6A is a plan view of the component built-in module according to the second modification, and FIG. 6B is a plan view of the component built-in module according to the third modification. When a large number of component built-in modules 100 are simultaneously created in the multi-cavity module 200, the dummy vias 1 may be provided along the respective outer peripheral portions of the component built-in modules 100 as shown in FIG. Further, as shown in FIG. 6B, the dummy via 1 may be provided along the outer peripheral portion of the multi-chamfer module 200.

なお本実施の形態ではダミービア1を設けた例を示したが、本発明はこれに限定されず、電気絶縁層の熱硬化性樹脂よりも低温で硬化するインナービア位置ずれ防止体を設ければよい。   In the present embodiment, an example in which the dummy via 1 is provided is shown. However, the present invention is not limited to this, and an inner via misalignment prevention body that cures at a lower temperature than the thermosetting resin of the electrical insulating layer is provided. Good.

また、インナービア2およびダミービア1が電気絶縁層の熱硬化性樹脂よりも低温で硬化する低温熱硬化性樹脂を有する例を示したが、本発明はこれに限定されず、インナービア2およびダミービア1は光硬化性樹脂を有してもよい。この場合は、インナービア2及びダミービア1に光を照射して硬化させた後、両配線基板6及び5を未硬化の電気絶縁層10に向けて加圧して半導体チップ3を電気絶縁層10に埋め込めば前述した効果と同様の効果を得ることができる。   Moreover, although the example in which the inner via 2 and the dummy via 1 have a low-temperature thermosetting resin that cures at a lower temperature than the thermosetting resin of the electrical insulating layer is shown, the present invention is not limited to this, and the inner via 2 and the dummy via 1 may have a photocurable resin. In this case, the inner via 2 and the dummy via 1 are irradiated with light and cured, and then both the wiring boards 6 and 5 are pressed toward the uncured electrical insulating layer 10 to make the semiconductor chip 3 into the electrical insulating layer 10. If embedded, the same effect as described above can be obtained.

さらに、半導体チップ3を電気絶縁層4に内蔵した例を示したが、抵抗、コンデンサ、及びインダクタから選ばれる少なくとも1つを内蔵してもよい。また、両者を内蔵してもよい。   Furthermore, although the example in which the semiconductor chip 3 is built in the electrical insulating layer 4 is shown, at least one selected from a resistor, a capacitor, and an inductor may be built in. Moreover, you may incorporate both.

本発明は、半導体等の能動部品、コンデンサ等の受動部品を電気絶縁層に内蔵した部品内蔵モジュール及びその製造方法に適用することができる。   The present invention can be applied to a component built-in module in which an active component such as a semiconductor and a passive component such as a capacitor are built in an electrical insulating layer and a method for manufacturing the module.

本実施の形態に係る部品内蔵モジュールの断面図である。It is sectional drawing of the component built-in module which concerns on this Embodiment. 図1の断面AAに沿った平面断面図である。FIG. 2 is a plan sectional view taken along a section AA in FIG. 1. (a)〜(c)は本実施の形態に係る部品内蔵モジュールの製造方法を示す断面図である。(A)-(c) is sectional drawing which shows the manufacturing method of the component built-in module which concerns on this Embodiment. (a)〜(b)は本実施の形態に係る部品内蔵モジュールの製造方法を示す断面図である。(A)-(b) is sectional drawing which shows the manufacturing method of the component built-in module which concerns on this Embodiment. 第1変形例に係る部品内蔵モジュールの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the component built-in module which concerns on a 1st modification. (a)は第2変形例に係る部品内蔵モジュールの平面図であり、(b)は第3変形例に係る部品内蔵モジュールの平面図である。(A) is a top view of the component built-in module which concerns on a 2nd modification, (b) is a top view of the component built-in module which concerns on a 3rd modification. 従来の部品内蔵モジュールの構成を示す断面図である。It is sectional drawing which shows the structure of the conventional component built-in module. (a)〜(c)は従来の部品内蔵モジュールの製造方法を示す断面図である。(A)-(c) is sectional drawing which shows the manufacturing method of the conventional component built-in module. 従来の部品内蔵モジュールの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the conventional component built-in module.

符号の説明Explanation of symbols

1 ダミービア
2 インナービア
3 回路部品
4 電気絶縁層
5、6配線基板
7 配線パターン
8、9貫通孔
10 電気絶縁層
11 キャビティ
100 部品内蔵モジュール
200 多面取りモジュール
DESCRIPTION OF SYMBOLS 1 Dummy via 2 Inner via 3 Circuit component 4 Electrical insulation layer 5 and 6 Wiring board 7 Wiring pattern 8 and 9 Through-hole 10 Electrical insulation layer 11 Cavity 100 Component built-in module 200 Multi-cavity module

Claims (15)

無機フィラー及び熱硬化性樹脂を含む混合物からなる電気絶縁層と、電気絶縁層上下面をそれぞれ覆う一対の配線基板とを備え、一対の配線基板の少なくとも一方には電気絶縁層に埋め込まれた回路部品が接合され、電気絶縁層の熱硬化性樹脂よりも低温で硬化したインナービアが両配線基板を電気的に接続して電気絶縁層に設けられ、このインナービアに対して回路部品の反対側に電気絶縁層の熱硬化性樹脂よりも低温で硬化したインナービア位置ずれ防止体を設けたことを特徴とする部品内蔵モジュール。 An electric insulating layer made of a mixture containing an inorganic filler and a thermosetting resin, and a pair of wiring boards covering the upper and lower surfaces of the electric insulating layer, and a circuit embedded in the electric insulating layer in at least one of the pair of wiring boards Inner vias, which are bonded to each other and cured at a lower temperature than the thermosetting resin of the electrical insulation layer, are provided in the electrical insulation layer by electrically connecting the two wiring boards. A component built-in module characterized in that an inner via misalignment prevention body hardened at a lower temperature than the thermosetting resin of the electrical insulating layer is provided. 無機フィラー及び熱硬化性樹脂を含む混合物からなる電気絶縁層と、電気絶縁層上下面をそれぞれ覆う一対の配線基板とを備え、一対の配線基板の少なくとも一方には電気絶縁層に埋め込まれた回路部品が接合され、光により硬化したインナービアが両配線基板を電気的に接続して電気絶縁層に設けられ、このインナービアに対して回路部品の反対側に光により硬化したインナービア位置ずれ防止体を設けたことを特徴とする部品内蔵モジュール。 An electric insulating layer made of a mixture containing an inorganic filler and a thermosetting resin, and a pair of wiring boards covering the upper and lower surfaces of the electric insulating layer, and a circuit embedded in the electric insulating layer in at least one of the pair of wiring boards Inner vias where parts are joined and hardened by light are provided in the electrical insulation layer by electrically connecting both wiring boards, and the inner vias that are hardened by light on the opposite side of the circuit parts are prevented from shifting to the inner vias. A component built-in module characterized by providing a body. インナービアは回路部品を囲んで複数個配置され、インナービア位置ずれ防止体は電気絶縁層の外周部に複数個配置される請求項1又は2記載の部品内蔵モジュール。 3. The component built-in module according to claim 1, wherein a plurality of inner vias are disposed so as to surround the circuit component, and a plurality of inner via misalignment prevention bodies are disposed on an outer peripheral portion of the electrical insulating layer. 複数個のインナービア位置ずれ防止体は複数個のインナービアを囲むように配置される請求項3記載の部品内蔵モジュール。 4. The component built-in module according to claim 3, wherein the plurality of inner via position misalignment prevention bodies are arranged so as to surround the plurality of inner vias. インナービア位置ずれ防止体はダミービアで構成される請求項1乃至4の何れかに記載の部品内蔵モジュール。 The component built-in module according to claim 1, wherein the inner via position misalignment prevention body is formed of a dummy via. インナービア位置ずれ防止体はそれぞれが電気的に接続されている請求項1乃至5記載の部品内蔵モジュール。 6. The component built-in module according to claim 1, wherein the inner via misalignment prevention bodies are electrically connected to each other. インナービア位置ずれ防止体はアース接続されている請求項1乃至6の何れかに記載の部品内蔵モジュール。 7. The component built-in module according to claim 1, wherein the inner via position misalignment prevention body is grounded. インナービア及びダミービアは、銀、銅、金及びニッケルから選ばれる少なくとも1つを含む金属粉体と、光硬化樹脂又は電気絶縁層の熱硬化樹脂よりも低温で硬化する低温熱硬化性樹脂とを含む請求項5乃至7の何れかに記載の部品内蔵モジュール。 The inner via and the dummy via include a metal powder containing at least one selected from silver, copper, gold, and nickel, and a low-temperature thermosetting resin that cures at a lower temperature than the photo-curing resin or the thermosetting resin of the electrical insulating layer. The module with a built-in component according to any one of claims 5 to 7. 電気絶縁層は、70重量%以上95重量%以下の無機フィラーと5重量%以上30重量%以下の熱硬化性樹脂とを含む請求項1乃至8の何れかに記載の部品内蔵モジュール。 The component built-in module according to any one of claims 1 to 8, wherein the electrical insulating layer includes 70 wt% or more and 95 wt% or less of an inorganic filler and 5 wt% or more and 30 wt% or less of a thermosetting resin. 熱硬化性樹脂は、エポキシ樹脂、フェノール樹脂及びシアネート樹脂から選ばれる少なくとも1つを含む請求項1乃至9の何れかに記載の部品内蔵モジュール。 The component built-in module according to claim 1, wherein the thermosetting resin includes at least one selected from an epoxy resin, a phenol resin, and a cyanate resin. 無機フィラーは、アルミナ、マグネシア、シリカ、窒化アルミニウム及び窒化珪素から選ばれる少なくとも1つを含む請求項1乃至10の何れかに記載の部品内蔵モジュール。 The component built-in module according to claim 1, wherein the inorganic filler includes at least one selected from alumina, magnesia, silica, aluminum nitride, and silicon nitride. 回路部品は、ベアICチップを含み、配線基板にフリップチップ実装されている請求項1乃至11の何れかに記載の部品内蔵モジュール。 12. The component built-in module according to claim 1, wherein the circuit component includes a bare IC chip and is flip-chip mounted on the wiring board. 回路部品は、抵抗、コンデンサ、及びインダクタから選ばれる少なくとも1つを含む請求項1乃至12の何れかに記載の部品内蔵モジュール。 The component built-in module according to claim 1, wherein the circuit component includes at least one selected from a resistor, a capacitor, and an inductor. 一対の配線基板の少なくとも一方に回路部品を接合し、上下面を各配線基板でそれぞれ覆って回路部品を埋め込むための電気絶縁層を無機フィラー及び未硬化状態の熱硬化性樹脂を含む混合物で形成し、熱硬化性樹脂よりも低温で硬化して両配線基板を電気的に接続するためのインナービアを電気絶縁層に形成し、熱硬化性樹脂よりも低温で硬化するインナービア位置ずれ防止体をインナービアに対して、埋め込まれた回路部品の反対側に位置するように電気絶縁層に形成し、両配線基板を電気絶縁層の上下側にそれぞれ配置し、電気
絶縁層の熱硬化性樹脂の硬化温度よりも低くインナービア及びインナービア位置ずれ防止体の硬化温度よりも高い温度で加熱した状態で両配線基板を電気絶縁層に向けて加圧して回路部品を電気絶縁層に埋め込み、熱硬化性樹脂の硬化温度よりも高い温度で加熱することを特徴とする部品内蔵モジュールの製造方法。
A circuit component is bonded to at least one of a pair of wiring boards, and an electrical insulating layer for embedding the circuit parts by covering the upper and lower surfaces with each wiring board is formed of a mixture containing an inorganic filler and an uncured thermosetting resin. The inner via misalignment prevention body that cures at a lower temperature than the thermosetting resin and forms an inner via in the electrically insulating layer for electrically connecting both wiring boards, and cures at a lower temperature than the thermosetting resin. Is formed on the electrical insulation layer so as to be located on the opposite side of the embedded circuit component with respect to the inner via, and both wiring boards are arranged on the upper and lower sides of the electrical insulation layer, respectively, and the thermosetting resin of the electrical insulation layer The circuit board is embedded in the electrical insulation layer by pressing both wiring boards toward the electrical insulation layer while being heated at a temperature lower than the cure temperature of the inner via and the cure temperature of the inner via misalignment prevention body. See, method for producing a component built-in module, characterized by heating at a temperature higher than the curing temperature of the thermosetting resin.
一対の配線基板の少なくとも一方に回路部品を接合し、上下面を各配線基板でそれぞれ覆って回路部品を埋め込むための電気絶縁層を無機フィラー及び未硬化状態の熱硬化性樹脂を含む混合物で形成し、光により硬化して両配線基板を電気的に接続するためのインナービアを電気絶縁層に形成し、光により硬化するインナービア位置ずれ防止体を、インナービアに対して、埋め込まれた回路部品の反対側に位置するように電気絶縁層に形成し、インナービア及びインナービア位置ずれ防止体に光を照射して硬化させ、両配線基板を電気絶縁層の上下側にそれぞれ配置し、両配線基板を電気絶縁層に向けて加圧して回路部品を電気絶縁層に埋め込み、熱硬化性樹脂の硬化温度よりも高い温度で加熱することを特徴とする部品内蔵モジュールの製造方法。 A circuit component is bonded to at least one of a pair of wiring boards, and an electrical insulating layer for embedding the circuit parts by covering the upper and lower surfaces with each wiring board is formed of a mixture containing an inorganic filler and an uncured thermosetting resin. A circuit in which an inner via for curing by light and electrically connecting both wiring boards is formed in the electrically insulating layer, and an inner via misalignment prevention body that is cured by light is embedded in the inner via. It is formed on the electrical insulation layer so as to be located on the opposite side of the component, and the inner via and the inner via misalignment prevention body are irradiated with light and cured, and both wiring boards are arranged on the upper and lower sides of the electrical insulation layer, respectively. The circuit board is embedded in the electrical insulation layer by pressing the wiring board toward the electrical insulation layer, and heated at a temperature higher than the curing temperature of the thermosetting resin. Method.
JP2005183193A 2004-12-28 2005-06-23 Module with built-in component, and manufacturing method thereof Pending JP2006210870A (en)

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