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JP2006274369A - Method and apparatus for forming substrate wiring, and plating suppressing substance transfer stamp - Google Patents

Method and apparatus for forming substrate wiring, and plating suppressing substance transfer stamp Download PDF

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JP2006274369A
JP2006274369A JP2005096511A JP2005096511A JP2006274369A JP 2006274369 A JP2006274369 A JP 2006274369A JP 2005096511 A JP2005096511 A JP 2005096511A JP 2005096511 A JP2005096511 A JP 2005096511A JP 2006274369 A JP2006274369 A JP 2006274369A
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plating
substrate
wiring
stamp
substance
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Akira Kodera
章 小寺
Hirokuni Hiyama
浩国 檜山
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Ebara Corp
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Ebara Corp
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Priority to US11/389,178 priority patent/US20060234499A1/en
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and apparatus for forming substrate wiring capable of suppressing the occurrence of a failure, such as disconnection, controlling the time required for a CMP process to an appropriate range, performing sufficient planarization at the end time point of a plating process and in the CMP process, completely removing the excess metals, and forming substrate wiring by forming such metallic plating film which does give rise to peeling among a seed layer, barrier layer, insulation layer, etc., and does not give rise to dishing and erosion by an electrolytic plating on a substrate., and a transfer stamp for a plating suppressing substance. <P>SOLUTION: The substrate wiring forming method of forming the wiring by embedding recessed parts 11, such as wiring grooves, and contact holes, formed on a substrate 10 with copper 13 by electroplating is equipped with a process of sticking the plating suppressing substance (ink 4) to the extreme surface of the substrate 10 exclusive of the inner surface of the recessed parts 11 of the substrate, a process for performing the electrolytic plating, a process of desorbing the plating suppressing substance (ink 4) and a process of performing the electroplating. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体基板の表面に形成された配線溝やコンタクトホール等の凹部内を電解めっきにより金属で埋め込み半導体デバイス(半導体集積回路)の配線を形成する基板配線形成方法、基板配線形成装置、及び基板の凹部内表面を除く表面にめっき抑制物質を転写するめっき抑制物質転写スタンプに関するものである。   The present invention relates to a substrate wiring forming method, a substrate wiring forming apparatus, and a method for forming a wiring of a semiconductor device (semiconductor integrated circuit) by filling a concave portion such as a wiring groove or a contact hole formed on a surface of a semiconductor substrate with a metal by electrolytic plating. The present invention also relates to a plating suppression material transfer stamp for transferring a plating suppression material to the surface of the substrate excluding the concave inner surface.

半導体集積回路の内部配線の金属材料としては、従来はアルミニウムやアルミニウム合金が使われてきたが、昨今では電気抵抗が低くエレクトロマイグレーション耐性のある銅が用いられてきている。銅で配線を形成するために図1(a)に示すように、銅(銅めっき膜102)を基板の絶縁層100に設けたコンタクトホールや配線溝(以下「トレンチ」ともいう)101内に埋め込み、更に基板のコンタクトホールや配線溝101が加工された面の全表面に堆積させてめっき工程を終了し、その後過剰の銅や銅拡散防止のバリア層103をCMP(Chemical Mechanical Polishing:化学機械研磨)により除去・平坦化するダマシン法が用いられている。この銅の埋め込みには通常電解銅めっきを行うが、通電のためのシード層とよばれる銅の層(図示せず)をスパッタリング等によりバリア層103の上に予め成膜している。   Conventionally, aluminum or an aluminum alloy has been used as a metal material for internal wiring of a semiconductor integrated circuit. Recently, however, copper having low electrical resistance and electromigration resistance has been used. In order to form wiring with copper, as shown in FIG. 1A, copper (copper plating film 102) is placed in a contact hole or wiring groove (hereinafter also referred to as “trench”) 101 provided in the insulating layer 100 of the substrate. The plating process is completed by embedding and depositing on the entire surface of the substrate where contact holes and wiring grooves 101 are processed, and then the excess copper and copper diffusion preventing barrier layer 103 is formed by CMP (Chemical Mechanical Polishing) A damascene method is used which is removed and planarized by polishing. This copper embedding is usually performed by electrolytic copper plating, but a copper layer (not shown) called a seed layer for energization is formed in advance on the barrier layer 103 by sputtering or the like.

上記CMP工程により銅めっき膜102が形成された側の基板の表面を平坦化する場合、図1(b)に示すように残しておくべき銅めっき膜102の配線部102aも一部削ってしまうディシング104やエロージョン105を発生させてしまうので、これらを避けるために、図3に示すように予め銅めっき膜102の厚さを厚くする。即ち、基板の配線形成側表面全体に堆積させる銅めっき膜102の堆積厚さを厚くすることで、めっき表面全体を平坦化させる方法がとられている。しかしながら、銅めっき膜102の厚さを厚くすると、CMP工程の時間が多くかかってしまう。一方、銅めっき膜102が薄い程めっき終了後の表面形状は半導体基板のコンタクトホールやトレンチ等の凹凸をそのまま準えてしまい、基板表面に凹凸(図1(a)102b参照)を残すこととなる。   When the surface of the substrate on which the copper plating film 102 is formed by the CMP process is planarized, a part of the wiring portion 102a of the copper plating film 102 that should be left as shown in FIG. Since the dishing 104 and the erosion 105 are generated, in order to avoid these, the thickness of the copper plating film 102 is previously increased as shown in FIG. That is, a method of flattening the entire plating surface by increasing the deposition thickness of the copper plating film 102 deposited on the entire wiring forming surface of the substrate is employed. However, if the thickness of the copper plating film 102 is increased, a longer time is required for the CMP process. On the other hand, as the copper plating film 102 is thinner, the surface shape after the plating finishes the irregularities such as contact holes and trenches of the semiconductor substrate as they are, and the irregularities (see FIG. 1 (a) 102b) remain on the substrate surface. .

この状態でCMPを行ってしまうと、基板表面の余剰な銅めっき膜102の除去や基板表面の平坦化が困難となるばかりでなく、基板の配線部にディシング104やエロージョン105を発生してしまう。即ち、銅めっき膜102の厚さを厚くするとCMP工程に多大な時間を要することになるし、反対に薄くすると余剰な銅めっき膜102の除去や基板の平坦化が困難となったり、ディシング104やエロージョン105をが発生する等の不具合がある。   If CMP is performed in this state, it becomes difficult not only to remove the excessive copper plating film 102 on the substrate surface and to flatten the substrate surface, but also to generate a dishing 104 and an erosion 105 in the wiring portion of the substrate. . That is, if the thickness of the copper plating film 102 is increased, a long time is required for the CMP process. On the other hand, if the thickness is reduced, it is difficult to remove the excessive copper plating film 102 and planarize the substrate, Or erosion 105 occurs.

そこでめっき終了時点での表面の平坦化を図るため、従来からめっき液中に様々な添加剤を入れている。めっき液として硫酸銅めっき液を使用した電解銅めっきで微細な配線パターンになる溝(トレンチやビアホール)に銅の埋め込みを行うためには、均一電着性(厚さが均一にめっきされる浴の能力)及びレベリング性(素地の微視的な凹凸や、研磨の条こん等を平滑化する電気めっき浴の能力)の高いめっきプロセスを実現する必要があるからである。そのため従来は平坦にめっきを行うための技術として、めっき液に下記(1)乃至(3)に示すような添加剤と呼ばれる化合物を加えることが一般に行われている。尚めっきにより銅を埋め込んで微細な配線等を形成するために半導体基板の表面に形成された凹部は前述したようにコンタクトホール、ビアホール、配線溝、トレンチ、溝等のように凹部の形成等に応じていくつかの呼び方があるが、本発明ではそれら凹部をあえて区別する必要が無いので、以降この呼称によって文意を明確にする必要があるときには統一的に、凹部と呼ぶか又は配線溝等と呼ぶ。   Therefore, various additives are conventionally added to the plating solution in order to flatten the surface at the end of plating. In order to bury copper in trenches (trench and via holes) that become fine wiring patterns by electrolytic copper plating using a copper sulfate plating solution as the plating solution, a uniform electrodeposition (thickness plating bath) This is because it is necessary to realize a plating process having a high leveling ability and a leveling property (the ability of the electroplating bath to smooth the microscopic unevenness of the substrate and the polishing conditions). Therefore, conventionally, as a technique for performing flat plating, a compound called an additive as shown in the following (1) to (3) is generally added to a plating solution. The concave portions formed on the surface of the semiconductor substrate in order to form fine wiring by embedding copper by plating can be used to form concave portions such as contact holes, via holes, wiring grooves, trenches, and grooves as described above. There are several ways to call them. However, in the present invention, it is not necessary to distinguish these recesses. Therefore, when it is necessary to clarify the meaning of the wording by this name, they are collectively referred to as a recess or a wiring groove. And so on.

(1)めっき面の多数の箇所に結晶核を生成させて析出粒子の微細化を促進するキャリアと呼ばれる硫黄化合物
(2)銅析出の過電圧を高めて均一電着性を向上させるポリマ
(3)めっきが成長しやすい凸部(基板においては、配線溝等の凹部が加工形成されていない部分、即ち基板の最表面に相当する)に吸着し過電圧を増加させて凸部即ち最表面への析出を遅らせることにより、平坦なめっきを可能とするレベラと呼ばれる窒素化合物
なお、前述のように基板においては、(イ)配線溝等の凹部が加工形成された部分と、(ロ)配線溝等が加工形成されていない部分とが有り、これらは例えば図3に代表的に例示する通りである。本発明においては、これらに対する呼称によって文意を明確にする必要があるときには、前記(イ)の部分即ち凹部内の表面を基板の凹部内表面または凹部内表面と言い、前記(ロ)の部分を基板の最表面又は基板凸部と言う。図2及び図3において、51は基板の最表面を、52は凹部内表面を指す。
(1) Sulfur compounds called carriers that generate crystal nuclei at many locations on the plating surface and promote the refinement of the precipitated particles. (2) Polymers that increase the overpotential of copper deposition and improve the throwing power. (3) Plating that is easy to grow plating (in the substrate, the portion where the recess such as the wiring groove is not formed, that is, corresponding to the outermost surface of the substrate) is adsorbed to increase the overvoltage to deposit on the protruding portion, that is, the outermost surface. Nitrogen compound called leveler that enables flat plating by delaying (2) In the substrate, as described above, (a) a portion in which a recess such as a wiring groove is processed and (b) a wiring groove or the like There are portions that are not processed and formed, for example, as representatively illustrated in FIG. In the present invention, when it is necessary to clarify the meaning of the word by referring to these, the part (a), that is, the surface in the recess is called the inner surface of the recess or the inner surface of the recess. Is called the outermost surface of the substrate or the substrate protrusion. 2 and 3, 51 indicates the outermost surface of the substrate, and 52 indicates the inner surface of the recess.

しかしながら、めっき液中に上記(1)乃至(3)の化合物を添加剤として入れると、めっきされた銅めっき膜102中にこれらの化合物が不純物として取込まれ、電気伝導度に悪影響を与える可能性がある。   However, when the above compounds (1) to (3) are added as additives to the plating solution, these compounds are taken in as impurities in the plated copper plating film 102, which may adversely affect the electrical conductivity. There is sex.

平坦な電解銅めっきを実現させる方法として電気化学機械析出(ECMD)技術が「Method and Apparatus for Electrochemical Mechanical Deposition」と題して下記特許文献1に開示されている。この方法によれば銅を析出する際に銅配線部を形成しないフィールド領域をパッドで研磨することによって、該フィールド領域上への銅析出を最小限にしながら、基板表面上のトレンチの中への銅の優先的な析出を達成し、それにより最終的には銅が析出される側の基板表面に全体的に平坦な銅析出物を生成するという。   As a method for realizing flat electrolytic copper plating, an electrochemical mechanical deposition (ECMD) technique is disclosed in Patent Document 1 below as “Method and Apparatus for Electrochemical Mechanical Deposition”. According to this method, when the copper is deposited, the field region in which the copper wiring portion is not formed is polished with the pad, thereby minimizing the copper deposition on the field region and into the trench on the substrate surface. The preferential deposition of copper is achieved, which ultimately produces a generally flat copper deposit on the substrate surface on which the copper is deposited.

また、シリコーン樹脂上に塗布したアルカンチオールを基板に対して接触転写する所謂マイクロコンタクトプリンデングを用いた論文が下記非特許文献1に掲載されている。この方法は、基板の銅配線を埋め込む側の最表面(基板凸部)に予めクイクロコンタクトプリンティングを用いてめっき抑制物質であるアルカンチオールを転写させてその部分における銅めっきを抑制し、凹部にのみ銅を堆積させる方法で、新しいプロセスとして提唱されている。   Non-patent document 1 below discloses a paper using so-called microcontact printing in which an alkanethiol coated on a silicone resin is contact-transferred to a substrate. In this method, alkanethiol, which is a plating inhibitory material, is transferred in advance to the outermost surface (substrate convex portion) on the side where the copper wiring of the substrate is embedded using copper contact printing to suppress copper plating in that portion, and to the concave portion. Only a method of depositing copper has been proposed as a new process.

この方法ならば確かに、CMP工程において余剰な銅の除去や基板の平坦化は一層好ましく行うことができ、またディシング104やエロージョン105(図1(b)参照)の発生も抑えることができる。しかしながらこの方法は、基板凸部(基板の最表面)においてはダマシン銅めっきを完全に抑制して配線部になる配線溝等の内部即ちトレンチ内部やコンタクトホール内部のみを埋め込んでいるため、トレンチ101の幅が結晶粒子の大きさよりも小さい場合、めっき工程後行われる熱処理工程において、その目的である銅の再結晶や歪みの緩和等の効果が少なくなる場合がある。   If this method is used, the removal of excess copper and the planarization of the substrate can be more preferably performed in the CMP process, and the occurrence of the dishing 104 and the erosion 105 (see FIG. 1B) can be suppressed. However, in this method, since the damascene copper plating is completely suppressed at the substrate convex portion (the outermost surface of the substrate), only the inside of the wiring groove or the like that becomes the wiring portion, that is, the inside of the trench or the contact hole is buried. In the case where the width is smaller than the size of the crystal grains, the effects of copper recrystallization and strain relaxation, which are the purposes, may be reduced in the heat treatment step performed after the plating step.

また、めっき工程終了時のトレンチ101部分の銅埋め込みの上部(銅めっき膜102の上部)の形状が図2に示すように、凸状102cになっているために、後の工程であるCMP工程において局所的にせん断力が加わり、銅層とその下地のバリア層(膜)103間、又はバリア膜とlow−k材等の絶縁層100間、又はその両方で剥離が生じる場合がある。即ち前述の銅めっき膜(層)102の再結晶や歪の緩和の効果が不十分であることによるストレスマイグレーションやエレクトロマイグレーションという不具合が生じ易くなる。
米国特許第6,176,992号 Electrochemical and Solid−State Letters 2004年9月号 C101−C103
In addition, since the shape of the upper part of the copper embedding (upper part of the copper plating film 102) in the trench 101 at the end of the plating process is a convex shape 102c as shown in FIG. In this case, a shearing force is locally applied to the film, and peeling may occur between the copper layer and the underlying barrier layer (film) 103, or between the barrier film and the insulating layer 100 such as a low-k material, or both. That is, problems such as stress migration and electromigration due to insufficient effects of recrystallization and strain relaxation of the copper plating film (layer) 102 are likely to occur.
US Pat. No. 6,176,992 Electrochemical and Solid-State Letters September 2004 C101-C103

添加剤を調整して均一電着性とレベリング性を高めためっき液を使用した電解銅めっきで、コンタクトホールやトレンチ等(配線溝等)の内部への電解めっきにより銅の埋め込みを行うと、基板表面にはコンタクトホールやトレンチ等が形成されている部分を含め、全面に銅膜が形成されるが、その膜厚は図1(a)に示すように配線等の密集部分、即ちトレンチ101の密集部分においては膜厚が非配線部の膜厚に比べて厚くなる一方で、幅の広い配線が形成された部分においては非配線部分の膜厚に比べて薄くなるという現象が生じる。このように膜厚にばらつきが生じると、配線部の銅の埋め込み自体は問題とならないが、めっきの後段プロセスであるCMP工程における平坦化が極めて困難になってしまう。   When copper is embedded by electrolytic plating inside contact holes, trenches, etc. (wiring grooves, etc.) using electrolytic plating with a plating solution that has improved electrodeposition and leveling properties by adjusting additives, A copper film is formed on the entire surface including the portion where contact holes, trenches and the like are formed on the substrate surface, and the film thickness thereof is a dense portion such as wiring, that is, trench 101 as shown in FIG. In the dense portion, the film thickness becomes thicker than the film thickness of the non-wiring portion, while in the portion where the wide wiring is formed, the phenomenon becomes thinner than the film thickness of the non-wiring portion. When the film thickness varies in this way, the copper embedding itself in the wiring part does not cause a problem, but flattening in the CMP process, which is a subsequent process of plating, becomes extremely difficult.

即ち、上述したように、CMP工程に要する時間の短縮化のため膜厚を薄く形成しようとすると、例え均一電着性やレベリング性の高いめっき液を使用しても、上記のようにめっき終了後の膜厚のばらつきによりめっき表面に凹凸が存在するので、余剰な銅膜の除去や基板表面の平坦化が十分に行われなかったり、ディシング104やエロージョン105(図1(b)参照)を生じてしまうという不具合が発生する。また、このようなめっき膜厚のばらつきによる不具合を抑えるために、図3に示すように厚い銅めっき膜102を施すと、CMP工程における加工時間が長くなってしまう場合があった。   That is, as described above, if a thin film is formed to shorten the time required for the CMP process, the plating is completed as described above even if a plating solution having high uniform electrodeposition and leveling properties is used. Since unevenness is present on the plating surface due to subsequent variations in film thickness, removal of excess copper film and flattening of the substrate surface are not performed sufficiently, or the dishing 104 and erosion 105 (see FIG. 1B) are used. The problem that it occurs will occur. In addition, when a thick copper plating film 102 is applied as shown in FIG. 3 in order to suppress such defects due to variations in the plating film thickness, the processing time in the CMP process may become long.

また、配線部になるコンタクトホールやトレンチ101等(配線溝等)の側壁面や底面のように基板に形成された凹部内表面以外の基板表面(即ち、基板の最表面であって、基板凸部とも言う)をめっき抑制剤(めっき抑制物質)により完全に覆ったうえで電解めっきすると、図2に示すように、コンタクトホールやトレンチ101等の凹部が形成された配線部のみ銅めっき膜102が形成され、めっき表面が非配線部の基板の最表面(基板凸部)よりも高くなった凸状のめっき膜102が形成される。   Further, the substrate surface other than the inner surface of the recess formed on the substrate, such as the contact hole or the trench 101 or the like (wiring groove or the like) or the bottom surface of the substrate (that is, the outermost surface of the substrate, the substrate surface When the electroplating is carried out after completely covering the substrate with a plating inhibitor (plating inhibitor), as shown in FIG. 2, only the wiring portion in which the concave portion such as the contact hole or the trench 101 is formed is provided with the copper plating film 102. A convex plating film 102 having a plating surface higher than the outermost surface (substrate convex portion) of the substrate in the non-wiring portion is formed.

この場合、後工程である熱処理やCMP工程時に以下のようなことが起こる。即ち配線部のみに銅めっき膜102が堆積されているために銅自体の体積が限られてしまい、熱処理工程時にめっき銅の再結晶や歪みの緩和等の効果が少なくなる場合がある。また、上述のようにコンタクトホールやトレンチ101等において銅埋め込み部の表面形状が凸状102cになっているため、CMP工程時に局所的にせん断力が加わり、銅層とその下地のバリア層103、又はバリア層103とlow−k材等の絶縁層100間、又はその両方で剥離が生じてしまう。   In this case, the following occurs during the heat treatment or CMP process, which is a subsequent process. That is, since the copper plating film 102 is deposited only on the wiring portion, the volume of the copper itself is limited, and the effects of recrystallization of plated copper, relaxation of strain, and the like may be reduced during the heat treatment process. Further, as described above, since the surface shape of the copper embedded portion in the contact hole, the trench 101 or the like is the convex shape 102c, a shearing force is locally applied during the CMP process, and the copper layer and the underlying barrier layer 103, Alternatively, separation occurs between the barrier layer 103 and the insulating layer 100 such as a low-k material, or both.

本発明は上述の点に鑑みてなされたもので、めっき工程後に行われる熱処理工程においてめっき銅の再結晶や歪の緩和を十分に行うことが出来、CMP工程において当該工程に要する時間を短縮でき、余剰な銅膜の除去や基板表面の平坦化を十分に行うことが出来、またディッシングやエロージョン等の不具合を発生すること無く、銅層、バリア層、絶縁層の相互間に剥離等の不具合を生じることも無いようなめっき膜を、めっき工程終了の時点で得られることが強く望まれている。そのため本発明においてはめっき工程終了時点でのめっき膜が、基板の配線溝等が形成された側の面即ち基板のめっきされる側の面全体に亘ってめっき膜が形成され、且つ当該めっき膜の表面に平坦に形成され、さらにめっき膜厚さ即ち基板の最表面上に堆積しためっき層の厚さを薄く形成できるような、電解めっきによる基板配線形成方法、基板配線形成装置、及びめっき抑制物質転写スタンプを提供することを目的とする。   The present invention has been made in view of the above points, and can sufficiently recrystallize plated copper and relax strain in a heat treatment process performed after the plating process, and can reduce the time required for the process in the CMP process. , Removal of excess copper film and flattening of the substrate surface can be sufficiently performed, and defects such as peeling between copper layers, barrier layers and insulating layers can be achieved without causing problems such as dishing and erosion. It is strongly desired to obtain a plating film that does not cause the occurrence of plating at the end of the plating process. Therefore, in the present invention, the plating film at the end of the plating step is formed over the entire surface of the substrate on which the wiring grooves and the like are formed, that is, the surface of the substrate to be plated, and the plating film. A substrate wiring forming method by electrolytic plating, a substrate wiring forming apparatus, and plating suppression, which can be formed flat on the surface of the substrate and further reduce the plating film thickness, that is, the thickness of the plating layer deposited on the outermost surface of the substrate. The object is to provide a mass transfer stamp.

上記課題を解決する請求項1に記載の発明は、基板に形成された配線溝等の凹部を電解めっきにより金属で埋め込み配線を形成する基板配線形成方法において、前記基板の凹部内表面を除く該基板の表面即ち基板の最表面にめっきを抑制するめっき抑制物質を付着させるめっき抑制物質付着工程と、その後に電解めっきを行う電解めっき(電気めっき)工程とを備えたことを特徴とする。   The invention according to claim 1, which solves the above problem, is a substrate wiring forming method in which a recessed portion such as a wiring groove formed on a substrate is filled with metal by electrolytic plating to remove the inner surface of the recessed portion of the substrate. It is characterized by comprising a plating inhibiting substance attaching step for attaching a plating inhibiting substance that suppresses plating to the surface of the substrate, that is, the outermost surface of the substrate, and an electrolytic plating (electroplating) step for performing electrolytic plating thereafter.

請求項2に記載の発明は、請求項1に記載の基板配線形成方法において、前記電解めっき工程の後に、前記めっき抑制物質を基板の表面から離脱させるめっき抑制物質離脱工程を備えたことを特徴とする。   The invention according to claim 2 is the substrate wiring forming method according to claim 1, further comprising a plating inhibitor release process for releasing the plating inhibitor from the surface of the substrate after the electrolytic plating process. And

請求項3に記載の発明は、請求項2に記載の基板配線形成方法において、前記めっき抑制物質離脱工程後に、電解めっきを行う電解めっき工程を備えたことを特徴とする。   According to a third aspect of the present invention, in the substrate wiring forming method according to the second aspect of the present invention, an electrolytic plating step of performing electrolytic plating is provided after the plating suppression substance removing step.

請求項4に記載の発明は、請求項2又は3に記載の基板配線形成方法において、前記めっき抑制物質離脱工程は、前記電解めっき方向とは逆に電解をかける(電源の正負が逆の電解めっきを行う)ことにより行うことを特徴とする。   According to a fourth aspect of the present invention, in the method for forming a substrate wiring according to the second or third aspect, in the plating inhibiting substance removing step, electrolysis is performed in the opposite direction to the electrolytic plating direction (electrolysis in which the positive and negative of the power source are reversed). It is characterized by performing by plating.

請求項5に記載の発明は、請求項4に記載の基板配線形成方法において、前記めっき抑制物質離脱工程の電解めっき方向とは逆に電解をかける時点は、前記電解めっき工程により前記基板の凹部内に埋め込まれた金属の表面と前記めっき抑制物質を付着させた前記基板の表面(基板の最表面)とが同一面になった時点即ち基板の凹部内が金属で埋め込まれた結果、これらの両表面が互いに同一の高さとなった時点であることを特徴とする。   According to a fifth aspect of the present invention, in the method for forming a substrate wiring according to the fourth aspect, when the electrolysis is applied in the direction opposite to the electroplating direction of the plating inhibitor releasing step, the concave portion of the substrate is formed by the electrolytic plating step. When the surface of the metal embedded in the substrate and the surface of the substrate on which the plating inhibitor is adhered (the outermost surface of the substrate) are flush with each other, that is, as a result of the recesses in the substrate being embedded with metal, these It is characterized in that both surfaces are at the same height.

請求項6に記載の発明は、請求項1乃至5のいずれか1項に記載の基板配線形成方法において、前記めっき抑制物質付着工程は、スタンプに予め前記めっき抑制物質を担持させた後、該スタンプを前記基板の表面(基板の最表面)に押し当てることにより、該めっき抑制物質を該基板の表面に転写させることを特徴とする。   According to a sixth aspect of the present invention, in the substrate wiring forming method according to any one of the first to fifth aspects, the plating suppression substance attaching step includes supporting the plating suppression substance on a stamp in advance, The plating inhibitor is transferred to the surface of the substrate by pressing the stamp against the surface of the substrate (the outermost surface of the substrate).

請求項7に記載の発明は、請求項1乃至6のいずれか1項に記載の基板配線形成方法において、前記電解めっき工程で前記基板の凹部内を埋め込む金属は、銅、又は銅合金、又は銀であることを特徴とする。   The invention according to claim 7 is the substrate wiring forming method according to any one of claims 1 to 6, wherein the metal embedded in the concave portion of the substrate in the electrolytic plating step is copper, a copper alloy, or It is characterized by being silver.

請求項8に記載の発明は、請求項1乃至7のいずれか1項に記載の基板配線形成方法において、前記めっき抑制物質付着工程で前記基板の表面に付着しためっき抑制物質は、厚さが一様な膜状態であることを特徴とする。   The invention according to claim 8 is the method for forming a substrate wiring according to any one of claims 1 to 7, wherein the plating inhibiting substance attached to the surface of the substrate in the plating inhibiting substance attaching step has a thickness of It is characterized by a uniform film state.

請求項9に記載の発明は、請求項6乃至8のいずれか1項に記載の基板配線形成方法において、前記スタンプとして前記めっき抑制物質を担持するめっき抑制物質担持部が、シリコーン樹脂又はフッ素樹脂の少なくとも一方を有して構成されたスタンプを用いることを特徴とする。   A ninth aspect of the present invention is the method for forming a substrate wiring according to any one of the sixth to eighth aspects, wherein the plating suppression material-carrying portion that carries the plating suppression material as the stamp is a silicone resin or a fluororesin. A stamp having at least one of the above is used.

請求項10に記載の発明は、請求項9に記載の基板配線形成方法において、前記スタンプとして、めっき抑制物質担持部が支持体により支持されたスタンプを用いることを特徴とする。   According to a tenth aspect of the present invention, in the substrate wiring forming method according to the ninth aspect of the present invention, the stamp is a stamp in which a plating-suppressing substance carrying portion is supported by a support.

請求項11に記載の発明は、請求項9又は10に記載の基板配線形成方法において、前記スタンプとして、少なくともめっき抑制物質担持部外表面が平板状又は円柱状に構成されているスタンプを用いることを特徴とする。   According to an eleventh aspect of the present invention, in the substrate wiring forming method according to the ninth or tenth aspect of the present invention, as the stamp, a stamp in which at least the outer surface of the plating suppression substance-carrying part is configured in a flat plate shape or a cylindrical shape is used. It is characterized by.

請求項12に記載の発明は、めっき液を収容するめっき液槽を備え、該めっき液槽のめっき液中に配線溝等の凹部が形成された基板と陽極電極を配置し、めっき電源より該陽極電極と前記基板との間に所定のめっき電圧を印加し、電解めっきにより該基板の凹部内を金属で埋め込み配線を形成する基板配線形成装置において、前記基板は凹部内表面を除く前記基板の表面、即ち基板の最表面にめっきを抑制するめっき抑制物質を付着させた基板であることを特徴とする。   The invention according to claim 12 includes a plating solution tank for containing a plating solution, and a substrate on which a recess such as a wiring groove is formed in the plating solution in the plating solution tank and an anode electrode, In a substrate wiring forming apparatus in which a predetermined plating voltage is applied between an anode electrode and the substrate, and a wiring is formed by embedding the concave portion of the substrate with metal by electrolytic plating, the substrate is formed on the substrate except for the inner surface of the concave portion. The substrate is characterized in that a plating inhibitory substance that suppresses plating is attached to the surface, that is, the outermost surface of the substrate.

請求項13に記載の発明は、請求項12に記載の基板配線形成装置において、前記電解めっき中に所定のタイミングで前記陽極電極と前記基板の間に印加する電圧の極性の正負を前記電解めっき時とは前記極性の正負が逆になるように切替えて印加する極性切替手段を備えたことを特徴とする。   The invention according to claim 13 is the substrate wiring forming apparatus according to claim 12, wherein the polarity of the polarity of the voltage applied between the anode electrode and the substrate is determined at a predetermined timing during the electrolytic plating. It is characterized by comprising polarity switching means for switching and applying the polarity so that the polarity is reversed.

請求項14に記載の発明は、基板に形成された配線溝等の凹部を電解めっきにより金属で埋め込むことにより該基板に配線を形成する際に、前記基板の凹部内表面を除く該基板の表面即ち基板の最表面にめっきを抑制するめっき抑制物質を転写させるのに用い、めっき抑制物質担持部を有するめっき抑制物質転写スタンプであって、前記スタンプの少なくともめっき抑制物質担持部はシリコーン樹脂又はフッ素樹脂の少なくとも一方を有して成ることを特徴とする。   In the invention described in claim 14, when the wiring is formed on the substrate by embedding a recess such as a wiring groove formed on the substrate with metal by electrolytic plating, the surface of the substrate excluding the inner surface of the recess of the substrate That is, a plating suppression material transfer stamp used to transfer a plating suppression material that suppresses plating to the outermost surface of the substrate and having a plating suppression material supporting portion, and at least the plating suppression material supporting portion of the stamp is made of silicone resin or fluorine It has at least one of resin, It is characterized by the above-mentioned.

請求項15に記載の発明は、請求項14に記載のめっき抑制物質転写スタンプにおいて、前記スタンプは少なくともめっき抑制物質担持部が支持体に支持された構成であることを特徴とする。   According to a fifteenth aspect of the present invention, in the plating suppression material transfer stamp according to the fourteenth aspect, the stamp has a configuration in which at least a plating suppression material carrying portion is supported by a support.

請求項16に記載の発明は、請求項14又は15に記載のめっき抑制物質転写スタンプにおいて、前記スタンプは少なくともめっき抑制物質担持部外表面が平板状又は円柱状であることを特徴とする。   The invention described in claim 16 is the plating inhibitor transfer stamp according to claim 14 or 15, characterized in that the stamp has at least an outer surface of the plating inhibitor carrying part having a flat plate shape or a cylindrical shape.

本発明によれば、配線溝等の凹部内表面即ちトレンチやコンタクトホール等の凹部の側壁面、底面などであって、それらの面に接して配線用としての銅を堆積すべき面以外の基板表面(即ち基板の最表面であり、基板凸部とも言う)を、めっき抑制物質(めっき抑制剤)で覆った後に、電解めっきを行い、次に電解めっきの電解方向とは逆に電解をかけることで、めっき抑制物質(めっき抑制剤)を基板最表面から脱離させ、その後電解めっきを再開し適切な時間行うことでめっき工程終了時点において薄くてめっき表面の平坦度が高いめっき膜を、基板の配線埋め込み側の表面全面に亘って成膜することが実現できるので前記の諸課題を解決することができる。   According to the present invention, a substrate other than the inner surface of a recess such as a wiring groove, that is, the side wall surface or the bottom surface of a recess such as a trench or a contact hole, on which copper for wiring is to be deposited in contact with these surfaces After covering the surface (that is, the outermost surface of the substrate, also referred to as the convex portion of the substrate) with a plating inhibitor (plating inhibitor), electrolytic plating is performed, and then electrolysis is performed opposite to the electrolytic direction of electrolytic plating. By removing the plating inhibitor (plating inhibitor) from the outermost surface of the substrate, and then restarting the electrolytic plating and performing it for an appropriate time, a plating film that is thin at the end of the plating process and has a high flatness on the plating surface, Since the film can be formed over the entire surface on the wiring embedding side of the substrate, the above-described problems can be solved.

即ち本発明に係る基板配線形成方法は、配線溝等即ちトレンチやコンタクトホール等の凹部が加工形成された基板の該凹部内に電解めっきにより金属を埋め込んで配線を形成する方法であり、前記凹部の壁面や底面等の凹部内表面を除く面に、めっきを抑制する物質を付着させる抑制物質付着工程と、その後の電解めっきを行う電解めっき工程とを含むことを特徴とする。   That is, the substrate wiring forming method according to the present invention is a method of forming a wiring by embedding a metal by electrolytic plating in a concave portion of a substrate on which a concave portion such as a trench or a contact hole is processed and formed. The method further includes a suppressive substance attaching step for attaching a substance that suppresses plating to a surface excluding the inner surface of the recess, such as a wall surface and a bottom surface, and an electrolytic plating step for performing subsequent electrolytic plating.

また、本発明においては、上記抑制物質付着工程と電解めっき工程のさらに後にめっきの電解方向とは逆の方向に電解を行い前記めっきを抑制する物質を基板の最表面から離脱させるめっき抑制物質離脱工程を行うことが好ましく、加えて、上記諸工程の後工程として、再び電解めっき工程を行うのが更に好ましい。   Further, in the present invention, the plating suppression substance detachment that causes the substance that suppresses the plating to be released from the outermost surface of the substrate by performing electrolysis in a direction opposite to the electrolysis direction of the plating further after the above-described suppression substance attaching step and the electrolytic plating step. It is preferable to perform the process, and in addition, it is more preferable to perform the electrolytic plating process again as a subsequent process of the above-mentioned various processes.

なお、前記めっきの電解方向とは逆の方向に電解を行うめっき抑制物質離脱工程以外にも、めっきを抑制する物質を基板の最表面から離脱させる方法には、下記の方法がある。   In addition to the plating suppression substance removing step of performing electrolysis in the direction opposite to the electrolysis direction of the plating, there are the following methods for releasing the substance that suppresses plating from the outermost surface of the substrate.

基板に傷を付けない物性を持った弾性体によりめっきを抑制する物質をめっき液中またはめっき液外において基板の最表面から離脱させる方法。   A method in which a substance that suppresses plating is removed from the outermost surface of the substrate in or outside the plating solution by an elastic body having physical properties that do not damage the substrate.

めっきを抑制する物質を溶解する溶液にめっき液外において基板を浸漬させて該基板の最表面からめっきを抑制する物質を離脱させる方法。   A method of detaching a substance that suppresses plating from the outermost surface of the substrate by immersing the substrate outside a plating solution in a solution that dissolves the substance that suppresses plating.

めっき液中またはめっき液外において基板の最表面を超音波により振動させてめっきを抑制する物質を該基板の最表面から離脱させる方法。   A method in which a substance that suppresses plating is detached from the outermost surface of the substrate by vibrating the outermost surface of the substrate with ultrasonic waves in or outside the plating solution.

めっき液中またはめっき液外において基板の最表面にノズル等により水圧を印加して、めっきを抑制する物質を該基板の最表面から離脱させる方法。
以上の通り、めっきを抑制する物質を基板の最表面から離脱させるためのいくつかの方法を示した。
A method in which a water pressure is applied to the outermost surface of the substrate in a plating solution or outside the plating solution by a nozzle or the like to release a substance that suppresses plating from the outermost surface of the substrate.
As described above, several methods for releasing the material for suppressing plating from the outermost surface of the substrate have been shown.

上記のように基板の最表面(基板凸部)にのみめっきを抑制する物質を付着させ、配線溝等即ちトレンチやコンタクトホール等の凹部の内表面には該めっきを抑制する物質を付着させないので、電解めっきを行うと銅層が凹部を埋め込むように形成される。   As described above, a substance that suppresses plating is attached only to the outermost surface (substrate convex part) of the substrate, and a substance that suppresses plating is not attached to the inner surface of a recess such as a wiring groove, that is, a trench or a contact hole. When the electrolytic plating is performed, the copper layer is formed so as to fill the recess.

上記のようにして基板の凹部を銅で埋め込み、該銅の表面がめっきを抑制する物質を付着させた基板の最表面と同一面に達した時点でめっきと逆の電解方向に電解を行って、めっきを抑制する物質を基板の最表面から離脱させる。なお前記「基板の最表面と同一面」とは言うまでもなく、基板の最表面に形成されたシード層及びバリア層が形成する表面と同一面と言う趣旨であって、基板の最表面に付着させためっき抑制物質が形成する面と同一面と言うことではない。また、このことは本発明(明細書)の全体に渡って同趣旨である。   As described above, the concave portion of the substrate is filled with copper, and when the surface of the copper reaches the same surface as the outermost surface of the substrate to which a substance that suppresses plating is attached, electrolysis is performed in the opposite electrolysis direction to plating. The material that suppresses plating is released from the outermost surface of the substrate. Needless to say, “the same surface as the outermost surface of the substrate” is the same surface as the surface formed by the seed layer and the barrier layer formed on the outermost surface of the substrate, and is attached to the outermost surface of the substrate. It is not the same surface as the surface on which the plating inhibitor is formed. This also has the same meaning throughout the present invention (specification).

次に再び電解めっきを行うと、配線溝等の凹部に埋め込まれて形成された銅層(半導体集積回路の配線等となる部分)の表面に加え、めっきを抑制する物質が離脱した基板の最表面(基板凸部)においても同時に電解めっきが進行し基板の片面全体(即ち配線溝等の凹部が加工形成されている側の全面)に、均一な厚さで銅膜が堆積する。従って、基板の最表面上に堆積した銅膜の厚みが所望の値になった時点で電解めっきを終了すれば、全面に渡って平坦度の高い銅めっき表面を備えた基板を得る事ができる。   Next, when electrolytic plating is performed again, in addition to the surface of the copper layer (the portion that becomes the wiring of the semiconductor integrated circuit) embedded in the recess such as the wiring groove, the most of the substrate from which the substance that suppresses the plating has separated is removed. On the surface (substrate convex portion), electrolytic plating proceeds simultaneously, and a copper film is deposited with a uniform thickness on the entire surface of one side of the substrate (that is, the entire surface where the concave portions such as the wiring grooves are processed and formed). Therefore, if the electroplating is completed when the thickness of the copper film deposited on the outermost surface of the substrate reaches a desired value, a substrate having a copper plating surface with high flatness over the entire surface can be obtained. .

上記のような基板を得ることができるので、下記のような利点が得られる。
(1)めっき工程後に行われる熱処理工程において、堆積した金属銅は基板の全体に亘って均一な温度に制御されるから、理想的な熱処理効果を得ることが出来るので、再結晶や歪の緩和が十分になされる。従って、例えば基板上に形成された半導体チップの断線などの不具合の発生を抑制できる。
Since the above substrate can be obtained, the following advantages are obtained.
(1) In the heat treatment step performed after the plating step, the deposited copper metal is controlled at a uniform temperature over the entire substrate, so that an ideal heat treatment effect can be obtained, so recrystallization and strain relief. Is made enough. Therefore, for example, it is possible to suppress the occurrence of problems such as disconnection of a semiconductor chip formed on the substrate.

(2)また、めっき膜厚は基板全体の銅膜がその厚み方向も含めて均一な温度で熱処理できる程度の厚みを有すれば良いので、小さい値に抑えることが出来るため、CMP工程に要する時間を短くできる。   (2) Further, the plating film thickness can be suppressed to a small value as long as the copper film on the entire substrate has a thickness that can be heat-treated at a uniform temperature including the thickness direction. Time can be shortened.

(3)さらに例えば電解めっきの電解方向とは逆に電解をかける時点とその条件(電流密度、印加電圧、電解めっきの電解方向とは逆に電解をかける処理時間など)を適切に選べば、めっき工程完了時点でのめっき表面を十分な平坦度にすることが出来るからその後のCMP工程において、下記のような利点が得られる。   (3) Further, for example, if the time of electrolysis opposite to the electrolysis direction of electroplating and the conditions (current density, applied voltage, treatment time for electrolysis opposite to electrolysis direction of electroplating, etc.) are appropriately selected, Since the plating surface can be made sufficiently flat when the plating process is completed, the following advantages can be obtained in the subsequent CMP process.

・十分な平坦化ができると共に余剰な銅を余すこと無く除去できる。
・砥石等の研磨材によって、基板の銅配線等に過大な剪断力が加わることが無いから、銅層、バリア層、絶縁材等の間に前記したような剥離を生じることが無い。
・その上、CMP工程の当初から平坦度が高いから、ディッシングやエロージョンを生じることも無い。
-It can be sufficiently flattened and removed without excess copper.
-An abrasive such as a grindstone does not apply an excessive shearing force to the copper wiring or the like of the substrate, so that the above-described peeling does not occur between the copper layer, the barrier layer, the insulating material and the like.
In addition, since the flatness is high from the beginning of the CMP process, dishing and erosion do not occur.

さらに本発明では、めっきを抑制する物質を基板の最表面(基板凸部)に付着させるに際し、スタンプに予め、めっきを抑制する物質を付着させた後にスタンプを基板の最表面に押し当てることにより転写する方法を採用することにより、めっき抑制物質を一様な厚さで基板の最表面に付着できるから、平坦なめっき膜が得られるという有利な結果を得ることが出来る。   Furthermore, in the present invention, when a substance that suppresses plating is attached to the outermost surface (substrate convex portion) of the substrate, a substance that suppresses plating is attached to the stamp in advance, and then the stamp is pressed against the outermost surface of the substrate. By adopting the transfer method, the plating inhibiting substance can be adhered to the outermost surface of the substrate with a uniform thickness, so that an advantageous result that a flat plating film can be obtained can be obtained.

また、本発明に係る基板配線形成方法では、めっき金属として銅、または銅合金、または銀を用いる。これにより実用性の高い基板配線を得ることが出来る。   In the substrate wiring forming method according to the present invention, copper, a copper alloy, or silver is used as the plating metal. Thereby, a highly practical substrate wiring can be obtained.

さらに本発明に係る基板配線形成方法では、基板の最表面に、めっきを抑制する物質がその厚さが一様になるように付着されることにより、例えば基板の最表面(基板凸部)全体について一様にめっきを抑制でき、電解めっきの電解方向とは逆に電解をかけたときには、めっきを抑制する物質を基板の最表面から一様に離脱することが出来る。従って、電解めっき工程終了時点でのめっき表面の平坦化に貢献する。   Furthermore, in the substrate wiring forming method according to the present invention, a substance that suppresses plating is attached to the outermost surface of the substrate so that the thickness thereof is uniform, for example, the entire outermost surface (substrate convex portion) of the substrate. When the electrolysis is applied in the direction opposite to the electrolysis direction of the electroplating, the substance that suppresses the plating can be uniformly detached from the outermost surface of the substrate. Therefore, it contributes to the flattening of the plating surface at the end of the electrolytic plating process.

さらに本発明に係る基板配線形成方法で用いるスタンプは上記のように、基板の配線溝等例えばトレンチやコンタクトホール等の凹部内表面を除く面、即ち基板の最表面にめっきを抑制する物質を付着させる器具であり、そのめっき抑制物質担持部は、シリコーン樹脂又はフッ素樹脂の少なくとも一方を用いて製作されている。なお必要に応じてこれらの樹脂以外の材料を交えて製作しても良い。まためっき抑制物質担持部自体の機械的強度が小さい等の事情があるときにはめっき抑制物質担持部に支持体を備えてスタンプを構成するのが好ましい。   Furthermore, as described above, the stamp used in the substrate wiring forming method according to the present invention attaches a substance that suppresses plating to the surface other than the inner surface of the recess, such as a wiring groove of the substrate, such as a trench or a contact hole, that is, the outermost surface of the substrate. The plating suppression substance carrying part is manufactured using at least one of silicone resin or fluororesin. In addition, you may manufacture together with materials other than these resin as needed. In addition, when there is a situation such as the mechanical strength of the plating suppression substance carrying part itself being small, it is preferable that the stamp is formed by providing a support on the plating suppression substance carrying part.

めっき抑制物質担持部の材料として上記の材料を用いてスタンプを製作したので、インクの離型性が良いという有利な効果が得られる。さらに本発明によるスタンプは、少なくともめっき抑制物質担持部の外表面が平板状または円柱状に形成されている。めっき抑制物質担持部の表面形状が平板状のスタンプはその外形を例えば矩形や円形に加工して使用できるから汎用性がある。また円柱状に形成されたスタンプは、その軸心の周りに回転させることが出来る。   Since the stamp is manufactured using the above-mentioned material as the material for the plating suppression substance supporting portion, an advantageous effect that the ink releasability is good can be obtained. Further, in the stamp according to the present invention, at least the outer surface of the plating suppression substance supporting portion is formed in a flat plate shape or a cylindrical shape. A stamp having a plate-like surface shape of the plating-suppressing substance-carrying portion is versatile because it can be used by processing its outer shape into, for example, a rectangle or a circle. A cylindrically formed stamp can be rotated around its axis.

請求項1に記載の発明によれば、めっき抑制物質付着工程と、電解めっき工程とを備えるので、基板の最表面にめっき膜を形成することなく、配線溝等の凹部内表面のみに効果的に金属めっき膜を形成した基板が得られる。   According to the first aspect of the present invention, since the plating suppression substance attaching step and the electrolytic plating step are provided, it is effective only on the inner surface of the recess such as a wiring groove without forming a plating film on the outermost surface of the substrate. A substrate having a metal plating film formed thereon is obtained.

請求項2に記載の発明によれば、電解めっき工程の後に、めっき抑制物質離脱工程を備えるので、基板最表面のめっき抑制物質が除去され、その後の電解めっき工程で、基板の配線溝等の凹部が形成された側の全面に金属めっき膜を形成できる形態を備えた基板が得られる。   According to the second aspect of the present invention, since the plating suppression substance removal step is provided after the electrolytic plating step, the plating suppression material on the outermost surface of the substrate is removed. A substrate having a configuration in which a metal plating film can be formed on the entire surface on the side where the recesses are formed is obtained.

請求項3乃至11に記載の発明では、めっき抑制物質離脱工程後に、電解めっき工程を備えるので、基板の配線溝等の凹部が形成された側の全面に金属めっき膜が形成された基板が得られるから、下記のような優れた効果が得られる。   In the inventions according to claims 3 to 11, since the electrolytic plating step is provided after the plating inhibitor releasing step, a substrate in which a metal plating film is formed on the entire surface of the substrate on which the recesses such as wiring grooves are formed is obtained. Therefore, the following excellent effects can be obtained.

(1)基板の配線溝やコンタクトホール等の凹部が形成された側の全面に金属めっき膜が形成されているので、電解めっき工程後の熱処理工程において、再結晶や歪の緩和を十分に行えるので、例えば基板中に形成された半導体チップの配線の断線等の不具合発生を抑止できる。
(2)また、めっき膜厚例えば基板の最表面を被覆するように堆積しためっき膜の厚みを適正な値に制御できるので、CMP工程に要する時間を妥当な値に抑えることが出来る。
(3)さらに、CMP(化学的機械的研磨)工程において基板全体の平坦化を実現できると共に余剰な銅膜を除去でき、且つディッシングやエロージョンを生じにくいので、優れたCMP加工を行うことができる。
(1) Since the metal plating film is formed on the entire surface of the substrate where the recesses such as wiring grooves and contact holes are formed, recrystallization and distortion can be sufficiently relaxed in the heat treatment step after the electrolytic plating step. Therefore, it is possible to suppress the occurrence of problems such as disconnection of the wiring of the semiconductor chip formed in the substrate, for example.
(2) Since the plating film thickness, for example, the thickness of the plating film deposited so as to cover the outermost surface of the substrate can be controlled to an appropriate value, the time required for the CMP process can be suppressed to an appropriate value.
(3) Further, in the CMP (Chemical Mechanical Polishing) step, the entire substrate can be flattened, the excess copper film can be removed, and dishing and erosion are less likely to occur, so that excellent CMP processing can be performed. .

請求項12及び13に記載の発明によれば、上記(1)乃至(3)の効果を有する基板配線形成装置を提供できる。   According to invention of Claim 12 and 13, the board | substrate wiring formation apparatus which has the effect of said (1) thru | or (3) can be provided.

請求項14乃至16に記載の発明によれば、基板の最表面に、めっきを抑制する物質を、その厚さが一様になるように付着することができるめっき抑制物質転写スタンプを提供できる。   According to the fourteenth to sixteenth aspects of the present invention, it is possible to provide a plating-inhibiting substance transfer stamp capable of adhering a substance that suppresses plating to the outermost surface of the substrate so that the thickness thereof is uniform.

以下、本発明の実施の形態例を説明する。本発明に係る基板配線形成方法では、基板に形成された配線溝等即ち配線溝やコンタクトホール等の凹部を電解めっきにより金属で埋め込む、所謂ダマシンめっき前に行われる工程として、基板の最表面(通常は絶縁材を被覆するバリア層とその上のシード層からなっている)の上に選択的にめっきを抑制するためのインク(めっき抑制物質)を転写等により付着することにより、ダマシンめっき後の工程で除去される銅層の膜厚を制御するめっき抑制物質付着工程を備えている。なお、ここで“インク”とは、被付着面である例えば基板の最表面の銅層やバリア層に最終的に付着されるべき物質であり、通常はこれを溶質として、適切な溶媒に溶解された溶液の状態で、スタンプのめっき抑制物質担持部に塗布されたり、被付着面(被転写面)に付着(転写)したりする。   Hereinafter, embodiments of the present invention will be described. In the substrate wiring forming method according to the present invention, as a process performed before so-called damascene plating in which a wiring groove or the like formed on the substrate, that is, a recess such as a wiring groove or a contact hole is filled with metal by electrolytic plating, After damascene plating, an ink (plating inhibitor) that selectively suppresses plating is usually applied onto the barrier layer covering the insulating material and the seed layer on the insulating layer by transfer or the like. A plating-inhibiting substance adhering step for controlling the film thickness of the copper layer removed in this step. Here, “ink” is a substance that should be finally attached to the adherend surface, for example, the copper layer or barrier layer on the outermost surface of the substrate, and is usually dissolved in an appropriate solvent as a solute. In the state of the solution thus applied, it is applied to the plating-suppressing substance carrying portion of the stamp or adhered (transferred) to the adherend surface (transfer surface).

上記インクの付着方法は、ダマシンめっき後の工程で除去される部分である半導体デバイスの配線を除く余剰な銅シード層(基板に形成されてトレンチやコンタクトホール等である凹部として形成された微細配線パターンに電気めっきにより銅を埋め込むために、基板全体に電気伝導性を持たせるために予めスパッタやCVDで成膜された層)やバリア層(層間絶縁膜内に配線金属種が拡散するのを防止することを目的に成膜された層)上に選択的にインクを付着する方法で、ダマシンめっき前に行われる工程であって、電解めっきであるダマシンめっきにおいて、めっきを抑制するために行われる。   The ink deposition method is an excess copper seed layer excluding semiconductor device wiring that is removed in the post-damascene plating process (fine wiring formed as recesses such as trenches and contact holes formed on the substrate) In order to embed copper in the pattern by electroplating, it is necessary to prevent the metal species from diffusing in the interlayer insulating film or barrier layer (layer formed by sputtering or CVD in advance to provide electrical conductivity to the entire substrate). This is a method of selectively depositing ink on a layer formed for the purpose of prevention, and is a step performed before damascene plating, and is performed to suppress plating in damascene plating, which is electrolytic plating. Is called.

電解めっき方法は、基板の金属を埋め込むトレンチやコンタクトホール等の凹部が加工形成された側面であって、凹部の壁面や底面等の凹部内表面を除く基板の表面(基板の最表面、即ち基板凸部)にめっきを抑制する物質を付着させる工程と、その後の電解めっきを行う工程とを含むめっき方法である。   The electrolytic plating method is a side surface in which concave portions such as trenches and contact holes for embedding metal in a substrate are processed and formed, and the surface of the substrate excluding the inner surface of the concave portion such as the wall surface and bottom surface of the concave portion (the outermost surface of the substrate, that is, the substrate It is a plating method including a step of attaching a substance that suppresses plating to the projections) and a step of performing subsequent electrolytic plating.

上記めっきを抑制する物質を付着させる工程、及び電解めっきを行う工程の後に、めっきの電解方向とは逆の方向に電解をかけてめっきを抑制する物質を基板の最表面から離脱させる工程を行うことが好ましく、加えて、上記諸工程の後工程として、再び電解めっき工程を行うことが更に好ましい。   After the step of attaching the substance that suppresses plating and the step of performing electrolytic plating, the step of separating the substance that suppresses plating from the outermost surface of the substrate by performing electrolysis in the direction opposite to the electrolytic direction of plating is performed. In addition, it is more preferable to perform the electroplating step again as a subsequent step of the above steps.

めっきを抑制する物質を基板表面から離脱させる方法には、上記めっきの電解方向とは逆の方向に電解をかけてめっきを抑制する物質を基板表面から離脱する以外にも下記(a)乃至(d)の方法がある。
(a)基板表面に傷を付けない物性を持った弾性体によって該めっきを抑制する物質をめっき液中又はめっき液外において基板の最表面から離脱させる方法。
(b)めっきを抑制する物質を溶解する溶液にめっき液外において浸漬させて離脱させる方法。
(c)めっき液中又はめっき液外において、基板の最表面を超音波により振動させてめっきを抑制する物質を基板の最表面から離脱させる方法。
(d)めっき液中又はめっき液外において基板の最表面にノズル等により水圧を印加して、めっきを抑制する物質を基板の最表面から離脱させる方法。
The method for releasing the substance that suppresses plating from the substrate surface includes the following (a) to (a) in addition to releasing the substance that suppresses plating from the substrate surface by performing electrolysis in a direction opposite to the electrolytic direction of the plating. There is a method d).
(A) A method in which a substance that suppresses plating is separated from the outermost surface of the substrate in or outside the plating solution by an elastic body having physical properties that do not damage the substrate surface.
(B) A method of immersing in a solution that dissolves a substance that suppresses plating outside the plating solution and releasing it.
(C) A method in which a substance that suppresses plating is detached from the outermost surface of the substrate by vibrating the outermost surface of the substrate with ultrasonic waves in or outside the plating solution.
(D) A method of applying a water pressure to the outermost surface of the substrate with a nozzle or the like in the plating solution or outside the plating solution to release the substance that suppresses plating from the outermost surface of the substrate.

めっき抑制物質の付着方法として転写を行うときには、スタンプと、溶媒中に溶解されたインクを用いる。転写方法は先ずスタンプを製作し、該スタンプに対して溶媒中に溶解されたインクを塗布し、次にスタンプのインクの塗布された面を基板の被転写面に接触させ、インクを該基板の被転写面に転写する。図4及び図5は上記インクの転写方法の概要を示す図で、図4は平坦なスタンプを用いた転写方法を、図5はローラー状(円柱状)のスタンプを用いた転写方法を示す。   When transfer is performed as a method for attaching a plating inhibitor, a stamp and ink dissolved in a solvent are used. In the transfer method, a stamp is first manufactured, ink dissolved in a solvent is applied to the stamp, and then the surface of the stamp where the ink is applied is brought into contact with the transfer surface of the substrate. Transfer to the transfer surface. 4 and 5 are diagrams showing an outline of the ink transfer method. FIG. 4 shows a transfer method using a flat stamp, and FIG. 5 shows a transfer method using a roller-shaped (columnar) stamp.

図4に示す転写方法は、図4(a)に示すように、インク4を担持するためのシリコーン樹脂材又はフッ素樹脂材からなるめっき抑制物質担持部1と、該めっき抑制物質担持部1を支持する支持体2を有する構成のスタンプ3を用意し、図示するように、外表面が平坦なめっき抑制物質担持部1にインク4を塗布する。なお、インクは通常では適切な溶媒に溶解されて溶液の状態になっている。次に図4(b)に示すように、トレンチやコンタクトホール等の凹部11が加工形成された基板10の該凹部11の内表面を含む表面に形成されたシード層及びバリア層12のうち、基板の最表面に対して、めっき抑制物質担持部1にインク4が塗布されたスタンプ3を当接させることにより、図4(c)に示すように、基板10の凹部11の内表面を除くシード層及びバリア層12の表面にインク4を転写する。   As shown in FIG. 4 (a), the transfer method shown in FIG. 4 includes a plating inhibitor carrying part 1 made of a silicone resin material or a fluororesin material for carrying the ink 4, and the plating inhibitor carrying part 1 A stamp 3 having a support 2 to be supported is prepared, and an ink 4 is applied to a plating inhibitor carrying part 1 having a flat outer surface as shown in the figure. The ink is usually dissolved in an appropriate solvent to be in a solution state. Next, as shown in FIG. 4B, among the seed layer and the barrier layer 12 formed on the surface including the inner surface of the recess 11 of the substrate 10 in which the recess 11 such as a trench and a contact hole is formed. As shown in FIG. 4C, the inner surface of the concave portion 11 of the substrate 10 is removed by bringing the stamp 3 coated with the ink 4 into contact with the plating suppression substance carrying portion 1 against the outermost surface of the substrate. The ink 4 is transferred to the surface of the seed layer and the barrier layer 12.

図5に示す転写方法は、支持体7の外周に外表面がローラー状(円柱状)のめっき抑制物質担持部5を設けた構成のスタンプ6を用意し、該めっき抑制物質担持部5の外周面にインク4を塗布する。このインク4が塗布されためっき抑制物質担持部5を、基板10のトレンチやコンタクトホール等の凹部11が加工形成された側のシード層及びバリア層12のうち、基板の最表面に当接回転させることにより、基板10の凹部11の内表面を除くシード層及びバリア層12の表面にインク4を転写する。   In the transfer method shown in FIG. 5, a stamp 6 having a structure in which a plating suppression substance supporting portion 5 having an outer surface of a roller (columnar) is provided on the outer periphery of a support 7 is prepared, and the outer periphery of the plating suppression substance supporting portion 5 is prepared. Ink 4 is applied to the surface. The plating-suppressing substance supporting portion 5 coated with the ink 4 is rotated in contact with the outermost surface of the substrate among the seed layer and the barrier layer 12 on the side where the recesses 11 such as trenches and contact holes of the substrate 10 are processed and formed. As a result, the ink 4 is transferred to the surface of the seed layer and the barrier layer 12 excluding the inner surface of the recess 11 of the substrate 10.

〔スタンプのめっき抑制物質担持部〕
〔めっき抑制物質担持部の材料〕
スタンプ3のめっき抑制物質担持部1の材料には、シリコーン系樹脂を用いる。ポリジメチルシロキサン(PDMS)やPDMS−メチルHシロキサン共重合体、H末端ポリジメチルシロキサン等を好ましく使用できる。これらは既存のマイクロコンタクトプリンティング技術では通常使われている樹脂である。シリコーン樹脂は通常の炭素骨格C−C結合(イオン結合性はほぼ0%)をもつゴムではなくSi−O結合を主鎖に持ち、このSi−O結合ではイオン結合性がほぼ50%と大きいために、Siに結合した側鎖の熱運動性が上がり、隣接する他の物質を近づきにくくしているためインク等の離型性がより良くなっている。
[Stamp plating inhibitor carrying part]
[Material for plating inhibitor carrying part]
Silicone resin is used as the material of the plating inhibiting substance supporting portion 1 of the stamp 3. Polydimethylsiloxane (PDMS), PDMS-methyl H siloxane copolymer, H-terminal polydimethyl siloxane and the like can be preferably used. These are resins usually used in existing microcontact printing technology. Silicone resin is not a rubber having a normal carbon skeleton C—C bond (the ionic bond is approximately 0%) but has a Si—O bond in the main chain, and this Si—O bond has a large ionic bond of approximately 50%. For this reason, the thermal mobility of the side chain bonded to Si is increased, and other adjacent substances are hardly approached, so that the releasability of ink or the like is improved.

また、めっき抑制物質担持部1としては平坦度の高いものであれば、前記シリコーン樹脂以外の樹脂や、金属、ガラス、セラミック等の無機化合物でもよい。平坦度は被転写物である基板の最表面の表面粗さやうねりよりも高度な平坦度であることが望ましい。またインク4を塗布したときにめっき抑制物質担持部1が膨潤して平坦度を損うことのない材料であることが望ましい。   Moreover, as long as the plating suppression substance carrying | support part 1 is a thing with high flatness, inorganic compounds, such as resin other than the said silicone resin, a metal, glass, a ceramic, may be sufficient. The flatness is preferably higher than the surface roughness and waviness of the outermost surface of the substrate that is the transfer object. In addition, it is desirable that the material is such that when the ink 4 is applied, the plating-suppressing substance-carrying portion 1 does not swell and impair the flatness.

また、めっき抑制物質担持部1の材料の硬度は、被転写物表面に意図的に形成された凹凸がある場合、例えば半導体ウエハのようにインクを転写しない部分、即ちトレンチやコンタクトホール等の凹部が加工形成されている場合には、その凹部にスタンプ1が潜り込むほど軟らかいものは望ましくない。   In addition, the hardness of the material of the plating inhibitor carrying part 1 is such that when there is unevenness intentionally formed on the surface of the transfer object, for example, a portion where ink is not transferred, such as a semiconductor wafer, that is, a recess such as a trench or a contact hole Is processed and formed, it is not desirable that the stamp 1 is so soft that the stamp 1 enters the recess.

また、めっき抑制物質担持部1が非導電性又は非磁性の場合は、導電性材料{金属類(金属粒子、金属ファイバー、金属フレーク)、カーボン類(カーボンナノチューブ、カーボンワイヤー、カーボンコイル、カーボン粒子)、有機導電性物質}や磁性材料をめっき抑制物質担持部1の材料に混入し電界・磁界による転写工程を制御するようにすることもできる。また、非導電性である場合はその非導電性を積極的に利用して静電的に転写工程を制御するも可能である。   In addition, when the plating inhibitor supporting part 1 is non-conductive or non-magnetic, conductive materials {metals (metal particles, metal fibers, metal flakes), carbons (carbon nanotubes, carbon wires, carbon coils, carbon particles) ), An organic conductive substance} or a magnetic material can be mixed in the material of the plating inhibitor carrying part 1 to control the transfer process using an electric field / magnetic field. Further, in the case of non-conductivity, the transfer process can be electrostatically controlled by positively utilizing the non-conductivity.

〔スタンプのめっき抑制物質担持部の製造方法〕
めっき抑制物質担持部1の製造方法は、被転写物の表面粗さ、即ち銅シード層及びバリア層12の表面等の被転写面の表面粗さやうねりよりも高度な平坦度の面(通常は鏡面)を備えためっき抑制物質担持部成形用の型(めっき抑制物質担持部1を鋳物に例えれば鋳型に相当するもの)にめっき抑制物質担持部1の材料、例えばPDMSを液体状態で塗布する。次に温室又は高温で又は必要に応じて硬化剤を用いて硬化させて離型することで鏡面状態をめっき抑制物質担持部1に持たせる。
[Manufacturing Method of Stamping Plating Suppressing Substance Carrier]
The method for producing the plating inhibitor carrying part 1 is a surface having a higher degree of flatness than the surface roughness of the transfer object, that is, the surface roughness or waviness of the transfer surface such as the surface of the copper seed layer and the barrier layer 12 (normally The material of the plating inhibitor supporting part 1, for example, PDMS, is applied in a liquid state to a mold for forming a plating inhibitor supporting part having a mirror surface (which corresponds to a mold if the plating inhibitor supporting part 1 is a casting). . Next, it is cured using a curing agent at a greenhouse or at a high temperature or if necessary, to release the mirror surface, so that the plating-suppressing substance-carrying part 1 has a mirror surface state.

また、一旦シリコーン樹脂等のめっき抑制物質担持部1の材料を硬化させた後に研磨等により表面を鏡面に仕上げることもできる。転写作業を行うときにめっき抑制物質担持部1が軟弱で機械的強度が十分でない場合には、めっき抑制物質担持部1の下地に補強用の支持体2を備えるのが好ましい。このとき支持体2にプライマーを塗布してから液体状態にあるめっき抑制物質担持部1の材料と接触させた上でめっき抑制物質担持部1の材料を硬化させる。このことにより支持体2とめっき抑制物質担持部1である例えばシリコーン樹脂とが、しっかりと接着してスタンプ3として好ましく用いることができる。   In addition, after the material of the plating inhibitor carrying part 1 such as a silicone resin is once cured, the surface can be finished to a mirror surface by polishing or the like. When the plating inhibitor carrying part 1 is soft and the mechanical strength is not sufficient when performing the transfer operation, it is preferable to provide a support 2 for reinforcement on the base of the plating inhibitor carrying part 1. At this time, the primer is applied to the support 2 and then brought into contact with the material of the plating inhibitor carrying part 1 in a liquid state, and then the material of the plating inhibitor carrying part 1 is cured. As a result, the support 2 and, for example, a silicone resin, which is the plating-suppressing substance-carrying part 1, can be preferably used as the stamp 3 by firmly bonding.

なお、上記は平坦なめっき抑制物質担持部1の構成材料及び製造方法等について説明したが、図5に示すローラー状(円柱状)のめっき抑制物質担持部5の場合でも略同様である。   In addition, although the above demonstrated the structural material, manufacturing method, etc. of the flat plating inhibitory substance support part 1, it is substantially the same also in the case of the roller-shaped (columnar-shaped) plating inhibitory substance support part 5 shown in FIG.

〔インク〕
基板10に形成された前記シード層及びバリア層12にインク4を接着させる方法として、吸着(化学吸着、物理吸着等)や化学結合、表面凹凸を利用した投錨(アンカー)効果、融着、静電吸着等がある。上述の通りインク4は成膜、特にめっき抑制機能を果たす膜を形成する必要があるので、シード層及びバリア層12に対して適度な接着力を有する必要があるが、後の工程である電解めっきの電解方向とは逆方向に電解をかける工程において完全に除去される程度の接着力でなければならない。また、被転写物であるシード層及びバリア層12に転写されたインク4の厚みは、配線部の配線溝等のアスペクト比が2倍以下の値に抑えられる厚みであることが好ましい。即ちインク4を転写する前の配線溝等の深さ(基板の最表面から当該配線溝等の底面までの距離)の値以下にインク4の厚さを抑えることが好ましい。そして、その厚さは10Å乃至1μm程度となる。
〔ink〕
As a method for adhering the ink 4 to the seed layer and the barrier layer 12 formed on the substrate 10, adsorption (chemical adsorption, physical adsorption, etc.), chemical bonding, anchoring effect utilizing surface irregularities, fusion, static There are electroadsorption. As described above, the ink 4 needs to have a proper adhesion to the seed layer and the barrier layer 12 because it is necessary to form a film, particularly a film that performs a plating suppression function. The adhesive strength must be such that it can be completely removed in the process of electrolysis in the direction opposite to the electrolysis direction of the plating. In addition, the thickness of the ink 4 transferred to the seed layer and the barrier layer 12 as the transfer target is preferably such that the aspect ratio of the wiring groove or the like of the wiring portion is suppressed to a value of 2 times or less. That is, it is preferable to suppress the thickness of the ink 4 to a value equal to or less than the depth of the wiring groove before transferring the ink 4 (distance from the top surface of the substrate to the bottom surface of the wiring groove). The thickness is about 10 to 1 μm.

インク4を吸着・化学結合する場合、インクの被転写物であるシード層及びバリア層12との接着力については、電子を受容する酸である金属や陽イオンと電子を供与する塩基である陰イオンや分子との結合の安定性を判断するHSAB(Hard and Soft Acids and Bases)則により知ることが出来るから、インク4として適切な物質を選択することができる。   When the ink 4 is adsorbed and chemically bonded, the adhesion force between the seed layer and the barrier layer 12 that is the transferred object of the ink is a metal that is an acid that accepts electrons or a negative ion that is a base that donates electrons and cations. Since it can be known by the HSAB (Hard and Soft Acids and Bases) rule for determining the stability of the bond with ions and molecules, an appropriate substance can be selected as the ink 4.

被転写物である基板10のシード層及びバリア層12の材質が銅や銅合金、チタン、チタン合金、タンタル、タンタル合金、ルテニウム、ルテニウム合金の場合にはRSH、R2S、RS-、I-、SCN-、S2o3 2-、R3P、R3As、(RO)3P、CN-、RCN-、CO、C24、C66等(Rはアルカリ基又はアリール基)の化学構造を分子の末端に持つ、例えば下記のものがインク4に適した物質として挙げられる。 When the material of the seed layer and the barrier layer 12 of the substrate 10 to be transferred is copper, copper alloy, titanium, titanium alloy, tantalum, tantalum alloy, ruthenium, ruthenium alloy, RSH, R2S, RS , I , SCN , S 2 o 3 2− , R 3 P, R 3 As, (RO) 3 P, CN , RCN , CO, C 2 H 4 , C 6 H 6 and the like (R is an alkali group or an aryl group The following are examples of substances suitable for the ink 4.

アルカンチオール、ベンゾトリアゾール、カゼイン、デキストリン、ジメチルアミノ誘導体、1,8−ジスルホン酸、エチレンオキシド、ゼラチン、グリュー(のり)、ラクトースベンゾイルヒドラゾーン、モラセス(糖蜜)、石油スルホン酸、o−フェナントロリン、ポリエトキシエーテル(ポリエチレングリコール)、ポリエチレンイミン、ポリN,N’−ジエチルサフラニン、ポリプロピレンエーテル、プロピレンオキシド、砂糖、チオ尿素、ポリアルキレングリコール、動物性グリュー、エーテル基を含むポリマー、アミノ酸の高タンパク質ポリマー、ポリアルキレングリコール、ポリエチレンオキシド、ヒドロキノンまたはエトキシ化アルキルフェノール、ポリエチレンオキシド、グリコール、アミン、アルコキシル化ラクタムアミド、二置換エタンスルホン酸、尿素およびグリセリン、尿素、ラウリルスルホン酸ナトリウム、トシルまたはメシルスホン酸、フェナジン染料、ポリエーテル界面活性剤+ベンゼンスルホン酸+グレイン改良剤、ポリエーテル+メルカプトイミダゾール+ベンゼンスルホン酸、ポリエーテル+有機二価硫黄化合物+三級アルキルアミン+ポリエピクロロヒドリン、スルファミン酸、アルキル化ポリアルキレインイミン、ω−スルホ−n−プロピル−N、N−ジエチルジチオカルバミン酸塩+ポリエチレングリコール+クリスタルバイオレット、フタロシアニン+三級アルキルアミン+ポリエピクロロヒドリン+ベンゼンスルホン酸、ポリエーテル+メルカプトイミンダゾール+ベンゼンスルホン酸、フェノールフタレイン、置換フタロシアニンラジカル、レギュラーコーヒー、アルキル化ポリアルキレインイミン、ジスルフィド、スルホン酸、脂肪族アルデヒド、ジまたはトリアミノトリフェニルメタン染料とスルホアルキルスルフィド、尿素、ポリエーテル、ポリスルフィド、ヘテロ環式硫黄およびポリエーテル化合物、ポリエチレンイミン、ポリエチレングリコール、ホルムアルデヒドおよびチオ尿素、エチレンオキシド生成物と2−メルカプトピリジン、ポリスルフィド、チオ尿素およびポリエーテル、ポリエーテル類、フェナゾニウム高分子化合物、タンニン(酸)、銅と配位結合する各種錯化剤。   Alkanethiol, benzotriazole, casein, dextrin, dimethylamino derivative, 1,8-disulfonic acid, ethylene oxide, gelatin, mulberry, lactose benzoyl hydrazone, molasses, petroleum sulfonic acid, o-phenanthroline, polyethoxy Ether (polyethylene glycol), polyethyleneimine, poly N, N'-diethylsafranine, polypropylene ether, propylene oxide, sugar, thiourea, polyalkylene glycol, animal mulberry, polymers containing ether groups, high protein polymers of amino acids, poly Alkylene glycol, polyethylene oxide, hydroquinone or ethoxylated alkylphenol, polyethylene oxide, glycol, amine, alkoxylated lactam , Disubstituted ethanesulfonic acid, urea and glycerin, urea, sodium lauryl sulfonate, tosyl or mesyl sulfonic acid, phenazine dye, polyether surfactant + benzene sulfonic acid + grain improver, polyether + mercaptoimidazole + benzene sulfonic acid , Polyether + organic divalent sulfur compound + tertiary alkylamine + polyepichlorohydrin, sulfamic acid, alkylated polyalkyleneimine, ω-sulfo-n-propyl-N, N-diethyldithiocarbamate + polyethylene glycol + Crystal violet, phthalocyanine + tertiary alkylamine + polyepichlorohydrin + benzene sulfonic acid, polyether + mercaptoimindazole + benzene sulfonic acid, phenolphthalein, substituted phthalocyanine radicals, Regular coffee, alkylated polyalkyleneimine, disulfide, sulfonic acid, aliphatic aldehyde, di- or triaminotriphenylmethane dye and sulfoalkyl sulfide, urea, polyether, polysulfide, heterocyclic sulfur and polyether compounds, polyethyleneimine , Polyethylene glycol, formaldehyde and thiourea, ethylene oxide product and 2-mercaptopyridine, polysulfide, thiourea and polyether, polyethers, phenazonium polymer, tannin (acid), various complexing agents that coordinate with copper .

インク4としては、これら溶質が液体の場合はそのまま使用されることもあるが、固体の場合を含め一般的には溶剤へ溶かして使用される。溶解度パラメーターや混合性を考慮して溶解可能な溶媒(溶剤)で溶解させて濃度を調整する。   The ink 4 may be used as it is when these solutes are liquid, but is generally used after being dissolved in a solvent, including the case where it is solid. In consideration of solubility parameters and mixing properties, the concentration is adjusted by dissolving in a solvent that can be dissolved (solvent).

被転写面の材質即ち基板10の最表面の材質が銅や銅合金、チタン、チタン合金、タンタル、タンタル合金、ルテニウム、ルテニウム合金であるとき、インク4を基板10へ投錨効果により接着させる場合には、既存のフォトレジスト等の高分子化合物をインク4として用いることができる。   When the material of the transfer surface, that is, the material of the outermost surface of the substrate 10 is copper, copper alloy, titanium, titanium alloy, tantalum, tantalum alloy, ruthenium, or ruthenium alloy, the ink 4 is adhered to the substrate 10 by the throwing effect. Can use an existing high molecular compound such as a photoresist as the ink 4.

また、同様に融着による接着にはインク4及びその溶媒に代えて低融点金属を用いることができる。   Similarly, a low-melting-point metal can be used in place of the ink 4 and its solvent for adhesion by fusing.

また、静電吸着による接着の場合には複素誘電率の異なる溶媒とインク4の働きをする微粒子を含む溶液を用いることもできる。これは溶媒を蒸発させない状態でスタンプ3(又はスタンプ6)のめっき抑制物質担持部1(又はめっき抑制物質担持部5)と被転写物(シード層及びバリア層12)との間に直流や交流の電圧を印加して生じる電気泳動や誘電泳動を利用して微粒子をインク4として被転写物上へ固定するものである。微粒子としては金属や非金属の酸化物粒子や高分子化合物の微粒子を用いることができる。   In the case of adhesion by electrostatic adsorption, a solution containing a solvent having a different complex dielectric constant and fine particles functioning as the ink 4 can be used. This is because direct current or alternating current is present between the plating suppression substance supporting part 1 (or the plating suppression substance supporting part 5) of the stamp 3 (or stamp 6) and the transfer target (seed layer and barrier layer 12) in a state where the solvent is not evaporated. Electrophoresis or dielectrophoresis generated by applying the above voltage is used to fix the fine particles as ink 4 on the transfer object. As the fine particles, metal or non-metallic oxide particles or polymer compound fine particles can be used.

〔スタンプのめっき抑制物質担持部へのインクの塗布方法〕
前記各種インク4は、通常の場合はインク4が溶媒に溶解された状態でスタンプ3(又はスタンプ6)に塗布される。スタンプ上へ塗布するために各種塗工装置を用いることができる。例えば、正回転ロールコーター、リバースロールコーター、グラビアコーター、ナイフコーター、ブレードコーター、ロッドコーター、エアドクターコーター、カーテンコーター、ファウンテンコーター、キスコーター、スピンコーター、スプレーコーター、含浸機、押出しコーター、浸漬塗工機、スクリーン印刷機、キャスト塗工機、真空塗工機、LB法を用いた塗工機等がある。
[Method of applying ink to stamping plating inhibitor carrying part]
The various inks 4 are normally applied to the stamp 3 (or the stamp 6) in a state where the ink 4 is dissolved in a solvent. Various coating devices can be used for coating on the stamp. For example, forward rotation roll coater, reverse roll coater, gravure coater, knife coater, blade coater, rod coater, air doctor coater, curtain coater, fountain coater, kiss coater, spin coater, spray coater, impregnation machine, extrusion coater, dip coating Machine, screen printing machine, cast coating machine, vacuum coating machine, coating machine using LB method, and the like.

〔スタンプのめっき抑制物質担持部から被転写物への転写及び接着(固着)方法〕
ここでインク4がめっき抑制物質担持部1(又はめっき抑制物質担持部5)から被転写物(被転写面)へ転写される状況と、インク4が被転写面に固着(接着)する状況について説明する。通常は溶媒に溶解された溶液の状態でスタンプ3(又はスタンプ6)のめっき抑制物質担持部1(又はめっき抑制物質担持部5)に塗布されたインク4は、一般に被転写面に対して当該めっき抑制物質担持部1(又はめっき抑制物質担持部5)を押し付けることによって被転写面側に転写される。このときスタンプ3(又はスタンプ6)には例えばプレス機構等によって押し付け力を与える。この押し付け力は被転写面とめっき抑制物質担持部1(又はめっき抑制物質担持部5)との間に作用する圧力が適切な値となるように制御されるのが好ましい。また押し付け時間も適切な時間であることが好ましい。
[Method of transferring and adhering (fixing) the stamp from the plating-suppressing substance-bearing part to the transfer object]
Here, the situation in which the ink 4 is transferred from the plating suppression substance carrying portion 1 (or the plating inhibition substance carrying portion 5) to the transfer target (transfer target surface) and the situation in which the ink 4 is fixed (adhered) to the transfer target surface. explain. In general, the ink 4 applied to the plating inhibiting substance carrying part 1 (or the plating inhibiting substance carrying part 5) of the stamp 3 (or stamp 6) in the state of a solution dissolved in a solvent is generally applied to the surface to be transferred. By being pressed against the plating inhibiting substance carrying part 1 (or the plating inhibiting substance carrying part 5), it is transferred to the transfer surface side. At this time, a pressing force is applied to the stamp 3 (or the stamp 6) by, for example, a press mechanism. This pressing force is preferably controlled so that the pressure acting between the transferred surface and the plating suppression substance carrying part 1 (or the plating suppression substance carrying part 5) becomes an appropriate value. The pressing time is preferably an appropriate time.

次にインク4が被転写面に接着する状況について述べる。一般に被転写面へは前述のようにインクを溶質として、溶質を溶かし込んでいる溶媒(溶剤)が媒体となって転写される。転写された後、溶媒(溶剤)が揮発することによって被転写物へのインクの接着がなされるため、被転写面である基板の最表面の銅シード層及びバリア層12の表面に転写された時点においては、未だ溶媒が存在している状態なので溶媒を揮発・蒸発させるように接着(転写)現場環境の温度・湿度等の調整が必要である。   Next, the situation where the ink 4 adheres to the transfer surface will be described. Generally, ink is used as a solute as described above, and a solvent (solvent) in which the solute is dissolved is transferred onto the transfer surface as a medium. After the transfer, the ink adheres to the transfer object by volatilization of the solvent (solvent). Therefore, the ink is transferred to the surface of the copper seed layer and the barrier layer 12 on the outermost surface of the substrate as the transfer surface. At the time, since the solvent is still present, it is necessary to adjust the temperature / humidity of the adhesion (transfer) site environment so that the solvent is volatilized and evaporated.

〔めっき抑制物質の除去方法〕
基板10の凹部11を加工形成した側の最表面に付着させたインク4を除去(離脱)させるには下記(1)乃至(5)に示す方法がある。
[Plating inhibitor removal method]
In order to remove (separate) the ink 4 adhered to the outermost surface of the substrate 10 on which the concave portion 11 is formed, there are methods shown in the following (1) to (5).

(1)電解めっきにより凹部11に埋め込まれた銅の上面がめっきを抑制する物質を付着させた基板の最表面と同一面に達した時点で電解めっきとは逆方向に電界をかけ、めっきを抑制する物質を基板の最表面から離脱させる方法。(なお前記「めっきを抑制する物質を付着させた基板の最表面」とは言うまでも無く基板の最表面に形成されたシード層及びバリア層12が形成する面を指すのであって、基板の最表面に付着させためっき抑制物質が形成する面のことではない。このことについては本発明全体(本明細書全体)について同趣旨である。)   (1) When the upper surface of the copper embedded in the recess 11 by electrolytic plating reaches the same surface as the outermost surface of the substrate to which a substance that suppresses plating is applied, an electric field is applied in the opposite direction to the electrolytic plating, and plating is performed. A method in which the substance to be suppressed is released from the outermost surface of the substrate. (It should be noted that the “outermost surface of the substrate on which a substance that suppresses plating is attached” refers to the surface on which the seed layer and the barrier layer 12 formed on the outermost surface of the substrate are formed. (This is not the surface formed by the plating-suppressing substance attached to the outermost surface, which is the same for the entire present invention (the entire present specification).)

(2)電解めっきにより凹部11に埋め込まれた銅の上面がめっきを抑制する物質を付着させた基板の最表面と同一面に達した時点で基板に傷を付けない物性を持った弾性体、例えばゴム、ポリウレタン、アクリル樹脂等の不織布、パッドによりめっきを抑制する物質をめっき液中またはめっき液外において基板最表面から離脱させる方法。   (2) An elastic body having physical properties that does not damage the substrate when the upper surface of the copper embedded in the recess 11 by electrolytic plating reaches the same surface as the outermost surface of the substrate on which a substance that suppresses plating is adhered; For example, a non-woven fabric such as rubber, polyurethane, acrylic resin, or the like, and a method of releasing a substance that suppresses plating with a pad from the outermost surface of the substrate in or outside the plating solution.

(3)電解めっきにより凹部11に埋め込まれた銅の上面がめっきを抑制する物質を付着させた基板の最表面と同一面に達した時点でめっきを抑制する物質を溶解する有機系溶媒や酸、アルカリ等の水溶液によりめっき液外において浸漬させて離脱させる方法。   (3) An organic solvent or acid that dissolves the substance that suppresses plating when the upper surface of the copper embedded in the recess 11 by electrolytic plating reaches the same surface as the outermost surface of the substrate to which the substance that suppresses plating is attached. A method of detaching by immersing outside the plating solution with an aqueous solution of alkali or the like.

(4)電解めっきにより凹部11に埋め込まれた銅の上面がめっきを抑制する物質を付着させた基板の最表面と同一面に達した時点でめっき液中またはめっき液外において基板の最表面を超音波振動子を用いて液を振動させ、めっきを抑制する物質を離脱させる方法。   (4) When the upper surface of the copper embedded in the recess 11 by electrolytic plating reaches the same surface as the outermost surface of the substrate to which a substance that suppresses plating is adhered, the outermost surface of the substrate is exposed in the plating solution or outside the plating solution. A method of detaching substances that suppress plating by vibrating the liquid using an ultrasonic vibrator.

(5)電解めっきにより凹部11に埋め込まれた銅の上面がめっきを抑制する物質を付着させた基板の最表面と同一面に達した時点でめっき液中またはめっき液外において基板の最表面にノズル等により水圧を印加して、めっきを抑制する物質を離脱させる方法。   (5) When the upper surface of the copper embedded in the recess 11 by electrolytic plating reaches the same surface as the outermost surface of the substrate to which a substance that suppresses plating is adhered, the uppermost surface of the substrate in the plating solution or outside the plating solution A method of removing a substance that suppresses plating by applying water pressure with a nozzle or the like.

先ず本発明による基板配線形成を行うについて電解銅めっき工程を中心とした一実施例を説明する。図6は本発明に係る基板配線形成装置の構成例を示す図である。本基板配線形成装置20は電解めっき装置であり、めっき液(硫酸銅めっき)Qを収容するめっき槽21を具備する。めっき槽21内には基板ホルダ22に保持された基板10とアノードホルダ23に保持されたアノード24が対向して配置されている。めっき槽21の外側にはオーバーフロー槽26が配置され、めっき槽21の溢流堰25をオーバーフローしためっき液が該オーバーフロー槽26に流入するようになっている。   First, an embodiment of the present invention for forming a substrate wiring will be described with a focus on an electrolytic copper plating process. FIG. 6 is a diagram showing a configuration example of the substrate wiring forming apparatus according to the present invention. This board | substrate wiring formation apparatus 20 is an electroplating apparatus, and comprises the plating tank 21 in which the plating solution (copper sulfate plating) Q is accommodated. In the plating tank 21, the substrate 10 held by the substrate holder 22 and the anode 24 held by the anode holder 23 are arranged to face each other. An overflow tank 26 is disposed outside the plating tank 21, and the plating solution overflowing the overflow weir 25 of the plating tank 21 flows into the overflow tank 26.

オーバーフロー槽26に流入しためっき液Qはポンプ28により、循環配管27に設けられた恒温ユニット29、フィルタ30を通って、めっき槽21内に供給され、循環するようになっている。即ち、オーバーフロー槽26内のめっき液Qは恒温ユニット29でその温度が所定の温度に調整され、フィルタ30で汚染物が除去され、めっき槽21内に供給される。32は切替え手段(切替えスイッチ等)であり、切替え手段32が接点a、aに接触しているときはめっき電源(直流電源)31の陰極が基板10に陽極がアノード24に接続され、基板10に陰極、アノード24に陽極が印加されるようになっている。また、切替え手段32が接点b、bに接触しているときはめっき電源31の陽極が基板10に陰極がアノード24に接続され、基板10に陽極、アノード24に陰極が印加されるようになっている。   The plating solution Q flowing into the overflow tank 26 is supplied by the pump 28 through the constant temperature unit 29 and the filter 30 provided in the circulation pipe 27 into the plating tank 21 and circulates. That is, the temperature of the plating solution Q in the overflow tank 26 is adjusted to a predetermined temperature by the constant temperature unit 29, contaminants are removed by the filter 30, and supplied to the plating tank 21. Reference numeral 32 denotes a switching means (a changeover switch or the like). When the switching means 32 is in contact with the contacts a and a, the cathode of the plating power supply (DC power supply) 31 is connected to the substrate 10 and the anode is connected to the anode 24. The cathode is applied to the anode, and the anode is applied to the anode 24. When the switching means 32 is in contact with the contacts b and b, the anode of the plating power source 31 is connected to the substrate 10 and the cathode is connected to the anode 24, and the anode is applied to the substrate 10 and the cathode is applied to the anode 24. ing.

上記構成の基板配線形成装置20に用いる、本発明に係る基板配線形成方法例を図7に基づいて説明する。図7は主に本発明によるめっき工程における基板のめっき進行状況を示している。図7(a)に示すように、基板10のトレンチやコンタクトホール等の凹部11が加工形成された側のシード層及びバリア層12の凹部11の内表面を除く基板10の表面即ち基板10の最表面にインク4を付着させた基板10を、そのインク4を付着させた面がアノード24に対向するように基板ホルダ22に保持させる。その後、切替え手段32が接点a、aに接触させることにより、めっき電源31から基板10に陰極、アノード24に陽極を印加し、電解めっきを開始する。これにより基板10の凹部11内に銅13が堆積する。この凹部11内に堆積する銅13の上面13aが図7(b)に示すように、インク4が付着しているシード層及びバリア層12の上面12aと一致したら、切替え手段32を接点a、aから離間させ、電解めっきを停止する。   An example of a substrate wiring forming method according to the present invention used in the substrate wiring forming apparatus 20 having the above configuration will be described with reference to FIG. FIG. 7 mainly shows the progress of the plating of the substrate in the plating process according to the present invention. As shown in FIG. 7A, the surface of the substrate 10, that is, the surface of the substrate 10 excluding the seed layer on the side where the recesses 11 such as the trenches and contact holes of the substrate 10 are processed and the inner surface of the recesses 11 of the barrier layer 12 is formed. The substrate 10 with the ink 4 attached to the outermost surface is held by the substrate holder 22 so that the surface with the ink 4 attached faces the anode 24. Thereafter, when the switching means 32 is brought into contact with the contacts a and a, the cathode is applied to the substrate 10 and the anode is applied to the anode 24 from the plating power source 31, and the electrolytic plating is started. As a result, copper 13 is deposited in the recess 11 of the substrate 10. When the upper surface 13a of the copper 13 deposited in the recess 11 coincides with the seed layer to which the ink 4 is adhered and the upper surface 12a of the barrier layer 12 as shown in FIG. The electroplating is stopped after separating from a.

その後、切替え手段32を接点b、bにて接触させて、めっき電源31から基板10に陽極、アノード24に陰極を印加し、電解めっき時とは逆方向の電解を所定時間かける。これにより、図7(c)に示すようにシード層及びバリア層12に付着しているインク4が除去され、銅13の上面13aとシード層及びバリア層12の上面12aが一致した状態で現れる。次にこの状態で、切替え手段32を接点a、aにて接触させ、所定時間電解めっきを行うことにより、基板10の凹部11が加工形成された側の全面に平坦な銅13の堆積層が形成される(図7(d)参照)。図7において、51は基板10の最表面、52は凹部内表面、53は本発明によるめっき工程終了時に得られる平坦なめっき表面、即ちめっき工程終了時表面を指す。   Thereafter, the switching means 32 is brought into contact at the contacts b and b, an anode is applied to the substrate 10 from the plating power source 31 and a cathode is applied to the anode 24, and electrolysis in the direction opposite to that during electrolytic plating is applied for a predetermined time. As a result, the ink 4 attached to the seed layer and the barrier layer 12 is removed as shown in FIG. 7C, and the upper surface 13a of the copper 13 and the upper surface 12a of the seed layer and the barrier layer 12 appear to coincide with each other. . Next, in this state, the switching means 32 is brought into contact with the contacts a and a and electrolytic plating is performed for a predetermined time, whereby a flat deposited layer of copper 13 is formed on the entire surface of the substrate 10 on the side where the recess 11 is formed. It is formed (see FIG. 7D). In FIG. 7, 51 indicates the outermost surface of the substrate 10, 52 indicates the inner surface of the recess, and 53 indicates the flat plating surface obtained at the end of the plating process according to the present invention, that is, the surface at the end of the plating process.

上記のように、凹部11が加工形成された側の全面に平坦な銅13の堆積層が形成された基板10を上記めっき工程の、後工程で熱処理することにより、再結晶や歪の緩和を十分に行えるから、配線の断線等の不具合発生を抑止できる。また、銅13の堆積層の厚さを適正な値に制御することにより、CMP工程に要する時間を妥当な値に抑えることが出来る。こうして基板10全体の平坦化を実現できると共に余剰な銅13の堆積層を除去でき、且つディッシング104やエロージョン105(図1(b)参照)さらには銅層、バリア層、絶縁層相互間の剥離などの不具合を生じにくいので、CMPを好適に行うことができる。   As described above, the substrate 10 on which the flat deposited layer of copper 13 is formed on the entire surface on which the concave portion 11 is formed is heat-treated in a subsequent step of the plating step, thereby reducing recrystallization and strain. Since it can be performed sufficiently, it is possible to suppress the occurrence of problems such as disconnection of wiring. Further, by controlling the thickness of the deposited layer of copper 13 to an appropriate value, the time required for the CMP process can be suppressed to an appropriate value. Thus, planarization of the entire substrate 10 can be realized, and an excess deposited layer of the copper 13 can be removed, and the dishing 104, the erosion 105 (see FIG. 1B), and the peeling between the copper layer, the barrier layer, and the insulating layer can be performed. Therefore, CMP can be suitably performed.

次に本発明による基板配線形成方法やめっき抑制物質転写スタンプなどを用いて、半導体ウエーハに電解銅めっきによって銅めっき膜を形成した実施例を示す。スタンプにはシリコーンゴムとして、ダウコーニング社製二液常温硬化型シリコーンゴム(商品名;シルポット184W/C)を用いる。   Next, an embodiment in which a copper plating film is formed on a semiconductor wafer by electrolytic copper plating using a substrate wiring forming method or a plating inhibitor transfer stamp according to the present invention will be described. For the stamp, a two-component room temperature curing type silicone rubber (trade name; Sylpot 184W / C) manufactured by Dow Corning is used as the silicone rubber.

スタンプ1の支持体2には、SiO2酸化膜付き8インチSiウェーハ(第1のウエーハ)を用いる。このウェーハをUVオゾン洗浄により洗浄し、鏡面側にプライマー(FSXA−2869;ダウコーニング社)を塗布する。続いて前述のシルポット184W/Cを混合・減圧脱泡して、前述の第1のウェーハ上に滴下する。この上に別途の酸化膜付き8インチウェーハ(第2のウェーハ)をプライマーを用いずに鏡面側が前記シリコーンゴム(シルポット184W/C)に接するように向けて被せて室温で約1日または恒温槽で一定時間(例えば150℃で約1時間)放置してシリコーンゴムを硬化させる。   For the support 2 of the stamp 1, an 8-inch Si wafer (first wafer) with a SiO2 oxide film is used. This wafer is cleaned by UV ozone cleaning, and a primer (FSXA-2869; Dow Corning) is applied to the mirror surface side. Subsequently, the above-mentioned sylpot 184 W / C is mixed and degassed under reduced pressure, and dropped onto the above-described first wafer. An 8-inch wafer (second wafer) with a separate oxide film is placed on this so that the mirror side is in contact with the silicone rubber (Sylpot 184W / C) without using a primer, and is kept for about one day at room temperature or a constant temperature bath. The silicone rubber is cured by allowing it to stand for a certain time (for example, about 1 hour at 150 ° C).

上記硬化後、プライマ−の付いていない上記別途の酸化膜付き8インチウェーハ(第2のウエーハ)をシリコーンゴムから剥がし、シリコーンゴムが一定の膜厚で付いているウェーハ(第1のウエーハ)をスタンプとして用いる。   After the curing, the separate 8-inch wafer with oxide film (second wafer) without the primer is peeled off from the silicone rubber, and the wafer with the silicon rubber having a certain thickness (first wafer) is removed. Used as a stamp.

上記スタンプのめっき抑制物質担持部即ち、シリコーンゴム表面は適宜インクの溶媒として用いた溶剤と同種の溶剤を用いて洗浄するが、初期状態で使用する場合にはUVオゾン洗浄のみでよい。   The plating-suppressing substance-carrying portion of the stamp, that is, the silicone rubber surface is appropriately cleaned using the same solvent as the solvent used for the ink, but when used in the initial state, only UV ozone cleaning is required.

めっき抑制物質即ちインク(溶質)としてオクタデシルトリクロロシランを溶媒であるヘキサンやトルエンに約0.1〜50mmol/l(ミリモル・パー・リットル)混合した溶液や、インクとしてアルカンチオールCn2n+1SH(n=8、n=10)を溶媒であるアルコール類(エチルアルコール、イソプロピルアルコール、ブチルアルコール)に約0.1〜50mmol/l(ミリモル・パー・リットル)混合した溶液を用いて被転写面に転写する。なお、アルカンチオールはn数が多いほど金属表面に吸着した後に、アルカンチオールのアルキル鎖同士がファンデルワールス力によりその引力と反発力が釣り合った安定なエネルギー状態となって高密度に吸着しやすくなるからインクとして好ましい。しかし、n数が多いと溶媒中への溶解度が下がるためnの数は8〜10が好ましい。 As a plating inhibitor, that is, a solution in which octadecyltrichlorosilane is mixed with hexane or toluene as a solvent as an ink (solute) in an amount of about 0.1 to 50 mmol / l (mole per liter), or an alkanethiol C n H 2n + 1 as an ink. Using SH (n = 8, n = 10) mixed with alcohol (ethyl alcohol, isopropyl alcohol, butyl alcohol) as a solvent in an amount of about 0.1 to 50 mmol / l (mmole per liter) Transfer to the surface. Alkanethiol adsorbs on the metal surface as the number of n increases, and then the alkanethiol alkyl chains tend to adsorb at high density in a stable energy state in which the attractive force and repulsive force are balanced by van der Waals forces. Therefore, it is preferable as an ink. However, when the number of n is large, the solubility in a solvent is lowered, and therefore the number of n is preferably 8-10.

上記のインクを含んだ溶液を前述のスタンプ表面のめっき抑制物質担持部であるシリコーンゴムへスピンコーターを用いて塗布する。   The solution containing the ink is applied to the silicone rubber, which is a plating inhibitor supporting part on the stamp surface, using a spin coater.

上記スタンプのシリコーンゴムの面を配線溝等の凹部が形成され、銅シード層が成膜された半導体ウエーハのインクを転写すべき面に向けて押し付け、インクが溶解した溶液を転写する。転写するときには、接触時間は3秒間から2分間の範囲で適宜変化させる。そして通常では約1分間以内に硫酸銅めっき液に浸漬して電解銅めっきを開始する。硫酸銅めっきの溶液組成の一例を下記に示す。
CuSO4・H2O 225g/l
2SO4 55g/l
Cl− 60ppm
基板における電流密度として、−5〜−50mA/cm2で、基板の凹部の埋め込みが完了するまでめっきを行う。
A concave portion such as a wiring groove is formed on the surface of the silicone rubber of the stamp, and the semiconductor wafer on which the copper seed layer is formed is pressed against the surface to be transferred to transfer the solution in which the ink is dissolved. When transferring, the contact time is appropriately changed within a range of 3 seconds to 2 minutes. Usually, the electrolytic copper plating is started by dipping in a copper sulfate plating solution within about 1 minute. An example of the solution composition of copper sulfate plating is shown below.
CuSO 4 · H 2 O 225 g / l
H 2 SO 4 55 g / l
Cl-60 ppm
Plating is performed at a current density of −5 to −50 mA / cm 2 on the substrate until filling of the recesses of the substrate is completed.

めっきによりトレンチ内部を金属で埋め込んだ後に逆電解を行う。即ち基板における電流密度を+極側の+5〜+50mA/cm2として、時間としては10ミリ秒から5秒間印加することで被転写物である基板からインクをめっき溶液中へ脱離させる。 Reverse electrolysis is performed after the trench is filled with metal by plating. That is, the current density in the substrate is set to +5 to +50 mA / cm 2 on the positive electrode side, and the time is applied for 10 to 5 seconds to desorb the ink from the substrate to be transferred into the plating solution.

その後、再度前述の条件で電解めっきを行う。以上の一連の工程を行った結果、基板の最表面の上における厚さが数10nmの薄い銅膜を基板の被めっき表面(即ち配線溝等の凹部が形成された側の表面)全面に渡って平坦に成膜することが出来た。   Thereafter, electrolytic plating is again performed under the above-described conditions. As a result of the above series of steps, a thin copper film having a thickness of several tens of nanometers on the outermost surface of the substrate is spread over the entire surface to be plated (that is, the surface on the side where the recesses such as the wiring grooves are formed). It was possible to form a flat film.

以上本発明の実施形態を説明したが、本発明は上記実施形態に限定されるものではなく、特許請求の範囲、及び明細書と図面に記載された技術的思想の範囲内において種々の変形が可能である。   Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the technical idea described in the claims and the specification and drawings. Is possible.

従来のダマシン法による基板配線形成プロセスの途中過程での基板の状態を示す図である。It is a figure which shows the state of the board | substrate in the middle of the board | substrate wiring formation process by the conventional damascene method. 従来のダマシン法による基板配線形成プロセス中の一つの過程での基板の状態を示す図である。It is a figure which shows the state of the board | substrate in one process in the board | substrate wiring formation process by the conventional damascene method. 従来のダマシン法による基板配線形成プロセス中の一つの過程での基板の状態を示す図である。It is a figure which shows the state of the board | substrate in one process in the board | substrate wiring formation process by the conventional damascene method. 本発明に係る基板配線形成プロセスのインク転写プロセスを示す図である。It is a figure which shows the ink transfer process of the board | substrate wiring formation process which concerns on this invention. 本発明に係る基板配線形成プロセスのインク転写プロセスを示す図である。It is a figure which shows the ink transfer process of the board | substrate wiring formation process which concerns on this invention. 本発明に係る基板配線形成装置の構成例を示す図である。It is a figure which shows the structural example of the board | substrate wiring formation apparatus which concerns on this invention. 本発明に係る基板配線形成プロセスを示す図である。It is a figure which shows the board | substrate wiring formation process which concerns on this invention.

符号の説明Explanation of symbols

1 めっき抑制物質担持部
2 支持体
3 スタンプ
4 インク
5 めっき抑制物質担持部
6 スタンプ
7 支持体
10 基板
11 凹部
12 シード層及びバリア層
13 銅
20 基板配線形成装置
21 めっき槽
22 基板ホルダ
23 アノードホルダ
24 アノード
25 溢流堰
26 オーバーフロー槽
27 循環配管
28 ポンプ
29 恒温ユニット
30 フィルタ
31 めっき電源
32 切替え手段
51 基板の最表面
52 凹部内表面
53 めっき工程終了時表面
DESCRIPTION OF SYMBOLS 1 Plating suppression substance carrying part 2 Support body 3 Stamp 4 Ink 5 Plating suppression substance carrying part 6 Stamp 7 Support body 10 Substrate 11 Recess 12 Seed layer and barrier layer 13 Copper 20 Substrate wiring formation device 21 Plating tank 22 Substrate holder 23 Anode holder 24 Anode 25 Overflow weir 26 Overflow tank 27 Circulating piping 28 Pump 29 Constant temperature unit 30 Filter 31 Plating power source 32 Switching means 51 Substrate outer surface 52 Recessed inner surface 53 Surface at end of plating process

Claims (16)

基板に形成された配線溝等の凹部を電解めっきにより金属で埋め込み配線を形成する基板配線形成方法において、
前記基板の凹部内表面を除く該基板の表面にめっきを抑制するめっき抑制物質を付着させるめっき抑制物質付着工程と、その後に電解めっきを行う電解めっき工程とを備えたことを特徴とする基板配線形成方法。
In a substrate wiring forming method for forming a wiring by embedding a recess such as a wiring groove formed on a substrate with a metal by electrolytic plating,
A substrate wiring comprising: a plating suppressing substance attaching step for attaching a plating suppressing substance for suppressing plating to the surface of the substrate excluding the inner surface of the concave portion of the substrate; and an electrolytic plating step for performing electrolytic plating thereafter. Forming method.
請求項1に記載の基板配線形成方法において、
前記電解めっき工程の後に、前記めっき抑制物質を基板の表面から離脱させるめっき抑制物質離脱工程を備えたことを特徴とする基板配線形成方法。
In the board | substrate wiring formation method of Claim 1,
A substrate wiring forming method, comprising: a plating suppression substance detachment step of detaching the plating suppression substance from the surface of the substrate after the electrolytic plating step.
請求項2に記載の基板配線形成方法において、
前記めっき抑制物質離脱工程後に、電解めっきを行う電解めっき工程を備えたことを特徴とする基板配線形成方法。
In the substrate wiring formation method of Claim 2,
A substrate wiring forming method comprising an electroplating step of performing electroplating after the plating inhibitor releasing step.
請求項2又は3に記載の基板配線形成方法において、
前記めっき抑制物質離脱工程は、前記電解めっき方向とは逆に電解をかけることにより行うことを特徴とする基板配線形成方法。
In the board | substrate wiring formation method of Claim 2 or 3,
The method for forming a substrate wiring according to claim 1, wherein the plating inhibiting substance removing step is performed by applying electrolysis in the direction opposite to the electrolytic plating direction.
請求項4に記載の基板配線形成方法において、
前記めっき抑制物質離脱工程の電解めっき方向とは逆に電解をかける時点は、前記電解めっき工程により前記基板の凹部内に埋め込まれた金属の表面と前記めっき抑制物質を付着させた前記基板の表面とが同一面になった時点であることを特徴とする基板配線形成方法。
In the substrate wiring formation method of Claim 4,
The time of applying electrolysis in the direction opposite to the electroplating direction of the plating inhibitor release process is the surface of the substrate embedded in the recess of the substrate by the electrolytic plating process and the surface of the substrate on which the plating inhibitor is adhered. A method for forming a substrate wiring, characterized in that the two are on the same plane.
請求項1乃至5のいずれか1項に記載の基板配線形成方法において、
前記めっき抑制物質付着工程は、スタンプに予め前記めっき抑制物質を担持させた後、該スタンプを前記基板の表面に押し当てることにより、該めっき抑制物質を該基板の表面に転写させることを特徴とする基板配線形成方法。
In the board | substrate wiring formation method of any one of Claims 1 thru | or 5,
The plating inhibiting substance adhering step is characterized in that after the plating inhibiting substance is previously supported on a stamp, the plating inhibiting substance is transferred to the surface of the substrate by pressing the stamp against the surface of the substrate. Substrate wiring forming method.
請求項1乃至6のいずれか1項に記載の基板配線形成方法において、
前記電解めっき工程で前記基板の凹部内を埋め込む金属は、銅、又は銅合金、又は銀であることを特徴とする基板配線形成方法。
In the board | substrate wiring formation method of any one of Claims 1 thru | or 6,
The method of forming a substrate wiring according to claim 1, wherein the metal embedded in the concave portion of the substrate in the electrolytic plating step is copper, a copper alloy, or silver.
請求項1乃至7のいずれか1項に記載の基板配線形成方法において、
前記めっき抑制物質付着工程で前記基板の表面に付着しためっき抑制物質は厚さが一様な膜状態であることを特徴とする基板配線形成方法。
In the board | substrate wiring formation method of any one of Claims 1 thru | or 7,
The method of forming a substrate wiring according to claim 1, wherein the plating inhibitor substance adhered to the surface of the substrate in the plating inhibitor substance attaching step is in a film state having a uniform thickness.
請求項6乃至8のいずれか1項に記載の基板配線形成方法において、
前記スタンプとして前記めっき抑制物質を担持するめっき抑制物質担持部が、シリコーン樹脂又はフッ素樹脂の少なくとも一方を有して構成されたスタンプを用いることを特徴とする基板配線形成方法。
In the board | substrate wiring formation method of any one of Claim 6 thru | or 8,
A method for forming a substrate wiring according to claim 1, wherein the stamping material carrying part carrying the plating inhibiting material as the stamp uses a stamp having at least one of silicone resin or fluororesin.
請求項9に記載の基板配線形成方法において、
前記スタンプとして、めっき抑制物質担持部が支持体により支持されたスタンプを用いることを特徴とする基板配線形成方法。
In the board | substrate wiring formation method of Claim 9,
A substrate wiring forming method, wherein the stamp is a stamp in which a plating suppressing substance supporting portion is supported by a support.
請求項9又は10に記載の基板配線形成方法において、
前記スタンプとして少なくともめっき抑制物質担持部外表面が、平板状又は円柱状に構成されているスタンプを用いることを特徴とする基板配線形成方法。
In the board | substrate wiring formation method of Claim 9 or 10,
A method for forming a substrate wiring according to claim 1, wherein at least the outer surface of the plating-suppressing substance-carrying part is formed in a flat plate shape or a cylindrical shape as the stamp.
めっき液を収容するめっき液槽を備え、該めっき液槽のめっき液中に配線溝等の凹部が形成された基板と陽極電極を配置し、めっき電源より該陽極電極と前記基板との間に所定のめっき電圧を印加し、電解めっきにより該基板の凹部内を金属で埋め込み配線を形成する基板配線形成装置において
前記基板は凹部内表面を除く前記基板の表面にめっきを抑制するめっき抑制物質を付着させた基板であることを特徴とする基板配線形成装置。
A plating solution tank containing a plating solution is provided, and a substrate and an anode electrode having a recess such as a wiring groove formed in the plating solution in the plating solution tank are disposed between the anode electrode and the substrate from a plating power source. In a substrate wiring forming apparatus in which a predetermined plating voltage is applied and a recess is formed with metal by electrolytic plating to form a wiring, the substrate is provided with a plating inhibitor that suppresses plating on the surface of the substrate except the inner surface of the recess. A substrate wiring forming apparatus, which is an attached substrate.
請求項12に記載の基板配線形成装置において、
前記電解めっき中に所定のタイミングで前記陽極電極と前記基板の間に印加する電圧の極性の正負を前記電解めっき時とは前記極性の正負が逆になるように切替えて印加する極性切替手段を備えたことを特徴とする基板配線形成装置。
The board | substrate wiring formation apparatus of Claim 12 WHEREIN:
Polarity switching means for switching the polarity of the voltage applied between the anode electrode and the substrate at a predetermined timing during the electrolytic plating so that the polarity of the polarity is opposite to that during the electrolytic plating. A substrate wiring forming apparatus comprising:
基板に形成された配線溝等の凹部を電解めっきにより金属で埋め込むことにより該基板に配線を形成する際に、
前記基板の凹部内表面を除く該基板の表面にめっきを抑制するめっき抑制物質を転写させるのに用いるめっき抑制物質転写スタンプであって、
前記スタンプの少なくともめっき抑制物質担持部はシリコーン樹脂又はフッ素樹脂の少なくとも一方を有して成ることを特徴とするめっき抑制物質転写スタンプ。
When forming a wiring on the substrate by embedding a recess such as a wiring groove formed on the substrate with metal by electrolytic plating,
A plating inhibitor transfer stamp used to transfer a plating inhibitor that suppresses plating to the surface of the substrate excluding the concave inner surface of the substrate,
The plating inhibitor transfer stamp, wherein at least the plating inhibitor carrying part of the stamp comprises at least one of silicone resin or fluororesin.
請求項14に記載のめっき抑制物質転写スタンプにおいて、
前記スタンプは少なくともめっき抑制物質担持部が支持体に支持された構成であることを特徴とするめっき抑制物質転写スタンプ。
The plating-inhibiting substance transfer stamp according to claim 14,
The stamping material transfer stamp is characterized in that the stamp has a structure in which at least a plating restraining material carrier is supported by a support.
請求項14又は15に記載のめっき抑制物質転写スタンプにおいて、
前記スタンプは少なくともめっき抑制物質担持部外表面が平板状又は円柱状であることを特徴とするめっき抑制物質転写スタンプ。
The plating inhibitor transfer stamp according to claim 14 or 15,
The stamping material transfer stamp characterized in that the stamp has at least an outer surface of the plating restraining material carrying part being flat or cylindrical.
JP2005096511A 2005-03-29 2005-03-29 Method and apparatus for forming substrate wiring, and plating suppressing substance transfer stamp Withdrawn JP2006274369A (en)

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