JP2006270945A - Semiconductor device and electronic apparatus using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has advanced features, multi-functionalized, and enhanced added value. <P>SOLUTION: The semiconductor device is provided the substrate of which has a circuit (a phase locked loop circuit, PLL circuit) which outputs the signal of accurate frequency. A PLL circuit is a circuit which outputs the signal of the frequency with a fixed scale factor based on the signal supplied. The PLL circuit comprises a phase comparator, a loop filter, a voltage controlled oscillator, and a frequency divider. By preparing the PLL circuit on a substrate, advanced features, multi-functionalization, and the enhanced added value are realizable. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device including a thin film transistor provided over a substrate.

In recent years, development of semiconductor devices in which various circuits are integrated on the same insulating surface has been promoted (see, for example, Patent Document 1).
JP 2004-247373 A

An object of the present invention is to provide a semiconductor device that realizes high functionality, multi-function, and added value.

The present invention provides a semiconductor device in which a circuit for outputting a signal having an accurate frequency is provided on a substrate. An example of a circuit that outputs a signal having an accurate frequency is a phase-locked loop circuit (hereinafter sometimes referred to as a PLL circuit). The PLL circuit has a function of outputting a signal having a constant magnification based on a supplied signal. The present invention in which such a PLL circuit is provided on a substrate can realize high functionality, multiple functionality, and high added value.

In the semiconductor device of the present invention, a voltage controlled oscillator is provided on a substrate. The voltage controlled oscillator includes a first circuit including a plurality of first N-channel thin film transistors and a first P-channel thin film transistor connected in series, and a first circuit connected in series with the first N-channel thin film transistor. A second circuit including a plurality of N-channel thin film transistors, a third circuit including a plurality of second P-channel thin film transistors connected in series with the first P-channel thin film transistor, and a second circuit connected in series. A fourth circuit including three N-channel thin film transistors and a third P-channel thin film transistor.

In the semiconductor device having the above structure, one of the source and the drain of the first N-type thin film transistor is connected to one of the source and the drain of the first P-type thin film transistor. The other of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the second N-type thin film transistor. The other of the source and drain of the first P-type thin film transistor is connected to one of the source and drain of the second P-type thin film transistor. One of the source and the drain of the third N-type thin film transistor is connected to one of the source and the drain of the third P-type thin film transistor.

In the semiconductor device having the above structure, the other of the source and the drain of the second N-type thin film transistor and the other of the source and the drain of the third N-type thin film transistor are connected to a low potential power source. The other of the source and drain of the second P-type thin film transistor and the other of the source and drain of the third P-type thin film transistor are connected to a high potential power source. That is, the other of the source and drain of the second N-type thin film transistor and the other of the source and drain of the third N-type thin film transistor are kept at a constant potential (low potential). The other of the source and drain of the second P-type thin film transistor and the other of the source and drain of the third P-type thin film transistor are kept at a constant potential (high potential).

In the semiconductor device having the above structure, the first circuit, the second circuit, and the third circuit each include one or both of a P-channel thin film transistor and an N-channel thin film transistor. The configuration is not limited, and each circuit may be provided with one or both of a P-channel thin film transistor and an N-channel thin film transistor.

In the semiconductor device having the above structure, the second N-channel thin film transistor controls conduction between the first N-channel thin film transistor and the low-potential power supply, and the second P-channel thin film transistor is the first P-channel thin film transistor. The conduction between the thin film transistor and the high potential power source is controlled. The threshold voltages of the second N-channel thin film transistor and the third N-channel thin film transistor are lower than the threshold voltage of the first N-channel thin film transistor. When the first signal is input to the gate of the second N-channel thin film transistor and the gate of the third N-channel thin film transistor, the first N-channel thin film transistor and the first P-channel thin film transistor are connected to each other. The second signal is output from the selected node.

Note that a node of a thin film transistor refers to three nodes of a gate, a source, and a drain. The nodes of the first N-channel thin film transistor and the first P-channel transistor connected to each other correspond to the source of the first N-channel thin film transistor and the drain of the first P-channel thin film transistor. The nodes of the first N-channel thin film transistor and the first P-channel thin film transistor connected to each other are one of the source and drain of the first N-channel thin film transistor and the source or drain of the first P-channel thin film transistor. Corresponds to one of the drains.

In the semiconductor device having the above structure, the channel lengths of the second N-type transistor and the third N-type transistor are smaller (shorter) than the channel length of the first N-type transistor. The concentration of the impurity element imparting N-type conductivity in the channel formation region of the semiconductor layer included in the second N-type transistor and the third N-type transistor is determined by the channel formation region of the semiconductor layer included in the first N-type transistor. Higher than the concentration in The concentration of the impurity element imparting P-type conductivity in the channel formation region of the semiconductor layer included in the second N-type transistor and the third N-type transistor is determined by the channel formation region of the semiconductor layer included in the first N-type transistor. Lower than the concentration in

In the semiconductor device of the present invention, a voltage controlled oscillator is provided on a substrate. The voltage controlled oscillator includes a first circuit including a plurality of first N-channel thin film transistors and P-channel thin film transistors connected in series, and a second N connected in series with the first N-channel thin film transistor. A second circuit including a plurality of channel thin film transistors is included.

In the semiconductor device having the above structure, one of the source and the drain of the first N-type thin film transistor is connected to one of the source and the drain of the P-type thin film transistor. The other of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the second N-type thin film transistor.

In the semiconductor device having the above structure, the other of the source and the drain of the second N-type thin film transistor is connected to a low potential power source. The other of the source and the drain of the P-type thin film transistor is connected to a high potential power source. That is, the other of the source and the drain of the second N-type thin film transistor is kept at a constant potential (low potential). The other of the source and the drain of the P-type thin film transistor is kept at a constant potential (high potential).

In the semiconductor device having the above structure, the first circuit and the second circuit each include one or both of a P-channel thin film transistor and an N-channel thin film transistor. However, the present invention is limited in its structure. Instead, one or both of a P-channel thin film transistor and an N-channel thin film transistor may be provided in each circuit.

In the semiconductor device having the above structure, the second N-channel thin film transistor controls conduction between the first N-channel thin film transistor and the low-potential power source. The threshold voltage of the second N-channel thin film transistor is lower than the threshold voltage of the first N-channel thin film transistor. Then, when the first signal is input to the gate of the second N-channel thin film transistor, the second signal is output from the node where the first N-channel thin film transistor and the P-channel thin film transistor are connected to each other.

In the semiconductor device having the above structure, the channel length of the second N-type transistor is smaller (shorter) than the channel length of the first N-type transistor. The concentration of the impurity element imparting N-type in the channel formation region of the semiconductor layer included in the second N-type transistor is higher than the concentration in the channel formation region of the semiconductor layer included in the first N-type transistor. The concentration of the impurity element imparting P-type in the channel formation region of the semiconductor layer included in the second N-type transistor is lower than the concentration in the channel formation region of the semiconductor layer included in the first N-type transistor.

In the semiconductor device of the present invention, a voltage controlled oscillator is provided on a substrate. The voltage controlled oscillator includes a first circuit including a plurality of first N-channel thin film transistors and a first P-channel thin film transistor connected in series, and a first circuit connected in series with the first N-channel thin film transistor. A second circuit including a plurality of N-channel thin film transistors, a third circuit including a plurality of second P-channel thin film transistors connected in series with the first P-channel thin film transistor, and a second circuit connected in series. A fourth circuit including three N-channel thin film transistors and a third P-channel thin film transistor.

In the semiconductor device having the above structure, one of the source and the drain of the first N-type thin film transistor is connected to one of the source and the drain of the first P-type thin film transistor. The other of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the second N-type thin film transistor. The other of the source and drain of the first P-type thin film transistor is connected to one of the source and drain of the second P-type thin film transistor. One of the source and the drain of the third N-type thin film transistor is connected to one of the source and the drain of the third P-type thin film transistor.

In the semiconductor device having the above structure, the other of the source and the drain of the second N-type thin film transistor and the other of the source and the drain of the third N-type thin film transistor are connected to a low potential power source. The other of the source and drain of the second P-type thin film transistor and the other of the source and drain of the third P-type thin film transistor are connected to a high potential power source. That is, the other of the source and drain of the second N-type thin film transistor and the other of the source and drain of the third N-type thin film transistor are kept at a constant potential (low potential). The other of the source and drain of the second P-type thin film transistor and the other of the source and drain of the third P-type thin film transistor are kept at a constant potential (high potential).

In the semiconductor device having the above structure, the first circuit, the second circuit, and the third circuit each include one or both of a P-channel thin film transistor and an N-channel thin film transistor. The configuration is not limited, and each circuit may be provided with one or both of a P-channel thin film transistor and an N-channel thin film transistor.

In the semiconductor device having the above structure, the second N-channel thin film transistor controls conduction between the first N-channel thin film transistor and the low-potential power supply, and the second P-channel thin film transistor is the first P-channel thin film transistor. The conduction between the thin film transistor and the high potential power source is controlled. The threshold voltages of the second P-channel thin film transistor and the third P-channel thin film transistor are higher than the threshold voltage of the first P-channel thin film transistor. When the first signal is input to the gate of the second P-channel thin film transistor and the gate of the third P-channel thin film transistor, the first N-channel thin film transistor and the first P-channel thin film transistor are connected to each other. The second signal is output from the selected node.

In the semiconductor device having the above structure, the channel lengths of the second P-type transistor and the third P-type transistor are smaller (shorter) than the channel length of the first P-type transistor. The concentration of the impurity element imparting P-type in the channel formation region of the semiconductor layer included in the second P-type transistor and the third P-type transistor is determined in the channel formation region of the semiconductor layer included in the first P-type transistor. Higher than concentration. The concentration of the impurity element imparting N-type conductivity in the channel formation region of the semiconductor layer included in the second P-type transistor and the third P-type transistor depends on the channel formation region of the semiconductor layer included in the first P-type transistor. Lower than the concentration in

In the semiconductor device of the present invention, a voltage controlled oscillator is provided on a substrate, and the voltage controlled oscillator includes a first circuit including a plurality of N-channel thin film transistors and a first P-channel thin film transistor connected in series. And a second circuit including a plurality of second P-channel thin film transistors connected in series with the first P-channel thin film transistor.

In the semiconductor device having the above structure, one of the source and the drain of the first P-type thin film transistor is connected to one of the source and the drain of the N-type thin film transistor. The other of the source and drain of the first P-type thin film transistor is connected to one of the source and drain of the second P-type thin film transistor.

In the semiconductor device having the above structure, the other of the source and the drain of the second P-type thin film transistor is connected to a high potential power source. The other of the source and the drain of the N-type thin film transistor is connected to a low potential power source. That is, the other of the source and the drain of the second P-type thin film transistor is kept at a constant potential. The other of the source and the drain of the N-type thin film transistor is kept at a constant potential.

In the semiconductor device having the above structure, the first circuit and the second circuit each include one or both of a P-channel thin film transistor and an N-channel thin film transistor. However, the present invention is limited in its structure. Instead, one or both of a P-channel thin film transistor and an N-channel thin film transistor may be provided in each circuit.

In the semiconductor device having the above structure, the second P-channel thin film transistor controls conduction between the first P-channel thin film transistor and the high potential power source. The threshold voltage of the second P-channel thin film transistor is higher than the threshold voltage of the first P-channel thin film transistor. When the first signal is input to the gate of the second P-channel thin film transistor, the second signal is output from the mutually connected node of the first N-channel thin film transistor and the first P-channel thin film transistor.

In the semiconductor device having the above structure, the channel length of the second P-type transistor is smaller (shorter) than the channel length of the first P-type transistor. The concentration of the impurity element imparting P-type in the channel formation region of the semiconductor layer included in the second P-type transistor is higher than the concentration in the channel formation region of the semiconductor layer included in the first P-type transistor. The concentration of the impurity element imparting N-type in the channel formation region of the semiconductor layer included in the second P-type transistor is lower than the concentration in the channel formation region of the semiconductor layer included in the first P-type transistor.

In the above structure, the substrate included in the semiconductor device of the present invention is made of glass or plastic. When the substrate is made of glass, mass production can be achieved and costs can be reduced as compared with the case where a single crystal substrate is used. Further, when the substrate is made of plastic, it is thin, lightweight, and can be bent, so that it is excellent in design and easy to be processed into a flexible shape.

In addition, a phase comparator, a loop filter, and a frequency divider are provided on a substrate included in the semiconductor device of the present invention.

An antenna is provided over a substrate included in the semiconductor device of the present invention. Therefore, a semiconductor device that performs transmission, reception, or transmission / reception of electromagnetic waves using an antenna can be provided.

In addition, a pixel portion including a plurality of pixels is provided over a substrate included in the semiconductor device of the present invention, and each of the plurality of pixels includes a liquid crystal element or a light-emitting element. Accordingly, it is possible to provide a semiconductor device that has a function of displaying an image and realizes high functionality, multiple functions, and high added value.

The present invention also provides an electronic apparatus using the semiconductor device having any one of the above-described configurations.

Note that an N-channel thin film transistor may be referred to as an N-type thin film transistor. A P-channel thin film transistor may be referred to as a P-type thin film transistor.

The present invention in which a PLL circuit having a function of keeping the frequency of the supplied signal constant and a function of controlling the frequency of the supplied signal is provided on the substrate realizes high functionality, multi-function and high added value. A semiconductor device can be provided. By utilizing the function of the PLL circuit, for example, if the frequency of an input signal is increased and a signal having the increased frequency is supplied to another circuit, the operation of the other circuit can be accelerated. . Further, the PLL circuit has a function of outputting a signal having an accurate frequency by synchronizing with the average frequency even when the frequency of the input signal is not accurate. Can prevent the operation error.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

The structure of the semiconductor device of the present invention will be described with reference to FIG. The semiconductor device of the present invention includes a phase comparator 11, a loop filter 12, a voltage controlled oscillator (also referred to simply as VCO) 13 and a frequency divider 14.

The phase comparator 11 compares the phase of the signal Fs input from the outside with the signal Fo / N input from the frequency divider 14. The loop filter 12 generates a signal obtained by removing the AC component from the signal supplied from the phase comparator 11. The voltage controlled oscillator 13 outputs a signal Fo based on the signal Vin input from the loop filter 12. The frequency divider 14 outputs a signal Fo / N obtained by dividing the signal Fo input from the voltage controlled oscillator 13 by 1 / N.

Note that the semiconductor device of the present invention includes the voltage controlled oscillator 13, and the phase comparator 11, the loop filter 12, and the frequency divider 14 are appropriately provided depending on the application. Further, the semiconductor device of the present invention may have other components, for example, a crystal oscillator, a prescaler, a swallow counter, and the like.

The phase comparator 11, the loop filter 12, the voltage controlled oscillator 13, and the frequency divider 14 are provided on the same substrate. The phase comparator 11, the voltage controlled oscillator 13, and the frequency divider 14 include at least one or a plurality selected from a thin film transistor, a capacitive element, and a resistive element. The loop filter 12 includes at least one or both of a resistance element and a capacitance element.

The substrate is made of glass or plastic. When the substrate is made of glass, mass production can be achieved and costs can be reduced as compared with the case where a single crystal substrate is used. This is because a single crystal substrate is circular and has a diameter of about 30 cm at the maximum, and is expensive compared to a glass substrate or the like. Further, when the substrate is made of plastic, it is thin, lightweight, and can be bent, so that it is excellent in design and can be easily processed into a flexible shape. Moreover, it is excellent in impact resistance, and can be easily affixed or embedded in various articles, and can be used in various fields. Plastic is a general term for organic polymer substances, such as phenol resin, melamine resin, polyethylene, polyvinyl chloride, polyether amide, polyether sulfone, acrylic, and polyvinyl chloride.

Next, an equivalent circuit of the semiconductor device having the above structure will be described with reference to FIG. The phase comparator 11 has a unit circuit 21. The loop filter 12 includes resistance elements 22 and 23 and capacitance elements 24 and 25. Although the illustrated loop filter 12 is a lag reed filter, the present invention is not limited to this configuration, and other configurations such as a lag filter may be used. The frequency divider 14 has three unit circuits 26 and is an divide-by-8 circuit. The number of unit circuits 26 included in the frequency divider 14 is not particularly limited.

The lag lead filter is a filter composed of two resistance elements and one capacitance element. A lag filter is a filter composed of one resistive element and one capacitive element.

The voltage controlled oscillator 13 includes a circuit 120 (also referred to as a first circuit) including a plurality of first N-type transistors and first P-type transistors connected in series, and is connected in series with the first N-type transistors. A circuit 121 (also referred to as a second circuit) including a plurality of second N-type transistors, and a circuit 122 (also referred to as a third circuit) including a plurality of second P-type transistors connected in series with the first P-type transistor ), And a circuit 123 (also referred to as a fourth circuit) including a third N-type transistor and a third P-type transistor connected in series.

In the configuration shown, the circuit 120 includes a first N-type transistor 141 and a first P-type transistor 131 connected in series, a first N-type transistor 142 and a first P-type transistor 132 connected in series. The first N-type transistor 143 and the first P-type transistor 133 connected in series, the first N-type transistor 144 and the first P-type transistor 134 connected in series, the first N-type transistor connected in series N-type transistor 145 and first P-type transistor 135.

The circuit 121 includes a plurality of second N-type transistors 112 to 116, and the circuit 122 includes a plurality of second P-type transistors 102 to 106. The plurality of second N-type transistors 112 to 116 controls conduction between the first N-type transistors 141 to 145 and the low potential power supply (VSS). The plurality of second P-type transistors 102 to 106 controls conduction between the first P-type transistors 131 to 135 and the high potential power supply (VDD).

The circuit 123 includes a third P-type transistor 101 and a third N-type transistor 111. The circuit 123 is a circuit that controls conduction between the loop filter 12 and the circuits 121 and 122.

Note that in the above structure, the four transistors connected in series of the second P-type transistor 102, the first P-type transistor 131, the first N-type transistor 141, and the second N-type transistor 112 are arranged in one stage. Then, said structure is a case of 5 steps | paragraphs. However, the present invention is not limited to this configuration. The voltage controlled oscillator 13 may have an odd number of stages of three or more stages.

The gate of the third P-type transistor 101 and one of the source and drain of the third P-type transistor 101 are connected to each other, and the other of the source and drain of the third P-type transistor 101 is a high potential power source. (VDD). The gate of the third N-type transistor 111 is connected to the loop filter 12, and one of the source and drain of the third N-type transistor 111 is connected to a low potential power supply (VSS).

In the above configuration, the threshold voltages of the second N-type transistors 112 to 116 and the third N-type transistor 111 are the threshold voltages of the first N-type transistors 141 to 145 and the N-type transistors of other circuits. Lower than. The N-type transistors in other circuits are N-type transistors included in the phase comparator 11 and the frequency divider 14.

As described above, the threshold voltages of the second N-type transistors 112 to 116 and the third N-type transistor 111 are the threshold voltages of the first N-type transistors 141 to 145 and the N-type transistors of other circuits. In order to make it lower than this, the channel length is designed to an appropriate value. Specifically, the channel lengths of the second N-type transistors 112 to 116 and the third N-type transistor 111 are smaller than the channel lengths of the first N-type transistors 141 to 145 and other circuit N-type transistors. Design to be (short).

Alternatively, the concentration of the impurity element imparting N-type conductivity in the channel formation regions of the semiconductor layers of the second N-type transistors 112 to 116 and the third N-type transistor 111 is changed to that of the first N-type transistors 141 to 145 and others. The concentration is higher than the concentration of the channel formation region of the semiconductor layer of the N-type transistor of the circuit. Note that the impurity element imparting N-type corresponds to phosphorus (P) or arsenic (As).

Alternatively, the concentration of the impurity element imparting p-type conductivity in the channel formation regions of the semiconductor layers of the second n-type transistors 112 to 116 and the third n-type transistor 111 is changed to the first n-type transistors 141 to 145 and others. The n-type transistor of this circuit is manufactured so as to be lower in concentration than the impurity element in the channel formation region of the semiconductor layer. Note that the impurity element imparting P-type specifically corresponds to boron (B).

In the present invention having the above configuration, the performance of the voltage controlled oscillator 13 can be improved. Specifically, when the signal Vin is input to the second N-type transistors 112 to 116 and the third N-type transistor 111, the voltage-controlled oscillator 13 is connected to the source or drain of the first N-type transistor 145. And a signal Fo from one of the source and the drain of the first P-type transistor 135. According to the present invention, the range of the effective signal Vin can be expanded. Hereinafter, this effect will be described with reference to FIG. 6 showing a graph of the relationship between the signal Vin input to the voltage controlled oscillator 13 and the signal Fo output from the voltage controlled oscillator 13.

The signal Vin input to the voltage controlled oscillator 13 changes from 0 to VDD (VDD is the potential of the high potential power supply). The signal Vin input to the voltage controlled oscillator 13 is input to the gate electrodes of the second N-type transistors 112 to 116 and the third N-type transistor 111. Therefore, if the voltage value of the signal Vin is smaller (lower) than the threshold voltage (VTH1) of the second N-type transistors 112 to 116 and the third N-type transistor 111, the output signal is not oscillated. (See FIG. 6B). Further, in the graph showing the relationship between the voltage Vin (signal Vin) and the signal Fo, a portion having a steep slope is formed in the characteristic curve. If there is a steep part in the characteristic curve, the frequency of the signal to be output is likely to vary, and it may not operate normally.

Such a defect is caused by the fact that the voltage controlled oscillator 13 is constituted by a thin film transistor and the voltage controlled oscillator 13 is a circuit for processing an analog signal. In other words, the thin film transistor may vary in its characteristics (threshold voltage, mobility, etc.), but the phase comparator 11 and the frequency divider 14 are controlled by digital signals, so that the characteristics of the thin film transistor Insensitive to variations. However, since the voltage controlled oscillator 13 is controlled by an analog signal, it is easily affected by variations in characteristics of the thin film transistor.

Therefore, the present invention having the above-described structure is characterized in that the threshold voltages of the second N-type transistors 112 to 116 and the third N-type transistor 111 are lower than the threshold voltages of the other transistors. . That is, in the present invention having the above-described configuration, the threshold voltages (VTH2) of the second N-type transistors 112 to 116 and the third N-type transistor 111 are smaller (lower) than the voltage value of the signal Vin. The range of the effective signal Vin can be expanded (see FIG. 6A). In addition, the characteristic curve has no steep part, and the frequency of the output signal is less likely to vary. Therefore, an excellent effect of improving the performance of the voltage controlled oscillator 13 is achieved.

Next, a voltage controlled oscillator 13 different from the above configuration will be described with reference to FIG. The voltage controlled oscillator 13 includes a circuit 120 (also referred to as a first circuit) and a circuit 121 (also referred to as a second circuit). Compared with the configuration shown in FIG. 2, the second P-type transistors 102 to 106, the third P-type transistor 101, and the third N-type transistor 111 are omitted. In this configuration, the number of elements can be reduced, so that the size and weight can be reduced by reducing the area occupied by the elements, and the yield can be improved by reducing the number of elements.

Next, a voltage controlled oscillator 13 different from the above configuration will be described with reference to FIG. The voltage controlled oscillator 13 includes a circuit 120 (also referred to as a first circuit), a circuit 121 (also referred to as a second circuit), and a circuit 123 (also referred to as a third circuit). Compared with the configuration shown in FIG. 2, the signal supplied from the loop filter 12 is input to the second P-type transistors 102 to 106 and the third P-type transistor 101, the third N-type transistor 111 is different in that the gate electrode and the drain electrode are connected to each other.

Next, a voltage controlled oscillator 13 different from the above configuration will be described with reference to FIG. The voltage controlled oscillator 13 includes a circuit 120 (also referred to as a first circuit) and a circuit 122 (also referred to as a second circuit). Compared with the configuration shown in FIG. 4, the second N-type transistors 112 to 116 and the third N-type transistor 111 are omitted. In this configuration, the number of elements can be reduced, so that the size and weight can be reduced by reducing the area occupied by the elements, and the yield can be improved by reducing the number of elements.

4 and 5, the threshold voltages of the second P-type transistors 102 to 106 and the third P-type transistor 101 are the P voltages of the first P-type transistors 131 to 135 and other circuits. It is characterized by being higher than the threshold voltage of the type transistor. The P-type transistors in other circuits are P-type transistors included in the phase comparator 11 and the frequency divider 14.

Thus, the threshold voltages of the second P-type transistors 102 to 106 and the third P-type transistor 101 are the threshold voltages of the first P-type transistors 131 to 135 and the P-type transistors of other circuits. In order to make it higher than this, the channel length is designed to an appropriate value. Specifically, the channel lengths of the second P-type transistors 102 to 106 and the third P-type transistor 101 are smaller than the channel lengths of the first P-type transistors 131 to 135 and P-type transistors of other circuits. Design to be (short).

Alternatively, the concentration of the impurity element included in the channel formation region included in the semiconductor layers of the second P-type transistors 102 to 106 and the third P-type transistor 101 is set to P of the first P-type transistors 131 to 135 and other circuits. The channel formation region included in the semiconductor layer of the type transistor is formed so as to be higher than the concentration of the impurity element. Note that the impurity element is an element imparting P-type, and specifically corresponds to boron (B).

Alternatively, the concentration of the impurity element included in the channel formation region included in the semiconductor layers of the second P-type transistors 102 to 106 and the third P-type transistor 101 is set to P of the first P-type transistors 131 to 135 and other circuits. The channel formation region included in the semiconductor layer of the type transistor is formed so as to be lower than the concentration of the impurity element. Note that the impurity element is an element imparting N-type, and specifically corresponds to phosphorus or arsenic.

Note that the transistor included in the voltage controlled oscillator 13 is connected to a high potential power supply (VDD) and a low potential power supply (VSS). The high potential power source and the low potential power source may be provided on the same substrate as the substrate on which the voltage controlled oscillator 13 is provided, or may be provided on different substrates. Note that the threshold voltage of the first N-channel thin film transistor is lower than the threshold voltage of the second N-channel thin film transistor means that the absolute value of the threshold voltage of the first N-channel thin film transistor is It means that it is smaller than the absolute value of the threshold voltage of the second N-channel thin film transistor. The threshold voltage of the first P-channel thin film transistor is lower than the threshold voltage of the second P-channel thin film transistor. The absolute value of the threshold voltage of the first N-channel thin film transistor is It means that it is smaller than the absolute value of the threshold voltage of the second N-channel thin film transistor.

This embodiment mode can be freely combined with the following examples.

Hereinafter, the configuration of the unit circuit 21 included in the phase comparator 11 will be described with reference to FIG. The unit circuit 21 includes a NOR circuit 221 and transistors 222 to 227. The unit circuit 21 has two input terminals (denoted as 1 and 2 in the drawing) and one output terminal (denoted as 3 in the drawing).

When the same signal is input to each of the input terminal 1 and the input terminal 2, the unit circuit 21 outputs an H level signal from the output terminal 3. When different signals are input to the input terminal 1 and the input terminal 2, an L level signal is output from the output terminal 3.

That is, the unit circuit 21 compares the phase of the signal input to the input terminal 1 and the signal input to the input terminal 2, and outputs a signal from the output terminal 3 based on the result. The configuration of the unit circuit 21 is not limited to this configuration, and other known configurations may be used.

Next, the configuration of the unit circuit 26 included in the frequency divider 14 will be described with reference to FIG. The unit circuit 26 includes an inverter circuit 200, NAND circuits 201 to 207, and inverter circuits 208 and 209. The unit circuit 26 has four input terminals (denoted as 1, 2, 3, 4 in the drawing) and two output terminals (denoted as 5, 6 in the drawing).

The unit circuit 26 has a total of three latches: a latch composed of NAND circuits 202 and 203, a latch composed of NAND circuits 204 and 205, and a latch composed of NAND circuits 206 and 207. When the set signal is input from the input terminal 1, the data signal is input from the input terminal 2, the clock signal is input from the input terminal 3, and the reset signal is input from the input terminal 4, the data signal is output from the output terminal 5. And a data signal is output from the output terminal 6. Although the above configuration is a set / reset type D flip-flop circuit, the present invention is not limited to this configuration, and for example, a JK flip-flop circuit or a T flip-flop circuit may be used.

Note that examples of the flip-flop (also referred to as a flip-flop circuit as described above) include an RS flip-flop, a D flip-flop, a JK flip-flop, and a T flip-flop. The RS flip-flop has an R terminal and an S terminal that are input terminals, and a Q terminal that is an output terminal. The D flip-flop has a D terminal as an input terminal and a Q terminal as an output terminal. The JK flip-flop has a J terminal and a K terminal as input terminals, and a Q terminal as an output terminal. The T flip-flop has a T terminal as an input terminal and a Q terminal as an output terminal.

A method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings. In the following, the structure of a semiconductor device including a memory element and an antenna as well as a thin film transistor constituting a voltage controlled oscillator will be described.

A separation layer 702 is formed over one surface of a substrate 701 (also referred to as a base) (see FIG. 9A). The substrate 701 has an insulating surface. The substrate 701 is made of glass or plastic. In the case where the substrate 701 is made of glass, there is no significant limitation on the area or shape thereof. Therefore, if the substrate 701 is, for example, a rectangle having one side of 1 meter or more and a rectangular shape, productivity can be significantly improved. Such an advantage is a great advantage as compared with the case of using a circular single crystal silicon substrate. In the case where the substrate 701 is made of plastic, it is thin, lightweight, and can be bent, so that it is excellent in design and can be easily processed into a flexible shape. Moreover, it is excellent in impact resistance, and can be easily affixed or embedded in various articles, and can be used in various fields. In the case where the substrate 701 is made of plastic, it is necessary to use heat-resistant plastic that can withstand the processing temperature in the manufacturing process. As will be described later, it is preferable to provide a thin film transistor over a glass substrate 701 and then peel off the thin film transistor so that the peeled thin film transistor is provided over a plastic substrate.

In the above process, the release layer 702 is provided over the entire surface of the substrate 701. However, if necessary, after the release layer 702 is provided over the entire surface of the substrate 701, patterning is performed by a photolithography method to selectively perform the process. It may be provided. In addition, although the separation layer 702 is formed so as to be in contact with the substrate 701, an insulating layer serving as a base is formed so as to be in contact with the substrate 701 as necessary, and the separation layer 702 is formed so as to be in contact with the insulation layer. May be.

The release layer 702 is formed by a known means (sputtering method, plasma CVD method, etc.) tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt An element selected from (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), silicon (Si) A layer formed of an alloy material or a compound material containing an element as a main component is formed as a single layer or a stacked layer. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

Next, an insulating layer 703 serving as a base is formed so as to cover the separation layer 702. The insulating layer 703 is formed as a single layer or a stacked layer including a silicon oxide or a silicon nitride by a known means (such as a sputtering method or a plasma CVD method). The silicon oxide material is a substance containing silicon (Si) and oxygen (O), and corresponds to silicon oxide, silicon oxynitride, silicon nitride oxide, or the like. The silicon nitride material is a substance containing silicon and nitrogen (N), and corresponds to silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. The insulating layer 703 serving as a base functions as a blocking film that prevents impurities from entering from the substrate 701.

Next, an amorphous semiconductor layer 704 is formed over the insulating layer 703. The amorphous semiconductor layer 704 is formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Subsequently, the amorphous semiconductor layer 704 is subjected to a known crystallization method (laser crystallization method, thermal crystallization method using an RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, crystallization A crystalline semiconductor layer is formed by crystallization by a combination of a thermal crystallization method using a promoting metal element and a laser crystallization method). After that, the obtained crystalline semiconductor layer is patterned into a desired shape to form crystalline semiconductor layers 706 to 710 (see FIG. 9B).

An example of a manufacturing process of the crystalline semiconductor layers 706 to 710 will be described below. First, an amorphous semiconductor layer is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element for promoting crystallization, is held on the amorphous semiconductor layer, the amorphous semiconductor layer is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor layer. Thereafter, laser light is irradiated as necessary, and crystalline semiconductor layers 706 to 710 are formed by pattern processing using a photolithography method. When the crystalline semiconductor layers 706 to 710 are formed by laser crystallization, a continuous wave or pulsed gas laser or solid laser is used.

Note that when an amorphous semiconductor layer is crystallized using a metal element that promotes crystallization, crystallization can be performed in a short time at a low temperature and the crystal orientation is aligned. Remains in the crystalline semiconductor layer, resulting in an increase in off-current and unstable characteristics. Therefore, an amorphous semiconductor layer functioning as a gettering site is preferably formed over the crystalline semiconductor layer. Since the amorphous semiconductor layer serving as a gettering site needs to contain an impurity element such as phosphorus or argon, it is preferably formed by a sputtering method in which argon can be contained at a high concentration. After that, heat treatment (RTA method or thermal annealing using a furnace annealing furnace) is performed to diffuse the metal element in the amorphous semiconductor layer, and then the amorphous semiconductor layer containing the metal element is removed. To do. Then, the content of the metal element in the crystalline semiconductor layer can be reduced or removed.

Next, a gate insulating layer 705 is formed to cover the crystalline semiconductor layers 706 to 710. The gate insulating layer 705 is formed by a known method (plasma CVD method or sputtering method) as a single layer or a stack of layers containing silicon oxide or silicon nitride. Specifically, a layer containing silicon oxide, a layer containing silicon oxynitride, or a layer containing silicon nitride oxide is formed as a single layer or a stacked layer.

Next, a first conductive layer and a second conductive layer are stacked over the gate insulating layer 705. The first conductive layer is formed with a thickness of 20 to 100 nm by a known means (plasma CVD method or sputtering method). The second conductive layer is formed with a thickness of 100 to 400 nm by a known means.

The first conductive layer and the second conductive layer include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used.

As examples of the combination of the first conductive layer and the second conductive layer, a tantalum nitride (TaN, composition ratio of tantalum (Ta) and nitrogen (N) is not limited) layer, a tungsten (W) layer, and tungsten nitride (The composition ratio of WN, tungsten (W) and nitrogen (N) is not limited) The layer and tungsten layer, The molybdenum nitride (MoN, the composition ratio of molybdenum (Mo) and nitrogen (N) is not limited) layer and molybdenum (Mo ) Layer. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the formation of the first conductive layer and the second conductive layer. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a molybdenum layer, an aluminum layer, and a molybdenum layer may be employed.

Next, a resist mask is formed by photolithography, and an etching process is performed to form a gate electrode and a gate line, so that a conductive layer functioning as a gate electrode (sometimes referred to as a gate electrode layer) 716 to 725 are formed.

Next, a resist mask is formed by photolithography, and an impurity element imparting N-type is added to the crystalline semiconductor layers 706 and 708 to 710 at a low concentration by ion doping or ion implantation. N-type impurity regions 711 and 713 to 715 and channel formation regions 780 and 782 to 784 are formed. The impurity element imparting N-type may be an element belonging to Group 15, for example, phosphorus (P) or arsenic (As).

Next, a resist mask is formed by photolithography, and an impurity element imparting P-type conductivity is added to the crystalline semiconductor layer 707 to form a P-type impurity region 712 and a channel formation region 781. For example, boron (B) is used as the impurity element imparting P-type.

Next, an insulating layer is formed so as to cover the gate insulating layer 705 and the conductive layers 716 to 725. The insulating layer may be a single layer or a layer containing an inorganic material such as silicon, silicon oxide, or silicon nitride, or an organic material such as an organic resin, by a known means (plasma CVD method or sputtering method). It is formed by stacking. Next, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction to form insulating layers (also referred to as sidewalls) 739 to 743 that are in contact with the side surfaces of the conductive layers 716 to 725 (see FIG. 9 (C)). At the same time as the formation of the insulating layers 739 to 743, insulating layers 734 to 738 obtained by etching the insulating layer 705 are formed. The insulating layers 739 to 743 are used as a mask for doping when an LDD (Lightly Doped Drain) region is formed later.

Next, an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 706 and 708 to 710 using a resist mask formed by a photolithography method and the insulating layers 739 to 743 as masks. N-type impurity regions (also referred to as LDD regions) 727, 729, 731 and 733, and second N-type impurity regions 726, 728, 730 and 732 are formed. The concentration of the impurity element in the first N-type impurity regions 727, 729, 731, and 733 is lower than the concentration of the impurity element in the second N-type impurity regions 726, 728, 730, and 732. Through the above steps, N-type thin film transistors 744 and 746 to 748 and a P-type thin film transistor 745 are completed.

In order to form the LDD region, a method in which the gate electrode has a stacked structure of two or more layers, etching or anisotropic etching is performed on the gate electrode, and the lower conductive layer constituting the gate electrode is used as a mask. There is a method using an insulating layer of a sidewall as a mask. The latter method using the sidewall insulating layer as a mask makes it easy to control the width of the LDD region, and the LDD region can be reliably formed.

Next, an insulating layer is formed as a single layer or a stacked layer so as to cover the thin film transistors 744 to 748 (see FIG. 10A). The insulating layer covering the thin film transistors 744 to 748 is formed by a known means (SOG method, droplet discharge method, etc.), an inorganic material such as silicon oxide or silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy. It is formed of a single layer or a laminated layer using an organic material such as siloxane. Siloxane corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Further, a fluoro group may be used as a substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

For example, when the insulating layer covering the thin film transistors 744 to 748 has a three-layer structure, a layer containing silicon oxide is formed as the first insulating layer 749, and a layer containing resin is formed as the second insulating layer 750, A layer containing silicon nitride is preferably formed as the third insulating layer 751.

Note that before the insulating layers 749 to 751 are formed or after one or more thin films of the insulating layers 749 to 751 are formed, the crystallinity of the semiconductor layer is restored and the activity of the impurity element added to the semiconductor layer is increased. Heat treatment for the purpose of hydrogenation of the semiconductor layer may be performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

Next, the insulating layers 749 to 751 are etched by photolithography to form openings that expose the second N-type impurity regions 726, 728, 730, 732, and the P-type impurity region 785. Subsequently, a conductive layer is formed so as to fill the opening, and the conductive layer is patterned to form conductive layers 752 to 761 functioning as a source wiring or a drain wiring.

The conductive layers 752 to 761 are mainly composed of an element selected from titanium (Ti), aluminum (Al), neodymium (Nd), or the like by a known means (plasma CVD method or sputtering method). An alloy material or a compound material is formed as a single layer or a laminated layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive layers 752 to 761 include, for example, a laminated structure of a barrier layer, an aluminum silicon (Al—Si) layer, and a barrier layer, a barrier layer, an aluminum silicon (Al—Si) layer, titanium nitride (TiN, titanium (Ti), and nitrogen). (The composition ratio of (N) is not limited) A laminated structure of a layer and a barrier layer may be employed. Silicon contained in aluminum silicon is about 0.1 to 5 wt%. The barrier layer corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the conductive layers 752 to 761 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier layer made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced and the crystalline semiconductor layer and the barrier are reduced. The layers can be connected well.

Next, an insulating layer 762 is formed so as to cover the conductive layers 752 to 761 (see FIG. 10B). The insulating layer 762 is formed as a single layer or a stacked layer using an inorganic material or an organic material by a known means (SOG method, droplet discharge method or the like). The insulating layer 762 is preferably formed with a thickness of 0.75 μm to 3 μm.

Subsequently, the insulating layer 762 is etched by photolithography to form openings that expose the conductive layers 757, 759, and 761. Subsequently, a conductive layer is formed so as to fill the opening. The conductive layer is formed of a conductive material using a known means (plasma CVD method or sputtering method). Next, the conductive layer is patterned to form conductive layers 763 to 765.

The conductive layers 763 to 765 are one of a pair of conductive layers included in the memory element. Therefore, the conductive layers 763 to 765 are preferably formed as a single layer or a stacked layer using titanium, or an alloy material or compound material containing titanium as a main component. Titanium has a low resistance value, which leads to a reduction in the size of the memory element and can achieve high integration. In the photolithography process for forming the conductive layers 763 to 765, wet etching may be performed in order to prevent damage to the lower thin film transistors 744 to 748, and the etchant contains hydrogen fluoride or ammonia excess. Use water.

Next, an insulating layer 766 is formed so as to cover the conductive layers 763 to 765. The insulating layer 766 is formed as a single layer or a stacked layer using an inorganic material or an organic material by a known means (SOG method, droplet discharge method, or the like). The insulating layer 766 is preferably formed with a thickness of 0.75 μm to 3 μm. Subsequently, the insulating layer 766 is etched by photolithography to form openings 767 to 769 that expose the conductive layers 763 to 765.

Next, a conductive layer 786 functioning as an antenna is formed so as to be in contact with the conductive layer 765 (see FIG. 11A). The conductive layer 786 is formed using a conductive material by a known method (plasma CVD method, sputtering method, printing method, droplet discharge method). Preferably, the conductive layer 786 is an element selected from aluminum (Al), titanium (Ti), silver (Ag), and copper (Cu), or an alloy material or a compound material containing these elements as a main component. It is formed by layer or lamination.

Specifically, the conductive layer 786 is formed by a screen printing method using a paste containing silver, and then heat-treated at 50 to 350 degrees. Alternatively, an aluminum layer is formed by a sputtering method, and the aluminum layer is formed by patterning. For the pattern processing of the aluminum layer, wet etching processing is preferably used, and after the wet etching processing, heat treatment at 200 to 300 ° C. is preferably performed.

Next, a layer 787 containing an organic compound is formed so as to be in contact with the conductive layers 763 and 764 (see FIG. 11B). The layer 787 containing an organic compound is formed by a known means (such as a droplet discharge method or an evaporation method). Subsequently, a conductive layer 771 is formed so as to be in contact with the layer 787 containing an organic compound. The conductive layer 771 is formed by a known means (such as a sputtering method or an evaporation method).

Through the above steps, the memory element 789 including the conductive layer 763, the layer 787 including the organic compound, and the conductive layer 771, and the memory including the layer including the conductive layer 764, the layer 787 including the organic compound, and the conductive layer 771 are stored. Element 790 is completed.

Note that in the above manufacturing process, since the heat resistance of the layer 787 including an organic compound is not strong, the step of forming the layer 787 including an organic compound is performed after the step of forming the conductive layer 786 functioning as an antenna. Features.

Next, an insulating layer 772 functioning as a protective layer is formed by a known means (SOG method, droplet discharge method, or the like) so as to cover the memory elements 789 and 790 and the conductive layer 786 functioning as an antenna. The insulating layer 772 is formed of a layer containing carbon such as DLC (diamond-like carbon), a layer containing silicon nitride, a layer containing silicon nitride oxide, or an organic material, and preferably formed of an epoxy resin.

Next, the insulating layers 703, 749, 750, 751, 762, and 766 are etched by photolithography so that the separation layer 702 is exposed, so that openings 773 and 774 are formed (see FIG. 12A). .

Next, an etchant is introduced into the openings 773 and 774 to remove the separation layer 702 (see FIG. 12B). As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, there are chlorine trifluoride (ClF ₃ ), nitrogen trifluoride (NF ₃ ), bromine trifluoride (BrF 3), and hydrogen fluoride (HF). Note that when hydrogen fluoride is used, a layer formed of silicon oxide is used as the separation layer 702.

Through the above steps, the thin film integrated circuit 791 is peeled from the substrate 701. The thin film integrated circuit 791 has a group of thin film transistors 744 to 748 and memory elements 789 and 790 and a conductive layer 786 functioning as an antenna. That is, as described above, a plurality of elements separated from a substrate may be referred to as a thin film integrated circuit.

The substrate 701 from which the thin film integrated circuit 791 is peeled is preferably reused for cost reduction. The insulating layer 772 is provided so that the thin film integrated circuit 791 is not scattered after the separation layer 702 is removed. Since the thin film integrated circuit 791 is small and thin, the thin film integrated circuit 791 is likely to be scattered after being removed from the substrate 701 after the peeling layer 702 is removed. However, by forming the insulating layer 772 over the thin film integrated circuit 791, the thin film integrated circuit 791 is weighted and scattering from the substrate 701 can be prevented. In addition, although the thin film integrated circuit 791 is thin and light, the insulating layer 772 is formed, so that a certain shape of strength can be secured without forming a wound shape.

Next, one surface of the thin film integrated circuit 791 is attached to the first substrate 776 and completely peeled from the substrate 701 (see FIG. 13). Subsequently, the other surface of the thin film integrated circuit 791 is bonded to the second substrate 775, and then one or both of heat treatment and pressure treatment are performed, so that the thin film integrated circuit 791 is bonded to the first substrate 776 and the first substrate 776. The second substrate 775 is sealed.

The first substrate 776 and the second substrate 775 are a film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, a paper made of a fibrous material, a base film (polyester, polyamide, inorganic vapor deposition film, Paper) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to an adhesion treatment with a target object by heat treatment and pressure treatment. When performing the heat treatment and the pressure treatment, the adhesive layer provided on the outermost surface of the film or the layer (not the adhesive layer) provided on the outermost layer is melted by the heat treatment and adhered by the pressure.

Further, an adhesive layer may be provided on the surfaces of the first substrate 776 and the second substrate 775, or the adhesive layer may not be provided. Adhesive layer is thermosetting resin, UV curable resin, vinyl acetate resin adhesive, vinyl copolymer resin adhesive, epoxy resin adhesive, urethane resin adhesive, rubber adhesive, acrylic resin adhesive, etc. This corresponds to a layer containing an adhesive.

In the above structure, the memory elements 789 and 790 are elements each including a layer containing an organic compound between a pair of conductive layers. Data writing is performed by short-circuiting the pair of conductive layers of the memory elements 789 and 790. Data is read by reading the difference in resistance value between the memory elements 789 and 790. Such memory elements 789 and 790 are characterized by being non-volatile, incapable of rewriting data, and capable of adding data as long as there is a memory element to which no data is written. To do. Moreover, since it consists of a laminated body of 3 layers, it is characterized by the easy production. Further, since it is composed of a three-layer laminate, it is characterized in that high integration can be easily realized by reducing the area of the laminate portion.

A method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

Over the substrate 701, thin film transistors 744 to 748, memory elements 789 and 790, and a conductive layer 786 functioning as an antenna are provided (see FIG. 14A). In the steps up to here, conductive layers 801 and 802 electrically connected to the source or drain of the thin film transistor 744 and conductive layers 803 and 804 electrically connected to the source or drain of the thin film transistor 745 are newly provided. Since it is the same as that of the process shown to FIGS. 9-11B except having been described, description is abbreviate | omitted.

Next, an insulating layer 805 is formed so as to cover the plurality of elements. Subsequently, the insulating layer 805 is selectively removed so that parts of the conductive layers 802 and 804 are exposed.

Next, the insulating layers 703, 749, 750, 751, 762, 766, and 805 are etched by photolithography so that the separation layer 702 is exposed, so that openings 773 and 774 are formed (FIG. 14B). reference). Subsequently, an etching agent is introduced into the openings 773 and 774 to remove the peeling layer 702.

Next, the thin film integrated circuit 791 is adhered to the substrate 809 provided with the conductive layers 807 and 808 using the anisotropic conductive paste 806, and the thin film integrated circuit 791 is peeled from the substrate 701 (see FIG. 15). ).

Note that when the thin film integrated circuit 791 is bonded to the substrate 809, the conductive layer 802 and the conductive layer 807 and the conductive layer 804 and the conductive layer 808 are electrically connected to each other. The substrate 809 is provided with, for example, a pixel portion that displays an image and other arithmetic circuits, and the conductive layers 807 and 808 are electrically connected to the pixel portion and other arithmetic circuits.

A method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

Over the substrate 701, thin film transistors 744 to 748, memory elements 789 and 790, and a conductive layer 786 functioning as an antenna are provided. The steps so far are the same as the steps shown in FIGS. 9 to 11B except that conductive layers 821 and 822 are newly provided, and thus the description thereof is omitted (see FIG. 16A). The conductive layer 821 is connected to the source or drain of the thin film transistor 744 and is in contact with the substrate 701. The conductive layer 822 is connected to the source or drain of the thin film transistor 745 and is in contact with the substrate 701.

Next, the insulating layers 703, 749, 750, 751, 762, 766, and 772 are etched by photolithography so that the separation layer 702 is exposed to form openings 773 and 774 (FIG. 16B). reference). Subsequently, an etching agent is introduced into the openings 773 and 774 to remove the peeling layer 702.

Next, a substrate 825 is attached to one surface of the thin film integrated circuit 791, and the thin film integrated circuit 791 is separated from the substrate 701 (see FIG. 17A). Next, the other surface of the thin film integrated circuit 791 is attached to a substrate 809 provided with conductive layers 807 and 808 with an anisotropic conductive paste 806 (see FIG. 17B). The substrate 809 is provided with, for example, a pixel portion that displays an image and other arithmetic circuits, and the conductive layers 807 and 808 are electrically connected to the pixel portion and other arithmetic circuits.

An IC card and a panel which are one embodiment of the semiconductor device of the present invention will be described with reference to FIGS.

First, an IC card will be described (see FIG. 18A). In the IC card, a thin film integrated circuit 611 is attached to a substrate 610 provided with a conductive layer 612 functioning as an antenna. The conductive layer 612 over the substrate 610 and the conductive layer 615 connected to the thin film transistor 614 included in the thin film integrated circuit 611 are electrically connected through an anisotropic conductive paste 616 (FIG. 18C ) (D)). As the substrate 610, a substrate made of plastic is preferably used. Then, since it is thin, lightweight, and can be bent, it is excellent in design and can be easily processed into a flexible shape (see FIG. 18B). In addition, an IC card having excellent impact resistance can be provided.

In addition to the PLL circuit described in the above embodiment, the thin film integrated circuit 611 may include one or more selected from an arithmetic processing circuit, a memory circuit, a power supply circuit, a demodulation circuit, and a modulation circuit.

In addition, the IC card transmits or receives electromagnetic waves with a reader / writer through a conductive layer 612 that functions as an antenna. Such an operation of transmitting or receiving an electromagnetic wave will be briefly described below.

First, when the reader / writer transmits an electromagnetic wave, the electromagnetic wave is converted into an AC electrical signal in the conductive layer 612 functioning as an antenna. The power supply circuit generates a power supply voltage using an alternating electrical signal and supplies the power supply voltage to each circuit. The demodulating circuit demodulates an alternating electrical signal and supplies the demodulated signal to the arithmetic processing circuit. The arithmetic processing circuit performs various arithmetic processes based on the input signal and outputs a control signal to the memory circuit or the like. The modulation circuit applies load modulation to the conductive layer 612 functioning as an antenna based on a signal supplied from the arithmetic processing circuit. The reader / writer receives the load modulation applied to the antenna as an electromagnetic wave. In this way, the IC card receives electromagnetic waves from the reader / writer and generates a power supply voltage based on the received electromagnetic waves.

Next, the panel will be described (see FIGS. 19A and 19B). The panel is obtained by attaching the thin film integrated circuits 624 and 625 of the present invention over a substrate 620 provided with a pixel portion 623 having a function of displaying an image. In addition, thin film integrated circuits 628 and 629 are pasted on the connection films 626 and 627.

The substrate 620 and the substrate 621 are attached to each other with a sealant 630. The pixel portion 623 and the thin film integrated circuit 624 are electrically connected. Specifically, the conductive layer 631 connected to the pixel portion 623 and the conductive layer 656 connected to the thin film transistor 655 included in the thin film integrated circuit 624 are electrically connected through an anisotropic conductive paste 640. Yes.

In addition, various circuits over the substrate 620 and the conductive layer 635 of the connection film 626 are electrically connected. Specifically, the conductive layer 634 on the substrate 620 and the conductive layer 635 on the connection film 626 are electrically connected through an anisotropic conductive paste 657. The conductive layer 635 of the connection film 626 and the thin film integrated circuit 628 are electrically connected. Specifically, the conductive layer 635 on the connection film 626 and the thin film integrated circuit 628 included in the thin film integrated circuit 628 are connected. The conductive layer 652 is electrically connected through an anisotropic conductive paste 653.

Note that the semiconductor device of the present invention is not limited to the IC card and the panel as described above. The semiconductor device of the present invention can be a CPU, various processors, and the like.

The semiconductor device of the present invention in which an antenna is provided over a substrate can transmit, receive, or transmit and receive electromagnetic waves using the antenna. Accordingly, the application of the semiconductor device 51 is wide-ranging. The semiconductor device 51 includes, for example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 20A), packaging containers (wrapping paper, bottles, etc.) 20 (B)), recording medium (DVD software, video tape, etc., see FIG. 20 (C)), vehicles (bicycles, etc., see FIG. 20 (D)), accessories (such as bags and glasses), FIG. )), And can be used by attaching to foods, clothing, daily necessities, electronic devices and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also referred to as televisions, television receivers, television receivers), portable terminals, and the like.

The semiconductor device is fixed to the article by being attached to the surface of the article or being embedded in the article. For example, if it is a book, it is embedded in a cardboard of a cover, and if it is a wrapping paper, it is embedded in an organic resin constituting the wrapping paper. For example, banknotes, coins, securities, bearer bonds, and certificates are pasted or embedded on the surface. Among the items listed above, for example, by providing semiconductor devices in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., inspection systems, rental store systems, etc. Efficiency can be improved.

In addition, by utilizing the semiconductor device in a system for managing and distributing objects, the system can be multi-functionalized. For example, if a portable terminal including a display unit is provided with a reader / writer and a semiconductor device is provided on the article, the display unit displays the raw material, origin, distribution history, etc. of the article when the reader / writer is held over the semiconductor device. System. In addition, the system can be multifunctional and have high added value. As another example, if a reader / writer is provided on the side of the belt conveyor and a semiconductor device is provided on the article, the article can be inspected easily. And the system can be multi-functionalized. This embodiment can be freely combined with other embodiment modes and embodiments.

The semiconductor device of the present invention in which a pixel portion including a plurality of pixels is provided over a substrate can display an image using the pixel portion. Therefore, it is suitable for use in electronic equipment, and an example thereof will be described below.

The cellular phone device includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 21). The panel 2701 includes a pixel portion 2709 in which a plurality of pixels are arranged in a matrix and a functional circuit portion 2710, and these circuits are sealed by a pair of substrates. The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of IC chips corresponding to one or more selected from a central processing circuit (CPU), a controller circuit, a power supply circuit, a buffer amplifier, a source driver, and a gate driver are mounted on the printed wiring board 2703. A module corresponds to a state in which a printed wiring board 2703 is mounted on a panel.

The functional circuit portion 2710 is provided with the PLL circuit described in the above embodiment, in addition to the driver circuit that controls the pixel portion 2709. The PLL circuit has a function of keeping the frequency of the supplied signal constant and a function of controlling the frequency of the supplied signal. For example, in a PLL circuit, if the frequency of a signal is increased and a signal having the increased frequency is supplied to the drive circuit, the operation of the drive circuit can be increased. Further, even when the frequency of the input signal is not accurate, the PLL circuit can output a signal having an accurate frequency by synchronizing with the average frequency. Accordingly, even when the frequency of the input signal is not accurate, a signal with an accurate frequency can be supplied to the pixel portion 2709 and the driver circuit, and a desired image can be displayed in the pixel portion 2709. . Therefore, high functionality, multi-function, and high added value can be realized.

The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel portion 2709 included in the panel 2701 is arranged so that it can be seen from an opening window provided in the housing 2700.

Note that the casings 2700 and 2706 are examples of the external shape of the mobile phone device, and the electronic device according to the present embodiment can be transformed into various modes depending on the function and application. Therefore, an example of an aspect of the electronic device will be described below with reference to FIG.

A cellular phone device which is a portable terminal includes a pixel portion 9102 and the like (see FIG. 22A). A portable game device which is a portable terminal includes a pixel portion 9801 and the like (see FIG. 22B). The digital video camera includes pixel portions 9701 and 9702 and the like (see FIG. 22C). A PDA (personal digital assistant) which is a portable information terminal includes a pixel portion 9201 and the like (see FIG. 22D). The television device includes a pixel portion 9301 and the like (see FIG. 22E). The monitor device includes a pixel portion 9401 and the like (see FIG. 22F).

The present invention relates to a mobile phone device (also referred to as a mobile phone or simply a mobile phone), a PDA, an electronic notebook and a portable game machine, a television device (also referred to as a television or a television receiver), a display (monitor). It can also be applied to various electronic devices such as a digital camera, a digital video camera, a sound reproduction device such as a car audio, and a home game machine. This embodiment can be freely combined with other embodiment modes and embodiments.

As described above, the thin film transistor is used as the element constituting the voltage controlled oscillator. However, the element constituting the voltage controlled oscillator is not limited to the thin film transistor, and a MOS transistor may be used.

4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention. 4A and 4B illustrate a structure of a semiconductor device of the invention.

Claims (25)

Having a voltage controlled oscillator provided on the substrate;
The voltage controlled oscillator has a first circuit, a second circuit, a third circuit, and a fourth circuit,
The first circuit includes a first N-type thin film transistor and a first P-type thin film transistor,
The second circuit includes a second N-type thin film transistor,
The third circuit has a second P-type thin film transistor,
The fourth circuit includes a third N-type thin film transistor and a third P-type thin film transistor,
One of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the first P-type thin film transistor,
The other of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the second N-type thin film transistor,
The other of the source and drain of the first P-type thin film transistor is connected to one of the source and drain of the second P-type thin film transistor,
One of the source and drain of the third N-type thin film transistor is connected to one of the source and drain of the third P-type thin film transistor,
The other of the source and drain of the second N-type thin film transistor and the other of the source and drain of the third N-type thin film transistor are connected to a low potential power source,
The other of the source and drain of the second P-type thin film transistor and the other of the source and drain of the third P-type thin film transistor are connected to a high potential power source,
The threshold voltage of the second N-type thin film transistor is lower than the threshold voltage of the first N-type thin film transistor,
The threshold voltage of the third N-type thin film transistor is lower than the threshold voltage of the first N-type thin film transistor,
A first signal is input to the gate of the second N-type thin film transistor and the gate of the third N-type thin film transistor;
2. A semiconductor device, wherein a second signal is output from one of a source and a drain of the first N-type thin film transistor and one of a source and a drain of the first P-type thin film transistor. Having a voltage controlled oscillator provided on the substrate;
The voltage controlled oscillator has a first circuit and a second circuit,
The first circuit includes a first N-type thin film transistor and a P-type thin film transistor,
The second circuit includes a second N-type thin film transistor,
One of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the P-type thin film transistor,
The other of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the second N-type thin film transistor,
The other of the source and the drain of the second N-type thin film transistor is connected to a low potential power source,
The other of the source and drain of the P-type thin film transistor is connected to a high potential power source,
The threshold voltage of the second N-type thin film transistor is lower than the threshold voltage of the first N-type thin film transistor,
A first signal is input to a gate of the second N-type thin film transistor;
2. A semiconductor device, wherein a second signal is output from one of a source or a drain of the first N-type thin film transistor and one of a source or a drain of the P-type thin film transistor. Having a voltage controlled oscillator provided on the substrate;
The voltage controlled oscillator has a first circuit, a second circuit, a third circuit, and a fourth circuit,
The first circuit includes a first N-type thin film transistor and a first P-type thin film transistor,
The second circuit includes a second N-type thin film transistor,
The third circuit has a second P-type thin film transistor,
The fourth circuit includes a third N-type thin film transistor and a third P-type thin film transistor,
One of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the first P-type thin film transistor,
The other of the source and drain of the first N-type thin film transistor is connected to one of the source and drain of the second N-type thin film transistor,
The other of the source and drain of the first P-type thin film transistor is connected to one of the source and drain of the second P-type thin film transistor,
One of the source and drain of the third N-type thin film transistor is connected to one of the source and drain of the third P-type thin film transistor,
The other of the source and drain of the second N-type thin film transistor and the other of the source and drain of the third N-type thin film transistor are connected to a low potential power source,
The other of the source and drain of the second P-type thin film transistor and the other of the source and drain of the third P-type thin film transistor are connected to a high potential power source,
The threshold voltage of the second P-type thin film transistor is higher than the threshold voltage of the first P-type thin film transistor,
The threshold voltage of the third P-type thin film transistor is higher than the threshold voltage of the first P-type thin film transistor,
A first signal is input to the gate of the second P-type thin film transistor and the gate of the third P-type thin film transistor;
2. A semiconductor device, wherein a second signal is output from one of a source and a drain of the first N-type thin film transistor and one of a source and a drain of the first P-type thin film transistor. Having a voltage controlled oscillator provided on the substrate;
The voltage controlled oscillator has a first circuit and a second circuit,
The first circuit includes an N-type thin film transistor and a first P-type thin film transistor,
The second circuit has a second P-type thin film transistor,
One of the source and drain of the first P-type thin film transistor is connected to one of the source and drain of the N-type thin film transistor,
The other of the source and drain of the first P-type thin film transistor is connected to one of the source and drain of the second P-type thin film transistor,
The other of the source and the drain of the second P-type thin film transistor is connected to a low potential power source,
The other of the source and drain of the N-type thin film transistor is connected to a high potential power source,
The threshold voltage of the second P-type thin film transistor is higher than the threshold voltage of the first P-type thin film transistor,
A first signal is input to a gate of the second P-type thin film transistor;
2. A semiconductor device, wherein a second signal is output from one of a source or a drain of the N-type thin film transistor and a source or a drain of the first P-type thin film transistor. In claim 1,
The channel length of the second N-type thin film transistor is shorter than the channel length of the first N-type thin film transistor,
The channel length of the third N-type thin film transistor is shorter than the channel length of the first N-type thin film transistor. In claim 1,
The first N-type thin film transistor includes a first semiconductor layer including a first channel formation region,
The second N-type thin film transistor includes a second semiconductor layer including a second channel formation region,
The third N-type thin film transistor includes a third semiconductor layer including a third channel formation region,
The concentration of the impurity element imparting N-type in the second channel formation region is higher than the concentration of the impurity element imparting N-type in the first channel formation region,
The semiconductor device is characterized in that the concentration of the impurity element imparting N-type in the third channel formation region is higher than the concentration of the impurity element imparting N-type in the first channel formation region. In claim 1,
The first N-type thin film transistor includes a first semiconductor layer including a first channel formation region,
The second N-type thin film transistor includes a second semiconductor layer including a second channel formation region,
The third N-type thin film transistor includes a third semiconductor layer including a third channel formation region,
The concentration of the impurity element imparting P-type in the second channel formation region is lower than the concentration of the impurity element imparting P-type in the first channel formation region,
The semiconductor device is characterized in that the concentration of the impurity element imparting P-type in the third channel formation region is lower than the concentration of the impurity element imparting P-type in the first channel formation region. In claim 1 or claim 3,
The first circuit includes a plurality of the first N-type thin film transistors and the first P-type thin film transistors,
The second circuit includes a plurality of the second N-type thin film transistors,
The semiconductor device, wherein the third circuit includes a plurality of the second P-type thin film transistors. In claim 2,
The semiconductor device according to claim 1, wherein a channel length of the second N-type thin film transistor is shorter than a channel length of the first N-type thin film transistor. In claim 2,
The first N-type thin film transistor includes a first semiconductor layer including a first channel formation region,
The second N-type thin film transistor includes a second semiconductor layer including a second channel formation region,
The semiconductor device is characterized in that the concentration of the impurity element imparting N-type in the second channel formation region is higher than the concentration of the impurity element imparting N-type in the first channel formation region. In claim 2,
The first N-type thin film transistor includes a first semiconductor layer including a first channel formation region,
The second N-type thin film transistor includes a second semiconductor layer including a second channel formation region,
The semiconductor device is characterized in that the concentration of the impurity element imparting P-type in the second channel formation region is lower than the concentration of the impurity element imparting P-type in the first channel formation region. In claim 2,
The first circuit includes a plurality of the first N-type thin film transistors and the P-type thin film transistors,
The second circuit includes a plurality of the second N-type thin film transistors. In claim 3,
The channel length of the second P-type thin film transistor is shorter than the channel length of the first P-type thin film transistor,
The channel length of the third P-type thin film transistor is shorter than the channel length of the first P-type thin film transistor. In claim 3,
The first P-type thin film transistor includes a first semiconductor layer including a first channel formation region,
The second P-type thin film transistor includes a second semiconductor layer including a second channel formation region,
The third P-type thin film transistor has a third semiconductor layer including a third channel formation region,
The concentration of the impurity element imparting P-type in the second channel formation region is higher than the concentration of the impurity element imparting P-type in the first channel formation region,
The semiconductor device is characterized in that the concentration of the impurity element imparting P-type in the third channel formation region is higher than the concentration of the impurity element imparting P-type in the first channel formation region. In claim 3,
The first P-type thin film transistor includes a first semiconductor layer including a first channel formation region,
The second P-type thin film transistor includes a second semiconductor layer including a second channel formation region,
The third P-type thin film transistor has a third semiconductor layer including a third channel formation region,
The concentration of the impurity element imparting N-type in the second channel formation region is lower than the concentration of the impurity element imparting N-type in the first channel formation region,
The semiconductor device is characterized in that the concentration of the impurity element imparting N-type in the third channel formation region is lower than the concentration of the impurity element imparting N-type in the first channel formation region. In claim 4,
The semiconductor device, wherein a channel length of the second P-type thin film transistor is shorter than a channel length of the first P-type thin film transistor. In claim 4,
The first P-type thin film transistor includes a first semiconductor layer including a first channel formation region,
The second P-type thin film transistor includes a second semiconductor layer including a second channel formation region,
The semiconductor device is characterized in that the concentration of the impurity element imparting P-type in the second channel formation region is higher than the concentration of the impurity element imparting P-type in the first channel formation region. In claim 4,
The first P-type thin film transistor includes a first semiconductor layer including a first channel formation region,
The second P-type thin film transistor includes a second semiconductor layer including a second channel formation region,
The semiconductor device is characterized in that the concentration of the impurity element imparting N-type in the second channel formation region is lower than the concentration of the impurity element imparting N-type in the first channel formation region. In claim 4,
The first circuit includes a plurality of the N-type thin film transistors and the first P-type thin film transistors,
The second circuit includes a plurality of the second P-type thin film transistors. In any one of Claims 1 to 19,
A semiconductor device comprising a phase comparator, a loop filter, and a frequency divider provided on the substrate. In any one of Claims 1 to 19,
A phase comparator, a loop filter and a frequency divider provided on the substrate;
The first signal is a signal generated by the loop filter;
The semiconductor device, wherein the second signal is supplied to the frequency divider. In any one of Claims 1 to 19,
The semiconductor device is characterized in that the substrate is made of glass or plastic. In any one of Claims 1 to 19,
A semiconductor device comprising an antenna provided over the substrate. In any one of Claims 1 to 19,
A pixel portion including a plurality of pixels provided on the substrate;
Each of the plurality of pixels includes a liquid crystal element or a light emitting element. An electronic apparatus using the semiconductor device according to any one of claims 1 to 24.

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