JP2006270652A - Load driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that setting a high clamp voltage causes an increase in power consumption in an FET for driving a load, resulting in an increase in the peak temperature of the FET. <P>SOLUTION: A load driving circuit 1 is provided with an FET 10, a clamp circuit 20, and a control circuit 30. The FET 10 is a transistor for driving a load 90. The clamp circuit 20 is connected between a gate and a drain of the FET 10. The clamp circuit 20 interrupts the flow of carries from the gate to the drain when a voltage between the gate and the drain of the FET 10 is not higher than a predetermined clamp voltage, and permits the flow of carriers from the gate to the drain when the voltage between the gate and the drain is higher than the predetermined clamp voltage. The control circuit 30 controls the magnitude of the clamp voltage on the basis of a previously set program. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a load driving circuit.

As a conventional load driving circuit, for example, there is one described in Patent Document 1. The load drive circuit described in the document includes a load drive FET (field effect transistor) and a clamp circuit connected between the gate and drain thereof. The clamp circuit limits the voltage between the gate and the drain so as not to exceed a predetermined clamp voltage.
JP 2002-84174 A

  In the load driving circuit, it is desirable that the current off time, which is the time from when the load driving FET is turned off to when the current flowing through the load actually becomes zero, is as short as possible. Such shortening of the current off time can be realized by setting the clamp voltage high. However, if the clamp voltage is set high, the power consumption in the FET for driving the load increases, thereby increasing the peak temperature of the FET.

  A load driving circuit according to the present invention is connected between a field effect transistor that drives a load and a gate and a drain of the field effect transistor, and a gate-drain voltage that is a voltage between the gate and the drain is a predetermined value. When the voltage is lower than the clamp voltage, the flow of carriers from the gate to the drain is interrupted, and when the gate-drain voltage exceeds the clamp voltage, a clamp circuit that allows the carrier flow, and the magnitude of the clamp voltage And a control circuit for controlling.

  As described above, when the clamp voltage is set high to shorten the current off time, the peak temperature of the field effect transistor increases. That is, the current off time and the peak temperature are in a trade-off relationship. Here, the load driving circuit includes a control circuit that controls the magnitude of the clamp voltage. For this reason, by controlling the magnitude of the clamp voltage within a range where the peak temperature does not exceed the allowable upper limit value, the current off time can be shortened while suppressing an increase in the peak temperature.

  The control circuit may control the magnitude of the clamp voltage according to a preset program. In this case, the clamp voltage can be controlled with a simple configuration.

  According to the present invention, a load driving circuit capable of shortening the current off time while suppressing an increase in the peak temperature of the load driving transistor is realized.

  Hereinafter, a preferred embodiment of a load driving circuit according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  FIG. 1 is a block diagram showing an embodiment of a load driving circuit according to the present invention. FIG. 2 is a circuit configuration diagram showing an example of the configuration of the load drive circuit of FIG. The load drive circuit 1 includes an FET 10, a clamp circuit 20, a control circuit 30, a gate control terminal 50, and a load connection terminal 60. One end of a load 90 is connected to the load connection terminal 60. The other end of the load 90 is connected to the power supply terminal 92. The potential (power supply potential) applied to the power supply terminal 92 is, for example, 12V.

  The FET 10 is a transistor for driving the load 90. In this embodiment, the conductivity type of the FET 10 is an N type. The source and drain of the FET 10 are connected to the ground and the load connection terminal 60, respectively. Further, the gate of the FET 10 is connected to the gate control terminal 50 through the resistance element 52. The gate control terminal 50 is a terminal for inputting a control signal for controlling the gate of the FET 10. The FET 10 is turned on / off by the control signal.

  A clamp circuit 20 is connected between the gate and drain of the FET 10. That is, one end of the clamp circuit 20 is connected to the gate of the FET 10 and the other end is connected to the drain. The clamp circuit 20 blocks the flow of carriers (electrons in the present embodiment) from the gate to the drain when the gate-drain voltage of the FET 10 is equal to or lower than a predetermined clamp voltage. On the other hand, when the gate-drain voltage exceeds the clamp voltage, the clamp circuit 20 allows carriers to flow from the gate to the drain. In other words, when the gate-drain voltage is equal to or lower than the clamp voltage, the clamp circuit 20 cuts off the current flowing from the drain to the gate through the clamp circuit 20, while the gate-drain voltage is When the clamp voltage is exceeded, a current that flows from the drain to the gate through the clamp circuit 20 is passed. The clamp circuit 20 is configured such that the clamp voltage is variable.

  As shown in FIG. 2, the clamp circuit 20 includes a plurality (eight in this example) of Zener diodes 22 connected in series with each other. The Zener voltage of the Zener diode 22 is, for example, 7.5V. In FIG. 4, four of eight Zener diodes 22 are provided with transfer gates 24 connected in parallel with each Zener diode 22. The transfer gate 24 is a P-type FET, and its source and drain are connected to the cathode and anode of the Zener diode 22, respectively. A resistance element 26 is connected between the source and gate of each transfer gate 24.

  In the clamp circuit 20 having such a configuration, when the voltage applied to each Zener diode 22 is equal to or lower than the Zener voltage, the flow of carriers from the gate of the FET 10 to the drain (the anode to the cathode of the Zener diode 22) is blocked by the Zener diode 22. Is done. However, the Zener diode 22 provided with the transfer gate 24 contributes to the blocking of the carrier when the transfer gate 24 is in the OFF state, while the carrier is blocked when the transfer gate 24 is in the ON state. Does not contribute. This is because in the latter case, the carrier can flow from the anode to the cathode of the Zener diode 22 through the transfer gate 24.

  Therefore, in the clamp circuit 20, the number of Zener diodes 22 that contribute to blocking the flow of carriers from the gate to the drain of the FET 10 can be changed by switching the transfer gate 24 on and off. For example, if all of the four transfer gates 24 are in the OFF state, the number of Zener diodes 22 that contributes to blocking the carrier flow is eight. If one of the four transfer gates 24 is in an on state and the other three are in an off state, the number of Zener diodes 22 that contribute to blocking the carrier flow is seven. At this time, the clamp voltage of the clamp circuit 20 is equal to the sum of the Zener voltages of the Zener diodes 22 that contribute to the blockage of the carrier flow.

  The control circuit 30 controls the magnitude of the clamp voltage of the clamp circuit 20. In the present embodiment, the control circuit 30 controls the magnitude of the clamp voltage based on a preset program. Specifically, the control circuit 30 controls the magnitude of the clamp voltage so that the temperature of the FET 10 approaches a predetermined target value according to the program. That is, the control circuit 30 controls the clamp voltage so that the temperature is maintained near the target value during the dynamic clamp period. This target value is set lower than the allowable upper limit value of the temperature of the FET 10. Here, the allowable upper limit value is an upper limit value of a temperature range in which normal operation of the FET 10 is ensured, and is 150 ° C., for example. The program may be configured such that the inductance and resistance values of the load 90 are given as arguments.

  As shown in FIG. 2, the control circuit 30 includes a switch control unit 32 and a counter 34. The switch control unit 32 includes a storage circuit that stores the program used for controlling the clamp voltage, and a driver that controls the gate of the transfer gate 24 of the clamp circuit 20. The memory circuit is, for example, FLASH or ROM. The driver is connected to the gate of each transfer gate 24. A signal from the counter 34 is input to the switch control unit 32. In the switch control unit 32, when a certain count is reached according to the program, the control signal sent from the driver to the gate of each transfer gate 24 is changed.

In this example, the combinations of the control signals are (i) (1, 1, 1, 1), (ii) (0, 1, 1, 1), (iii) (0, 0, 1, 1), ( iv) There are five ways (0, 0, 0, 1) and (v) (0, 0, 0, 0). The meaning of each combination is as follows.
(I) Turn off all four transfer gates 24 (ii) Turn on one of the four transfer gates 24 and turn off the other three (iii) Two of the four transfer gates 24 Turn on and turn off the other two (iv) turn on three of the four transfer gates 24 and turn off the other one (v) turn on all four transfer gates 24

  The combinations (i) to (v) correspond to cases where the number of Zener diodes 22 contributing to the blockage of the carrier flow in the clamp circuit 20 is 8, 7, 6, 5, 4. As described above, the control circuit 30 changes the number of the Zener diodes 22 that contribute to the interruption of the carrier flow among the plurality of Zener diodes 22 provided in the clamp circuit 20, thereby increasing the clamp voltage of the clamp circuit 20. Change the size. The control circuit 30 switches whether the Zener diode 22 connected to the transfer gate 24 contributes to the interruption of the carrier flow by switching the transfer gate 24 on and off.

  As described above, in the program, the initial value of the clamp voltage and the control pattern for changing the clamp voltage to what count are set.

An example of clamp voltage control by the control circuit 30 will be described with reference to FIG. In the graph of the figure, the vertical axis and the horizontal axis represent the clamp voltage V and time t, respectively. In this example, first, the clamping voltage is set to V _4. Thereafter, as time elapses, the clamp voltage is controlled to increase stepwise in the order of V ₅ , V ₆ , V ₇ , and V ₈ . V ₄ , V ₅ , V ₆ , V ₇ , and V ₈ correspond to cases where the number of Zener diodes 22 that contribute to the blockage of the carrier flow is ₄ , ₅ , ₆ , ₇ , and ₈ , respectively. Such a control pattern can be suitably applied when an SOI substrate having a lower heat dissipation than a silicon substrate is used as the semiconductor substrate on which the FET 10 is formed.

  Next, the effect of the load driving circuit 1 will be described. The load drive circuit 1 includes a control circuit 30 that controls the magnitude of the clamp voltage of the clamp circuit 20. For this reason, by controlling the magnitude of the clamp voltage in a range where the peak temperature of the FET 10 does not exceed the allowable upper limit value, the current off time can be shortened while suppressing an increase in the peak temperature.

On the other hand, in the load driving circuit described in Patent Document 1, since the configuration for controlling the magnitude of the clamp voltage is not provided, the clamp voltage is always constant during the dynamic clamp period when the output is off. Therefore, the output voltage and output current of the load driving circuit change as shown in FIG. Here, the output voltage is a voltage on the drain side (the side to which the load is connected) of the load driving FET, and the output current is a current flowing therethrough. In the figure, broken lines L1 and L2 indicate changes in output voltage and output current, respectively. Times t ₀ and t ₁ represent the time when the FET is turned off and the time when the output current becomes zero, respectively. Therefore, (t ₁ -t ₀ ) is the current off time.

As shown in the figure, at the moment when the FET is turned off, the load keeps flowing current, so that the output voltage rises rapidly. When the output voltage exceeds the clamp voltage, a current flows from the drain to the gate of the FET through the clamp circuit, so that the FET is turned on. Thereby, the energy accumulated in the load is dissipated in the FET, the output voltage with the output current becomes zero eventually at time t ₁ is equal to the supply voltage.

Further, the temperature change of the FET during the dynamic clamping period is approximately as shown in FIG. That is, the temperature of the FET is gradually increased from the clamp start, after reaching the peak temperature T _0, it descends gradually.

On the other hand, when the clamp voltage is controlled by the control circuit 30 in the load driving circuit 1 as shown in FIG. 3, the temperature change of the FET 10 during the dynamic clamping period is substantially as shown in FIG. That is, the temperature of the FET10 is hovering near the target value _{T a.} In the load driving circuit 1, the clamp voltage is relatively large when the FET temperature is relatively low in the conventional temperature profile (see FIG. 5A), and the clamp voltage is relatively high when the FET temperature is relatively high. This is because it is controlled to be relatively small. Due to such control, the state in which the energy consumption in the FET 10 is large is maintained, so that the energy accumulated in the load 90 is consumed in a short time. Thereby, reduction of the current off time is realized.

  The control circuit 30 controls the magnitude of the clamp voltage according to a preset program. As a result, the clamp voltage can be controlled with a simple configuration. However, in the load driving circuit 1, it is not essential to control the clamp voltage according to the program. For example, a temperature measurement unit that measures the temperature of the FET 10 may be provided, and the control circuit 30 may be configured to control the magnitude of the clamp voltage based on the output of the temperature measurement unit.

  The control circuit 30 controls the magnitude of the clamp voltage so that the temperature of the FET 10 approaches a predetermined target value according to the program. Thus, when the temperature of the FET 10 is relatively low, the clamp voltage is increased to increase the energy consumption in the FET 10, and when the temperature of the FET 10 is relatively high, the clamp voltage is decreased to reduce the energy consumption in the FET 10. By controlling so, the current off time can be more effectively shortened.

  The clamp circuit 20 includes a plurality of Zener diodes 22 connected in series with each other. Thereby, the clamp circuit 20 can be realized with a simple configuration.

  The control circuit 30 changes the magnitude of the clamp voltage by changing the number of the Zener diodes 22 that contribute to blocking the carrier flow among the plurality of Zener diodes 22. Thereby, the magnitude | size of a clamp voltage can be changed with a simple mechanism.

  The control circuit 30 switches whether or not the Zener diode 22 connected to the transfer gate 24 contributes to the blockage of the carrier flow by switching the transfer gate 24 on and off. Thereby, the number of stages of the clamp circuit can be easily changed.

  When FLASH is used as the memory circuit of the control circuit 30, the program can be rewritten.

  When the program is configured such that the inductance and resistance values of the load 90 are given as arguments, the control circuit 30 can control the clamp voltage according to the characteristics of the load 90 connected to the load connection terminal 60. it can. Thereby, the load drive circuit 1 with high versatility is realized.

  A simulation result in which the effect of the load drive circuit 1 is confirmed will be described with reference to FIGS. FIGS. 6, 7 and 8 show the results when the clamp voltage is not controlled during the dynamic clamp period and is kept constant, and corresponds to the case where the Zener diode has four, five and six stages, respectively. On the other hand, FIG. 9 shows the result when the clamp voltage is controlled according to the program. In each figure, graphs C1, C2, and C3 indicate the temperature, output voltage, and output current of the load driving FET, respectively. The vertical axis represents temperature (° C.), voltage (V), and current (A), and the horizontal axis represents time (s).

  In this simulation, the inductance and resistance of the load 90 are 15 mH and 12Ω, respectively. The power supply voltage of the power supply terminal 92 is 14V. The Zener voltage of each Zener diode is about 7.5V. Accordingly, in FIGS. 6, 7 and 8, the clamp voltages are about 30V, 37.5V and 45V, respectively.

  Table 1 summarizes the simulation results. A in the table indicates the result in FIG. 9, that is, when the clamp voltage is controlled. B, C, and D in the table correspond to FIGS. For example, referring to FIG. 6, the load driving transistor is turned off when the time is 10.0 ms, and the output voltage is settled at the power supply voltage when the time is 10.65 ms. Therefore, the current off time at this time is 650 μs as shown in the table. Regarding the temperature, since the temperature immediately before turning off the FET is 5 ° C. and the peak temperature during the dynamic clamping period is 38 ° C., the temperature increase width is 33 ° C. As can be seen from a comparison of FIGS. 6 to 8, as the clamp voltage is set higher, the current off time can be shortened, but the peak temperature (temperature rise width) becomes larger.

In contrast, in FIG. 9, the clamp voltage is switched during the dynamic clamp period. In this simulation, the program is set so that the number of Zener diodes that contribute to carrier blocking can be switched from four to eight stages. As shown in the figure, the output voltage also changes stepwise as the clamp voltage changes. At this time, the current off time was 480 μm, and the temperature rise was 33 ° C. From this result, it can be seen that by controlling the clamp voltage, the current off time can be shortened while suppressing an increase in peak temperature.

  The load driving circuit according to the present invention is not limited to the above embodiment, and various modifications can be made. For example, although the example in which the FET 10 is connected to the low side of the load 90 has been described in the above embodiment, the FET 10 may be connected to the high side of the load 90 as shown in FIG. In the load driving circuit 2, the conductivity type of the FET 10 is P type. The source and drain of the FET 10 are connected to the power supply terminal 92 and the load connection terminal 60, respectively.

  Similar to the load driving circuit 1, a clamp circuit 20 is connected between the gate and drain of the FET 10. The clamp circuit 20 blocks the flow of carriers (holes in this example) from the gate to the drain when the gate-drain voltage of the FET 10 is equal to or lower than a predetermined clamp voltage. On the other hand, when the gate-drain voltage exceeds the clamp voltage, the clamp circuit 20 allows carriers to flow from the gate to the drain. In the load drive circuit 2, the cathode side of the Zener diode 22 included in the clamp circuit 20 is connected to the gate of the FET 10, and the anode side is connected to the drain of the FET 10.

  Further, the load drive circuits 1 and 2 may be provided on both sides of the load 90, respectively. That is, the load driving circuit 1 may be provided on the low side of the load 90 and the load driving circuit 2 may be provided on the high side.

  The number of Zener diodes 22 provided in the clamp circuit 20 is not limited to eight and may be any number as long as it is plural. In the above embodiment, the transfer gate 24 is provided in only a part of the plurality of Zener diodes 22. However, the transfer gates 24 may be provided in all the Zener diodes 22.

The control of the clamp voltage by the control circuit 30 is not limited to that described with reference to FIG. 3, and can be performed in various patterns. FIG. 11 is a graph for explaining a modification of the clamp voltage control by the control circuit 30. In this example, first, the clamping voltage is set to V _8. Thereafter, as time elapses, the clamp voltage is controlled to gradually decrease in the order of V ₇ , V ₆ , V ₅ , and V ₄ . The clamp voltage is controlled to increase stepwise after decreasing to V _{4 in} the order of V ₅ , V ₆ , V ₇ , and V ₈ . Such a control pattern can be suitably applied when a silicon substrate having better heat dissipation than an SOI substrate is used as a semiconductor substrate on which the FET 10 is formed.

It is a block diagram which shows one Embodiment of the load drive circuit by invention. FIG. 2 is a circuit configuration diagram illustrating an example of a configuration of a load driving circuit in FIG. 1. It is a graph for demonstrating an example of control of the clamp voltage by a control circuit. It is a graph which shows typically change of output voltage and output current in the conventional load drive circuit. (A) is a graph which shows typically the temperature change of load drive FET in the conventional load drive circuit. (B) is a graph schematically showing a temperature change of the load driving FET in the load driving circuit of FIG. 1. It is a graph which shows the simulation result of the load drive circuit concerning a comparative example. It is a graph which shows the simulation result of the load drive circuit concerning a comparative example. It is a graph which shows the simulation result of the load drive circuit concerning a comparative example. It is a graph which shows the simulation result of the load drive circuit concerning an embodiment. It is a block diagram which shows the load drive circuit which concerns on the modification of embodiment. It is a graph for demonstrating the modification of control of the clamp voltage by a control circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Load drive circuit 2 Load drive circuit 10 FET
20 Clamp Circuit 22 Zener Diode 24 Transfer Gate 26 Resistive Element 30 Control Circuit 32 Switch Control Unit 34 Counter 50 Gate Control Terminal 52 Resistive Element 60 Load Connection Terminal 90 Load 92 Power Supply Terminal

Claims (6)

A field effect transistor driving the load;
It is connected between the gate and drain of the field effect transistor, and when the gate-drain voltage, which is the voltage between the gate and the drain, is below a predetermined clamp voltage, the flow of carriers from the gate to the drain is cut off. And a clamp circuit that allows the carrier to flow when the gate-drain voltage exceeds the clamp voltage;
A control circuit for controlling the magnitude of the clamp voltage;
A load driving circuit comprising: The load driving circuit according to claim 1,
The control circuit is a load drive circuit that controls the magnitude of the clamp voltage according to a preset program. The load driving circuit according to claim 2,
The control circuit is a load driving circuit that controls the magnitude of the clamp voltage so that the temperature of the field effect transistor approaches a predetermined target value in accordance with the program. The load driving circuit according to any one of claims 1 to 3,
The clamp circuit includes a plurality of Zener diodes connected in series with each other. The load driving circuit according to claim 4,
The control circuit is a load drive circuit that changes the magnitude of the clamp voltage by changing the number of Zener diodes that contribute to blocking the carrier flow among the plurality of Zener diodes. The load driving circuit according to claim 5,
For some or all of the plurality of Zener diodes, comprising a transfer gate connected in parallel with each Zener diode,
The control circuit is a load drive circuit that switches whether or not the Zener diode connected to the transfer gate contributes to blockage of the carrier flow by switching on and off the transfer gate.