JP2006254170A - Ota circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To expand an amplification range of an input signal in which transconductance operates at a constant value in an OTA with adjustable transconductance. <P>SOLUTION: Third and fourth transistors (M3 and M4) are connected between the sources of first and second transistors (M1 and M2), and control signals generated by transistors (M5 and M6) of a control circuit 11 are fed back to gate electrodes of the third and fourth transistors, respectively on the basis of source potential of the first and second transistors. Consequently, it is possible to expand a linear area for an amount corresponding to amplitude of an AC component of a feedback signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an OTA circuit capable of adjusting transconductance (gm), and more particularly to an OTA circuit capable of improving linearity of transconductance.

The structure of transconductance control in OTA is a circuit described in Non-Patent Document 1 below. Generally, a control transistor M3 is arranged between source electrodes of input transistors M1 and M2 as shown in FIG. The resistance value was changed by controlling the gate voltage of M3.
CMOS analog circuit design technology, supervised by Satoshi Iwata, published by Nov. 13, 1998 (PP.152-153) JP-A-8-242130

FIG. 4 is a circuit diagram for explaining the operation principle of a conventional OTA circuit. The difference from FIG. 3 is that a resistor R is connected between the source electrodes of the input transistors M1 and M2 instead of the control transistor M3. It is a point. In this case, the output current of the OTA circuit is expressed by the following equation.
Iout = gm * Vin (1)
Where Vin is the differential input voltage of OTA, and gm is the transconductance as OTA.

As in the case of FIG. 4, when the circuit is completely targeted, the output current is expressed by the following equation.
Iout = Iout1-Iout2 = Vin / {R + (2 / gm (M1))}
(2)
However, gm (M1) is the transconductance of the input transistors M1 and M2.

From the expression (2), it can be confirmed that the output current Iout of the OTA greatly depends on the value of the resistor R. The circuit shown in FIG. 3 is obtained by replacing the resistor R with a MOS transistor (M3). By controlling the gate voltage of the transistor M3, the equivalent resistance value of the transistor M3, that is, the output current can be adjusted. In this case, an expression corresponding to the expression (2) is as follows.
Iout = Iout1-Iout2 = Vin / {R (MOS) + (2 / gm (M1))}
.... (3)
However, R (MOS) is the equivalent resistance value of the transistor M3, and gm (M1) is the transconductance of the input transistors M1 and M2.

In the circuit configuration of FIG. 3, the equivalent resistance of the control transistor M3 is often used under the condition of the linear region formula of the MOS transistor expressed by the following formula (4). The linear region of the MOS transistor is generally expressed by the following equation.
VDS <VGS−Vth (4)
Or
VD <VG−Vth (4) ′
However, VDS is a drain-source potential of the transistor M3, VGS is a gate-source potential, and Vth is a threshold value.

Under the condition of the equation (4), the value of the equivalent resistance R (MOS) of the transistor M3 can be expressed by the following equation.
R (MOS) ≈ (VGS−Vth) / μ * Co * (W / L) (5)
Where μ is the carrier mobility, Co is the capacitance of the MOS transistor, and W / L is the aspect ratio of the MOS transistor.

The equivalent resistance value represented by Expression (5) operates as a substantially linear resistance under the condition of Expression (4) (or Expression (4) ′). However, when a large-amplitude input signal is input to the input transistors M1 and M2, the source potentials of M1 and M2 greatly fluctuate. When a sin waveform signal having a phase difference of 180 ° is input to the gates of M1 and M2, and the control voltage applied to the gate electrode of the control transistor M3 is Vcont, the source potential of M1 is
VM1s (t) = Asin (ωt) + Vdc
Where Vdc is the level of the DC potential and A is a constant representing the amplitude,
The source potential of M2 is
VM2s (t) = Asin (ωt−π) + Vdc
And Using the source potential VM1s of the input transistor M1 and the source potential VM2s of the input transistor M2 and substituting it into equation (4) ′, which is an equivalent equation of equation (4),
VD = VM2s = Asin (ωt−π) + Vdc,
VG = Vcont
Because
Asin (ωt−π) <Vcont−Vdc−Vth (6)
The relationship is obtained.

From the above equation (6), in order for the transistor M5 to operate in the linear region for all angular frequencies ω,
| Sin (ωt−π) | ≦ 1
From the relationship, it can be seen that the value of the amplitude A needs to satisfy the following expression.
A <(Vcont−Vdc−Vth) (7)

  When the amplitude of the input signal becomes a large amplitude signal that does not satisfy the above equation (7), the operation region of the MOS transistor M3 shifts from the linear region operation to the non-linear region operation, so that the linear operation of the circuit is lost. . For this reason, the equivalent resistance value of the MOS transistor M3 cannot be expressed by the equation (5) with respect to the input signal, and the linearity of the transconductance is lost.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to expand the amplitude range of an input signal in which transconductance operates at a constant value in an OTA capable of adjusting transconductance.

In the OTA circuit according to the present invention, first and second input terminals for inputting the first and second input signals, respectively, and a first differential pair comprising a gate electrode connected to the input terminal, respectively. And a second transistor, forming a first output signal corresponding to the first input signal at the drain of the second transistor and a second input signal at the drain of the first transistor. A differential amplifier that forms a second output signal corresponding to the first and second output signals and forms a differential output signal by the first and second output signals, and is connected between the source electrodes of the first transistor and the second transistor First variable resistance means for variably controlling a resistance value by a first control signal based on a signal of the source electrode of the first transistor, and a source of the first transistor and the second transistor. Is connected between the electrodes, and the second variable resistance means for variably controlling the resistance value by a second control signal based on the signal of the source electrode of the second transistor,
And a control unit for forming the first and second control signals.

  In the OTA circuit according to the present invention, the first and second transistors are configured by first-conductivity-type MOS transistors, and the first variable resistance means has a drain electrode as a source electrode of the second transistor. And a source electrode connected to the source electrode of the first transistor as a first conductivity type MOS transistor (third transistor). The second variable resistance means includes a drain electrode connected to the first transistor. And a first conductivity type MOS transistor (fourth transistor) having a source electrode connected to a source electrode of the second transistor and a source electrode connected to the source electrode of the second transistor. MOS transistors of the first conductivity type that form a differential pair by connecting the source electrode signals of the two transistors to the gate electrodes, respectively. The output signal from the drain electrode of the fifth transistor is connected to the gate electrode of the third transistor as a first control signal, and the drain of the sixth transistor An output signal from the electrode is connected to the gate electrode of the fourth transistor as a second control signal.

  In the OTA circuit according to the present invention, the third and fourth transistors are connected between the sources of the first and second transistors, and control signals generated based on the source potentials of the first and second transistors are respectively received. Since the feedback is made to the gate electrodes of the third and fourth transistors constituting the first and second variable resistance means, the linear region can be expanded by an amount corresponding to the amplitude of the AC component of the feedback signal. It becomes.

  Embodiments of the present invention will be described below with reference to the drawings. The drawings are merely schematically shown so that the contents of the present invention can be understood.

  FIG. 1 is a block diagram showing a configuration of an OTA circuit 10 according to the embodiment. A control MOS transistor M4 is added to a conventional OTA circuit (see FIG. 3), and a control transistor M3 ( A control circuit 11 for generating gate voltages of M4 (which constitutes the second variable resistance means) and M4 (which constitutes the second variable resistance means) is added. The transistors M9 and M10 in FIG. 1 are active loads, and a fixed potential Vb that operates as such an active load is applied to the commonly connected gate electrodes.

  FIG. 2 is a circuit diagram showing a detailed configuration of the control circuit 11, and includes two sets of subordinate connections of two MOS transistors (a set of (M5, M6) and a set of (M7, M8)) having different conductivity types. It has a circuit. The MOS transistors M5 and M6 are NMOS transistors, and M7 and M8 are PMOS transistors.

  The sources of the transistors M7 and M8 are connected to the power supply potential, and a common DC potential Vontl is applied to their gate electrodes in order to control the transconductance of OTA. The voltage Vcont1 is adjusted so that the DC level of the drain nodes of the transistors M5 and M6 is the same level as the control voltage Vcont in the circuit of FIG.

  The gate terminal 3 of the transistor M5 and the gate terminal 4 of the transistor M6 are connected to the nodes on the source side of the NMOS transistors M1 and M2, which are OTA input transistors, respectively, and the drain terminal 2 of the transistor M5 and the drain terminal of the transistor M6. 5 are connected to the gates of the control transistors M3 and M4, respectively.

The operation of the OTA circuit configured as described above will be described below. First, when sinusoidal signals that are 180 degrees out of phase are input to the gates of the input transistors M1 and M2, the source potentials of these transistors are respectively
VM1s (t) = Asin (ωt) + Vdc
VM2s (t) = Asin (ωt−π) + Vdc
.... (8)
It can be expressed.

The DC voltage Vcont1 as a control voltage is applied to the terminal 1 of the control circuit 11 (this voltage is equal to the control voltage Vcont in the circuit of FIG. 3 when the DC level of the drain nodes of the transistors M5 and M6 is as described above. Are input to the gate terminal 3 of the transistor M5 and the gate terminal 4 of the transistor M6, respectively, so that the signal represented by the above equation (8) is input to the drain terminal of each transistor. Signals represented by the following equation (9) are output from the terminals 2 and 5, and these signals are fed back to the gate terminals of the transistors M3 and M4, respectively.
VM5d = Bsin (ωt−π) + Vcont
VM6d = Bsin (ωt−2π) + Vcont
(9)
However, B is a constant that represents the amplitude of the AC component of the drain potential.

Therefore, the gate voltages VG3 and VG4 of the transistors M3 and M4 are respectively
VG3 = VM5d
VG4 = VM6d
The drain potentials of the transistors M3 and M4 are VD3 and VD4, respectively.
VD3 = VM2s (t)
VD4 = VM1s (t)
Therefore, from equation (4) ′, the conditions for the control transistors M3 and M4 to operate in the linear region are as follows:
Asin (ωt−π) + Vdc <Bsin (ωt−π) + Vcont−Vth
That is,
(AB) sin (ωt−π) <Vcont−Vdc−Vth (10)
Similarly, for the transistor M4,
(AB) sin (ωt) <Vcont−Vdc−Vth (11)
Is obtained.

For the above equations (10) and (11) to hold for all angular frequencies ω,
| Sin (ωt−π) | = | sin (ωt) | ≦ 1
Because
A <B + (Vcont−Vdc−Vth) (12)
Is a necessary condition.

  Comparing the equation (12) with the equation (7), the right side is increased by B. That is, it can be seen that the range of the amplitude A for the OTA circuit to operate in the linear operation region is expanded by the value B.

  In this embodiment, the conductivity type of each transistor may be changed from P-type to N-type, or from N-type to P-type, and a control transistor is connected to the source side of the input transistors M1 and M2. Instead, the same effect can be obtained by connecting to the drain side.

It is a block diagram which shows the structure of the OTA circuit which concerns on embodiment. It is a figure which shows the structure of the control circuit of FIG. It is a block diagram which shows the structure of the conventional OTA circuit. FIG. 4 is a diagram for explaining the operation principle of FIG. 3.

Explanation of symbols

M1, M2 input transistor M3, M4 control transistor M5, M6 transistor 10 OTA circuit according to the embodiment 11 control circuit

Claims (2)

First and second input terminals for inputting first and second input signals, respectively;
A first output signal corresponding to the first input signal is formed at a drain of the second transistor, the first and second transistors forming a differential pair each having a gate electrode connected to the input terminal; And a differential amplifier for forming a second output signal corresponding to the second input signal at the drain of the first transistor and forming a differential output signal from the first and second output signals. When,
First variable resistance means connected between the source electrodes of the first transistor and the second transistor and variably controlling a resistance value by a first control signal based on a signal of the source electrode of the first transistor;
A second variable resistance means connected between the source electrodes of the first transistor and the second transistor and variably controlling a resistance value by a second control signal based on a signal of the source electrode of the second transistor;
A control unit for forming the first and second control signals;
An OTA circuit comprising: The first and second transistors are first conductivity type MOS transistors,
The first variable resistance means includes a first conductivity type MOS transistor (third transistor) having a drain electrode connected to a source electrode of the second transistor and a source electrode connected to a source electrode of the first transistor. ) And
The second variable resistance means includes a first conductivity type MOS transistor (fourth transistor) having a drain electrode connected to a source electrode of the first transistor and a source electrode connected to a source electrode of the second transistor. ) And
The control unit includes fifth and sixth transistors that are first conductivity type MOS transistors that form a differential pair by connecting source electrode signals of the first and second transistors to gate electrodes, respectively. The output signal from the drain electrode of the fifth transistor is connected to the gate electrode of the third transistor as a first control signal, and the output signal from the drain electrode of the sixth transistor is used as the second control signal. Configured to connect to a gate electrode of a fourth transistor;
The OTA circuit according to claim 1.

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