JP2006253816A - Direct conversion receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce DC offset in a direct conversion receiver capable of receiving a plurality of bands. <P>SOLUTION: LNAs 5a, 5b, quadrature mixers 6a, 6b, phase-shifters 7a, 7b, and VCOs 8a, 8b are made independent from one another for each frequency band and share LPFs 14a-14d, HPFs 16a-16d, baseband variable gain amplifiers 15a-15f, and a PLL circuit 10. The HPFs 16a-16d switch cut-off frequencies corresponding to the instruction of an HPF control part 29. The switching of circuits independently provided for each frequency band is executed together with the update of frequency data to the PLL circuit 10 when the switching of frequency bands occurs. On that occasion, the DC offset can be quickly converged by increasing the cut-off frequencies of the high-pass filters 16a-16d. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a direct conversion receiver having a reception function for a plurality of bands, and more particularly to a direct conversion receiver having a DC offset reduction function.

  The direct conversion receiver superimposes a local signal (carrier) of the same frequency on an RF (Radio Frequency) signal received by an antenna, thereby omitting conversion to an intermediate frequency and converting it directly to a baseband signal. It is a receiver which has. Since such a function can reduce the number of filters, it is possible to reduce the size and weight of the receiver. In such a direct conversion receiver, it is important to suppress the DC offset. Various methods for suppressing the DC offset in the direct conversion receiver are disclosed in various documents (see, for example, Patent Document 1). According to the technique of Patent Document 1, a period during which a DC offset is highly likely to be detected is detected, and during that period, the time constant of the DC component blocking filter interposed in the signal path is made smaller than that during normal operation. The DC offset can be reduced by rapidly converging the transient response of the passed signal.

In addition, in a direct conversion receiver for multiple bands, the circuit scale is increased, and in order to reduce the size, the price, and the weight, the circuit is shared in the circuit block that handles the same frequency. It is common. In particular, in the direct conversion receiver, the frequency after the orthogonal mixer is a common frequency, and it is highly feasible to share the baseband circuit unit, and the baseband circuit unit is also shared in view of the size of the circuit scale. This is more effective for size reduction, price reduction, and weight reduction. When trying to realize a circuit configuration that shares the baseband circuit section, the circuit configuration before the orthogonal mixer becomes a separate circuit configuration, and if the circuit switching occurs before the orthogonal mixer, it is necessary to reduce the DC offset become. In other words, in a direct conversion receiver for multiple bands that employs a direct conversion method, sharing a baseband circuit is more effective in realizing miniaturization and weight reduction.
JP 2003-224488 A

  However, in the direct conversion receiver disclosed in Patent Document 1 described above, there is a possibility that a DC offset occurs when the gain fluctuation amount is large at the time of gain switching. Therefore, if necessary, the cutoff frequency of the high-pass filter is switched from a low frequency to a high frequency to cope with a reduction in DC offset. Such correspondence assumes that the gain set value is updated according to the measurement result of the received power, so that the cut-off frequency switching control of the high-pass filter is performed. That is, in a conventional direct conversion receiver that switches between different frequencies, particularly in a conventional direct conversion receiver that supports reception of a plurality of bands, a method for suppressing a DC offset that accompanies switching of a frequency band is complicated. Therefore, there is still room for improvement in the DC offset suppression method in the direct conversion receiver. In other words, in a conventional direct conversion receiver capable of receiving a plurality of bands for which some circuits are shared, further improvement is necessary to suppress the DC offset.

  The present invention has been made in view of such a point, and an object thereof is to provide a direct conversion receiver for a plurality of bands capable of performing control for suppressing a DC offset even when a frequency band is switched. And

  The direct conversion receiver according to the present invention has an AGC (Automatic Gain Control) circuit for making the Ich / Qch amplitude value substantially constant with respect to the signal power of the received demodulated signal, and has at least two frequency bands. A direct conversion receiver for multiple bands that can receive signals, and is in an independent system for each frequency band, and activates a circuit in a target frequency band to be controlled by an external input signal and is not a target for control Low-frequency filter and high-pass filter that share the system even if the frequency band is different from LNA (Low Noise Amplifier), quadrature mixer, phase shifter, and voltage controlled oscillator (VCO) that stop the circuit in the frequency band , Baseband variable gain amplifier and PLL (Phase Locked Loop) circuit, frequency band switching or A high-pass filter control unit that controls switching between high and low cut-off frequencies of the high-pass filter when any of the frequencies is switched. The high-pass filter is cut off based on an instruction from the high-pass filter control unit. A configuration is adopted in which the frequency is switched to at least two levels of high / low.

  That is, the direct conversion receiver for multiple bands according to the present invention has an AGC circuit for making the amplitude value of Ich / Qch substantially constant with respect to the signal power of the received demodulated signal, and has at least two types of frequencies. A direct conversion receiver capable of receiving a band, wherein an LNA, a quadrature mixer, a phase shifter, and a voltage controlled oscillator are provided as independent systems for each frequency band. The LNA, the quadrature mixer, the phase shifter, and the voltage controlled oscillator that are independent for each frequency band are activated and deactivated by the external input signal. On the other hand, the low-pass filter, the high-pass filter, the baseband variable gain amplifier, and the PLL circuit are shared systems even if the frequency bands are different. Further, the high-pass filter has a function of switching the cut-off frequency in at least two steps of high / low according to an instruction from the high-pass filter control unit. The high-pass filter control unit is configured to perform switching control so that the cut-off frequency of the high-pass filter is high / low when either switching of the frequency band or switching of the frequency is performed. According to such a configuration, in contrast to the sharing of the baseband variable amplifier circuit for the purpose of downsizing and cost reduction, even if the circuit having an individual system for each frequency band is switched, the high-pass filter It is possible to suppress the occurrence of DC offset by switching the cut-off frequency.

  The direct conversion receiver for a plurality of bands according to the present invention may be configured such that, in the configuration of the invention, the high-pass filter control unit performs switching to increase the cutoff frequency of the high-pass filter, and then passes the high-pass filter after a certain period has elapsed. The configuration is such that control is performed to lower the cutoff frequency of the filter.

  According to such a configuration, after the high-pass filter control unit performs switching to increase the cutoff frequency of the high-pass filter, the DC offset is suppressed by decreasing the cutoff frequency of the high-pass filter after a certain period of time has elapsed. In addition, the cutoff frequency of the high-pass filter that achieves high demodulation accuracy can be obtained.

  In addition to the configuration of the present invention, the direct conversion receiver for a plurality of bands according to the present invention further includes a control signal for performing frequency band switching control of the LNA, quadrature mixer, phase shifter, and voltage controlled oscillator. The delay circuit switching control timing in the high-pass filter is determined by the delay timing of the delay circuit.

  According to such a configuration, the cut-off frequency switching control timing in the high-pass filter is the control signal for performing the band switching control of the LNA, the quadrature mixer, the phase shifter, and the voltage controlled oscillator that are independent for each frequency band. Sending via delay circuit.

  Further, in the direct conversion receiver for a plurality of bands according to the present invention, in the configuration of the invention, the timing of switching control of the cut-off frequency in the high-pass filter is set to frequency data in a PLL circuit that performs frequency control of the voltage controlled oscillator. When the frequency is switched from the previous set value, the configuration is determined by controlling the output of the control signal via the delay circuit.

  In the direct conversion receiver for multiple bands according to the present invention, in the configuration of the invention, the delay circuit has a delay time equal to or longer than a circuit start-up stabilization time at the time of frequency band switching in the LNA, quadrature mixer, and phase shifter. The structure to generate is taken.

  According to such a configuration, the delay circuit has a delay time longer than the circuit start-up stabilization time when the frequency band of the LNA, the quadrature mixer, and the phase shifter that are independent for each frequency band is switched.

  In addition to the configurations of the respective inventions, the direct conversion receiver for multiple bands according to the present invention further determines the presence / absence of frequency switching, and switches the cut-off frequency when the frequency is switched. A configuration including a switching determination unit is employed.

  According to the direct conversion receiver of the present invention, the DC offset is stabilized by switching the cut-off frequency in the high-pass filter after the circuit switching stabilization time of the LNA, the quadrature mixer, and the phase shifter accompanying the frequency band switching. Can be converged to. That is, the DC offset can be effectively reduced by switching the cutoff frequency from the low frequency to the high frequency.

  In addition, the frequency switching time of the PLL synthesizer, which is performed at almost the same timing as the switching of the frequency band, is the switching procedure of switching the low frequency → high frequency → low frequency by switching the circuit switching stabilization time and the high-pass filter cutoff frequency. Even if it is included, since the frequency stabilization time is generally longer than that, the DC offset can be converged and high demodulation accuracy can be realized before the PLL synthesizer frequency stabilizes. .

<< Summary of Invention >>
The direct conversion receiver for a plurality of bands according to the present invention quickly converges the DC offset by performing cut-off frequency switching control in the high-pass filter when frequency band switching occurs. In this way, stabilization of AGC operation and securing of good reception performance can be realized by suppressing fluctuations in the DC offset due to circuit switching accompanying frequency band switching.

<< Best Mode of the Invention >>
The direct conversion receiver for multiple bands according to the present invention determines whether or not frequency bands are switched based on information from serial data used in a PLL synthesizer. When frequency band switching occurs, the control of switching the cutoff frequency of the high-pass filter from a low frequency to a high frequency is performed, thereby realizing a reduction in DC offset in a direct conversion receiver that supports multiple bands. In addition, stabilization of AGC control and high quality reception characteristics can be obtained.

  Further, in a direct conversion receiver capable of receiving a plurality of bands, a method for solving a DC offset when a baseband circuit is shared is as described below. Note that, in the DC offset reduction method by the direct conversion receiver of the present invention, in particular, in the CDMA (Code Division Multiple Access) method, the measurement of the different frequency level across the frequency band from the continuous reception state, and the return to the own station It is assumed that an effective AGC operation and good reception performance are ensured when there is an error.

  That is, in a direct conversion receiver that supports multiple bands, when the baseband circuit is shared, the LNA, VCO, phase shifter, and quadrature mixer, which are the previous circuit blocks of the shared part, perform band switching and circuit ON / OFF control is performed. In a plurality of bands, the unused band circuit blocks are generally not operated from the viewpoint of reducing current consumption. Also, the DC offset generation amount in the direct conversion receiver increases in proportion to the gain change amount. Further, when band switching occurs, a sudden gain fluctuation occurs by setting frequency data to the synthesizer or starting an LNA, VCO, or quadrature mixer. In particular, sudden gain fluctuations are caused by ON / OFF control of the orthogonal mixer that performs conversion to a signal of a baseband frequency.

  In such a case, in the DC offset reduction method disclosed in Patent Document 1 described above, since the cutoff frequency does not switch in the high-pass filter unless the gain value is updated in the continuous reception state, it is assumed that the DC offset is large. Even if this occurs, there is a possibility that the DC offset has not sufficiently converged by the frequency stabilization time of the synthesizer.

  Therefore, in the present invention, in a direct conversion receiver that supports multiple bands such as a synthesizer circuit and performs circuit control such as LNA and quadrature mixer in band switching, band switching control is performed by frequency setting data from serial data. When performed, immediately after the circuit switching operation of the LNA, VCO, quadrature mixer, and phase shifter is stabilized, the DC offset is rapidly converged by increasing the cutoff frequency of the high-pass filter. After the DC offset converges, the high-pass filter cut-off frequency is quickly restored. As a result, the DC offset value can be converged before the reception level measurement immediately after the circuit switching accompanying the frequency band switching.

  Hereinafter, some embodiments of the direct conversion receiver according to the present invention will be described in detail with reference to the drawings. In the drawings used in the embodiments, the same components are denoted by the same reference numerals, and redundant description is omitted as much as possible.

Embodiment 1
The direct conversion receiver according to Embodiment 1 of the present invention is characterized in that when the frequency band is switched, the cutoff frequency is switched in the high-pass filter. Here, the reason why switching the cut-off frequency of the high-pass filter in the direct conversion receiver is effective for reducing the DC offset value will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating characteristics of demodulation accuracy of an I / Q reception signal with respect to a cut-off frequency of the high-pass filter, where the horizontal axis represents the cut-off frequency (Hz) of the high-pass filter (HPF) and the vertical axis represents the received signal. Represents the demodulation accuracy (% rms). FIG. 2 is a graph showing the DC value characteristics with respect to time when the cutoff frequency of the high-pass filter is used as a parameter. That is, FIG. 2 shows the response characteristics of the cutoff frequency in the high pass filter (HPF), with the horizontal axis representing time (ms) and the vertical axis representing DC value (V).

  As can be seen from FIG. 1, the higher the cutoff frequency, the worse the demodulation accuracy. As can be seen from FIG. 2, the higher the cutoff frequency, the faster the DC offset converges. That is, as can be seen from FIG. 1 and FIG. 2, the lower the cutoff frequency of the high-pass filter is, the more advantageous when trying to improve the reception quality, but on the other hand, there is a problem specific to the direct conversion receiver. When trying to speed up the DC response convergence characteristic when a DC offset due to a certain gain fluctuation occurs, the higher the cutoff frequency of the high-pass filter, the better the convergence characteristic. It has become a relationship.

  Normally, in the CDMA system, in order to demodulate a multi-channel signal, it is essential to control the reception AGC so that the input amplitude to the AD converter becomes substantially constant even when the input electric field changes. However, if the DC offset remains, the temporal change in the received power measurement becomes large, and it is determined that a higher signal is received with respect to the actual signal amplitude even if a certain interval is averaged. Therefore, normal AGC operation cannot be expected due to the DC offset.

  From this, when there is a possibility that a DC offset may occur, the DC offset convergence time is increased by increasing the cutoff frequency of the high-pass filter, and the cutoff frequency of the high-pass filter is decreased after DC convergence. Thus, the reception AGC operation can be stabilized and the reception quality can be stabilized.

  Hereinafter, the configuration and operation of the direct conversion receiver according to Embodiment 1 of the present invention will be described in detail with reference to the drawings. FIG. 3 is a configuration diagram of a direct conversion receiver for a plurality of bands according to Embodiment 1 of the present invention. The configuration of the direct conversion receiver for multiple bands in Embodiment 1 shown in FIG. 3 assumes a receiver that can receive two bands, but antenna switching is also possible when receiving a frequency band higher than that. This can be easily realized by newly adding circuits from the switch 2 to the orthogonal mixers 6a and 6b for the frequency band.

  The direct conversion receiver according to Embodiment 1 shown in FIG. 3 includes an antenna 1, an antenna changeover switch 2, filters 4a and 4b, LNAs 5a and 5b, quadrature mixers 6a and 6b, phase shifters 7a and 7b, a VCO (voltage controlled oscillator). ) 8a, 8b, loop filters 9a, 9b, PLL circuit 10, reference clock 11, low pass filters (LPF) 14a, 14b, 14c, 14d, variable gain amplifiers 15a, 15b, 15c, 15d, 15e, 15f, high pass filters ( HPF) 16a, 16b, 16c, 16d, all-pass filters (APF) 17a, 17b, A / D converters 18a, 18b, received power measurement unit 19, decoder 20, data determination unit 21, gain calculation unit 22, gain control unit 23 , Timing generator 24, frequency controller 25, serial input Interface output unit 26, serial interface input unit 27, variable gain amplifier (GCA) control unit 28, high-pass filter (HPF) control unit 29, timer 30, band switching control unit 31, and delay circuit 32. Yes.

  Next, the operation of the direct conversion receiver shown in FIG. 3 will be described. A signal received from the antenna 1 is output to an output terminal connected to a desired reception band circuit by the antenna changeover switch 2. The band 1 RF signal 3a is input to the LNA 5a after signal components other than the received signal are removed by the filter 4a, and the amplified RF signal is transmitted to the orthogonal mixer 6a.

  Here, from the viewpoint of dynamic range and NF characteristics, an LNA may be further inserted before the filter 4a, or a shared machine is inserted at the output of the antenna changeover switch 2 in order to ensure isolation from the transmitter. It doesn't matter. Note that the VCOs 8a and 8b, the loop filters 9a and 9b, the PLL circuit 10 and the reference clock 11 are simply known PLL synthesizer circuits, and are well-known techniques, so detailed description thereof is omitted. . Further, a local signal having the same frequency as the carrier frequency of the reception frequency is input from the VCO 8a to the orthogonal mixer 6a via the phase shifter 7a, and the Ich signal 12a and the Qch signal 13a, which are demodulated signal components, are input from the orthogonal mixer 6a. Is output.

  On the other hand, the band 2 RF signal 3b from the antenna 1 is, like the band 1 RF signal 3a, the signal component other than the received signal is removed by the filter 4b, and then input to the LNA 5b and amplified as an RF signal to the orthogonal mixer 6b. Is output. Further, a local signal having the same frequency as the carrier frequency of the reception frequency is input from the VCO 8b to the quadrature mixer 6b via the phase shifter 7b, and the Ich signal 12b and Qch, which are demodulated signal components, are output from the quadrature mixer 6b. A signal 13b is output.

  Here, the circuits from the LNAs 5a and 5b to the orthogonal mixers 6a and 6b are independently provided for each frequency band, and the circuit block that matches the frequency band by the control signal from the band switching control unit 31 performs the ON operation. The non-target circuit that does not match the band performs an OFF operation, thereby preventing an increase in current consumption due to the multiple bands. Further, the Ich signals 12a and 12b and the Qch signals 13a and 13b output from the orthogonal mixers 6a and 6b for each frequency band are common gain circuits, and variable gain amplifiers 15a and 15b that perform baseband variable gain amplification, respectively. Sent to.

  Generally, if the frequency to be handled is different (or if the frequency band to be handled is separated), it is difficult to optimize each circuit, and it becomes difficult to obtain sufficient performance in terms of current or characteristics. If the frequency is the same, circuit sharing is relatively easy.

  The Ich signal 12a or Ich signal 12b and the Qch signal 13a or Qch signal 13b, which are the outputs of the quadrature mixer 6a or quadrature mixer 6b, are slightly separated from the baseband signal in the low-pass filters (LPF) 14a, 14b, 14c and 14d. The adjacent frequency is removed. The variable gain amplifiers 15a, 15b, 15c, 15d, 15e, and 15f perform arbitrary gain control for the purpose of reception AGC according to instructions from the variable gain amplifier (GCA) control unit 28, and each variable gain amplifier 15a, 15b, 15c, 15d, 15e, and 15f are connected by high pass filters (HPF) 16a, 16b, 16c, and 16d, and DC separation between the variable gain amplifiers 15a, 15b, 15c, 15d, 15e, and 15f is performed as much as possible. Thus, the DC offset when the gain fluctuation occurs is suppressed.

  The high-pass filters (HPF) 16a, 16b, 16c, and 16d switch the cut-off frequency between high and low according to instructions from the high-pass filter (HPF) control unit 29. The all-pass filters (APF) 17a and 17b suppress in-band group delay deviation caused by the low-pass filters (LPF) 14a, 14b, 14c, and 14d and the high-pass filters (HPF) 16a, 16b, 16c, and 16d, and have high demodulation accuracy. Is realized.

  The Ich signal and Qch signal having desired amplitude values, which are output signals of the variable gain amplifiers 15e and 15f, are converted into digital signals by the A / D converters 18a and 18b. Then, the Ich signal and the Qch signal converted into digital signals are output to the reception power measuring unit 19 and the decoder 20 that measure the reception power for the purpose of AGC control.

  The received power measurement unit 19 outputs an average power measurement value obtained from the measurement result of a certain section from the Ich signal and the Qch signal to the gain calculation unit 22, and the gain calculation unit 22 next time calculates the difference from the desired power measurement value. The gain value to be set when the gain is updated is output to the gain controller 23.

  On the other hand, the data determination unit 21 determines the reception timing and the frequency switching timing based on the network instruction based on the information from the decoder 20, and the timing instruction to the timing generation unit 24 and the frequency data to the frequency control unit 25. Update. In addition, the timing generation unit 24 instructs the gain control unit 23 and the frequency control unit 25 to set the data on the receiver side in accordance with the timing on the network, and sends it to the serial interface input unit 27 via the serial interface output unit 26. Perform data transfer.

  When the frequency control unit 25 performs frequency control on the receiver side via the serial interface output unit 26, the frequency data is updated to the PLL circuit 10 and, when band switching occurs, the serial interface input unit 27 is used. Then, an instruction is given to the band switching control unit 31.

  The variable gain amplifier (GCA) control unit 28 is connected to the variable gain amplifiers 15a, 15b, 15c, 15d, 15e, and 15f based on an instruction from the gain control unit 23 via the serial interface output unit 26 and the serial interface input unit 27. By performing gain control, reception AGC control is realized. When a gain fluctuation amount that is expected to generate a DC offset is detected, the high-pass filter (HPF) control unit 29 is instructed to perform cutoff switching. Here, the high-pass filter (HPF) control unit 29 has a timer 30, and a certain time has elapsed after switching the cutoff frequency of the high-pass filters (HPF) 16a, 16b, 16c, and 16d to a high frequency. After that, it is possible to switch the cut-off frequency of the high-pass filters (HPF) 16a, 16b, 16c, 16d back to a low frequency.

  On the other hand, the band switching control unit 31 instructs circuit switching control to the LNAs 5a and 5b, the quadrature mixers 6a and 6b, the phase shifters 7a and 7b, and the VCOs 8a and 8b, and the high-pass filter (via the delay circuit 32). The HPF) control unit 29 is instructed to switch the cutoff frequency in the high-pass filters (HPF) 16a, 16b, 16c, 16d. The delay circuit 32 has a delay time longer than the circuit activation stabilization time.

  Here, the operation when frequency band switching occurs will be described in detail using an operation example. FIG. 4 is a timing chart showing an operation example of high-pass filter switching and RX (reception) Ich signal waveform when frequency switching is performed (band switching) in a direct conversion receiver for a plurality of bands when the present invention is not applied. FIG. 5 is a timing chart showing an example of the operation of high-pass filter switching and the RXIch signal waveform at the time of frequency switching (band switching) in a direct conversion receiver for multiple bands when the present invention is applied. FIG. 4 shows the time course of frequency data, gain setting data, high-pass filter (HPF) cut-off frequency (fc) switching, and Rx (reception) Ich output. FIG. 5 shows the time course of frequency data, gain setting data, high-pass filter (HPF) cut-off frequency (fc) switching, and Rx (reception) Ich / Qch output.

  Incidentally, the operations shown in FIGS. 4 and 5 assume a compressed mode in which other frequency channels are monitored during a call or the like and then return to the local frequency. When monitoring, the operation | movement which may occur at the time of the switching operation across a frequency band is shown.

  In FIG. 4, when different frequency switching accompanied by band switching occurs from the local station frequency (time t1), a synthesizer pulling operation by updating frequency data to the PLL circuit 10 occurs, and a circuit switching operation for each frequency band Occurs. The frequency stabilization time of the synthesizer usually requires several hundreds of microseconds. After the stable operation is completed, the AGC operation is performed to ensure level measurement accuracy at a frequency where the received electric field is unknown, and then the level measurement is performed. After that, it returns to its own frequency.

  Here, when the frequency band is switched, ON / OFF control of the circuit for each frequency band is performed almost simultaneously with the frequency switching of the synthesizer. Therefore, a large DC offset is generated in the RX_Ich output due to a large gain fluctuation during the frequency switching. appear. In particular, if the gains of the baseband variable gain amplifiers 15a and 15b are increased, the fluctuation of the DC offset during the frequency switching operation is changed more greatly.

  FIG. 4 illustrates a characteristic in which the DC offset remains even after the frequency stabilization time has ended since the cutoff frequency of the high-pass filter remains low when the DC offset occurs. When high-speed AGC operation is performed in this state, normal AGC operation cannot be expected because measurement is performed higher than actual reception power due to residual DC offset. Even if the reception AGC operation is normally performed, the cut-off frequency switching of the high-pass filter is performed only when the gain fluctuation amount is large for the DC offset convergence.

  Incidentally, the high-speed AGC operation is desired in a short time by increasing the AGC gain feedback amount in order to obtain a desired Ich / Qch amplitude value in a state where the received electric field level is unknown, and by rapidly updating the gain. This is an AGC operation to obtain the Ich / Qch amplitude value of the AGC. It should be noted that a movement that gently follows level fluctuations due to fading or the like during such a receiving operation is regarded as a low-speed AGC operation.

  In addition, when the operation to return to the local station frequency is performed after the level measurement of the different frequency is completed (time t2), the same operation as that at the time t1 is performed. An offset has occurred. In this case, if there is no residual DC offset, the frequency is the frequency at which the previous reception operation was performed, and the desired gain value is reset by resetting the previous gain setting value at the local station frequency without newly performing a high-speed AGC operation. Since it is highly possible to obtain the Ich / Qch amplitude value, it is possible to shorten the non-reception section at the local frequency accompanying the different frequency level measurement. However, in order to switch the cutoff frequency of the high-pass filter, it is expected that the DC offset is removed again by the high-speed AGC operation. Alternatively, one of means for expecting convergence due to the transient response of the high-pass filter at a low cutoff frequency is selected.

  On the other hand, in the operation example of the present invention shown in FIG. 5, when performing band switching to a different frequency (time t 1), frequency switching of the synthesizer and circuit switching corresponding to the frequency band are performed. After the start-up stabilization time of the mixer or the like has elapsed (time t2), the cutoff frequency of the high-pass filter is switched (low frequency → high frequency) to quickly converge the DC offset, and thereafter (time t3), the high-pass filter cutoff Frequency switching (high frequency → low frequency) is performed. In this way, after the start-up stabilization time of the synthesizer circuit elapses, the DC offset can be converged and the DC offset can be removed by setting the cut-off frequency of the high-pass filter that can realize high demodulation accuracy. .

  In addition, when switching to the local frequency after measurement of the different frequency level occurs (time t4), the cutoff frequency of the high-pass filter is switched (low frequency → high frequency) at time t5, and the DC offset is promptly performed. And then switching the cutoff frequency of the high-pass filter (from high frequency to low frequency) at time t6, that is, by updating again the gain setting value before measuring the level of the different frequency, Even if there is no operation, the DC offset can be converged before the start of reception. Furthermore, it becomes possible to set the cutoff frequency of the high-pass filter that can realize high demodulation accuracy.

  With such an operation, in a direct conversion receiver that supports multiple bands, the cut-off frequency of high-pass filter switching can be switched from low frequency to high frequency to low frequency for the occurrence of DC offset due to circuit switching operation by band switching. By switching to, it is possible to achieve DC offset convergence and high demodulation accuracy before frequency stabilization.

<< Embodiment 2 >>
FIG. 6 is a configuration diagram of a direct conversion receiver for a plurality of bands according to Embodiment 2 of the present invention. The direct conversion receiver for multiple bands in the second embodiment shown in FIG. 6 determines whether or not frequency switching has occurred with respect to the configuration of the direct conversion receiver in the first embodiment shown in FIG. The frequency switching determination unit 33 is added.

  Next, the operation of the direct conversion receiver shown in FIG. The feature of the direct conversion receiver according to the second embodiment of the present invention is that the cutoff frequency is switched in the high-pass filters (HPF) 16a, 16b, 16c, and 16d when frequency switching occurs. It is. That is, the direct conversion receiver according to the first embodiment switches the cutoff frequency when the frequency band is switched, whereas the direct conversion receiver according to the second embodiment includes a frequency switching determination unit. The difference is that 33 determines whether or not the frequency is switched and switches the cutoff frequency when the frequency is switched.

  In FIG. 6, when the frequency is switched including whether or not the frequency band is switched, the frequency control unit 25 updates the frequency data of the PLL circuit 10 via the serial interface output unit 26 and the serial interface input unit 27. At this time, the frequency switching determination unit 33 that monitors the frequency setting data to the PLL circuit 10 passes the delay circuit 32 to the high-pass filter (HPF) control unit 29 when the frequency is switched. Instruct to increase the cut-off frequency.

  Here, the direct conversion receiver according to the first embodiment performs the cut-off frequency switching control of the high-pass filters (HPF) 16a, 16b, 16c, and 16d while following the switching of the frequency band. In the direct conversion receiver according to the form 2, when the frequency is switched, the cut-off frequency switching control of the high-pass filters (HPF) 16a, 16b, 16c, and 16d is unconditionally performed even if the frequency band is not changed. I have to.

  In other words, if the frequency is switched within the same frequency band, it is assumed that no DC offset occurs because the circuit is not switched. However, at the time of frequency switching, the frequency is always stable until at least the reception AGC operation and data reception are performed. Since it is necessary to secure a certain period of time in consideration of the time, the cut-off frequency of the high-pass filters (HPF) 16a, 16b, 16c, and 16d may be switched without identifying the frequency band. The effect similar to the form 1 of this can be acquired.

  The direct conversion receiver according to the present invention can be effectively used as a CDMA receiver having a small DC offset, a small size, and low power consumption.

The figure which shows the characteristic of the demodulation accuracy of the I / Q received signal with respect to the cutoff frequency of a high pass filter The figure which shows the characteristic of DC value with respect to time when the cutoff frequency of a high-pass filter is used as a parameter Configuration diagram of direct conversion receiver for multiple bands in Embodiment 1 of the present invention Timing chart showing an operation example and RXIch signal waveform of high-pass filter switching at the time of frequency switching (band switching) in a direct conversion receiver for multiple bands when the present invention is not applied Timing chart showing an operation example and RXIch signal waveform of high-pass filter switching at the time of frequency switching (band switching) in a direct conversion receiver for multiple bands when the present invention is applied Configuration diagram of direct conversion receiver for multiple bands in Embodiment 2 of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Antenna 2 Antenna changeover switch 3a Band 1 RF signal 3b Band 2 RF signal 4a, 4b Filter 5a, 5b LNA
6a, 6b Quadrature mixer 7a, 7b Phase shifter 8a, 8b VCO (Voltage Controlled Oscillator)
9a, 9b Loop filter 10 PLL circuit 11 Reference clock 12a, 12b Ich signal 13a, 13b Qch signal 14a, 14b, 14c, 14d Low pass filter (LPF)
15a, 15b, 15c, 15d, 15e, 15f Variable gain amplifiers 16a, 16b, 16c, 16d High pass filters (HPF)
17a, 17b All-pass filter (APF)
18a, 18b A / D converter 19 Received power measurement unit 20 Decoder 21 Data determination unit 22 Gain calculation unit 23 Gain control unit 24 Timing generation unit 25 Frequency control unit 26 Serial interface output unit 27 Serial interface input unit 28 Variable gain amplifier control unit 29 High Pass Filter (HPF) Control Unit 30 Timer 31 Band Switching Control Unit 32 Delay Circuit 33 Frequency Switching Determination Unit

Claims (6)

A direct conversion receiver for multiple bands that has an AGC circuit for making the amplitude value of Ich / Qch almost constant with respect to the signal power of the received demodulated signal and that can receive at least two types of frequency bands. There,
In an independent system for each frequency band, an LNA, a quadrature mixer, a phase shifter for starting a circuit in a target frequency band to be controlled by an external input signal and stopping a circuit in a non-target frequency band not to be controlled, And a voltage controlled oscillator,
A low-pass filter, a high-pass filter, a baseband variable gain amplifier, and a PLL circuit that share a system even if the frequency bands are different;
A high-pass filter control unit that performs control to switch the high-pass filter to a high / low cut-off frequency when either frequency band switching or frequency switching is performed;
The high-pass filter switches the cut-off frequency to at least two stages of high / low based on an instruction from the high-pass filter control unit, and is a direct conversion receiver for multiple bands.   The high-pass filter control unit performs control to lower the cutoff frequency of the high-pass filter after a certain period of time has elapsed after switching to increase the cutoff frequency of the high-pass filter. Direct conversion receiver described in 1. And a delay circuit for delaying a control signal for performing frequency band switching control of the LNA, the quadrature mixer, the phase shifter, and the voltage controlled oscillator,
The direct conversion receiver according to claim 2, wherein the timing of switching control of the cut-off frequency in the high-pass filter is determined by a delay timing of the delay circuit.   The timing of switching control of the cut-off frequency in the high-pass filter is the control when the frequency is switched from the previous set value when frequency data is set in the PLL circuit that controls the frequency of the voltage controlled oscillator. The direct conversion receiver according to claim 3, wherein the direct conversion receiver is determined by performing output control of a signal via the delay circuit.   5. The delay circuit according to claim 3, wherein the delay circuit generates a delay time that is equal to or longer than a circuit start-up stabilization time when the frequency band is switched in the LNA, the quadrature mixer, and the phase shifter. Direct conversion receiver.   6. The direct switching device according to claim 1, further comprising a frequency switching determination unit that determines whether or not frequency switching is performed and switches a cutoff frequency when the frequency is switched. Conversion receiver.

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