JP2006245602A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor integrated circuit device in which the miniaturization of a MISFET can be promoted by enabling a peripheral portion of an active region to be subjected to round processing without decreasing the dimension of the active region. <P>SOLUTION: Grooves 2a are formed in device isolation regions in a substrate 1 by dry etching using silicon nitride films 14 and side wall spacers 16 as masks. Thereafter, the side wall spacers 16 lying on side walls of the silicon nitride films 14 are removed and the substrate 1 is subjected to thermal oxidation, whereby the surface of the substrate 1 at the peripheral portion of the active region is subjected to round processing so as to have a sectional shape having a convex rounded shape. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly to an element isolation structure for forming a fine MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a technique effective when applied to a forming process thereof.

  With the miniaturization and high integration of semiconductor elements, as an element isolation structure that replaces the selective oxidation (Local Oxidization of Silicon: LOCOS) method, an element isolation groove (Shallow Groove Isolation) in which an insulating film is embedded in a groove formed in a silicon substrate. ; SGI) is being introduced.

  Compared with the selective oxidation method, the element isolation trench can (a) reduce the element isolation interval, (b) can easily control the element isolation film thickness, and can easily set the field inversion voltage. ) Since the inversion prevention layer can be separated from the diffusion layer and the channel region by separating impurities between the side wall and the bottom inside the trench, it is advantageous for securing the subthreshold characteristics, reducing junction leakage, and the back gate effect. It is thought that there is.

  A general method for forming the element isolation trench is as follows. First, a silicon substrate is thermally oxidized to form a thin silicon oxide film on its surface, and then a silicon nitride film is deposited thereon by a CVD (Chemical Vapor Deposition) method. Next, after the silicon nitride film in the element isolation region is removed by dry etching using the photoresist film as a mask, a groove is formed in the substrate by dry etching using the silicon nitride film remaining in the active region as a mask.

  Next, after a thick silicon oxide film is deposited on the substrate including the inside of the trench by a CVD method, the substrate is heat-treated, and the silicon oxide film embedded in the inside of the trench is densely baked (Densify). After that, the silicon oxide film on the top of the silicon nitride film is removed by a polishing process such as etch back or chemical mechanical polishing (CMP), and then the silicon nitride film that is no longer needed is removed, thereby separating the elements. The groove is completed.

The element isolation grooves are described in, for example, Japanese Patent Application Laid-Open No. 2-260660 (Patent Document 1), Japanese Patent Application Laid-Open No. 4-303942 (Patent Document 2), Japanese Patent Application Laid-Open No. 8-97277 (Patent Document 3), and the like. There is.
JP-A-2-260660 Japanese Patent Laid-Open No. 4-303942 JP-A-8-97277

  In the element isolation structure as described above, the inventor has developed thinning (local thinning) in which the gate oxide film formed on the substrate surface of the active region is locally thinned at the periphery of the active region, and draining with a low gate voltage. As a measure to solve the phenomenon (currently referred to as MOS-IV kink characteristics) in which a current flows, a technique for rounding the periphery of the active region (round processing) was studied.

  As a result, the inventor forms a groove in the substrate and then rounds the periphery of the active region (round processing), which requires high-temperature thermal oxidation treatment. As a result, the thermal oxide film formed on the inner wall of the trench grows on the active region side, reducing the size of the active region, and this has been found to hinder the high integration and miniaturization of the MISFET.

  That is, if round processing (roundness) is insufficient, thinning (local thinning) in which the gate oxide film is thinly formed in the peripheral portion of the sharp active region or the MOS-IV kink when the gate oxide film is oxidized. There arises a problem that the threshold voltage of the MISFET varies due to the characteristics. As a countermeasure, it is necessary to perform round processing (rounding) sufficiently. However, if sufficient rounding is performed on the periphery of the active region, the active region (especially in the gate width direction of the MISFET) becomes narrow. For this reason, the dimensions of the active region (particularly, the gate width of the MISFET) cannot be ensured and the semiconductor element cannot be miniaturized, and the width of the element isolation region isolation groove and the semiconductor element are miniaturized for high integration. Hinder.

  An object of the present invention is to provide a technique capable of promoting miniaturization of a MISFET.

  Another object of the present invention is to provide a technique capable of promoting the miniaturization of the width of the element isolation trench.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A manufacturing method of a semiconductor integrated circuit device according to one invention of the present application includes the following steps.
(A) a step of selectively forming a silicon nitride film on the main surface of the substrate;
(B) forming a groove in the substrate in an element isolation region by forming a sidewall spacer on the sidewall of the silicon nitride film and then etching the substrate in a self-aligned manner with respect to the sidewall spacer;
(C) After removing the sidewall spacers, the substrate surface in the periphery of the active region is rounded by thermally oxidizing the substrate;
(D) etching the silicon nitride film to retract the periphery of the silicon nitride film toward the center of the active region;
(E) After forming an insulating film on the substrate including the inside of the groove, the insulating film on the silicon nitride film is removed, and the insulating film is embedded in the groove to define the active region Forming an element isolation groove to be formed.

(2) A manufacturing method of a semiconductor integrated circuit device according to an invention of the present application includes the following steps.
(A) a step of selectively forming a silicon nitride film on each main surface of the first region and the second region of the substrate;
(B) forming a first sidewall spacer on a sidewall of the silicon nitride film remaining on the substrate;
(C) Covering the first region of the substrate with a first photoresist film and etching the first sidewall spacer in the second region, thereby forming a sidewall of the silicon nitride film in the second region; Forming a second sidewall spacer having a thickness smaller than that of the first sidewall spacer;
(D) forming a groove in the substrate by removing the first photoresist film and then etching the substrate in a self-aligned manner with respect to the first sidewall spacer and the second sidewall spacer; ,
(E) removing the first sidewall spacer and the second sidewall spacer and then thermally oxidizing the substrate to round the substrate surface in the periphery of the active region;
(F) After forming an insulating film on the substrate including the inside of the groove, the insulating film on the silicon nitride film is removed, and the insulating film is embedded in the groove to define the active region Forming an element isolation groove to be formed.

(3) A method for manufacturing a semiconductor integrated circuit device according to an invention of the present application includes the following steps.
(A) forming a first layer on the first region of the main surface of the substrate, forming a second layer on the second region of the main surface, and then forming a first sidewall on the side wall of the first layer; And forming a second sidewall having a width smaller than the width of the first sidewall on the sidewall of the second layer,
(B) A first groove is formed in the main surface of the first region in a self-aligned manner with respect to the first sidewall, and the main surface of the second region is formed with respect to the second sidewall. Forming the second groove in a self-aligning manner;
(C) burying a first insulating film in each of the first groove and the second groove;
(D) removing each of the first layer and the second layer;
(E) a step of forming a second insulating film on the main surface of the substrate after the step (d);
(F) After selectively removing the second insulating film in the first region, a third insulating film having a thickness smaller than that of the second insulating film is formed on the main surface of the first region. Forming step.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to one invention of this application, since the peripheral part can be round-processed, without reducing the dimension of an active region, refinement | miniaturization of MISFET can be accelerated | stimulated.

  According to one invention of the present application, it is possible to prevent a problem that the silicon oxide film in the element isolation trench is recessed (recessed) in the vicinity of the peripheral portion of the active region, so that the characteristics of the miniaturized MISFET can be improved. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a plan view of an essential part of a substrate during the manufacturing process, FIG. 2 is an equivalent circuit diagram of a DRAM memory array, and FIG. 3 is a cross-sectional view of the substrate along the line AA ′ in FIG. The figure and the right side part are sectional drawings of the board | substrate along the BB 'line | wire of FIG.

  For example, in a p-type well 3 formed on the main surface of a substrate 1 made of p-type single crystal silicon, an active region L whose periphery is defined by an element isolation trench 2 is formed. As shown in FIG. 1, the active region L is configured by an elongated island-like planar pattern extending in the A-A ′ line direction. Further, as shown in FIG. 3, the surface of the substrate 1 (p-type well 3) in the active region L has a flat central portion and a peripheral portion (end portion) having a cross-sectional shape with convex roundness. Yes.

  In each of the active regions L, two MISFETs (memory cell selection MISFETs Qs) sharing one of a source and a drain (n-type semiconductor region 10) are formed. This memory cell selection MISFET Qs and an information storage capacitive element C, which will be described later, are connected in series to constitute a 1-bit memory cell MC of a DRAM (Dynamic Random Access Memory). As shown in FIG. 2, memory cell MC is coupled to the intersection of word line WL and bit line BL.

  The memory cell selection MISFET Qs includes a gate oxide film 7 formed mainly on the surface of the substrate 1 (p-type well 3) in the active region L, a gate electrode 8 formed on the gate oxide film 7, and an active region. A pair of n-type semiconductor regions 10 and 10 (source and drain) formed on the L substrate 1 (p-type well 3). As will be described later, one of the n-type semiconductor regions 10 and 10 (source and drain) is electrically connected to the bit line BL, and the other is connected to one electrode (lower electrode 33) of the information storage capacitor element C. Electrically connected.

  The gate electrode 8 of the memory cell selecting MISFET Qs is formed integrally with the word line WL. That is, the gate electrode 8 is electrically connected to the word line WL. The gate electrode 8 (word line WL) linearly extends at the same width and the same interval along the BB ′ line direction of FIG. 1, that is, the short side direction of the active region L. The (gate length) (Lw) and the interval (Ls) are each equal to the minimum dimension (for example, 0.16 μm = Lw = Ls) determined by the resolution limit of photolithography.

  As described above, the wiring pitch that is the sum of the width (Lw) of the word line WL (gate electrode 8) and the interval (Ls) between the word lines WL (gate electrode 8) is configured to be twice the minimum processing dimension. The Thereby, the wiring pitch (Lw + Ls) in the direction in which the word line WL (gate electrode 8) extends can be reduced, so that the memory cell can be miniaturized and highly integrated.

  The gate electrode 8 (word line WL) includes a barrier metal film such as WN (tungsten nitride) and a W (tungsten) film on top of a low resistance polycrystalline silicon film doped with an n-type impurity such as P (phosphorus). It is comprised by the polymetal structure which laminated | stacked. A silicon nitride film 9 having the same planar pattern as that of the gate electrode 8 (word line WL) is formed on the gate electrode 8 (word line WL).

  As will be described later, the bit lines BL are configured with the same line width and the same interval along the direction intersecting the word line WL (gate electrode 8), and the line width (Lw ′) and the interval (Ls). ') Is composed of a minimum dimension (for example, 0.16 μm) determined by the resolution limit of photolithography (see FIG. 29).

  Thus, the wiring pitch, which is the sum of the width (Lw ′) of the bit line BL and the interval width (Ls ′) between the bit lines BL, is configured to be twice the minimum processing dimension. As a result, the wiring pitch (Lw ′ + Ls ′) in the direction intersecting the direction in which the bit line BL extends can be reduced, so that the memory cell can be miniaturized and highly integrated.

  An element isolation trench (element isolation region) 2 surrounding the substrate 1 (p-type well 3) in the active region L is formed within a trench having a depth of about 350 nm formed in the substrate 1 (p-type well 3). 6 is embedded. The surface of the silicon oxide film 6 is flattened, and its height is substantially equal to the surface of the substrate 1 (p-type well 3) in the active region L. In addition, a thin silicon oxide film 11 is formed at the interface between the inner wall of the element isolation trench 2 and the silicon oxide film 6 to relieve stress generated between the silicon oxide film 6 and the substrate 1 (p-type well 3). Has been. The short side dimension (a) of the active region L constitutes the gate width (a) of the memory cell selecting MISFET Qs.

  Next, a manufacturing method of the above-described DRAM memory cell will be described in the order of steps with reference to FIGS. Of these figures, the left side portions of FIGS. 4, 5, 7, 9, 11 to 20, 22, 24, 26, 28, and 30 to 35 are A cross-sectional view of the substrate 1 along the long side direction (AA ′ line direction in FIG. 1) of the active region L, and the right side portion is in the short side direction (BB ′ line direction in FIG. 1) of the active region L. It is sectional drawing of the board | substrate 1 along. In the plan views (FIGS. 6, 8, 25, 27, and 29), only the planar pattern of the active region, gate electrode (word line), bit line, and connection hole (contact hole, through hole) is shown. The illustration of the insulating film (silicon oxide film, silicon nitride film) and the conductive film constituting the plug is omitted.

  First, as shown in FIG. 4, a substrate 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is thermally oxidized at about 850 ° C., and a thin silicon oxide film having a thickness of about 10 nm is formed on the surface. After the (first silicon oxide film) 13 is formed, a silicon nitride film 14 having a thickness of about 120 nm is deposited on the silicon oxide film 13 by a CVD method. The silicon oxide film 13 between the silicon nitride film 14 and the substrate 1 relieves stress generated at the interface between the substrate 1 and the silicon nitride film 14, and defects such as dislocations are formed on the surface of the substrate 1 due to the stress. It is formed to prevent it from occurring.

  Next, as shown in FIG. 5, the silicon nitride film 14 in the element isolation region and the silicon oxide film 13 therebelow are selectively removed by dry etching using a photoresist film (not shown) as a mask. At this time, if even a slight amount of silicon oxide film remains on the surface of the substrate 1 in the element isolation region, foreign matter is generated. Therefore, the substrate 1 is over-etched to completely remove the silicon oxide film on the surface. The overetching amount of the substrate 1 may be about 10 to 30 nm. Further, the end portion of the over-etched portion of the substrate 1 is preferably not vertical, and a tapered portion tends to be rounded in the subsequent round processing.

  As shown in FIGS. 5 and 6, the silicon nitride film 14 remaining on the substrate 1 is constituted by an elongated island-like planar pattern that defines the active region L, and has a short side along the BB ′ line. The dimension (W) and the distance (S) between adjacent silicon nitride films 14 are equal to the minimum dimension (for example, 0.16 μm = W = S) determined by the resolution limit of photolithography. The long side dimension along the A-A ′ line of the silicon nitride film 14 is five times (for example, 0.8 μm) the short side dimension (W).

  As described above, in the present embodiment, the width Lw ′ of the bit line BL and the interval Ls ′ between the bit lines BL formed in a later process are configured with minimum dimensions determined by the resolution limit of photolithography. The dimension (W) of the short side of the silicon nitride film 14 that defines the active region L and the interval (S) between the silicon nitride films 14 are constituted by this minimum dimension.

  Next, as shown in FIGS. 7 and 8, sidewall spacers 16 are formed on the sidewalls of the silicon nitride film 14 by anisotropically etching the silicon oxide film deposited on the substrate 1 by the CVD method.

  The thickness (spacer length) Lsi of the sidewall spacer 16 is in the range of 5 nm to 40 nm, preferably in the range of 10 nm to 20 nm, and more preferably about 15 nm. When the spacer length is less than 5 nm, when the thermal oxidation process for round processing the peripheral portion of the active region L is performed in a later process, the dimension of the short side of the active region L after the process is photolithography. It becomes smaller than the minimum dimension (for example, 0.16 μm) determined by the resolution limit. On the other hand, when the spacer length Lsi exceeds 40 nm, the round amount around the active region L is insufficient. Further, since the aspect ratio (groove depth / width) of the groove 2a formed in the substrate 1 in the element isolation region in a later process is increased, the coverage and surface flatness of the silicon oxide film 6 embedded in the groove 2a are increased. Is insufficient.

  Next, as shown in FIG. 9, impurity ions are implanted into the substrate 1 to damage the surface of the substrate 1 in a region that becomes a peripheral portion of the active region L in a later process. Since the region that is the periphery of the active region L is located below the side wall spacer 16 at this time, in order to damage the substrate 1 in this region, impurity ion implantation is performed on the main surface of the substrate 1. Is performed from an oblique direction. This implantation of impurity ions is not an essential step, but if the surface of the substrate 1 is damaged in advance and the silicon covalent bond is locally cut, the active region L is formed when the substrate 1 is thermally oxidized. The peripheral part tends to be rounded. Further, when an element having a large atomic weight such as Ge (germanium) or As (arsenic) is used as the impurity, only the surface of the substrate 1 around the active region L can be damaged.

  Next, foreign matters remaining on the surface of the substrate 1 by cleaning using, for example, SC-1 solution (ammonia water / hydrogen peroxide solution mixture) and SC-2 solution (hydrochloric acid / hydrogen peroxide solution mixture). Then, the natural oxide film on the surface of the substrate 1 is removed by cleaning with hydrofluoric acid. Although not an indispensable step, as shown in FIG. 10, the surface of the substrate 1 is isotropically etched by performing the above-described cleaning for a longer time than usual, and an undercut is formed on the substrate 1 below the sidewall spacer 16. If this occurs, the peripheral portion of the active region L tends to be rounded in a later step.

Next, as shown in FIG. 11, a trench 2a having a depth of, for example, about 350 nm is formed in the substrate 1 in the element isolation region by dry etching using the silicon nitride film 14 and the sidewall spacer 16 as a mask. When the groove 2a is formed, the composition of a gas for etching the substrate 1 (for example, CF ₄ + O ₂ ) is adjusted to form a taper of about 80 ° on the side wall of the groove 2a. 6 is easily embedded in the groove 2a. However, it goes without saying that the taper angle is limited by the depth and width of the groove.

  Next, as shown in FIG. 12, the sidewall spacers 16 on the sidewalls of the silicon nitride film 14 are removed by wet etching using hydrofluoric acid. Although not an indispensable step, after performing this wet etching, further performing wet etching using SC-1 solution or the like to lightly round the surface of the substrate 1 below the side wall spacers 16; The peripheral portion of the active region L tends to be rounded by the next thermal oxidation treatment.

  As described above, in this embodiment, the groove 2a is formed in the substrate 1 in the element isolation region by dry etching using the silicon nitride film 14 and the sidewall spacers 16 formed on the sidewalls thereof as a mask. Thereby, the actual dimension W ′ of the active region L is larger than the dimension W of the silicon nitride film 14 defining the active region L by an amount corresponding to twice the film thickness (spacer length) Lsi of the sidewall spacer 16. (W ′ = W + 2Lsi> W). On the other hand, the interval between the active regions L along the short side direction (S ′ = S−2Lsi <S) is reduced accordingly. Therefore, when the dimension (W) and interval (S) of the short side of the silicon nitride film 14 defining the active region L are set to the minimum dimensions determined by the resolution limit of photolithography, respectively (W = S = minimum dimension). The dimension W ′ (> W) of the short side of the active region L actually obtained is larger than the minimum dimension determined by the resolution limit of photolithography, and the interval of the active regions L along the short side direction ( The dimension 2) S ′ (<S) of the groove 2a is smaller than the minimum dimension.

  Next, as shown in FIG. 13, the substrate 1 is thermally oxidized at about 850 ° C. to 1000 ° C. to form a thin silicon oxide film 11 having a thickness of about 10 nm on the inner wall of the groove 2a. This silicon oxide film 11 recovers damage from dry etching generated on the inner wall of the groove 2a, and at the same time, the interface between the silicon oxide film 6 embedded in the groove 2a and the substrate 1 (p-type well 3) in a later step. It is formed in order to relieve the stress that occurs. Further, by performing this thermal oxidation treatment, the surface of the substrate 1 at the periphery of the active region L is rounded to have a cross-sectional shape with convex roundness.

  As described above, the dimension of the active region L at the time when the groove 2a is formed in the substrate 1 of the element isolation region is larger than the dimension of the silicon nitride film 14 that defines the active region L (the thickness of the sidewall spacer 16). After that, even if a thin silicon oxide film 11 having a thickness of about 10 nm is formed on the inner wall of the trench 2a, the dimension (a) of the active region L is the dimension of the silicon nitride film 14 ( W) never smaller. Thus, according to the present embodiment, the surface of the substrate 1 at the end can be rounded without reducing the size of the active region L.

  The thermal oxidation treatment for rounding the periphery of the active region L may be performed in two steps. In this case, since the end portion is rounded to some extent by the first thermal oxidation treatment, it can be easily rounded by the second thermal oxidation treatment.

  If the thickness of the silicon oxide film 11 is too large, not only the size of the active region L is reduced, but also stress is generated in the peripheral portion of the active region L and the inner wall of the groove 2a, and defects are easily generated. Therefore, for example, when the thermal oxidation treatment is performed twice, the end portion is sufficiently rounded by the first thermal oxidation treatment, and the second thermal oxidation treatment is performed on the periphery of the active region L and the inner wall of the groove 2a. It is good also as light heat processing of the grade which improves a shape. In order to relieve the stress described above, the substrate 1 may be heat-treated in a high-temperature hydrogen atmosphere prior to the step of performing the thermal oxidation after removing the sidewall spacers 16. Further, the silicon oxide film 11 may be removed by wet etching using hydrofluoric acid or the like after round processing, or the film thickness may be reduced.

Next, as shown in FIG. 14, a silicon oxide film 6 is deposited by CVD on the substrate 1 including the inside of the groove 2a. The silicon oxide film 6 is deposited with a film thickness (for example, about 450 to 500 nm) thicker than the depth of the groove 2a so that the silicon oxide film 6 is buried in the groove 2a without any gap. The silicon oxide film 6 is deposited by a film forming method with good step coverage, such as a silicon oxide film formed by a CVD method using, for example, oxygen and tetraethoxysilane ((C ₂ H ₅ ) ₄ Si). . Prior to the step of depositing the silicon oxide film 6, a silicon nitride film (not shown) may be deposited thinly on the inner wall of the groove 2a by the CVD method. This silicon nitride film has an effect of suppressing the silicon oxide film 11 having a thin inner wall of the groove 2a from growing thickly toward the active region L when the silicon oxide film 6 embedded in the groove 2a is densified (baked). is there.

  Next, after the substrate 1 is thermally oxidized at about 1000 to 1150 ° C. to perform densification (baking) for improving the film quality of the silicon oxide film 6, as shown in FIG. By polishing the silicon oxide film 6 on the upper part of the groove 2a by the polishing (CMP) method, the surface thereof is flattened. This polishing is performed using the silicon nitride film 14 covering the substrate 1 in the active region L as a stopper so that the surface of the silicon nitride film 14 is exposed and the silicon oxide film 6 on the silicon nitride film 14 does not remain. The end point is the time when a slight over polishing is performed.

  When the silicon oxide film 6 is planarized, first, the silicon oxide film 6 on the silicon nitride film 14 is removed by dry etching using the photoresist film as a mask. Subsequently, after removing the photoresist film, the groove 2a is removed. The silicon oxide film 6 remaining on the top may be polished by a CMP method. The densification of the silicon oxide film 6 may be performed after the silicon oxide film 6 is planarized. In this case, since the densification is performed with the silicon oxide film 6 being thin, heat treatment conditions can be reduced as compared with the case where the thick silicon oxide film 6 before polishing is densified. Through the steps so far, the element isolation trench 2 in which the silicon oxide film 6 is embedded in the trench 2a is substantially completed.

  Next, the silicon nitride film 14 covering the substrate 1 in the active region L is removed by wet etching using hot phosphoric acid, thereby exposing the silicon oxide film 13 therebelow. When this etching is performed, as shown in FIG. 16, a high thickness corresponding to the film thickness of the silicon nitride film 14 is formed between the surface of the silicon oxide film 13 and the surface of the silicon oxide film 6 embedded in the element isolation trench 2. A level difference occurs.

  Next, as shown in FIG. 17, when the silicon oxide film 13 on the surface of the substrate 1 in the active region L is wet-etched with hydrofluoric acid, the surface of the substrate 1 in the active region L is exposed and simultaneously oxidized in the element isolation trench 2. The surface of the silicon film 6 is etched, and the step is reduced.

  When the wet etching is performed, the end portion of the silicon oxide film 6 in the element isolation trench 2, that is, the silicon oxide film 6 in the region in contact with the silicon nitride film 14 is exposed not only to the upper surface but also to the side surface. Therefore, the amount to be etched is larger than that in the portion away from the active region L. However, in this embodiment, since the dimension of the active region L is larger than the dimension of the silicon nitride film 14, the end of the silicon oxide film 6 at the time when the silicon nitride film 14 is removed is the end of the element isolation trench 2. It is located on the active region L side from the part. Therefore, even if the amount of etching at the end of the silicon oxide film 6 increases, the silicon oxide film 6 does not greatly recede (recess) downward at the end of the element isolation trench 2.

  Next, as shown in FIG. 18, the substrate 1 is thermally oxidized at about 850 ° C. to form a thin silicon oxide film 17 having a thickness of about 10 nm on the surface of the substrate 1 in the active region L. This silicon oxide film 17 is formed in order to reduce the influence of damage and contamination of the substrate 1 due to impurity ion implantation performed in the next step.

  Next, as shown in FIG. 19, in order to form wells (p-type well 3 and n-type well 4), p-type impurities (boron) and n-type impurities (for example, phosphorous) are applied to substrate 1 through silicon oxide film 17. ) Ion implantation. In addition, p-type impurities (boron) are ion-implanted into the substrate 1 through the silicon oxide film 17 in order to form a p-type semiconductor region (not shown) in which the channel of the memory cell selection MISFET Qs is formed. Impurity ions for forming wells (p-type well 3 and n-type well 4) are implanted into a deep region of substrate 1 with high energy, and impurity ions for forming a channel are shallow regions of substrate 1 with low energy. Type in.

  Next, as shown in FIG. 20, the substrate 1 is heat-treated at about 950 ° C. to diffuse the impurities, thereby forming the p-type well 3 and the n-type well 4. The n-type well 4 below the p-type well 3 is formed to prevent noise from entering the p-type well 3 through the substrate 1 from an input / output circuit (not shown).

  Next, after removing the silicon oxide film 17 on the surface of the substrate 1 by wet etching using hydrofluoric acid, the substrate 1 is thermally oxidized at about 800 to 850 ° C., so that a clean surface having a thickness of about 7 nm is formed on the surface. A gate oxide film 7 is formed. As described above, the surface of the substrate 1 at the periphery of the active region L is convexly rounded. Therefore, the thickness of the gate oxide film 7 is such that the central portion and the peripheral portion of the active region L Almost equal.

The gate oxide film 7 may be composed of a silicon oxynitride film containing silicon nitride in a part thereof. Since the silicon oxynitride film has higher effects of suppressing the generation of interface states in the film and reducing electron traps than the silicon oxide film, the hot carrier resistance of the gate oxide film 7 can be improved. it can. In order to form the silicon oxynitride film, for example, the substrate 1 may be thermally oxidized in a nitrogen-containing gas atmosphere such as NO or NO ₂ .

  In this way, by rounding the periphery of the active region L, a problem that the thickness of the gate oxide film 7 becomes thin (= thinning) in the periphery of the active region L is prevented, and in the periphery of the active region L Electric field concentration of the gate voltage is suppressed. As a result, generation of MOS-IV kink characteristics (or hump characteristics) in which drain current flows at a low gate voltage and reduction in breakdown voltage of the gate oxide film 7 can be prevented, and characteristics of the memory cell selection MISFET Qs are improved. In addition, since the occurrence of leakage current in the periphery of the active region L is suppressed, the refresh characteristics of the memory cell are improved. Also, variations in the threshold voltage of the MISFET due to thinning and MOS-IV kink characteristics are prevented.

  FIG. 21A is a cross-sectional view along the B-B ′ line direction of the substrate 1 when the gate oxide film 7 is formed. As shown in the drawing, in the steps so far, the short side dimension (a) of the active region L is equal to or larger than the short side dimension (W) of the silicon nitride film 14 that defines the dimension of the active region L (a ≧ W). The distance between the active regions L along the short side direction (the dimension of the element isolation trench 2) (b) is equal to or less than the distance (S) between the silicon nitride films 14 (b ≦ S). That is, when the short side dimension (W) and the interval (S) of the silicon nitride film 14 are set to the minimum dimension (for example, 0.16 μm) determined by the resolution limit of photolithography, the short side dimension of the active region L is obtained. (A) becomes more than this minimum dimension.

  On the other hand, after forming the element isolation trench by dry etching using only the silicon nitride film 14 as a mask without forming the side wall spacer 16 on the side wall of the silicon nitride film 14 pattern for defining the active region, FIG. In the case of rounding the periphery of the active region by round processing corresponding to No. 13, the round process can sufficiently round the periphery of the active region. Therefore, as shown in FIG. The dimension (a ′) of the short side of the region L is smaller than the dimension (W) of the short side of the silicon nitride film 14 that defines the dimension of the active region L (a ′ <W). The interval between the active regions L (the dimension of the element isolation trench 2) (b ′) is larger than the interval (S) between the silicon nitride films 14 (b ′> S). That is, in this case, since the active region L cannot secure the minimum dimension determined by the resolution limit of photolithography, a memory cell cannot be formed.

  Thus, for high integration of memory cells, the width (W ′) of the silicon nitride film 14 pattern and the interval (S ′) between the silicon nitride film 14 patterns for defining the active region are resolved by photolithography. Even in the case of the minimum processing dimension determined by the limit, the dimension (a) of the short side of the active region L that becomes the gate width of the MISFET Qs is equal to or larger than the minimum processing dimension, so that the MISFET Qs can be miniaturized. As a result, the wiring pitch (Lw ′ + Ls ′) in the bit line BL direction is configured to be twice the minimum processing size for high integration, and the size (a) of the active region L can be secured, and the MISFET Qs is miniaturized. be able to.

  Next, as shown in FIG. 22, a gate electrode 8 (word line WL) is formed on the gate oxide film 7. For the gate electrode 8 (word line WL), for example, a low-resistance polycrystalline silicon film doped with phosphorus (P) is deposited on the gate oxide film 7 by a CVD method, and then a WN film and a W film are formed thereon by a sputtering method. Then, a silicon nitride film 9 is deposited thereon by CVD, and these films are patterned by dry etching using a photoresist film (not shown) as a mask. The gate electrode 8 (word line WL) is formed such that the line width (gate length) and the interval thereof are the minimum dimensions (for example, 0.16 μm) determined by the resolution limit of photolithography.

  FIG. 23 is a cross-sectional view of the substrate 1 along the extending direction of the gate electrode 8 (word line WL). As shown in the figure, the word line WL extends across the short side of the active region L and the element isolation trench 2, and above the gate oxide film 7 formed on the surface of the substrate 1 in the active region L, the memory cell It functions as the gate electrode 8 of the selection MISFET Qs. As described above, in the present embodiment, the surface of the silicon oxide film 6 embedded in the element isolation trench 2 does not greatly recede (recess) downward near the periphery of the active region L. The portion does not reach the side wall of the element isolation trench 2 where the impurity concentration for forming the channel decreases. As a result, variations in the threshold voltage of the memory cell selecting MISFET Qs can be prevented.

  Next, an n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 3 to form an n-type semiconductor region 10 (source, drain), whereby the memory cell selection MISFET Qs shown in FIGS. Is completed.

  Next, as shown in FIG. 24, a silicon nitride film 18 having a film thickness of about 50 to 100 nm is deposited on the substrate 1 by the CVD method, and subsequently, an oxide film having a film thickness of about 600 nm is deposited on the silicon nitride film 18 by the CVD method. After the silicon film 20 is deposited, the silicon oxide film 20 is polished by CMP to flatten the surface.

  Next, as shown in FIGS. 25 and 26, using the photoresist film (not shown) as a mask, the silicon oxide film 20 and nitride on the source and drain (n-type semiconductor region 10) of the memory cell selection MISFET Qs. By dry-etching the silicon film 18, a contact hole 21 is formed in one upper part of the source and drain (n-type semiconductor region 10), and a contact hole 22 is formed in the other upper part. A plug 23 is formed inside 22. The contact holes 21 and 22 are formed by self-alignment with the gate electrode 8 using the silicon nitride film 18 as an etching mask. The plug 23 is formed by depositing a low resistance polycrystalline silicon film doped with an n-type impurity such as phosphorus (P) on the silicon oxide film 20 including the insides of the contact holes 21 and 22, and then depositing the polycrystalline silicon film. Is etched back (or polished by CMP) and left only in the contact holes 21 and 22.

  Next, as shown in FIGS. 27 and 28, a silicon oxide film 24 having a thickness of about 200 nm is deposited on the silicon oxide film 20 by CVD, and then oxidized using a photoresist film (not shown) as a mask. By through-etching the silicon film 24, a through hole 25 is formed above the contact hole 21 (plug 23). As shown in FIG. 24, the through hole 25 is formed in an elongated pattern in which a part thereof extends to the upper part of the element isolation trench 2.

  Next, as shown in FIGS. 29 and 30, after the plug 26 is formed inside the through hole 25, the bit line BL is formed on the silicon oxide film 24. The plug 26 is formed by depositing a Co film (or Ti film) on the silicon oxide film 24 including the inside of the through hole 25 by a sputtering method, and further depositing a TiN film and a W film on the upper portion by a CVD method. The W film, the TiN film, and the Co film (or Ti film) on the silicon film 24 are polished by the CMP method, and these films are formed only in the through holes 25.

  The bit line BL is formed by depositing a W film having a thickness of about 200 nm on the silicon oxide film 24 by sputtering and then dry etching the W film using a photoresist film (not shown) as a mask. To do. The bit lines BL are formed so as to extend linearly at the same line width and the same interval along the direction (AA ′ line direction) orthogonal to the gate electrode 8 (word line WL). The width Lw ′ and the interval Ls ′ are the minimum dimensions determined by the resolution limit of photolithography (for example, 0.16 μm = Lw ′ = Ls ′ = Lw = Ls).

  Next, as shown in FIG. 31, a silicon oxide film 27 having a film thickness of about 300 nm is deposited on the bit line BL by CVD, and then the silicon oxide film 27 and the silicon oxide film 24 underneath are dry-etched. Thus, a through hole 28 is formed above the contact hole 22 (plug 26).

  The through hole 28 is formed with a diameter smaller than the minimum dimension determined by the resolution limit of photolithography in order to prevent a short circuit between the plug 29 and the bit line BL formed in the next step. The through hole 28 having such a fine diameter is formed by the following method, for example.

  First, after a silicon oxide film 27 is deposited on the bit line BL, a first polycrystalline silicon film (not shown) is deposited on the silicon oxide film 27. Next, the polycrystalline silicon film is dry-etched using the photoresist film as a mask, thereby forming a through hole in the polycrystalline silicon film directly above the contact hole 22 (plug 26). The diameter of the through hole is the minimum dimension determined by the resolution limit of photolithography.

  Next, after depositing a second polycrystalline silicon film on the first polycrystalline silicon film including the inside of the through hole, the second polycrystalline silicon film is anisotropically etched to form an inner wall of the through hole. By leaving it only at the side wall, a side wall spacer is formed on the inner wall of the through hole. Thereby, the diameter of the through hole becomes smaller than the minimum dimension determined by the resolution limit of photolithography.

  Next, after the through hole 28 is formed in the silicon oxide film 27 at the bottom of the through hole and the silicon oxide film 24 below it by dry etching using the first polycrystalline silicon film and the sidewall spacer as a mask, it is unnecessary. The first polycrystalline silicon film and sidewall spacers thus formed are removed by etching.

  Next, as shown in FIG. 32, after a plug 29 is formed inside the through hole 28, a silicon nitride film 30 having a thickness of about 100 nm is deposited on the silicon oxide film 27 by CVD, followed by nitriding. A thick silicon oxide film 31 having a thickness of about 1.3 μm is deposited on the silicon film 30 by a CVD method. For example, the plug 29 is formed by depositing a low-resistance polycrystalline silicon film doped with an n-type impurity such as phosphorus (P) on the silicon oxide film 27 including the inside of the through hole 28 and then etching back the polycrystalline silicon film. Thus, it is formed by leaving only the inside of the through hole 28. The silicon nitride film 30 is used as an etching stopper when the silicon oxide film 31 is dry etched in the next step.

  Next, as shown in FIG. 33, the silicon oxide film 31 is dry-etched using a photoresist film (not shown) as a mask, and then the silicon nitride film 30 under the silicon oxide film 31 is wet-etched. A groove 32 is formed in the upper portion of the through hole 28.

  Next, as shown in FIG. 34, a low-resistance polycrystalline silicon film having a thickness of about 50 nm doped with n-type impurities such as phosphorus (P) is formed on the silicon oxide film 31 including the inside of the trench 32 by the CVD method. After the deposition, the polycrystalline silicon film above the silicon oxide film 31 is etched back and removed, thereby forming the lower electrode 33 along the inner wall of the trench 32.

  Next, as shown in FIG. 35, a capacitor insulating film 34 made of, for example, a tantalum oxide film and an upper electrode 35 made of, for example, a TiN film are formed on the lower electrode 33. In order to form the capacitor insulating film 34 and the upper electrode 35, first, a thin tantalum oxide film having a film thickness of about 20 nm is deposited on the silicon oxide film 31 including the inside of the trench 32 by the CVD method. A TiN film is deposited on the upper portion of the trench 32 by CVD and sputtering to embed the TiN film in the groove 32 without gaps, and then dry etching using a photoresist film (not shown) as a mask to dry the TiN film and tantalum oxide. Pattern the film. As a result, an information storage capacitive element C including the lower electrode 33 made of a polycrystalline silicon film, the capacitive insulating film 34 made of a tantalum oxide film, and the upper electrode 35 made of a TiN film is formed. Further, through the steps so far, a DRAM memory cell composed of the memory cell selection MISFET Qs and the information storage capacitive element C connected in series is completed.

  Thereafter, about two layers of Al (aluminum) wiring are formed on the information storage capacitor element C, and a surface protective film is further formed on the upper portion of the Al wiring.

(Embodiment 2)
In FIG. 36, a trench 2a is formed in the substrate 1 in the element isolation region by dry etching using the silicon nitride film 14 and sidewall spacers 16 (not shown in the figure) formed on the sidewalls as masks. After the wall spacer 16 is removed by wet etching, the substrate 1 is thermally oxidized to form a thin silicon oxide film 11 on the inner wall of the groove 2a, and the surface of the substrate 1 in the periphery of the active region L is rounded It is sectional drawing of the board | substrate 1 which shows. The steps up to here are the same as the steps (FIGS. 4 to 13) described in the first embodiment.

  Next, as shown in FIG. 37, the silicon nitride film 14 is isotropically etched by a dry etching process or the like. By this etching, the size of the silicon nitride film 14 is reduced, and its peripheral portion is set back to the center side of the active region L. The receding amount of the silicon nitride film 14 is, for example, about 20 nm, but the silicon oxide film 6 embedded in the groove 2a in the subsequent process until the gate oxide film 7 is formed on the surface of the substrate 1 in the active region L. It may be determined in consideration of the amount of recession (recess) to the substrate 1 side in the process.

  Next, in accordance with the steps described in the first embodiment (FIGS. 14 and 15), a silicon oxide film 6 is deposited on the substrate 1 including the inside of the groove 2a by the CVD method, and then the film quality of the silicon oxide film 6 is increased. After densification (baking) for improving the above, the silicon oxide film 6 on the upper portion of the groove 2a is polished by CMP to flatten the surface. Through the steps so far, the element isolation trench 2 in which the silicon oxide film 6 is embedded in the trench 2a is substantially completed (FIG. 38).

  Next, as in the first embodiment, the silicon nitride film 14 covering the substrate 1 in the active region L is removed by wet etching using hot phosphoric acid, thereby exposing the silicon oxide film 13 therebelow. When this etching is performed, a step having a height corresponding to the remaining film thickness of the silicon nitride film 14 is generated between the surface of the silicon oxide film 13 and the surface of the silicon oxide film 6 embedded in the element isolation trench 2. However, when the silicon oxide film 13 on the surface of the substrate 1 in the active region L is wet-etched with hydrofluoric acid, the surface of the substrate 1 in the active region L is exposed and the surface of the silicon oxide film 6 is simultaneously etched, and this step is reduced. . (FIG. 39).

  When the wet etching is performed, the end portion of the silicon oxide film 6 in the element isolation trench 2, that is, the silicon oxide film 6 in the region in contact with the silicon nitride film 14 is exposed not only to the upper surface but also to the side surface with hydrofluoric acid. Therefore, the amount to be etched is larger than that in the portion away from the active region L. However, in this embodiment, the periphery of the silicon nitride film 14 is retreated to the center side of the active region L, and the offset amount between the periphery of the active region L and the periphery of the silicon nitride film 14 is sufficiently increased in advance. Therefore, the end portion of the silicon oxide film 6 at the time when the silicon nitride film 14 is removed is located considerably closer to the center than the peripheral portion of the active region L. Therefore, even if the end portion of the silicon oxide film 6 recedes to the element isolation trench 2 side by wet etching for reducing the step, the silicon oxide film 6 recedes greatly at the end portion of the element isolation trench 2 ( There will be no recess). Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  As described above, according to the present embodiment, the problem that the surface of the silicon oxide film 6 in the element isolation trench 2 recedes (recesses) in the vicinity of the active region L can be prevented, so that the memory cell selection MISFET Qs Variations in threshold voltage can be suppressed.

  The manufacturing method of this embodiment in which the offset amount between the peripheral portion of the active region L and the peripheral portion of the silicon nitride film 14 is increased by retracting the peripheral portion of the silicon nitride film 14 toward the center of the active region L. When the design rule of the MISFET becomes very fine, and it becomes impossible to suppress the recession (recess) of the silicon oxide film 6 at the end of the element isolation trench 2 only by forming the sidewall spacer 16 on the side wall of the silicon nitride film 14. This is especially effective as a countermeasure.

  The recession of the silicon nitride film 14 by the above isotropic etching is preferably performed after performing a thermal oxidation process for rounding the surface of the substrate 1 in the periphery of the active region L. If dry etching is performed to recede the silicon nitride film 14 before round processing, that is, before forming the silicon oxide film 11 on the inner wall of the groove 2a by thermal oxidation, the surface of the substrate 1 on the inner wall of the groove 2a is also etched to some extent. As a result, the dimension of the active region L is likely to be reduced due to isotropic retreat.

(Embodiment 3)
Next, an embodiment in which the present invention is applied to a manufacturing process of an LSI (hereinafter referred to as a DRAM-logic mixed LSI) in which a DRAM and a logic LSI are formed on the same substrate will be described.

  In order to operate the logic LSI at high speed, it is required to form the gate oxide film as thin as possible. On the other hand, in a DRAM that requires a high voltage for boosting the word line potential, the thickness of the gate oxide film cannot be made very thin from the viewpoint of securing a breakdown voltage. Therefore, when manufacturing a DRAM-logic mixed LSI, it is necessary to form at least two types of MISFETs having different gate oxide film thicknesses.

  In the process of forming two types of gate oxide films having different thicknesses on the same substrate, silicon oxide in the element isolation trench is divided into a region where a thin gate oxide film is formed and a region where a thick gate oxide film is formed on the substrate. The amount of recession in the film will vary. For this reason, from the viewpoint of preventing variation in the characteristics of the MISFET, it is necessary to take a measure for making the amount of recession (recess) uniform between the region where the thin gate oxide film is formed and the region where the thick gate oxide film is formed.

  In FIG. 40, after the silicon nitride film 14 is formed on the substrate 1 in the active region L via the silicon oxide film 13 in accordance with the steps described in the first embodiment (FIGS. 4 to 8), the sidewall is oxidized. It is sectional drawing of the board | substrate 1 in which the side wall spacer 16A which consists of a silicon film was formed. 2A shows the substrate 1 in the logic region (first region) where a thin gate oxide film is formed, and FIG. 2B shows the DRAM region (second region) where a thick gate insulating film is formed. The substrate 1 is shown. The process so far is the same in the logic area and the DRAM area.

  Next, as shown in FIG. 41, the substrate 1 in the logic region is covered with a photoresist film 41, and the sidewall spacers 16A formed on the sidewalls of the silicon nitride film 14 in the DRAM region are etched to obtain the film thickness ( Reduce the spacer length. As a result, two types of sidewall spacers 16A and 16B having different spacer lengths are formed in the logic region and the DRAM region.

  Next, after removing the photoresist film 41, as shown in FIG. 42, a groove 2a is formed in the substrate 1 in the logic region by dry etching using the silicon nitride film 14 and the sidewall spacers 16A as a mask. A groove 2a is formed in the substrate 1 in the DRAM region by dry etching using the film 14 and the side wall spacer 16B as a mask. At this time, since the side wall spacers 16A and 16B formed on the side walls of the silicon nitride film 14 have different spacer lengths, the offset amount between the peripheral part of the active region L and the peripheral part of the silicon nitride film 14 is logic. The area differs from the DRAM area. That is, the distance from the sidewall of the trench 2a (peripheral portion of the active region L) to the peripheral portion of the silicon nitride film 14 is larger in the logic region where the sidewall spacer 16A having a larger thickness is formed.

  Next, after removing the sidewall spacers 16A and 16B on the sidewalls of the silicon nitride film 14 by wet etching using hydrofluoric acid, as shown in FIG. 43, the steps described in the first embodiment (FIG. 13 to FIG. 13). According to FIG. 15), the substrate 1 is thermally oxidized to form a thin silicon oxide film 11 on the inner wall of the groove 2a, and after rounding the surface of the substrate 1 around the active region L, the inside of the groove 2a is formed. The silicon oxide film 6 deposited on the substrate 1 is densified (baked), and then the silicon oxide film 6 on the upper portion of the groove 2a is polished by CMP to flatten the surface. Through the steps so far, the element isolation trench 2 in which the silicon oxide film 6 is embedded in the trench 2a is substantially completed.

  As described above, the distance (offset amount) from the peripheral portion of the active region L to the peripheral portion of the silicon nitride film 14 is larger in the logic region than in the DRAM region. For this reason, the end of the silicon oxide film 6 in the element isolation trench 2 is located closer to the center of the active region L in the logic region than in the DRAM region.

  Next, as shown in FIG. 44, the silicon nitride film 14 is removed, the silicon oxide film 13 is removed by wet etching, and the silicon oxide film 17 is formed in accordance with the steps described in the first embodiment (FIGS. 16 to 20). Impurity ion implantation through the silicon oxide film 17, formation of wells (p-type well 3 and n-type well 4) by heat treatment, removal of the silicon oxide film 17 by wet etching, and activation of each of the logic region and the DRAM region A clean gate oxide film 7 having a thickness of about 6 nm to 7 nm is formed on the surface of the substrate 1 in the region L.

  When the above-described wet etching of the silicon oxide film 13 is performed, the end of the silicon oxide film 6 retreats to the element isolation trench 2 side. As described above, since the end of the silicon oxide film 6 is located closer to the center of the active region L than the DRAM region, the end of the silicon oxide film 6 at the end of the element isolation trench 2 is formed. The amount of retreat is less in the logic area.

  Next, as shown in FIG. 45, the substrate 1 in the DRAM region is covered with a photoresist film 42, and the gate oxide film 7 on the surface of the substrate 1 in the logic region is selectively removed by wet etching using hydrofluoric acid. Thus, the surface of the substrate 1 is exposed. When this wet etching is performed, the surface of the silicon oxide film 6 embedded in the element isolation trench 2 in the logic region is also etched at the same time, and its end part recedes to the element isolation trench 2 side. At this time, since the substrate 1 in the DRAM region is covered with the photoresist film 42, the gate oxide film 7 formed on the surface of the substrate 1 in this region and the silicon oxide film 6 in the element isolation trench 2 are not etched. As a result, the retraction amount of the silicon oxide film 6 at the end portion of the element isolation trench 2 is substantially the same in the logic region and the DRAM region.

  Next, after removing the photoresist film 42, as shown in FIG. 46, the substrate 1 is thermally oxidized to form a thin gate oxide film 7A having a thickness of about 4 nm on the surface of the substrate 1 in the logic region. In addition, the gate oxide film 7 formed on the surface of the substrate 1 in the DRAM region is further oxidized by this thermal oxidation, and grows into a thick gate oxide film 7B having a thickness of about 8 nm to 9 nm.

  Thus, according to the present embodiment, the silicon oxide film 6 recedes at the end of the element isolation trench 2 between the logic region where the thin gate oxide film 7A is formed and the DRAM region where the thick gate oxide film 7B is formed. Since the (recess) amount can be made uniform, variation in characteristics between the MISFET formed in the logic region and the MISFET formed in the DRAM region can be reduced.

  In addition, according to the present embodiment, the groove 2a is formed in the substrate 1 in the element isolation region by dry etching using the silicon nitride film 14 and the sidewall spacers 16A and 16B formed on the sidewalls as a mask. The same effect as 1 can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Although the case where the present invention is mainly applied to a DRAM has been described in the above embodiment, the present invention is not limited to this, and the present invention can be widely applied to various LSIs in which a fine MISFET is formed on a substrate having an element isolation groove.

  The present invention is used for manufacturing a semiconductor integrated circuit device composed of MISFETs.

It is a principal part top view of the board | substrate in the middle of the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. FIG. 3 is an equivalent circuit diagram of a DRAM memory array. It is principal part sectional drawing of the board | substrate along the A-A 'line | wire and B-B' line | wire of FIG. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. (A), (b) is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. (A), (b) is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. (A), (b) is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. (A), (b) is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. (A), (b) is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. (A), (b) is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. (A), (b) is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. (A), (b) is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation trench 2a Groove 3 P-type well 4 N-type well 6 Silicon oxide film 7, 7A, 7B Gate oxide film 8 Gate electrode 9 Silicon nitride film 10 N-type semiconductor region 11 Silicon oxide film 13 Silicon oxide film 14 Nitride Silicon film 16, 16A, 16B Side wall spacer 17 Silicon oxide film 18 Silicon nitride film 20 Silicon oxide film 21, 22 Contact hole 23 Plug 24 Silicon oxide film 25 Through hole 26 Plug 27 Silicon oxide film 28 Through hole 29 Plug 30 Silicon nitride Film 31 Silicon oxide film 32 Groove 33 Lower electrode 34 Capacitor insulating film 35 Upper electrode 41, 42 Photoresist film BL Bit line C Information storage capacitor Qs Memory cell selection MISFET
WL Word line

Claims (19)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) a step of selectively forming a silicon nitride film on the main surface of the substrate;
(B) forming a groove in the substrate in an element isolation region by forming a sidewall spacer on the sidewall of the silicon nitride film and then etching the substrate in a self-aligned manner with respect to the sidewall spacer;
(C) After removing the sidewall spacers, the substrate surface in the periphery of the active region is rounded by thermally oxidizing the substrate;
(D) etching the silicon nitride film to retract the periphery of the silicon nitride film toward the center of the active region;
(E) After forming an insulating film on the substrate including the inside of the groove, the insulating film on the silicon nitride film is removed, and the insulating film is embedded in the groove to define the active region Forming an element isolation groove to be formed.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the etching for causing the peripheral portion of the silicon nitride film to recede toward the center of the active region is isotropic etching. A method of manufacturing a circuit device.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein after the insulating film is embedded in the trench, the substrate is thermally oxidized to form a gate insulating film of a MISFET on the substrate surface of the active region. A method of manufacturing a semiconductor integrated circuit device, further comprising forming and then forming a gate electrode of the MISFET on the gate insulating film.   4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein a step of forming a silicon oxide film on the surface of the substrate in the active region prior to the step of forming the gate insulating film, and the substrate through the silicon oxide film. A step of implanting impurity ions into the substrate, a step of heat-treating the substrate to diffuse the impurities, a step of forming a well in the substrate, and a step of removing the silicon oxide film by etching the surface of the substrate A method for manufacturing a semiconductor integrated circuit device, further comprising:   4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the gate electrode of the MISFET extends across the active region and the element isolation trench.   4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the MISFET is a memory cell selecting MISFET constituting a part of a DRAM memory cell.   7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the silicon nitride film has an elongated island-like planar pattern, and the dimension in the first direction of the silicon nitride film and the A method of manufacturing a semiconductor integrated circuit device, wherein a distance between the silicon nitride films adjacent in the first direction is equal to a minimum dimension determined by a resolution limit of photolithography.   8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the gate electrode of the MISFET linearly extends with the same width and the same interval along a second direction intersecting the first direction of the active region. The method for manufacturing a semiconductor integrated circuit device is characterized in that the width and the interval are each equal to a minimum dimension determined by a resolution limit of photolithography.   In the method for manufacturing a semiconductor integrated circuit device according to claim 1, after forming the sidewall spacer on the sidewall of the silicon nitride film, prior to the step of forming the groove in the substrate, The method of manufacturing a semiconductor integrated circuit device, further comprising the step of implanting impurity ions in the vicinity of the surface of the substrate including the lower region of the sidewall spacer.   10. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein when the substrate is etched in a self-aligned manner with respect to the sidewall spacer to form the groove, Etching the vicinity of the surface isotropically to etch near the surface of the substrate in the lower region of the sidewall spacer, and then anisotropically etching the substrate to form the groove A method of manufacturing a semiconductor integrated circuit device.   11. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein after the sidewall spacer is removed, the vicinity of the surface of the substrate in a lower region of the sidewall spacer is isotropically etched. Then, the substrate surface in the peripheral portion of the active region is round-processed by thermally oxidizing the substrate.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the thermal oxidation for round processing the surface of the substrate is performed in a plurality of times. Manufacturing method.   13. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the inner surface of the groove is etched prior to the step of embedding the insulating film in the groove after rounding the surface of the substrate. Thus, a method of manufacturing a semiconductor integrated circuit device is characterized in that the silicon oxide film formed on the inner wall of the groove is removed or thinned by thermal oxidation during the round processing. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) a step of selectively forming a silicon nitride film on each main surface of the first region and the second region of the substrate;
(B) forming a first sidewall spacer on a sidewall of the silicon nitride film remaining on the substrate;
(C) Covering the first region of the substrate with a first photoresist film and etching the first sidewall spacer in the second region, thereby forming a sidewall of the silicon nitride film in the second region; Forming a second sidewall spacer having a thickness smaller than that of the first sidewall spacer;
(D) forming a groove in the substrate by removing the first photoresist film and then etching the substrate in a self-aligned manner with respect to the first sidewall spacer and the second sidewall spacer; ,
(E) removing the first sidewall spacer and the second sidewall spacer and then thermally oxidizing the substrate to round the substrate surface in the periphery of the active region;
(F) After forming an insulating film on the substrate including the inside of the groove, the insulating film on the silicon nitride film is removed, and the insulating film is embedded in the groove to define the active region Forming an element isolation groove to be formed. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein after the step (f),
(G) removing the silicon nitride film and performing an etching process to reduce a step between the surface of the substrate in the active region and the surface of the insulating film in the element isolation trench;
(H) forming a first gate insulating film of a first MISFET on the surface of the active region by thermally oxidizing the substrate;
(I) removing the first gate oxide film in the first region by covering the second region of the substrate with a second photoresist film and etching the surface of the first region of the substrate; ,
(J) forming a second gate oxide film of a second MISFET on the surface of the first region of the substrate by thermally oxidizing the substrate after removing the second photoresist film;
A method for manufacturing a semiconductor integrated circuit device, further comprising: A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a first layer on the first region of the main surface of the substrate, forming a second layer on the second region of the main surface, and then forming a first sidewall on the side wall of the first layer; And forming a second sidewall having a width smaller than the width of the first sidewall on the sidewall of the second layer,
(B) A first groove is formed in the main surface of the first region in a self-aligned manner with respect to the first sidewall, and the main surface of the second region is formed with respect to the second sidewall. Forming the second groove in a self-aligning manner;
(C) burying a first insulating film in each of the first groove and the second groove;
(D) removing each of the first layer and the second layer;
(E) a step of forming a second insulating film on the main surface of the substrate after the step (d);
(F) After selectively removing the second insulating film in the first region, a third insulating film having a thickness smaller than that of the second insulating film is formed on the main surface of the first region. Forming step.   17. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the second insulating film and the third insulating film are formed by oxidizing a main surface of the substrate. Method.   18. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the second insulating film and the third insulating film are MISFET gate insulating films.   19. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein the first region is an active region in which a MISFET included in a logic circuit is formed, and the second region is A method of manufacturing a semiconductor integrated circuit device, comprising an active region in which a MISFET constituting a memory cell is formed.

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