JP2006245048A - Electronic component, multilayer ceramic capacitor and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component, a multilayer ceramic capacitor and an electronic apparatus in which deterioration in insulation resistance can be suppressed under high temperature high humidity environment. <P>SOLUTION: A pair of terminal electrodes 11, 13 comprise first electrode layers 11a, 13a, second electrode layers 11b, 13b, and third electrode layers 11c, 13c. The first electrode layers 11a, 13a are formed on the outer surface of a capacitor element 3 by baking conductive paste. The second electrode layers 11b, 13b are formed on the first electrode layers 11a, 13a by Ni plating. The third electrode layers 11c, 13c are formed on the second electrode layers 11b, 13b by Sn plating. Thickness of the first electrode layers 11a, 13a is set at 10 μm or less. Generation rate of pores in the first electrode layers 11a, 13a is set at 10% or less by pore area ratio in the cutting plane. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic component, a multilayer ceramic capacitor, and an electronic device.

As this type of electronic component, an electronic component including an element body and a terminal electrode formed on the element body is known (see, for example, Patent Document 1). The electronic component described in Patent Document 1 is a multilayer ceramic capacitor, in which a terminal electrode is formed on the outer surface of an element body, and a first electrode layer formed by baking a conductive paste; It has the 2nd electrode layer formed by Ni plating on one electrode layer, and the 3rd electrode layer formed by Sn plating or Sn alloy plating on the 2nd electrode layer.
JP 2002-203736 A

  An object of the present invention is to provide an electronic component, a multilayer ceramic capacitor, and an electronic device that can suppress the occurrence of insulation resistance deterioration under a high temperature and high humidity environment.

  In recent years, due to a demand for environmental protection, when an electronic component is mounted on a substrate by soldering, a lead-free solder, so-called lead-free solder has been used. This lead-free solder mainly contains Sn as a main component, and Sn—Ag—Cu, Sn—Cu, Sn—Sb, Sn—Zn—Al, and Sn—Zn—Bi solders are mainly used. In recent years, Sn-Zn solders having excellent solderability (solder wettability), soldering strength, and the like have been widely used.

  Therefore, when the present inventors experimentally investigated various characteristics of electronic components mounted on a substrate using lead-free solder containing Zn, the fact that the insulation resistance deteriorates greatly in a high temperature and high humidity environment. Newly found.

  The present inventors produced an electronic device in which a multilayer ceramic capacitor was mounted on a substrate with Sn—Zn—Al solder, and performed an acceleration test on the electronic device. The multilayer ceramic capacitor subjected to the acceleration test is a 2012 type (length 2.0 mm, width 1.2 mm, and height 1.0 mm) multilayer ceramic capacitor described in Patent Document 1, Similarly, the terminal electrode has a first electrode layer formed by baking a conductive paste containing Cu, a second electrode layer formed by Ni plating on the first electrode layer, and a second electrode layer And a third electrode layer formed by Sn plating.

In the acceleration test, a DC voltage of 4.0 V was continuously applied to an electronic device (multilayer ceramic capacitor) for 40 hours in a constant temperature and humidity environment (temperature: 121 ° C., relative humidity: 95%, pressure: 2 atm). . The insulation resistance of the multilayer ceramic capacitor before the acceleration test was 1 × 10 ⁸ Ω, whereas the insulation resistance of the multilayer ceramic capacitor after the lapse of a predetermined time (2 hours or more) from the acceleration test was 1 × 10 ⁶ Ω. Yes, the insulation resistance deteriorated. Note that the B characteristic of the multilayer ceramic capacitor subjected to the acceleration test is 10 μF.

  When the present inventors analyzed the multilayer ceramic capacitor in which the insulation resistance was deteriorated by the acceleration test, the Zn atoms contained in the lead-free solder are in the boundary region between the second electrode layer and the third electrode layer. The fact that it exists is confirmed. Presuming from this fact, it is considered that Zn atoms contained in the lead-free solder move into the element body of the multilayer ceramic capacitor due to some factors, and deteriorate the insulation resistance. Therefore, if the movement of Zn atoms contained in the lead-free solder into the element body can be suppressed, it is considered possible to prevent the insulation resistance from deteriorating.

  Accordingly, the present inventors have also intensively studied electronic components that can suppress the occurrence of insulation resistance deterioration in a high temperature and high humidity environment. First, the present inventors pay attention to the thickness of the first electrode layer, and by increasing the thickness of the first electrode layer, a new fact that it is possible to suppress the occurrence of insulation resistance deterioration under a high temperature and high humidity environment. I came to find. That is, it is considered that by increasing the thickness of the first electrode layer, the movement of Zn atoms contained in the lead-free solder into the element body is suppressed.

  Next, the present inventors paid attention to the conductive paste used for forming the first electrode layer. The conductive paste used for forming the first electrode layer generally contains glass frit. For this reason, when the first electrode layer is formed, the glass component moves to the surface of the first electrode layer and the interface with the element body, and innumerable pores are generated inside the first electrode layer. The present inventors believe that Zn atoms move to the interface between the first electrode layer and the element body through the pores generated in the first electrode layer, and then move into the element body. In view of this, the present inventors have found a new fact that by making the structure of the first electrode layer precise, it is possible to suppress the occurrence of insulation resistance deterioration in a high temperature and high humidity environment. That is, it is considered that by making the first electrode layer a dense structure with few pores, the movement of Zn atoms contained in the lead-free solder into the element body is suppressed.

  Based on this fact, the electronic component according to the present invention is an electronic component including an element body and a terminal electrode formed on the element body, and the terminal electrode is formed on the outer surface of the element body. And a first electrode layer formed by baking a conductive paste, a second electrode layer formed by Ni plating on the first electrode layer, and Sn plating or Sn alloy on the second electrode layer A third electrode layer formed by plating, wherein the thickness of the first electrode layer is set to 10 μm or more, and the pore generation rate of the first electrode layer is determined by the pore area on the cut surface. The ratio is set to 10% or less.

  In the electronic component according to the present invention, the thickness of the first electrode layer is set to 10 μm or more, and the pore generation rate of the first electrode layer is set to 10% or less in terms of the pore area ratio at the cut surface. Therefore, it is possible to suppress the occurrence of insulation resistance deterioration in a high temperature and high humidity environment.

  Further, it is preferable that the pore generation rate of the first electrode layer is set to 2% or more in terms of the pore area ratio in the cut surface. When the first electrode layer is formed by baking the conductive paste, as described above, pores are generated inside the first electrode layer. In order to suppress the generation of pores, it is necessary to adjust the baking temperature, the amount of glass frit, etc. If the generation of pores in the first electrode layer is prevented, the process control of the first electrode layer is more than necessary. It becomes complicated. On the other hand, in the present invention, since the pore generation rate of the first electrode layer is set to 2% or more in terms of the pore area ratio in the cut surface, the first electrode layer for suppressing the generation of pores The process management will not be more complicated than necessary.

  An electronic apparatus according to the present invention includes the electronic component and a substrate on which a wiring pattern is formed, and the terminal electrode of the electronic component and the wiring pattern formed on the substrate are made of lead-free solder containing Zn. It is characterized by being electrically and mechanically joined.

  In the electronic device according to the present invention, as described above, it is possible to suppress the occurrence of insulation resistance deterioration in a high temperature and high humidity environment.

  A multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising an element body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated, and a plurality of terminal electrodes formed on the element body. A plurality of terminal electrodes formed on the outer surface of the element body, and a first electrode layer formed by baking of a conductive paste, and a first electrode layer formed by Ni plating on the first electrode layer. 2 and a third electrode layer formed by Sn plating or Sn alloy plating on the second electrode layer, and the thickness of the first electrode layer is 10 μm or more and 20 μm or less. The pore generation rate of the first electrode layer is set to 10% or less in terms of the pore area ratio in the cut surface.

  In the multilayer ceramic capacitor according to the present invention, the thickness of the first electrode layer is set to 10 μm or more, and the pore generation rate of the first electrode layer is set to 10% or less in terms of the pore area ratio at the cut surface. Therefore, it is possible to suppress the deterioration of insulation resistance in a high temperature and high humidity environment.

  By the way, when the thickness of the first electrode layer is increased, the size of the element body must be reduced in order to make the size of the multilayer ceramic capacitor the same. When the size of the element body is reduced, the area of each internal electrode is inevitably reduced, the capacitance is reduced, and the basic performance of the multilayer ceramic capacitor cannot be guaranteed. However, in the present invention, since the thickness of the first electrode layer is set to 20 μm or less, the size of the element body is suppressed from being reduced, and the area of each internal electrode is reduced. Suppressed. As a result, it is possible to suppress the electrostatic capacity from being reduced, and to guarantee the basic performance of the multilayer ceramic capacitor.

  Further, it is preferable that the pore generation rate of the first electrode layer is set to 2% or more in terms of the pore area ratio in the cut surface. When the first electrode layer is formed by baking the conductive paste, as described above, pores are generated inside the first electrode layer. In order to suppress the generation of pores, it is necessary to adjust the baking temperature, the amount of glass frit, etc. If the generation of pores in the first electrode layer is prevented, the process management of the first electrode layer is more complicated than necessary. It will become. On the other hand, in the present invention, since the pore generation rate of the first electrode layer is set to 2% or more in terms of the pore area ratio in the cut surface, the first electrode layer for suppressing the generation of pores The process management will not be more complicated than necessary.

  An electronic apparatus according to the present invention includes the multilayer ceramic capacitor and a substrate on which a wiring pattern is formed, and the terminal electrode of the multilayer ceramic capacitor and the wiring pattern formed on the substrate are lead-free containing Zn. It is characterized by being electrically and mechanically joined using solder.

  In the electronic device according to the present invention, as described above, it is possible to suppress the occurrence of insulation resistance deterioration in a high temperature and high humidity environment.

  ADVANTAGE OF THE INVENTION According to this invention, the electronic component which can suppress generation | occurrence | production of insulation resistance deterioration in a high-temperature, high-humidity environment, a multilayer ceramic capacitor, and an electronic device can be provided.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. This embodiment is an example in which the present invention is applied to a multilayer ceramic capacitor.

  With reference to FIG.1 and FIG.2, the structure of the electronic device ED which concerns on this embodiment is demonstrated. FIG. 1 is a schematic diagram illustrating a configuration of an electronic apparatus according to the present embodiment. FIG. 2 is a schematic diagram showing a cross-sectional configuration of the multilayer ceramic capacitor according to the present embodiment.

  As shown in FIG. 1, the electronic device ED includes a multilayer ceramic capacitor 1 as an electronic component and a substrate B on which a wiring pattern WP is formed. The multilayer ceramic capacitor 1 includes a rectangular parallelepiped capacitor element 3 and a pair of terminal electrodes 11 and 13. The multilayer ceramic capacitor 1 is a 2012 type (length 2.0 mm, width 1.2 mm, and height 1.0 mm) multilayer ceramic capacitor.

  The multilayer ceramic capacitor 1 is formed by soldering the pair of terminal electrodes 11 and 13 to the wiring pattern WP so that the pair of terminal electrodes 11 and 13 and the wiring pattern WP are electrically and mechanically bonded to each other in the substrate B. Has been implemented. At this time, a solder fillet SF is formed across the terminal electrodes 11 and 13 and the wiring pattern WP. As the solder used for soldering, lead-free solder containing Zn is used. In this embodiment, Sn—Zn solder, particularly Sn—Zn—Bi solder is used. Sn-Zn-Al solder may be used instead of Sn-Zn-Bi solder.

  Soldering is performed by placing the multilayer ceramic capacitor 1 on the solder paste previously applied to the wiring pattern WP on the substrate B, and then heating the entire electronic device ED to a temperature higher than the solder melting temperature to fix the solder. This can be done by so-called reflow.

  As shown in FIG. 2, the capacitor element body 3 is configured by alternately laminating first internal electrodes 23 and second internal electrodes 25 with dielectric layers 21 interposed therebetween. That is, in the capacitor body 3, a plurality of dielectric layers 21 and a plurality of internal electrodes 23 and 25 are alternately stacked. The actual multilayer ceramic capacitor 1 is integrated so that the boundary between the dielectric layers 21 is not visible. In the present embodiment, a capacitor constituted by the first internal electrode 23, the second internal electrode 25, and the dielectric layer 21 serves as an internal circuit element.

  The pair of terminal electrodes 11 and 13 are formed on the outer surface of the capacitor body 3. More specifically, one terminal electrode 11 extends in the thickness direction of the capacitor element body 3 (in the stacking direction of the first inner electrode 23 and the second inner electrode 25) of the end face of the capacitor element body 3. One end face of the pair of end faces that are present and opposed to each other is formed so as to cover the entire area of the end face. The other terminal electrode 13 covers the entire region of the end face of the end face of the capacitor body 3 on the other end face of the pair of end faces that extend in the thickness direction of the capacitor body 3 and face each other. Is formed.

  The first internal electrode 23 has a rectangular shape. The first internal electrode 23 is formed at a position having a predetermined distance from the other end surface, and extends so as to face the one end surface. As a result, the first internal electrode 23 is drawn out to one end face and is electrically connected to the one terminal electrode 11.

  The second internal electrode 25 has a rectangular shape. The second internal electrode 25 is formed at a position having a predetermined distance from the one end face, and extends so as to face the other end face. As a result, the second internal electrode 25 is drawn out to the other end face and is electrically connected to the other terminal electrode 13.

The dielectric layer 21 is a layer containing BaTiO ₃ as a main component, and is formed by firing a ceramic green sheet containing BaTiO ₃ . The first and second internal electrodes 23 and 25 are electrode layers containing Ni as a main component. The first and second internal electrodes 23 and 25 may be electrode layers containing Pd, Ag—Pd, Cu, or a Cu alloy as a main component.

  The pair of terminal electrodes 11 and 13 have first electrode layers 11a and 13a, second electrode layers 11b and 13b, and third electrode layers 11c and 13c, respectively.

  The first electrode layers 11a and 13a are formed on the outer surface of the capacitor body 3 and are formed by baking a conductive paste. The thicknesses of the first electrode layers 11a and 13a are set to 10 μm or more and 20 μm or less. In the present embodiment, a conductive paste in which glass frit and an organic vehicle are mixed with metal powder containing Cu as a main component is used. The metal powder may contain Ni, Ag—Pd, or Ag as a main component.

  The pore generation rate of the first electrode layers 11a and 13a is set to 2% or more and 10% or less in terms of the pore area ratio in the cut surface. Here, the pore area ratio in the cut surface is obtained as follows. First, after the cut surfaces of the first electrode layers 11a and 13a are mirror-finished, the mirror-finished surfaces are photographed at a magnification of 1000 times using a scanning electron microscope (SEM). Next, the photographed image is subjected to image processing, and the pore region and the region other than the pore are binarized. Next, from the binarized image, the area of the pore region is obtained as the pore area, and the pore area relative to the visual field area of the photograph is obtained as the pore area ratio.

  The second electrode layers 11b and 13b are formed on the first electrode layers 11a and 13a by Ni plating. The thickness of the second electrode layers 11b and 13b is 1 to 3 μm, and is set to about 2 μm in this embodiment. Ni plating can be performed by a barrel plating method using a Ni plating bath (for example, a Watt bath).

  The third electrode layers 11c and 13c are formed on the second electrode layers 11b and 13b by Sn plating. In the present embodiment, the thickness of the third electrode layers 11c and 13c is set to about 3 μm. Sn plating can be performed by a barrel plating method using a Sn plating bath (for example, a neutral Sn plating bath). The third electrode layers 11c and 13c may be formed by Sn alloy plating.

  Here, the relationship between the thickness and the pore area ratio of the first electrode layers 11a and 13a and the deterioration of the insulation resistance of the multilayer ceramic capacitor 1 will be described in detail.

  The present inventors conducted the following experiment in order to clarify the relationship between the thickness and pore area ratio of the first electrode layers 11a and 13a and the insulation resistance IR. That is, 15 samples (samples 1 to 15) of multilayer ceramic capacitors having different thicknesses and pore area ratios of the first electrode layers 11a and 13a are prepared, and the samples 1 to 15 are soldered (reflowed) to the substrate. An acceleration test was performed in the mounted state, and the insulation resistance IR before and after each of the samples 1 to 15 was measured. The measurement results are shown in the table of FIG. In this experiment, the thicknesses of the first electrode layers 11a and 13a are made different by adjusting the solvent contained in the conductive paste and changing the coating amount of the conductive paste. The pore area ratio of the first electrode layers 11a and 13a is varied by adjusting the baking temperature, the amount of glass frit, and the like. In general, the generation of pores is suppressed by increasing the baking temperature. Further, the generation of pores is also suppressed by increasing the amount of glass frit.

  In the acceleration test, a DC voltage of 4.0 V was continuously applied to each sample 1 to 6 for 40 hours in a constant temperature and humidity environment (temperature: 121 ° C., relative humidity: 95%, pressure: 2 atm). The insulation resistance after the acceleration test was a value measured after a predetermined time (2 hours or more) elapsed from the acceleration test. Except that the thicknesses and the pore area ratios of the first electrode layers 11a and 13a are different, each of the samples 1 to 15 has the same configuration as the multilayer ceramic capacitor 1 of the above-described embodiment, and the B characteristic is 10 μF. Designed to. The composition of the Sn—Zn—Bi solder used for soldering was Sn: 89 wt%, Zn: 8 wt%, and Bi: 3 wt%. Reflow was performed using a reflow furnace, the furnace atmosphere temperature was set to 230 to 250 ° C., and the furnace passage time was set to 4 to 6 minutes.

From the measurement results shown in FIG. 3, it can be seen that the occurrence of insulation resistance deterioration is suppressed by increasing the thickness of the first electrode layers 11a and 13a and decreasing the pore area ratio. Samples 1 to 3 in which the thicknesses of the first electrode layers 11a and 13a are 9 μm have an insulation resistance IR after the acceleration test of 5.0 × 10 ^{6 to} 6.0 × 10 ⁶ Ω, and the insulation before the acceleration test It is significantly smaller than the resistance IR 1.3 × 10 ⁸ Ω. Moreover, even if the thickness of the first electrode layers 11a and 13a is 10 μm or more, Samples 4, 8, and 12 having a pore area ratio of 15% have an insulation resistance IR after the acceleration test of 5.0 × 10 ^5. Ω to 1.0 × 10 ⁶ Ω, which is significantly smaller than 1.3 × 10 ⁸ Ω, which is the insulation resistance IR before the acceleration test. On the other hand, samples 5 to 7, 9 to 11, and 13 to 15 in which the thicknesses of the first electrode layers 11a and 13a are 10 μm or more and the pore area ratio is 10% are the insulation resistance IR after the acceleration test. There is a ^{1.2 × 10 8 Ω~1.3 × 10 8} Ω, hardly changed with acceleration test is before the insulation resistance IR 1.3 × 10 ⁸ Ω. Therefore, the lower limit of the thickness of the second electrode layers 11b and 13b is 10 μm, and the upper limit of the pore area ratio is 10%.

  As described above, in the present embodiment, the thicknesses of the first electrode layers 11a and 13a are set to 10 μm or more, and the pore generation ratio of the first electrode layers 11a and 13a is the pore area ratio in the cut surface. Therefore, it is possible to suppress deterioration of insulation resistance in a high temperature and high humidity environment.

  By the way, if the thickness of the first electrode layers 11a and 13a is increased, the size of the capacitor body 3 must be reduced in order to make the multilayer ceramic capacitor 1 have the same size. If the size of the capacitor body 3 is reduced, the areas of the internal electrodes 23 and 25 must be reduced, the capacitance is reduced, and the basic performance of the multilayer ceramic capacitor 1 cannot be guaranteed. However, in the present invention, since the thickness of the first electrode layers 11a and 13a is set to 20 μm or less, the size of the capacitor element body 3 is suppressed from being reduced, and each internal electrode 23, It is suppressing that the area of 25 becomes small. As a result, it is possible to suppress the capacitance from becoming small, and the basic performance of the multilayer ceramic capacitor 1 can be guaranteed.

  In the present embodiment, the pore generation rate of the first electrode layers 11a and 13a is set to 2% or more in terms of the pore area ratio in the cut surface. When the first electrode layers 11a and 13a are formed by baking a conductive paste, pores are generated inside the first electrode layers 11a and 13a. In order to suppress the generation of pores, it is necessary to adjust the baking temperature, the amount of glass frit, etc. If the generation of pores in the first electrode layers 11a, 13a is prevented, the first electrode layers 11a, 13a Process management becomes more complicated than necessary. On the other hand, in the present embodiment, since the pore generation rate of the first electrode layers 11a and 13a is set to 2% or more in terms of the pore area ratio in the cut surface, the first electrode layer 11a and 13a are configured to suppress the generation of pores. The process management of one electrode layer 11a, 13a does not become more complicated than necessary.

  The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to the above embodiment. For example, the number of layers of the dielectric layer 21, the first internal electrode 23, and the first internal electrode 25 is not limited to the illustrated number. The multilayer ceramic capacitor 1 is not limited to the 2012 type described above, and may be a multilayer ceramic capacitor larger than the 2012 type, or may be a multilayer ceramic capacitor smaller than the 2012 type.

  The present invention is not limited to a multilayer ceramic capacitor, and can be applied to a capacitor, a thermistor, a varistor, and a composite electronic component including these as long as the electronic component includes an element body and a terminal electrode formed on the element body. May be.

It is a schematic diagram which shows the structure of the electronic device which concerns on this embodiment. It is a mimetic diagram showing the section composition of the multilayer ceramic capacitor concerning this embodiment. It is a graph which shows the measurement result of the insulation resistance before and behind an acceleration test.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multilayer ceramic capacitor, 3 ... Capacitor body, 11, 13 ... Terminal electrode, 11a, 13a ... 1st electrode layer, 11b, 13b ... 2nd electrode layer, 11c, 13c ... 3rd electrode layer, 21 ... Dielectric layer, 23 ... first internal electrode, 25 ... second internal electrode, B ... substrate, ED ... electronic device, WP ... wiring pattern.

Claims (6)

An electronic component comprising an element body and a terminal electrode formed on the element body,
The terminal electrode is
A first electrode layer formed on the outer surface of the element body and formed by baking a conductive paste;
A second electrode layer formed by Ni plating on the first electrode layer;
And a third electrode layer formed by Sn plating or Sn alloy plating on the second electrode layer,
The thickness of the first electrode layer is set to 10 μm or more;
An electronic component, wherein a pore generation ratio of the first electrode layer is set to 10% or less in terms of a pore area ratio in a cut surface.   2. The electronic component according to claim 1, wherein a pore generation rate of the first electrode layer is set to 2% or more in terms of a pore area ratio in a cut surface. The electronic component according to claim 1 or 2,
And a substrate on which a wiring pattern is formed,
The electronic device, wherein the terminal electrode of the electronic component and the wiring pattern formed on the substrate are electrically and mechanically joined using lead-free solder containing Zn. A multilayer ceramic capacitor comprising an element body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated, and a plurality of terminal electrodes formed on the element body,
The plurality of terminal electrodes are
A first electrode layer formed on the outer surface of the element body and formed by baking a conductive paste;
A second electrode layer formed by Ni plating on the first electrode layer;
A third electrode layer formed by Sn plating or Sn alloy plating on the second electrode layer,
The thickness of the first electrode layer is set to 10 μm or more and 20 μm or less,
The multilayer ceramic capacitor according to claim 1, wherein a pore generation ratio of the first electrode layer is set to 10% or less in terms of a pore area ratio in a cut surface.   5. The multilayer ceramic capacitor according to claim 4, wherein a pore generation rate of the first electrode layer is set to 2% or more in terms of a pore area ratio in a cut surface. The multilayer ceramic capacitor according to claim 4 or 5,
And a substrate on which a wiring pattern is formed,
The electronic device, wherein the terminal electrode of the multilayer ceramic capacitor and the wiring pattern formed on the substrate are joined electrically and mechanically using lead-free solder containing Zn.

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