JP2006135857A - Semiconductor integrated circuit apparatus and optical disk record reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit apparatus including a VCO to form a low jitter reference frequency signal at a high-frequency by a simple configuration. <P>SOLUTION: The apparatus is provided with a first current mirror circuit composed of a second conductive MOSFET to receive the drain current of the first MOSFET of a first conductive type to receive a control voltage, a second current mirror circuit composed of the first conductive MOSFET to receive the output current of the first current mirror circuit, and a ring oscillator composed of a plurality of amplification circuits to control an operation current based on the output current of the second current mirror circuit. The second current mirror circuit switches an input-output current ratio by a control signal, and the ring oscillator sets a maximum input-output current ratio in a range to meet an allowable value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device and an optical disc recording / reproducing device, and more particularly to a circuit technique suitable for use in a device having a variable frequency oscillation circuit such as a PLL (phase locked loop).

The causes of the jitter of the frequency signal formed by the PLL circuit are broadly divided into (1) noise entering the VCO control terminal and (2) noise entering the power supply of the VCO. An effective means for the above (1) is to lower Kv (VCO gain). However, when Kv is lowered, there arises a problem that the variable range of the VCO becomes small. Japanese Patent Application Laid-Open No. 2004-007588, Japanese Patent Application Laid-Open No. 2004-200742, and Japanese Patent Application Laid-Open No. 10-084278 are provided to supplement this portion.
JP 2004-007588 A JP 2004-200742 A, Japanese Patent Laid-Open No. 10-084278

  Depending on the loop band of the PLL, the jitter component appearing at the PLL output varies. Here, the loop band means the followability of the PLL. The higher the loop bandwidth of the PLL, the easier it is to follow the input signal and the weaker the input signal noise. Usually, the loop band of the PLL is determined at the optimum point where the jitter is minimized. However, since the wobble signal input to the optical disk drive PLL (WPLL) is read from the disk, it is affected by scratches on the disk, dust, eccentricity of the disk, etc., and is a signal with many defects. In order not to follow the defect, it is necessary to lower the loop bandwidth. The same applies to the current DVD and Blu-ray, one of the next generation DVDs.

  In the case of a normal PLL, the optimum value that can minimize the jitter is several tens of MHz. However, the write PLL (hereinafter referred to as WPLL) for DVD is as low as several KHz (which varies depending on the media). 1) + (2) dependent jitter increases. The countermeasure for the cause of the above (2) is a countermeasure due to the layout of the capacitor insertion, shield, etc., and is not quantitative. In addition, there is a problem that the chip size of the LSI is increased and the cost is increased. Inventors of the present application, when developing a WPLL for the next-generation Blu-ray, the clock frequency is higher than that of the current DVD and the allowable jitter is smaller, so a satisfactory solution cannot be obtained with a conventional PLL circuit. Faced a problem.

  The inventor of the present application has noticed that (3) noise generated by the VCO element itself does not affect the jitter. That is, any element (resistor, capacitor, MOSFET) is known to generate noise. In the case of a MOSFET, the largest noise is 1 / f (flicker) noise, and there is some thermal noise. This kind of noise is usually impossible to manage by the MOSFET process, and the amount of noise generated is considered to be a game. Accordingly, the present situation is that no attention is paid to the jitter reduction method focusing on the noise generated by the (3) VCO element itself.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device and an optical disc recording / reproducing device including a VCO that forms a high frequency and low jitter reference frequency signal with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A first current mirror circuit comprising a second conductivity type MOSFET receiving the drain current of the first conductivity type first MOSFET receiving the control voltage, and a first conductivity type MOSFET receiving the output current of the first current mirror circuit. A second current mirror circuit; and a ring oscillator including a plurality of amplifier circuits whose operation currents are controlled based on an output current of the second current mirror circuit. The maximum input / output current ratio is set within a range in which the current ratio is switched and the jitter of the ring oscillator satisfies the allowable value.

  Since the ring oscillator operates with a control current of the maximum input / output current ratio or less corresponding to the control signal, it is always possible to guarantee an operation with an allowable jitter or less.

  FIG. 1 shows a circuit diagram of an embodiment of a voltage-current (VI) conversion circuit constituting a VCO. The VI conversion circuit of this embodiment includes a VI conversion unit and an output current control unit. The VI conversion unit includes an N-channel MOSFET Q10 that receives a control voltage VC at its gate and forms a conversion current IC0 from its drain. The source of the MOSFET Q10 is supplied with the circuit ground potential. The MOSFET Q10 is formed in a relatively large size so that the operating current of a ring oscillator, which will be described later, can be maximized when the control voltage VC is maximized in order to improve jitter characteristics.

  The output current control unit is configured to include a first current mirror circuit configured with a P-channel MOSFET and a second current mirror circuit configured with an N-channel MOSFET. The first current mirror circuit includes a diode-shaped P-channel MOSFET Q11 provided between the drain of the MOSFET Q10 and the power supply voltage VDD, and a P-channel MOSFET Q12 having a common gate and source with the MOSFET Q11, and the drain of the MOSFET Q12. To form an output current IC0 ′. In other words, the first current mirror circuit performs an operation of converting the suction current signal IC0 formed by the VI conversion MOSFET Q10 into an extrusion current signal IC0 '. MOSFETs Q11 and Q12 are formed in the same size, and the input / output current ratio is 1: 1 so as not to have a current gain.

  The second current mirror circuit is composed of N-channel MOSFETs Q21 and Q22. The second current mirror circuit is provided with a current control function. The current control function is realized by the first current control circuit ATT1 and the second current control circuit ATT2. As representatively shown as a typical circuit configuration of the first current control circuit ATT1, switch MOSFETs Q14 to Q20 are connected in series to diode-connected MOSFETs Q13 to Q16 to form a series circuit. Control signals CB0 to CB3 are supplied to the gates of the switch MOSFETs Q14 to Q20. These four series circuits are connected in parallel to the input side MOSFET Q21. That is, these series circuits form a current bypass path as indicated by a dotted line in the figure for the current signal IC0 'supplied from the first current mirror circuit.

  The MOSFETs Q13 to Q16 are not particularly limited, but are formed so as to have a binary weight with the input side MOSFET Q21 as a reference 1. For example, if the size of the MOSFET Q21 is 1, the MOSFET Q13 is also the same size, the MOSFET Q14 is twice as large, the MOSFET Q15 is four times larger, and the MOSFET Q16 is eight times larger. Corresponding to such a size ratio, the control signals CB0 to CB3 have binary weights.

  When all of the control signals CB0 to CB3 are at the low level, since all of the current IC0 'is supplied to the MOSFET Q21, the output current IC is the same as the VI-converted current IC0 and becomes the maximum current. On the other hand, when the control signal CB0 becomes high level, the MOSFET Q17 is turned on, and the current IC0 ′ is attenuated to half current by bypassing 1/2 current because the MOSFETs Q13 and Q21 are the same size. Be made. As a result, the output current IC is attenuated to ½ of the VI-converted current IC0. When the control signal CB1 becomes high level, the MOSFET Q18 is turned on, and the current IC0 ′ is attenuated to 1/3 by bypassing 2/3 of the current because the MOSFETs Q14 and Q21 are 2: 1. . As a result, the output current IC is attenuated to 1/3 of the VI-converted current IC0.

  When the control signal CB2 becomes high level, the MOSFET Q19 is turned on, and the current IC0 ′ is attenuated to 1/5 by bypassing 4/5 of the current because the MOSFETs Q15 and Q21 are 4: 1. . As a result, the output current IC is attenuated to 1/5 of the VI-converted current IC0. When the control signal CB3 becomes high level, the MOSFET Q20 is turned on, and the current IC0 ′ is attenuated to 1/9 by bypassing the current of 8/9 because the MOSFETs Q16 and Q21 are 8: 1. . As a result, the output current IC is attenuated to 1/9 of the VI-converted current IC0. Hereinafter, by combining the control signals CB0 to CB3, the output current IC can be attenuated to 1/65 of the VI-converted current IC0 at the minimum.

  The second current control circuit ATT2 indicated by a black box in the figure is configured by a circuit similar to the first current control circuit ATT1, and is supplied with control signals TB0 and TB1. The first current control circuit ATT1 is used for switching the frequency range of the VCO. The second current control circuit ATT2 is used to compensate for process variations of elements. That is, when the circuit is formed in the semiconductor integrated circuit, the control signals TB0 and TB1 are adjusted so that the highest frequency of the VCO falls within the frequency range of use. Therefore, the control signals TB0 and TB1 are trimming signals that are fixedly set by a fuse or a nonvolatile memory element.

  FIG. 2 shows a circuit diagram of another embodiment of the VI conversion circuit constituting the VCO. In this embodiment, the output current control unit is changed. Although not particularly limited, in this embodiment, the second current control circuit ATT2 is provided on the first current mirror circuit side, and the first current control circuit ATT1 is provided on the second current mirror circuit side.

  The second current control circuit ATT2 provided in the first current mirror circuit includes a P-channel MOSFET Q31 and a P33 connected in parallel to the output-side MOSFET Q31 in the current mirror circuit including the P-channel MOSFETs Q30 and Q31. . CMOS switches S1 and S2 are provided between the gates and drains of the MOSFETs Q32 and Q33, respectively. These CMOS switches S1 and S2 are switch-controlled by the control signals TB0 and TB1, respectively. In this embodiment, the total size of the MOSFETs Q31 + Q32 and Q33 is the same as that of the MOSFET Q30. Therefore, when the MOSFETs Q32 and Q33 are placed in parallel with the MOSFET Q31 by the control signals TB0 and TB1, the size ratio of the MOSFETs in the current mirror circuit becomes 1: 1, and the maximum output current IC0 ″ corresponding to the VI conversion current IC0 is can get.

  Thereafter, when the CMOS switches S1 and S2 are turned off by the control signals TB0 and TB1, the number of MOSFETs arranged in parallel on the output side is reduced, and the output current IC0 ″ is attenuated correspondingly. For example, when the size ratio of the output MOSFETs Q31 to Q33 is set to 1, 2, and 4, when the switches S1 and S2 are turned off by the control signals TB0 and TB1, the minimum output current is 1/7 with respect to the VI conversion current IC0. IC0 ". The output current IC0 ″ attenuated with respect to the VI conversion current IC0 can be obtained as 3/7 when the switch 1 is in the on state and as 5/7 when the switch 2 is in the on state.

  FIG. 3 is a block diagram showing an embodiment of the VCO according to the present invention. In this embodiment, the VI converter and the output current controller shown in FIG. 1 or 2 form a ring oscillator control current IC using the differential amplifiers A1 to A3 as delay buffers. That is, the control voltage VC is supplied to the VI converter, and the oscillation frequency of the ring oscillator is controlled by the control current IC corresponding to the voltage VC, so that a VCO (voltage controlled oscillation circuit) is configured.

  This embodiment is characterized in that the output current controller has a current gain of 1 or less. That is, in the VI conversion unit, voltage / current conversion is performed so as to correspond to the control current IC that sets the oscillation frequency of the ring oscillator to the maximum frequency, thereby making it unnecessary for the output current control unit to perform current amplification. When noise is superimposed on the control current IC that controls the oscillation frequency of the ring oscillator, jitter is increased in the oscillation signal formed by the VCO. In the present invention, the noise component superimposed on the control current IC is reduced to reduce jitter. Noise (flicker noise, shot noise, thermal noise, etc.) generated by the elements constituting the circuit as described above basically depends on the manufacturing process and cannot be basically adjusted by the circuit.

  However, the inventors of the present application have noticed that the noise component superimposed on the control current IC can be reduced, in other words, minimized, by a circuit method from a certain point of interest. In the conventional VCO, the output current control unit has a current gain. On the premise of such current amplification, for example, when two control current ICs such as 500 mA and 100 mA are obtained for a control voltage VC of 1 V corresponding to two frequency ranges, the control voltage VC is obtained by the VI converter. A VI change operation of 20 mA is performed at 1 V, and the current amplification of 25 times and 5 times is switched from 20 mA to 500 mA by the output current control unit. At this time, the noise generated in the VI conversion unit is similarly amplified by 25 times and 5 times by the current amplification. In particular, when a high frequency signal is obtained, the amplification factor is large and a large jitter is generated. Therefore, there is a problem that the jitter becomes large with respect to a signal having a short period and the jitter ratio with respect to the period is increased.

  When the present invention is applied to the above example, the VI conversion unit performs a 500 mA VI changing operation when the control voltage VC is 1 V, and the output current control unit obtains 500 mA to 500 mA. Since it attenuates and obtains 100 mA, only the noise generated in the VI conversion unit and the noise generated in the output current control unit affect the control current IC. In other words, if the jitter at the highest frequency is maximized and it satisfies the allowable value, switching the frequency range will reduce the jitter and increase the period, so the ratio of jitter to the period will be greatly reduced. be able to.

  FIG. 6 is a waveform diagram for explaining the present invention. In the figure, the jitter when the current is amplified from 20 mA to 500 mA and the VCO is controlled as described above is about 2.52% in the period, and the same condition is applied as in the present application. It was confirmed by simulation that the jitter can be reduced to about 1.85% with respect to the period when 500 mA is formed in the VI converter and transmitted as it is.

  As described above, when gain is given to the current mirror circuit of the current control unit, the noise of the MOSFET itself constituting the VI conversion unit and the current mirror is amplified together. To avoid this, in this embodiment, as described above. The current mirror circuit constituting the output current control unit does not have a gain, and on the contrary, the current component is bypassed and discarded as in the embodiment of FIG. By setting the input / output MOSFET size ratio to 1 or less as described above, the noise component can be attenuated in response to the attenuation of the control current. Can be reduced.

  In the present invention, the MOSFET is formed with a relatively large element size because of the configuration for obtaining the maximum control current required in the VI conversion section. When the size of the MOSFET itself is increased and the gate capacitance is increased in this way, the influence of 1 / f noise is mitigated by the gate capacitance, and this is also effective in reducing noise and thus reducing jitter.

  FIG. 4 is a block diagram showing an embodiment of a PLL (phase locked loop) circuit provided in the semiconductor integrated circuit device according to the present invention. Each circuit block of this embodiment is formed on one semiconductor substrate together with other circuits constituting the semiconductor integrated circuit device. The PLL circuit of this embodiment is composed of the following circuit blocks.

The reference clock f _IN is supplied to the reference clock terminal. This reference clock _fIN is supplied to one input of the phase comparator. A feedback clock f _FB is supplied to the other input of the phase comparator through a variable M divider circuit. Although not particularly limited, a frequency division ratio (M) of the variable M frequency divider is set by a multiplication ratio M supplied from the outside. The frequency division ratio M is, for example, M = 32 for DVD + RW and M = 186 for DVD-RW. By setting the frequency division ratio M in this way, a plurality of clock signal frequencies can be set in the PLL circuit.

The charge pump circuit operates corresponding to the phase comparison result formed by the phase comparator, and forms a charge-up current or a discharge current corresponding to the phase difference. The charge-up current or discharge current is transferred to the capacitor C _F, the control voltage V _F is generated. The control voltage V _F corresponds to the control voltage VC. The control voltage V _F is a voltage-current converter is transmitted to the through current-controlled oscillator (FIG. 1, the embodiment circuit of Fig. 2) (ring oscillator of FIG. 3) to control its oscillation frequency. In the same figure, control signals for frequency range switching and process adjustment included in the voltage-current converter are omitted.

The output signal of the current controlled oscillator is output through a divide-by-2 circuit. This frequency divider circuit also functions as a ring oscillator as a current-controlled oscillator and an output level amplifier circuit, and forms a pulse signal with a duty of 50%. On the one hand, the output signal of this divide-by-2 is transmitted to the variable M divider as feedback clock f _FB . On the other hand, a necessary clock CLK is generated by being transmitted to the clock distribution system. In the PLL circuit constitutes a reference clock f _IN, and a feedback clock f _FB which are M frequency phase comparator (frequency comparison), the low-pass filter by the phase output corresponding to the phase difference (frequency difference) Chajihonpu Since the current control oscillator is controlled via the circuit, the capacitor C _F and the voltage-current converter (pulse width current converter), the oscillation of the current control oscillator is performed so that the phases (frequency) of both clocks f _IN and f _FB coincide. The operation will be performed.

  FIG. 5 shows a circuit diagram of an embodiment of the ring oscillator. In this embodiment, a differential amplifier circuit is used as the variable delay stage. That is, an N-channel type current source MOSFET Q7 that forms an operating current is provided between the common source of the N-channel type differential MOSFETs Q1 and Q2 and the ground potential VSS of the circuit. A current corresponding to the control current IC formed in FIGS. 1 and 2 flows through the gate of the MOSFET Q7. Although omitted in the figure, the control current IC output from the drain of the output MOSFET Q22 of FIG. 1 or FIG. 2 is supplied to a diode-connected N-channel MOSFET through a current mirror circuit composed of a P-channel MOSFET. The MOSFET and the MOSFET Q7 are formed in a current mirror configuration so that a current equal to the current flowing through the MOSFET Q22 shown in FIG. 1 or 2 flows through the MOSFET Q7.

  Between the drains of the differential MOSFETs Q1 and Q2 forming the differential input pair and the power supply voltage VDD, P-channel MOSFETs Q3 and Q4 connected to a terminal for operating as a differential output pair and connected in a diode form. Are provided respectively. Further, these MOSFETs Q3 and Q4 are respectively provided with P-channel MOSFETs Q5 and Q6 arranged in parallel, and a bias voltage VB is supplied to the gates of the MOSFETs Q5 and Q6 so that they are steadily turned on to be resistive elements. It is operated as. The MOSFETs Q1 to Q7 constitute the variable delay stage 1, and the variable delay stages 2 to N are constituted by a similar circuit, which are connected in a ring shape to constitute a ring oscillator. When the differential circuit is used as a delay stage, the delay time is shorter than when a CMOS inverter circuit is used, and differential signals are transmitted sequentially, so that a high-frequency oscillation signal can be stably obtained. Can withstand power supply noise. In addition, when an inverter circuit is used, a ring oscillator can be configured only at odd stages, but when a differential circuit is used, an oscillation operation can be performed if the transmission signal is reversed in phase as a whole even at even stages. .

  FIG. 7 is a block diagram showing an embodiment of a DVD recording / reproducing apparatus according to the present invention. An optical disk (DVD) is rotated by a motor. The motor is rotationally driven by a driver. The rotation control of the motor is performed by the servo unit. The optical disk is irradiated with a laser beam by an optical pickup, and writing or reading operation is performed. The laser beam is generated by driving a laser diode mounted on an optical pickup by a laser diode driver LDD. There are a photodetector that receives reflected light of the laser beam (not shown) and performs photoelectric conversion, and an IV converter that performs current-voltage conversion on the output of the photodetector.

  On the one hand, the output signal of the analog front end AFE is supplied to a reproduction PLL, and a reference clock for performing demodulation and a binarized reproduction signal are taken out. In the demodulator, the demodulating operation is performed from the reference clock and the reproduction signal, and temporarily recorded in the memory SDRAM (synchronous dynamic random access memory) via the DRAM controller. Although not particularly limited, the data is transmitted to the personal computer through the interface circuit ATAPI with the personal computer (personal computer) and output. That is, data is output.

  Write data generated by a personal computer or the like is held in the memory SDRAM via the interface circuit ATAPI and the DRAM controller, and is modulated by the modulation unit. The clock necessary for the modulation and writing is generated by a writing PLL (WPLL) that receives the output signal of the analog front end AFE. This write PLL is composed of a PLL circuit as shown in FIG. 4 (the voltage-current converter and the output current controller in FIGS. 1 and 2). MICOM is a microcomputer that controls the entire recording / reproducing operation in addition to data input / output control via a DRAM controller. Although not particularly limited, the reproduction PLL, demodulation unit, DRAM controller, memory SDRAM, interface circuit ATAPI, microcomputer MICOM, modulation unit, servo unit, and writing PLL are formed on a single semiconductor substrate such as silicon. . The analog front end AFE is a separate chip, and the signal line passes through the substrate of the DVD drive and is input to the WPLL. Here, the wobble signal from the analog front end AFE is electrically contaminated by noise on the board and other signals, and the signal quality is not guaranteed.

  The loop band means the followability of the PLL. The higher the loop band, the easier it is to follow the input signal, but the PLL reacts sensitively to the electric noise of the wobble signal received on the DVD board, increasing the jitter. Invite. Of course, it reacts sensitively to the wobble signal noise and signal defects generated by dirt, scratches, etc. on the optical disk. Therefore, the DVD WPLL needs to be as low as several KHz as described above. Regarding the jitter due to the cause (3), the noise of the element itself cannot be managed, but by applying the circuit technique of the above embodiment, the VI-converted current signal is substantially gained. It is possible to take measures with a circuit configuration that does not Therefore, the technique of the present invention is indispensable particularly for a DVD in which the loop band is set low in order to avoid the influence of scratches, dust, etc. on the optical disk. Further, even a circuit whose loop bandwidth is not determined can take measures against the cause of (3) which has not been taken until now, so that it is possible to mass-produce a PLL with lower jitter.

  In addition, products with strict specifications regarding PLL jitter include storage systems such as DVD and HDD, long / short distance optical communication systems such as SONET (OC-192 compliant), and PCs such as PC # express and Serial-ATAP. Jitter specifications are strict. In PC # express and Serial-ATAP, the jitter components are divided into random jitter and deterministic jitter in the specifications, and each value is specified. Since the random jitter is the (3) dependent jitter and the deterministic jitter is the (1) + (2) dependent jitter, the countermeasure for the (3) dependent jitter is effective when the random jitter specification is strict.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the ring oscillator may use a CMOS inverter circuit or the like in addition to the differential amplifier shown in FIG. That is, a current-controlled P-channel MOSFET and N-channel MOSFET are connected in series to each of the P-channel MOSFET and N-channel MOSFET constituting the CMOS inverter circuit, and the delay time in the inverter circuit stage is controlled to control the ring oscillator. You may make it comprise. Further, the output current control unit may have a slight current gain. That is, the first current mirror circuit or the second current mirror circuit amplifies the current to compensate for the process variation so that it can cope with the case where the maximum current signal required by the VI conversion unit cannot be obtained due to process variation. The attenuation may be adjusted to obtain a maximum output current that compensates for process variations. The present invention can be widely used in a semiconductor integrated circuit device including a VCO used in a PLL circuit or the like and an optical disc recording / reproducing device.

It is a circuit diagram which shows one Example of the voltage-current conversion circuit which comprises VCO. It is a circuit diagram which shows another Example of VI conversion circuit which comprises VCO. It is a block diagram which shows one Example of VCO which concerns on this invention. 1 is a block diagram showing an embodiment of a PLL circuit provided in a semiconductor integrated circuit device according to the present invention. It is a circuit diagram which shows one Example of the ring oscillator used for this invention. It is a wave form diagram for demonstrating this invention. It is a block diagram which shows one Example of the DVD recording / reproducing apparatus concerning this invention.

Explanation of symbols

  Q1 to Q33 ... MOSFET, ATT1 ... first current control circuit, ATT2 ... second current control circuit, A1 to A3 ... differential amplifier circuit, CF ... capacitor, AFE ... analog front end, LDD ... laser diode driver, SDRAM ... memory , ATAPI ... interface circuit, MICOM ... microcomputer.

Claims (16)

A first MOSFET of a first conductivity type that receives a control voltage;
A first current mirror circuit comprising a second conductivity type MOSFET receiving the drain current of the first MOSFET;
A second current mirror circuit comprising a first conductivity type MOSFET receiving the first output current of the first current mirror circuit;
A ring oscillator comprising a plurality of amplifier circuits whose operating currents are controlled based on the second output current of the second current mirror circuit,
The first output current input to the second current mirror circuit by the combination of a plurality of control signals input to the second current mirror circuit and the second output current output from the second current mirror circuit. A semiconductor integrated circuit device, wherein the input / output current ratio is switched, and the maximum input / output current ratio of the input / output current ratio is set in a range such that the jitter of the ring oscillator satisfies an allowable value. In claim 1,
The semiconductor integrated circuit device further includes a PLL circuit,
The PLL circuit includes the first MOSFET, the first current mirror circuit, the second current mirror circuit, and the ring oscillator.
2. The semiconductor integrated circuit device according to claim 1, wherein the ring oscillator is for forming a voltage-controlled oscillation frequency signal, and forms a plurality of reference frequency signals corresponding to the control signal. In claim 2,
The semiconductor integrated circuit device according to claim 1, wherein the first MOSFET forms the drain current substantially equal to a maximum operating current of an amplifier circuit constituting the ring oscillator when the control voltage is a maximum value. In claim 3,
The maximum input / output current ratio of the second current mirror circuit is 1,
By providing a circuit for bypassing the first output current of the first current mirror circuit by the plurality of control signals, the input / output current ratio set by the control signal is set to 1 or less. A semiconductor integrated circuit device. In claim 4,
On the input side of the second current mirror circuit, a plurality of first series circuits each including a first switch MOSFET that is switch-controlled by the plurality of control signals and a diode-shaped second MOSFET are provided in parallel.
The second current mirror circuit outputs the second output current corresponding to a difference between currents flowing in the first series circuit with respect to the first output current of the first current mirror circuit. A semiconductor integrated circuit device. In claim 5,
The diode-type second MOSFETs in the plurality of first series circuits are set to size ratios corresponding to binary weights, and the control signals having binary weights corresponding to the size ratios correspond to the second MOSFETs. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is supplied to a gate of a first switch MOSFET. In claim 3,
The input side circuit inside the second current mirror circuit is provided with a plurality of second series circuits composed of a second switch MOSFET and a diode-shaped third MOSFET which are switch-controlled by the plurality of control signals, in parallel.
A semiconductor integrated circuit device, wherein the gate of the output MOSFET of the second current mirror circuit is connected in common to the gate and drain of the third MOSFET in the diode form. In claim 7,
The third MOSFET in the diode form of the input side circuit is set to a size ratio corresponding to a binary weight, and the first switch to which the control signal having a binary weight corresponding to the size ratio corresponds. A semiconductor integrated circuit device supplied to a gate of a MOSFET. In claim 6,
A first circuit and a second circuit are provided in parallel on the input side of the second current mirror circuit,
The first circuit and the second circuit each include a plurality of third series circuits arranged in parallel,
The third series circuit includes a third switch MOSFET and a diode-shaped fourth MOSFET,
A first control signal corresponding to the oscillation range adjustment is supplied to the first circuit to control the switching operation of each of the third switch MOSFETs of the first circuit,
A semiconductor integrated circuit device characterized in that the second circuit is supplied with a second control signal corresponding to process variation adjustment to control the switching operation of each of the third switch MOSFETs of the second circuit. . In claim 8,
In the input side circuit of the second current mirror circuit, a third circuit and a fourth circuit are provided in parallel,
The third circuit and the fourth circuit each include a plurality of fourth series circuits arranged in parallel,
The fourth series circuit includes a fourth switch MOSFET and a diode-shaped fifth MOSFET,
The third circuit is supplied with a first control signal corresponding to the oscillation range adjustment to control the switching operation of each of the fourth switch MOSFETs of the third circuit,
A semiconductor integrated circuit device wherein the fourth circuit is supplied with a second control signal corresponding to process variation adjustment to control the switching operation of each of the fourth switch MOSFETs of the fourth circuit. . In claim 7,
In parallel with the circuit composed of the output side MOSFET of the first current mirror circuit, it has a fifth circuit and a sixth circuit,
The fifth circuit includes a first CMOS switch that is switch-controlled by a first control signal corresponding to a transmission range adjustment, the first CMOS switch, a gate and a drain connected to each other, and a source / drain path connected to the first current mirror circuit. And a sixth MOSFET provided in parallel with the connection state of the above circuit,
The sixth circuit includes a second CMOS switch that is switch-controlled by a second control signal corresponding to a process variation adjustment, the second CMOS switch, a gate and a drain connected to each other, and a source / drain path connected to the first current mirror circuit. And a seventh MOSFET provided in parallel with the connection state of the above circuit. In claim 2,
The PLL circuit performs a synchronization operation with a wobble signal read from a DVD optical disk, and forms a write clock signal at a plurality of double speeds on the DVD optical disk. apparatus. A first MOSFET of a first conductivity type that receives a control voltage;
A first current mirror circuit comprising a second conductivity type MOSFET receiving the drain current of the first MOSFET;
A second current mirror circuit comprising a first conductivity type MOSFET receiving the first output current of the first current mirror circuit;
A ring oscillator comprising a plurality of amplifier circuits whose operating currents are controlled based on the second output current of the second current mirror circuit,
The first output current input to the second current mirror circuit and the second output current output from the second current mirror circuit by a combination of a plurality of control signals input to the second current mirror circuit The semiconductor integrated circuit device is characterized in that the input / output current ratio is switched and the input / output current ratio can be made lower than 1. In claim 13,
The semiconductor integrated circuit device further includes a PLL circuit,
The PLL circuit includes the first MOSFET, the first current mirror circuit, the second current mirror circuit, and the ring oscillator.
2. The semiconductor integrated circuit device according to claim 1, wherein the ring oscillator is for forming a voltage-controlled oscillation frequency signal, and forms a plurality of reference frequency signals corresponding to the control signal. In claim 14,
The plurality of amplifier circuits each have a differential input pair, a differential output pair, and a source / drain path of a transistor constituting the differential input pair, and drains are commonly connected, and the operating current of the amplifier circuit is And an eighth MOSFET for supplying the semiconductor integrated circuit device. A first semiconductor integrated circuit having a PLL circuit and forming a write clock signal and a reference clock for demodulation and a binarized reproduction signal;
A motor for rotationally driving the optical disc;
An optical pickup capable of performing a reading operation by irradiating a laser beam;
An optical disc recording / reproducing apparatus having a second semiconductor integrated circuit that receives a signal based on a reflected laser beam from the optical pickup and forms an input signal necessary for the operation of the first semiconductor integrated circuit;
The PLL circuit is
A first MOSFET of a first conductivity type that receives a control voltage;
A first current mirror circuit comprising a second conductivity type MOSFET receiving the drain current of the first MOSFET;
A second current mirror circuit comprising a first conductivity type MOSFET receiving the first output current of the first current mirror circuit;
A ring oscillator comprising a plurality of amplifier circuits whose operating currents are controlled based on the second output current of the second current mirror circuit,
The first output current input to the second current mirror circuit and the second output current output from the second current mirror circuit by a combination of a plurality of control signals input to the second current mirror circuit The input / output current ratio is switched, and the input / output current ratio can be made lower than 1.
The ring oscillator is used to form a voltage-controlled oscillation frequency signal, and forms a plurality of reference frequency signals corresponding to the control signal.
The PLL circuit synchronizes with a wobble signal that is read from the optical disk, and forms a write clock signal at multiple speeds on the optical disk based on the multiple reference frequency signals. An optical disc recording / reproducing apparatus characterized by that.

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