JP2006134558A - Nonvolatile semiconductor memory device and its operating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize high speed writing in a NAND flash memory. <P>SOLUTION: The nonvolatile semiconductor memory device has a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, and a sense amplifier having 1st, 2nd, 3rd circuits to hold the written data. The 1st circuit receives data from the outside to transfer them to the 2nd and 3rd circuits. The 2nd and 3rd circuits transfer the data to the adjacent two bit lines respectively. At the same time, the data is written in the memory cell selected from the nonvolatile memory cells connected to the adjacent two bit lines. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to an electrically rewritable nonvolatile semiconductor memory device. Among nonvolatile semiconductor memory devices, in particular, it relates to a NAND flash memory.

In recent years, the demand for small-sized and large-capacity nonvolatile semiconductor memory devices has increased rapidly. In particular, NAND-type flash memory, which can be expected to have higher integration and larger capacity than conventional NOR-type flash memory, has attracted attention. .

Chip shrinking for higher integration will be promoted to increase the capacity of NAND flash memory, but as chip shrinking progresses, the bit line spacing is shrinking and the adjacent capacity of bit lines is increasing. . Recently, the adjacent bit line capacity has reached 80% of the total bit line capacity. In the future, with the increase in capacity of flash memory, chip shrinking will progress further and the adjacent bit line capacity will increase.

In the NAND flash memory, a “voltage sense method” for detecting the charge on the bit line is adopted in order to reduce the current consumption of the sense amplifier (S / A). The data sensing operation in a conventional voltage sensing NAND flash memory is as follows. (1) Charge is prestored in the bit line (precharge). (2) When the NAND memory cell is turned on, the precharged charge is discharged through the NAND memory cell, so that the potential of the bit line becomes VSS (discharge). (3) Since the precharged charge is not extracted unless the NAND memory cell is turned on, the potential of the bit line is kept at the precharged potential. In this case, the bit line is floating. (4) Data is read by detecting the voltage level of the bit line with a sense amplifier at the timing when the discharge is completed.

In recent years, chip shrink has progressed, and the bit line capacity adjacent to the floating bit line adjacent to the floating bit line in the state (3) (state where the NAND memory cell is not turned on) is increased. When the above-described (2) bit line discharge is performed, a so-called “coupling” phenomenon occurs in which the potential of the floating bit line decreases due to the influence of the adjacent capacitance of the bit line. Originally, in the state (3) described above, the potential of the bit line should be kept at the precharged level, but the potential of the bit line is lowered due to the coupling, which causes a false sense. . Therefore, there are cases where an accurate read operation cannot be performed. In order to avoid erroneous sensing due to the influence of this coupling, for example, a technique of shielding adjacent bit lines as recently disclosed in Patent Document 1 below has been adopted.

In this method of shielding adjacent bit lines (hereinafter referred to as “bit line shielding method”), as shown in FIG. 14, one sense amplifier circuit (S / A & latch) is shared by two bit lines. Has been. In other words, adjacent bit lines are classified into even (Even) and odd (Odd), and a configuration is adopted in which adjacent even and odd bit lines share one sense amplifier.

In the read operation of the bit line shield method, when reading even bit line data (when reading even pages), the even bit line transfer gate (BLSe) is turned on and the even bit lines are sense amplifiers. Connect to. At this time, by turning on the grounding transistor (BIASo), the odd-numbered bit line is connected to BLCRL and is set to the ground potential (VSS). In this state, if the potential (VDD) is precharged to the even bit line from the sense amplifier (S / A), the odd bit line potential remains held at VSS, so the even bit line is affected by the odd bit line. Precharge is performed appropriately without receiving it.

On the other hand, when reading the data of the odd bit line, the odd bit line transfer gate (BLSo) is turned on, and the odd bit line is connected to the sense amplifier. At this time, by turning on the grounding transistor (BIASe), the even-numbered bit line is connected to BLCRL and is set to the ground potential (VSS). In this state, if the potential (VDD) is precharged from the sense amplifier (S / A) to the odd-numbered bit line, the even-numbered bit line remains at VSS, so the odd-numbered bit line is affected by the even-numbered bit line. Precharge is performed appropriately without receiving it.

Thus, in the bit line shield method, it is possible to perform an accurate read operation without being affected by the signal of the adjacent bit line by setting the adjacent unselected bit line to the ground state during the read operation. It becomes.

In addition, during data write operation (program operation), even bit lines and odd bit lines can be simultaneously written because the bit lines adjacent to each other are not affected in order to increase the write speed. desirable.
JP-A-4-276393

However, in the conventional NAND flash memory using the bit line shield method shown in FIG. 14, it is impossible to simultaneously write even bit lines and odd bit lines because of its circuit configuration. Therefore, even when data is written, it is necessary to alternately write data to even bit lines and odd bit lines. On the other hand, the demand for speeding up NAND flash memory in the market is increasing, and it is required to simultaneously write even-numbered bit lines and odd-numbered bit lines to realize speed-up of the entire NAND-type flash memory system.

Therefore, the present invention has been made in view of the above-described problems, and is a non-volatile device that can simultaneously write data to even-numbered bit lines and odd-numbered bit lines at the time of a write operation, thereby realizing high-speed operation of the entire system. An object of the present invention is to provide a NAND flash memory which is a semiconductor memory device and an operation method thereof.

In the nonvolatile semiconductor memory device and the operating method thereof according to the present invention, the sense amplifier has a circuit that receives and holds data from the outside and two circuits that receive and hold data transferred from the circuit. . These circuits transfer the data to two bit lines, and the data is simultaneously written into selected memory cells among the nonvolatile memory cells connected to two adjacent bit lines. Therefore, in the nonvolatile semiconductor memory device and the operation method thereof according to the present invention, data can be written simultaneously on the even bit lines and the odd bit lines.

According to the present invention,
A memory cell array in which a plurality of electrically rewritable nonvolatile memory cells are arranged;
A sense amplifier having first, second and third circuits for holding write data;
A non-volatile semiconductor memory device comprising:
The first circuit receives data from the outside, transfers the data to the second circuit and the third circuit,
The second circuit and the third circuit respectively transfer the data to two adjacent bit lines,
A nonvolatile semiconductor memory device is provided, in which the data is simultaneously written into selected memory cells among the nonvolatile memory cells connected to the two adjacent bit lines.

The nonvolatile semiconductor memory device of the present invention can simultaneously write data on even bit lines and odd bit lines. In addition, after the data is simultaneously written on the even bit lines and the odd bit lines, the even page verify operation and the odd page verify operation can be continuously performed. The nonvolatile semiconductor memory device of the present invention can improve the effective writing speed of the nonvolatile semiconductor memory device while suppressing an increase in the occupied area by the additional circuit as much as possible.

FIG. 1 shows a schematic configuration diagram of a nonvolatile semiconductor memory device 10 according to the present embodiment of the present invention. A nonvolatile semiconductor memory device 10 according to the present embodiment includes a memory cell array 11, a column control circuit (column decoder) 12, a row control circuit (row decoder) 13, a source line control circuit 14, a P well control circuit 15, It has a data input / output buffer 16, a command interface 17, a state machine 18, a sense amplifier 19, and a selection circuit 20. The nonvolatile semiconductor memory device 10 according to the present embodiment transmits and receives data and control signals (commands) to and from the external I / O pad 21.

In the nonvolatile semiconductor memory device 10 of the present invention according to this embodiment, data and control signals are input from the external I / O pad 21 to the command interface 17 and the column control circuit 12 through the data input / output buffer 16. The state machine 18 controls the column control circuit 12, the row control circuit 13, the source line control circuit 14, and the P well control circuit 15 based on the control signal and data. The state machine 18 outputs access information for the memory cells of the memory cell array 11 to the column control circuit 12 and the row control circuit 13. The column control circuit 12 and the row control circuit 13 control the sense amplifier 19 and the selection circuit 20 based on the access information and data, activate the memory cell, and read, write, or erase data. The sense amplifier 19 connected to each bit line of the memory cell array 11 loads data to the bit line, detects the potential of the bit line, and holds it in the data cache. Data read from the memory cell by the sense amplifier 19 controlled by the column control circuit 12 is output to the external I / O pad 21 through the data input / output buffer 16. The selection circuit 20 selects a data cache connected to the bit line among a plurality of data caches constituting the sense amplifier.

Reference is now made to FIG. FIG. 2 shows a schematic configuration diagram of the memory cell array 11, the sense amplifier 19, and the selection circuit 20 of the nonvolatile semiconductor memory device 10 according to the present embodiment. In the present embodiment, the memory cell array 11 has m memory blocks each having 2n memory cells 23 (Memory Cells). In FIG. 2, a memory block i and a memory block (i + 1) are representatively shown. The memory cells 23 are connected to bit lines BLe0, BLo0, BLe1, BLo1, BLe2, BLo2,..., BLe (n−1), BLo (n−1), respectively. The sense amplifier 19 has n sense amplifiers (S / A0 to S / A (n-1)). The selection circuit 20 has n selection circuits (SC0, SC1,..., SC (n−1)). One even bit line and one odd bit line are paired and share one sense amplifier (S / A) and one selection circuit (SC). In the nonvolatile semiconductor memory device 10 of the present invention, one end of each bit line of the memory cell array 11 is floating. As shown in FIG. 4A, the memory cell 23 includes source / drains 23c and 23d, a channel formation region 23e, and a structure in which a charge storage layer 23a and a control gate 23b are stacked.

FIG. 3 shows a circuit configuration of the memory cell 23 of the memory cell array 11. Here, the memory block i and the memory block (i + 1) are shown among the memory cell blocks constituting the memory cell array, but the circuit configurations of the other memory blocks are the same.

Each memory cell 23 has three memory transistors MTr and two select gate transistors STr1 and STr2. Further, the memory cell 23 constituting the memory block i and the memory cell 23 constituting the memory block (i + 1) share a source line (C-source). In the present embodiment, the string length of the NAND memory cell is 4 (WL0 to WL3), but the string length may be 16, 32, or the like. Further, the page length (number of bit lines 2n) is set to 2 kByte including the even bit lines and the odd bit lines. The number of memory blocks (m) was 1024. Note that the number of memory blocks, the string length of the NAND memory cell, and the page length of the nonvolatile semiconductor memory device 10 of the present invention according to the present embodiment are not limited to the number of the present embodiment, but have a desired storage capacity. It may be changed in a timely manner accordingly. Further, the number of select gate transistors is not limited to this.

Reference is now made to FIG. FIG. 4B is a schematic configuration diagram of the sense amplifier S / A0 of the sense amplifier 19 according to the present embodiment. Note that the sense amplifiers SA1 to SA (n-1) of the sense amplifier 19 have the same configuration as the sense amplifier S / A0. As shown in FIG. 4B, the sense amplifier S / A0 includes a primary data cache (PDC) 30, a secondary data cache (SDC) 31, an ABL data cache (ABL). A data cache (ADC) 32, a dynamic data cache (DDC) 33, and a temporary data cache (TDC) 34 are provided. Note that the dynamic data cache 33 and the temporary data cache 34 may be provided as necessary. The dynamic data cache 33 can also be used as a cache for holding data for writing an intermediate potential (VQPW) between VDD (high potential) and VSS (low potential) to the bit line.

Reference is now made to FIG. FIG. 5 shows circuit configurations of the sense amplifier 19 and the selection circuit 20 of the present embodiment. Note that FIG. 5 representatively shows the sense amplifier SA0 and the selection circuit SC0 connected to the even-numbered bit line BLe0 and the odd-numbered bit line BLo0 for convenience of drawing, but other sense amplifiers SA1 to SA are shown. (n-1) and the selection circuits SC1 to SC (n-1) have the same circuit configuration.

The sense amplifier S / A0 includes a primary data cache (PDC) 30, a secondary data cache (SDC) 31, an ABL data cache (ADC) 32, a dynamic data cache (DDC) 33, and a temporary data cache. As described above, the cache (TDC) 34 is provided. In the present embodiment, the primary data cache 30 includes clocked inverters CLI1 and CLI2 and an N-channel transistor NMOS5. The secondary data cache 31 includes clocked inverters CLI3 and CLI4 and N-channel transistors NMOS6 and NMOS7. The ABL data cache 32 includes clocked inverters CLI5 and CLI6 and an N-channel transistor NMOS8. The dynamic data cache 33 includes N-channel transistors NMOS4 and NMOS9. The temporary data cache 34 has a capacity C. The circuit configurations of the primary data cache 30, the secondary data cache 31, the ABL data cache 32, the dynamic data cache 33, and the temporary data cache 34 are limited to those shown in FIG. Instead, other circuit configurations may be employed.

The sense amplifier S / A0 includes N-channel transistors NMOS11 to NMOS20 for controlling the input / output of data in these data caches. In this embodiment, the N-channel transistors NMOS5 to NMOS20 are used. However, the input / output of data in these data caches may be controlled using P-channel transistors.

The nonvolatile semiconductor memory device 10 of the present invention is characterized in that the sense amplifier S / A0 includes an ABL data cache 32. The ABL data cache 32 temporarily latches data, and may be smaller in size than the primary data cache 30 and the secondary data cache 31. Therefore, even if the ABL data cache 32 is added to the conventional sense amplifier, the occupation area is hardly increased.

The selection circuit SC0 includes AND circuits AND1 to AND4 and N-channel transistors NMOS0 to NMOS3, NMOS22, and NMOS23. As the selection circuit SC0, a circuit other than the circuit shown in FIG. 5 may be used as long as it has a function of transferring data from the sense amplifier S / A0 to the bit lines BLe0 and BLo0.

Next, a data write operation (program operation) of the nonvolatile semiconductor memory device 10 according to the present embodiment will be described. First, write data is transferred to the secondary data cache (SDC) 31 by the data lines IO and IOn. Since the data is transferred serially, the column control circuit 12 determines whether the data is even page (Oven page) data or odd page (Odd page) data, and uses even page (Even page) data. If there is, input “High” to BLC1, turn on NMOS13, transfer data to primary data cache (PDC) 30 and dynamic data cache (DDC) 33, and data of odd page (Odd page) If it is, the data is transferred to the ABL data cache (ADC) 32. Next, the data held in the primary data cache (PDC) 30 or the ABL data cache (ADC) 32 is transferred to the bit line BLe0 or BLo0. At this time, if the data is “0 (Low)”, VSS is transferred, and if the data is “1 (High)”, VDD is transferred (precharge). Here, data held in the primary data cache (PDC) 30 is transferred to BLe0, and data held in the ABL data cache (ADC) 32 is transferred to BLo0.

Here, the operation of transferring the data held in the primary data cache (PDC) 30 or the ABL data cache (ADC) 32 to the bit line BLe0 or BLo0 will be described in detail. First, BLSe, BLSo, BIASe and BIASo are all set to “High” and BLCRL is set to VDD. At this time, (1) when the node N1 of the primary data cache (PDC) 30 is “Low”, the node N1n becomes “High”, the NMOS0 is turned off, and the NMOS2 is turned on. Here, by inputting “High” to BLC1 and BLCLAMP and turning on NMOS10 and NMOS13, “Low (VSS in this embodiment)” is transferred to the even bit line BLe0. On the other hand, (2) when the node N1 of the primary data cache (PDC) 30 is “High”, the node N1n becomes “Low”, NMOS0 is turned on and NMOS2 is turned off. At this time, since the potential of BLCRL is VDD, VDD is input to the even bit line BLe0 and precharged.

(3) When the node N3 of the ABL data cache (ADC) 32 is “Low”, the node N3n becomes “High”, the NMOS 1 is turned off, and the NMOS 3 is turned on. Here, “High” is input to EVEN and NMOS 23 is turned on to transfer “Low (VSS)” directly from the ABL data cache (ADC) 32 to the odd bit line BLo0. On the other hand, (4) when the node N3 is “High”, the node N3n is “Low”, the NMOS1 is turned on, and the NMOS3 is turned off. At this time, since the potential of BLCRL is VDD, VDD is input to the odd bit line BLo0 and precharged.

The above operation is performed for all even and odd bit lines. After that, by applying a write voltage (Vpgm) to the word line WL to which the memory cell to which data is written is connected, all the memory cells on one page connected to all even bit lines and odd bit lines. Data can be written at the same time, and the writing speed can be improved.

Next, a verify operation when data is written will be described with reference to FIGS. Since the nonvolatile semiconductor memory device 10 of the present invention according to the present embodiment employs a voltage sensing method, the influence of coupling between adjacent bit lines is large, and all bit lines cannot be read simultaneously. The verify operation is continuously performed every even page and odd page. Immediately after the program operation, write data is held in the primary data cache (PDC) 30 and the ABL data cache (ADC) 32. Further, the secondary data cache (SDC) 31 needs to release the data for the cache operation (operation for holding the next write data).

First, an even page verify operation is performed. FIG. 6 shows a timing chart of the even page verify operation. FIG. 6 shows a timing chart of the even-numbered bit line BLe0 and odd-numbered bit line BLo0, and the selection circuit SC0 and sense amplifier S / A0 connected to them, but the timing chart of the verify operation on other bit lines is also shown. This is the same as that shown in FIG.

Reference is made to the period RCLK in FIG. During an even page verify operation, all odd bit lines BLo0 to BLo (n-1) must be grounded to VSS for bit line shielding. Therefore, BLCRL is set to 0V (VSS). Here, by inputting “High” to BIASo, BLSo, and EVEN, (1) When the node N3 of the ABL data cache (ADC) 32 is “Low”, the node N3n becomes “High” and the NMOS1 By turning off and turning on NMOS3, the data “Low” of the node N3 is transferred to the odd bit line BLo0. On the other hand, (2) when the node N3 of the ABL data cache (ADC) 32 is “High”, the node N3n becomes “Low”, the NMOS1 is turned on and the NMOS3 is turned off, so that VSS is transferred from BLCRL to BLo0. Transferred. As a result, regardless of the data held in the ABL data cache (ADC) 32, VSS can be transferred to the odd-numbered bit line BLo0 and a bit line shield can be realized.

Next, it is necessary to precharge the even bit line BLe0. Further, write data is held in the primary data cache (PDC) 30. Here, BIASe and BLSe are set to “High”. At this time, (1) when the node N1 of the primary data cache (PDC) 30 is “High”, this corresponds to non-write, and NMOS0 is turned on and NMOS2 is turned off. As a result, the even bit line BLe0 is charged with VSS. In this case, since it corresponds to non-write, there is no problem because it is not necessary to sense the potential of the bit line BLe0 and precharge is not required. On the other hand, (2) when the node N1 of the primary data cache (PDC) 30 is “Low”, NMOS0 is turned off and NMOS2 is turned on. At this time, the even bit line BLe0 can be precharged to VDD by inputting VPRE to VDD and inputting “High” to BLPRE and BLCLAMP to turn on NMOS10 and NMOS11. Thereafter, the data of the memory cell can be determined by sensing the change in the potential of the even bit line BLe0 when the select gate (SGS) of the corresponding memory cell 23 is set to “High”.

Next, the operation during the period SCLK in FIG. 6 will be described. By performing the operation shown in FIG. 7 at the timing of the period EXCLK1 in FIG. 6, the data held in the dynamic data cache (DDC) 33 is sequentially transferred to the temporary data cache (TDC) 34, The data of the node N1 held in the primary data cache (PDC) 30 is transferred to the dynamic data cache (DDC) 33, and the data held in the temporary data cache (TDC) 34 is transferred to the primary data cache (DDC) 33. Transfer to the node N1 of the data cache (PDC) 30.

Thereafter, VDD is applied to VPRE, “High (Vsg)” is input to BLPRE, and NMOS 11 is turned on to precharge temporary data cache (TDC) 34 with VDD. Subsequently, “High” is input to BLCLAMP and NMOS 10 is turned on to sense even bit line BLe0. Depending on the potential of the even bit line BLe0 at this moment, the temporary data cache (TDC) 34 is discharged or held in VDD.

Subsequently, the operation shown in FIG. 7 is performed again at the timing of the period EXCLK2 in FIG. With respect to the memory cell to which data has been written (node N1 of the primary data cache (PDC) 30 is “Low”), the dynamic data cache (DDC) 33 holds “Low”. Instead, the data held in the temporary data cache (TDC) 34 is taken into the node N1 of the primary data cache (PDC) 30. As a result, (1) when the temporary data cache (TDC) 34 holds “Low”, data writing is insufficient, so data writing is performed again in the next program operation. On the other hand, (2) when the temporary data cache (TDC) 34 holds “High”, the data writing is completed, so that the data is not written in the next program operation. Note that in a memory cell in which data has already been written or not written (the node N1 of the primary data cache (PDC) 30 is “High”), the dynamic data cache (DDC) 33 is set to “High”. Since it is held, NMOS4 is turned on, VDD is applied to VREG, “High” is input to REG, and NMOS12 is turned on, so the temporary data cache (TDC) 34 is automatically Is charged to VDD. As a result, “High” is again input to the node N1 of the primary data cache (PDC) 30, and the corresponding memory cell is not written in the next program. Note that a period after the period SCLK is necessary when an intermediate potential (QPW) needs to be written to the bit line.

Subsequently, the verify operation for odd pages is performed. A timing chart at this time is shown in FIG. FIG. 8 shows a timing chart of the even-numbered bit line BLe0 and odd-numbered bit line BLo0 and the selection circuit SC0 and sense amplifier S / A0 connected to them, but the timing chart of the verify operation on other bit lines is also shown. This is the same as that shown in FIG.

Reference is made to the period RCLK in FIG. First, the odd bit line BLo0 is precharged. BLCRL is set to 0 V (VSS). First, input “High” to ODD, BIASo and BLSo. (1) When the node N3 of the ABL data cache (ADC) 32 is “Low”, the node N3n becomes “High” and the NMOS 3 is turned on. At this time, the odd bit line BLo0 can be precharged to VDD by inputting VPRE to VDD and inputting “High” to BLPRE and BLCLAMP to turn on NMOS10 and NMOS11. On the other hand, (2) when the node N3 of the ABL data cache (ADC) 32 is “High”, the node N3n becomes “Low”, the NMOS1 is turned on, and VSS is transferred from the BLCRL to the odd bit line BLo0. At this time, since the memory cell corresponds to non-write, there is no problem even if precharging is not performed because it is not necessary to sense.

In addition, the verify operation of the odd bit line BLo0 is performed using the primary data cache (PDC) 30 as in the case of the even bit line BLe0. It is necessary to replace the data in the cache (ADC) 32. Therefore, in the period EXCLK1 in FIG. 8, the data in the primary data cache (PDC) 30 and the ABL data cache (ADC) 32 are exchanged by performing the operation shown in FIG.

First, “High” is input to the DTG, the NMOS 9 is turned on, and the data of the node N 1 of the primary data cache (PDC) 30 is transferred to the dynamic data cache (DDC) 33. Next, "High" is input to BLC1 and BLC3, and NMOS13 and NMOS14 are turned on to transfer the data of node N3 of ABL data cache (ADC) 32 to node N1 of primary data cache (PDC) 30 To do. Finally, the data of the dynamic data cache (DDC) 33 is transferred to the node N3 of the ABL data cache (ADC) 32, and the data of the primary data cache (PDC) 30 and the ABL data cache (ADC) 32 are transferred. The replacement is complete.

In order to perform bit line shielding, it is necessary to ground the even bit line BLe0 to VSS. However, since the data of the primary data cache (PDC) 30 is the write data of the ABL data cache (ADC) 32, the odd bit line BLo0 is shielded during the above-described verify operation of the even bit line. A similar method cannot be performed. Therefore, by inputting “High” to ODD and turning on NMOS0, VSS is transferred from BLCRL. Thereafter, the data of the memory cell can be determined by sensing the change in the potential of the odd bit line BLo0 when the select gate (SGS) of the corresponding memory cell is set to “High”. However, since the even-numbered page data is held in the ABL data cache (ADC) 32 at this time, depending on the data, the NMOS 3 connected to the odd-numbered bit line BLo0 in which the data is written may not be turned on. In some cases, the odd bit line BLo0 cannot be sensed.

Therefore, odd page sensing in consideration of the above will be described. After the period EXCLK1 in FIG. 8 ends, VSS is applied to VPRE, "High" is input to BLPRE, and NMOS 11 is turned on to discharge temporary data cache (TDC) 34. Next, in the period EXCLK2 of the period SCLK, the operation shown in FIG. 9 is performed again to sequentially transfer the data held in the primary data cache (PDC) 30 to the dynamic data cache (DDC) 33. The node N3 data held in the ABL data cache (ADC) 32 is transferred to the primary data cache (PDC) 30, and the data held in the dynamic data cache (DDC) 33 is transferred to the ABL. Transfer to node N3 of data cache (ADC) 32. As a result, even page data returns to the primary data cache (PDC) 30 and odd page data returns to the ABL data cache (ADC) 32. When the odd page data returns to the ABL data cache (ADC) 32, the NMOS 3 connected to the odd bit line BLo0 to be sensed is turned on.

Thereafter, VDD is applied to VPRE, “High” is input to BLPRE, and NMOS 11 is turned on to precharge temporary data cache (TDC) 34 with VDD. The odd bit line BLo0 is sensed by inputting “High” to BLCLAMP and turning on NMOS10. The temporary data cache (TDC) 34 is discharged by the potential of the odd bit line BLo0 at this time, or is kept charged to VDD. Subsequently, the operation of FIG. 10 is performed in the period EXCLK3 in FIG. For the memory cell that has written data (node N3 of the ABL data cache (ADC) 32 is “Low”), “Low” is held in the dynamic data cache (DDC) 33. Instead, the data held in the temporary data cache (TDC) 34 is taken into the node N3 of the ABL data cache (ADC) 32. As a result, (1) when the node N3 of the ABL data cache (ADC) 32 holds “Low”, the data writing is insufficient, so the data is written again in the next program operation. . On the other hand, (2) when the node N3 of the ABL data cache (ADC) 32 is “High”, the data writing is completed, so the data is not written in the next program operation. Note that in the originally non-written memory cell (the node N3 of the ABL data cache (ADC) 32 is “High”), the dynamic data cache (DDC) 33 holds “High”. On, VDD is applied to VREG, "High" is input to REG, and NMOS 12 is turned on, so that temporary data cache (TDC) 34 is automatically charged to VDD. As a result, “High” is again input to the node N3 of the ABL data cache (ADC) 32, and the corresponding memory cell is not written in the next program.

In the present embodiment, the dynamic data cache (DDC) 33 is connected to the primary data cache (PDC) 30, but the dynamic data cache (DC) 33 is connected to the ABL data cache. (ADC) 32 may be connected. One dynamic data cache (DDC) 33 may be provided in each of the primary data cache (PDC) 30 and the ABL data cache (ADC) 32. As a result, operations such as QPW are also possible.

As described above, in the nonvolatile semiconductor memory device 10 of the present invention according to this embodiment, after data is written simultaneously on the even bit lines and the odd bit lines, the even page verify operation and the odd page verify operation are performed. Can be performed continuously. The nonvolatile semiconductor memory device 10 of the present invention according to this embodiment can improve the effective writing speed of the nonvolatile semiconductor memory device while suppressing an increase in the occupied area by the additional circuit as much as possible.

Next, another example of the nonvolatile semiconductor memory device of the present invention will be described. The nonvolatile semiconductor memory device of the present invention according to this example is obtained by changing the circuit configurations of the sense amplifier 19 and the selection circuit 20 in the nonvolatile semiconductor memory device 10 described in the above embodiment.

FIG. 11 shows a circuit configuration of the sense amplifier 19 and the selection circuit 20 of the nonvolatile semiconductor memory device 10 according to the present embodiment. Note that FIG. 11 representatively shows the sense amplifier SA0 and the selection circuit SC0 connected to the even-numbered bit line BLe0 and the odd-numbered bit line BLo0 for convenience of drawing, but other sense amplifiers SA1 to SA are shown. (n-1) and the selection circuits SC1 to SC (n-1) have the same circuit configuration. Further, other circuits constituting the nonvolatile semiconductor memory device 10 are the same as those described in the above-described embodiment, and thus will not be described again here.

In the selection circuit SC0 of this example, in the selection circuit SC0 shown in FIG. 5 described in the above embodiment, some of the N-channel transistors are changed to P-channel transistors to reduce the total number of elements. . The selection circuit SC0 of this embodiment includes N-channel transistors (NMOS0 to NMOS3, NMOS22 to NMOS25), P-channel transistors (PMOS0 and PMOS1), and a capacitor C2. The circuit configuration of the sense amplifier S / A0 is the same as that described with reference to FIG. 5, and therefore will not be described again here.

Here, a data write operation (program operation) of the nonvolatile semiconductor memory device 10 according to the present embodiment will be described. First, write data is transferred to a primary data cache (PDC) 30 and an ABL data cache (ADC) 32. Next, the data held in the primary data cache (PDC) 30 and the ABL data cache (ADC) 32 is transferred to the bit line BLe0 or BLo0. At this time, when data “0 (Low)” is written, VSS is transferred, and when data “1 (High)” is written, VDD is transferred and precharge is performed. Here, as in the above-described embodiment, data in the primary data cache (PDC) 30 is transferred to the even bit line BLe0, and data in the ABL data cache (ADC) 32 is transferred to the odd bit line BLo0.

Here, the operation of transferring the data held in the primary data cache (PDC) 30 or the ABL data cache (ADC) 32 to the bit line BLe0 or BLo0 will be described in detail. First, BLSe and BLSo are set to “High”. Also, set BLCRL to VDD. At this time, (1) when the node N1 of the primary data cache (PDC) 30 is “Low”, the node N1n becomes “High”, the NMOS0 is turned on, and the PMOS0 is turned off. Here, by applying VSS to VPRE and inputting "High" to BLPRE to turn on NMOS 11, "Low (VSS in this embodiment)" can be transferred to even bit line BLe0. On the other hand, (2) when the node N1 of the primary data cache (PDC) 30 is “High”, the node N1n becomes “Low” and the PMOS0 is turned on. At this time, since the potential of BLCRL is VDD, VDD is input to the even bit line BLe0 and precharged.

(3) When the node N3 of the ABL data cache (ADC) 32 is “Low”, the node N3n becomes “High”, the NMOS1 is turned on, and the PMOS1 is turned off. At this time, VSS can be transferred to the odd bit line BLo0 by applying VSS to VPRE, inputting "High" to BLPRE, and turning on NMOS11. On the other hand, (4) when the node N3 of the ABL data cache (ADC) 32 is “High”, the node N3n becomes “Low” and the PMOS1 is turned on. At this time, since the potential of BLCRL is VDD, VDD is input to the odd bit line BLo0 and precharged.

The above operation is performed for all even and odd bit lines. After that, by applying a write voltage (Vpgm) to the word line WL to which the memory cell to which data is written is connected, all the memory cells on one page connected to all even bit lines and odd bit lines. Writing can be performed simultaneously, and writing speed can be improved.

Next, a verify operation when data is written will be described. As already described, since the nonvolatile semiconductor memory device 10 according to the present embodiment employs a voltage sensing method, the influence of coupling between adjacent bit lines is large, and all bit lines are simultaneously connected. Since the data cannot be read out, the verify operation is continuously performed for every even page and every odd page. Immediately after the program operation, write data is held in the primary data cache (PDC) 30 and the ABL data cache (ADC) 32. Further, the secondary data cache (SDC) 31 needs to release the data for the cache operation (operation for holding the next write data).

First, an even page verify operation is performed. FIG. 12 shows a timing chart of the even page verify operation. FIG. 12 shows a timing chart of the even-numbered bit line BLe0 and odd-numbered bit line BLo0 and the selection circuit SC0 and sense amplifier S / A0 connected to them, but the timing chart of the verify operation on other bit lines is also shown. This is the same as that shown in FIG.

Reference is made to the period RCLK in FIG. When verifying even pages, odd bit lines BLo0 to BLo (n-1) need to be grounded to VSS for bit line shielding. Therefore, BLCRL is set to 0V (VSS) and BIASo is turned on. As a result, PMOS1 is turned on and the odd-numbered bit line BLo0 becomes VSS, so that a bit line shield can be realized.

Next, it is necessary to precharge the even bit line BLe0. Further, write data is held in the primary data cache (PDC) 30. Here, BLSe is set to “High”. At this time, (1) when the node N1 of the primary data cache (PDC) 30 is “High”, this corresponds to non-write, the node N1n becomes “Low”, the PMOS0 is turned on, and the NMOS0 is turned off. As a result, the even bit line BLe0 is charged with VSS. In this case, since it corresponds to non-writing, it is not necessary to sense the potential of the even-numbered bit line BLe0, and there is no problem because precharge is not required. On the other hand, (2) when the node N1 of the primary data cache (PDC) 30 is “Low”, the node N1n becomes “High”, the PMOS0 is turned off, and the NMOS0 is turned on. At this time, the even bit line BLe0 can be precharged to VDD by applying VDD to VPRE and inputting "High" to BLPRE and BLCLAMP to turn on NMOS10 and MOS11. Thereafter, the data of the memory cell can be determined by sensing the change in the potential of the even bit line BLe0 when the select gate (SGS) of the corresponding memory cell 23 is set to “High”. Note that the sensing method is the same as the method described in the above embodiment, and is omitted here.

Subsequently, the verify operation for odd pages is performed. A timing chart at this time is shown in FIG. FIG. 13 shows a timing chart of the even-numbered bit line BLe0 and odd-numbered bit line BLo0 and the selection circuit SC0 and sense amplifier S / A0 connected to them, but the timing chart of the verify operation on other bit lines is also shown. It is the same as that shown in FIG.

Reference is made to the period RCLK in FIG. First, set BLCRL to 0 V (VSS) and input “High” to BIASe. As a result, PMOS0 is turned on and even bit line BLe0 becomes VSS, so that a bit line shield can be realized. Next, the odd bit line BLo0 is precharged. First, input “High” to BLSo. At this time, (1) when the node N3 of the ABL data cache (ADC) 32 is “Low”, the node N3n becomes “High” 1 and the NMOS1 is turned on. At this time, the odd bit line BLo0 can be precharged to VDD by applying VDD to VPRE and inputting "High" to BLPRE, BLCLAMP and ODD to turn on NMOS10, NMOS11 and NMOS22. On the other hand, (2) when the node N3 of the ABL data cache (ADC) 32 is “High”, the node N3n becomes “Low”, the PMOS1 is turned on, and VSS is transferred from the BLCRL to the odd bit line BLo0. At this time, since the cell corresponds to non-writing, there is no problem even if precharging is not performed. Further, BLSo is set to “Low” to turn off NMOS3, and the gate voltages of PMOS1 and NMOS1 are held by a capacitor such as C2. Further, since the verify operation of the odd bit line BLo0 is performed using the primary data cache (PDC) 30 as in the case of the even bit line BLe0, the data of the primary data cache (PDC) 30 It is necessary to replace the data in the ABL data cache (ADC) 32. The method of exchanging data is the same as the method described in the above embodiment, and will not be described here again.

Thereafter, the data of the memory cell can be determined by sensing the change in the potential of the odd bit line BLo0 when the select gate (SGS) of the corresponding memory cell 23 is set to “High”. Note that the sensing method is the same as the method described in the above embodiment, and is omitted here.

In this embodiment, the dynamic data cache (DDC) 33 is connected to the primary data cache (PDC) 30, but the dynamic data cache (DDC) 33 is connected to the ABL data cache. (ADC) 32 may be connected. One dynamic data cache (DDC) 33 may be provided in each of the primary data cache (PDC) 30 and the ABL data cache (ADC) 32. As a result, operations such as QPW are also possible.

As described above, in the nonvolatile semiconductor memory device 10 of the present invention according to the present embodiment, after the data is simultaneously written on the even bit lines and the odd bit lines, the even page verify operation and the odd page verify operation are performed. Can be performed continuously. The nonvolatile semiconductor memory device 10 according to this embodiment of the present invention can improve the effective writing speed of the nonvolatile semiconductor memory device while suppressing an increase in the occupied area by the additional circuit as much as possible. Furthermore, in the nonvolatile semiconductor memory device of this embodiment, it is possible to operate by charging / discharging all from VPRE, BLCRL, BIAS without charging / discharging bit lines from the data cache. The cache size can be made smaller than before.

The nonvolatile semiconductor memory device 10 of the present invention described in the above embodiment and Example 1 is a non-write cell when data is written from the ABL data cache (ADC) 32 as shown in FIGS. Can be precharged directly from BLCRL. Thus, a voltage higher than VDD can be input by connecting BLCRL to an external power supply or a booster circuit. As a result, a higher voltage can be transferred to the channel to the non-write memory cell, and erroneous writing can be suppressed. In the example shown in FIG. 11, by using a P-channel transistor, it is possible to transfer a voltage while avoiding step-down by a threshold value as in the case of using an N-channel transistor.

The present invention may further include a dynamic data cache circuit.

In the present invention, the dynamic data cache circuit may hold data for writing an intermediate potential between a high potential and a low potential to the bit line.

In the present invention, when the data is written using the data cache circuit, the bit line may be precharged directly.

The present invention may further include a temporary data cache circuit having a capacity.

In the present invention, the memory cell array has a structure in which the plurality of memory cells are connected between two selection gates.

In the present invention, the memory cell has a structure in which a charge storage layer and a control gate are stacked.

In the present invention,
A memory cell array in which a plurality of electrically rewritable nonvolatile memory cells are arranged;
A sense amplifier having first, second and third latch circuits for holding write data;
A selection circuit for controlling transfer of the data from the second latch circuit and the third latch circuit to two adjacent bit lines;
A non-volatile semiconductor memory device comprising:
The first latch circuit receives data from the outside, transfers the data to the second latch circuit and the third latch circuit,
The second latch circuit and the third latch circuit each transfer the data to the two adjacent bit lines via the selection circuit,
A nonvolatile semiconductor memory device is provided, in which the data is simultaneously written into selected memory cells among the nonvolatile memory cells connected to the two adjacent bit lines.

The present invention may further include a dynamic data cache circuit.

In the present invention,
A memory cell array in which a plurality of electrically rewritable nonvolatile memory cells are arranged;
A sense amplifier having first, second and third circuits for holding write data;
A method for operating a nonvolatile semiconductor memory device comprising:
The first circuit receives data from the outside, transfers the data to the second circuit and the third circuit,
The second circuit and the third circuit respectively transfer the data to two adjacent bit lines,
There is provided a method for operating a nonvolatile semiconductor memory device, wherein the data is simultaneously written into selected memory cells among the nonvolatile memory cells connected to the two adjacent bit lines. The

In the present invention, the first circuit, the second circuit, and the third circuit may be first, second, and third data cache circuits, respectively.

In the present invention, each of the first, second, and third data cache circuits may be a latch circuit.

In the present invention, each of the second and third data cache circuits may include two clocked inverters and one transistor.

In the present invention, the selection circuit includes a plurality of logic circuits that control a plurality of transistors and gate electrodes of the plurality of transistors, and the second and third data cache circuits each include A plurality of logic circuits may be controlled.

The present invention may further include a dynamic data cache circuit.

In the present invention, when the data is written using the data cache circuit, the bit line may be precharged directly.

The nonvolatile semiconductor memory device of the present invention can realize a high-speed write operation without substantially increasing the chip area, and can realize a high-speed NAND flash memory system as a whole. Therefore, according to the present invention, it is possible to realize a non-volatile semiconductor memory device that is cheaper, smaller, faster, and has a larger capacity. The nonvolatile semiconductor memory device of the present invention can be used as a memory device for electronic devices such as computers, digital cameras, mobile phones, and home appliances.

1 is a schematic configuration diagram of an embodiment of a nonvolatile semiconductor memory device of the present invention. 1 is a schematic configuration diagram of a memory cell array, a sense amplifier, and a selection circuit according to an embodiment of a nonvolatile semiconductor memory device of the present invention. 1 is a circuit configuration diagram of a memory cell of a memory cell array according to an embodiment of a nonvolatile semiconductor memory device of the present invention. (A) is sectional drawing of the memory cell which concerns on one Embodiment of the non-volatile semiconductor memory device of this invention, (b) is the outline of the sense amplifier which concerns on one Embodiment of the non-volatile semiconductor memory device of this invention. It is a block diagram. 1 shows a circuit configuration of a sense amplifier and a selection circuit according to an embodiment of a nonvolatile semiconductor memory device of the present invention. 5 is a timing chart of an even page verify operation in the embodiment of the nonvolatile semiconductor memory device of the present invention. 5 is a timing chart of an even page verify operation in the embodiment of the nonvolatile semiconductor memory device of the present invention. 5 is a timing chart of an odd-page verify operation in an embodiment of the nonvolatile semiconductor memory device of the present invention. 5 is a timing chart of an odd-page verify operation in an embodiment of the nonvolatile semiconductor memory device of the present invention. 5 is a timing chart of an odd-page verify operation in an embodiment of the nonvolatile semiconductor memory device of the present invention. 1 shows a circuit configuration of a sense amplifier and a selection circuit according to an embodiment of a nonvolatile semiconductor memory device of the present invention. 3 is a timing chart of the verify operation for even pages in one embodiment of the nonvolatile semiconductor memory device of the present invention. 3 is a timing chart of an odd page verify operation in one embodiment of the nonvolatile semiconductor memory device of the present invention; It is a schematic block diagram of a memory cell array and a sense amplifier of a conventional NAND flash memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Nonvolatile semiconductor memory device 11 Memory cell array 12 Column control circuit 13 Row control circuit 14 Source line control circuit 15 P well control circuit 16 Data input / output buffer 17 Command interface 18 State machine 19 Sense amplifier 20 Selection circuit 21 External I / O Pad 30 primary data cache (PDC)
31 Secondary data cache (SDC)
33 Dynamic Data Cache (DDC)
34 Temporary Data Cache (TDC)

Claims (5)

A memory cell array in which a plurality of electrically rewritable nonvolatile memory cells are arranged;
A sense amplifier having first, second and third circuits for holding write data;
A non-volatile semiconductor memory device comprising:
The first circuit receives data from the outside, transfers the data to the second circuit and the third circuit,
The second circuit and the third circuit respectively transfer the data to two adjacent bit lines,
The nonvolatile semiconductor memory device, wherein the data is simultaneously written into selected memory cells among the nonvolatile memory cells connected to the two adjacent bit lines. The nonvolatile semiconductor memory device according to claim 1, wherein the first circuit, the second circuit, and the third circuit are first, second, and third data cache circuits, respectively. 3. The nonvolatile semiconductor memory device according to claim 2, wherein each of the first, second, and third data cache circuits is a latch circuit. 4. The nonvolatile semiconductor memory device according to claim 3, wherein each of the second and third data cache circuits has two clocked inverters and one transistor. The selection circuit includes a plurality of logic circuits that control a plurality of transistors and gate electrodes of the plurality of transistors, and the second and third data cache circuits each control the plurality of logic circuits. The nonvolatile semiconductor memory device according to claim 4.

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