JP2006128526A - Semiconductor apparatus, its manufacturing method, and manufacturing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form an interlayer dielectric of multilayer wiring structure without a problem of depositing contamination, and with high flatness without spoiling electrical property. <P>SOLUTION: The method comprises a CVD process (step 1-5) of forming dopant content silicon oxide film in semi-ordinary pressure region by CVD method, and a reflowing process of reflowing the formed dopant content silicon oxide film. The CVD process is constituted by a first CVD process (step 2-4) of depositing the silicon oxide film containing dopant in high density using organic silicon system gas, dopant content organic system gas, and oxidizing gas as material gases; and a second CVD process (step 5) of depositing the silicon oxide film containing a small amount of dopant by controlling the dopant content organic system gas to be less in amount than that of the first CVD process. Problems of moisture absorption and depositing contamination caused by high density dopant, can be avoided by improving reflow ability in such a way that the dopant density is controlled in the first and second CVD processes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof and a manufacturing apparatus, and more particularly to an interlayer insulating film of a semiconductor device having a multilayer wiring structure.

  As semiconductor devices are miniaturized, a multilayer wiring structure using an interlayer insulating film is widely used. In order to form a multilayer wiring structure with high reliability, an interlayer insulating film is formed on the step generated by the lower layer wiring, and planarized using CMP (Chemical Mechanical Polishing), and the flat surface The upper layer wiring is formed on the upper side. The flattening of the interlayer insulating film is an important technique for securing a DOF (Depth of Focus) margin during resist exposure for patterning the upper layer wiring and for avoiding lower coverage of the upper layer wiring due to a step. .

As a method for forming an interlayer insulating film, it is known that a silicon oxide film with good step coverage can be formed by, for example, O ₃ / TEOS (Tetraethyl Orthosilicate) quasi-normal pressure CVD (quasi-normal pressure is about several Pa to 93,000 Pa). . Impurities such as boron and phosphorus are mixed in the O ₃ / TEOS material gas to form a PMD film (Pre Metal Dielectric) such as a BPSG film (Boron-Phosphoresce Silicate Glass), and heat treatment at about 800 to 900 ° C. There is also a method of improving flatness by applying and reflowing. When CMP is performed on the reflowed film, the flatness is further increased.

On the other hand, as the miniaturization of semiconductor devices and the improvement of operation speed progress, a technique called salicide (Self Aligned Silicide) is used to reduce the sheet resistance by siliciding the surface of the impurity diffusion layer and polysilicon gate electrode by self-alignment. It has been. In particular, by forming Co as a refractory metal over the entire surface and heat-treating it, silicidation occurs only with the underlying portion (impurity diffusion layer) of the silicon layer (polysilicon gate electrode) by self-alignment, and unreacted Co is wet etched. The salicide to be removed is useful because low-resistance CoSi ₂ is formed.

  However, as the miniaturization of semiconductor devices progresses, the transistor dimensions are shrunk, and the element spacing in which the PMD film to be deposited between the element region and the wiring layer has to be buried becomes smaller. In the element spacing region, voids are formed in the PMD film. If dry etching is performed to form a contact hole in this state, problems such as etch stop occur, and there is a problem that defective contact hole formation occurs.

Further, CoSi ₂ has low heat resistance, and there is a problem that CoSi agglomerates near the reflow temperature of the PMD film and sheet resistance increases. The same phenomenon occurs with salicide using Ni, which is a high melting point metal similar to Co. In order to perform reflow at a temperature at which CoSi aggregation does not occur, for example, 850 ° C. or less, the impurity concentration in the PMD film is increased to, for example, boron 5.0 wt% or more, phosphorus 6.0 wt% or more, or the pressure during film formation is increased. It is necessary to make it a high region of several hundred Pa or more, for example 20000 Pa or more (a high region is a state close to atmospheric pressure).

  However, the PMD film has higher hygroscopicity when the impurity concentration is increased, and the surface state becomes unstable in the air. Impurities such as boron and phosphorus are easy to absorb moisture and crystallize to form fine particles when moisture is absorbed. Even if CMP treatment is performed to flatten the film surface after reflow, problems such as defects and scratches occur. . When the pressure at the time of film formation is increased, the flatness can be improved even by heat treatment at a low temperature for a short time, but the hygroscopicity is further increased and the problem of crystallization becomes more significant than when the impurity concentration is increased. That is, void suppression and foreign matter precipitation are in a trade-off relationship.

  For this reason, in Patent Document 1, for example, a PMD film having a high impurity concentration (high concentration PMD film) is formed and reflowed in one chamber, and a silicon oxide film is further formed on the high concentration PMD film as a protective film in the chamber. As a result, the problem of precipitated foreign matter due to moisture absorption is solved.

In Patent Document 2, a silicon oxide film not containing impurities is formed on a high-concentration PMD film and then subjected to a reflow process, whereby the silicon oxide film containing no impurities is used as a cap film that suppresses the reaction between the PMD film and air. It works and solves the problem of foreign matter precipitation.
Japanese Patent Laid-Open No. 10-312998 JP-A-9-106985

  In the technology of Patent Document 1, as described above, the three processes of high concentration PMD film formation, reflow, and silicon oxide film formation are performed in the same chamber, and the PMD film formation temperature and reflow at that time are performed. Since the temperature and the deposition temperature of the silicon oxide film are different from each other, temperature control is performed to control the object to be processed to a predetermined temperature by lamp heating. However, since it takes time to change the temperature, the productivity is lowered, and there is a problem that the number of devices such as chambers must be increased in order to supplement the productivity. Further, there is a problem that thermal stress is applied to the laminated film of the PMD film and the silicon oxide film deposited on the inner wall of the chamber due to temperature change, film peeling occurs, and the particles adhere to the object to be processed.

  With the technique of Patent Document 2, when the silicon oxide film on the high-concentration PMD film becomes thick, high flatness cannot be obtained even if reflow is performed. Reflow that simply achieves flatness is possible by high-temperature heat treatment, but when manufacturing semiconductor devices with advanced technology nodes, the impurity profile of the impurity diffusion layer changes due to high-temperature heat treatment, and desired electrical characteristics are obtained. Therefore, the method of increasing the reflow temperature cannot be used to improve the reflow characteristics.

  An object of the present invention is to solve the above-described problems, and to form an interlayer insulating film having a multilayer wiring structure with high flatness without causing a problem of precipitated foreign matter and without impairing electric characteristics.

  As a result of researches to solve the above problems, the present inventors have found that the impurity concentration that reveals the deposited foreign matter is higher than the impurity concentration that does not impair the reflow property, and utilizes the difference between these impurity concentrations. By controlling the film quality, the flatness of the film was ensured without revealing the deposited foreign matter.

  That is, the manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device having a multilayer wiring structure in which an impurity-containing silicon oxide film is disposed as an interlayer insulating film between a lower layer wiring and an upper layer wiring, the impurity-containing silicon A CVD process for forming an oxide film by a CVD method; and a reflow process for reflowing the formed impurity-containing silicon oxide film. The CVD process includes an organic silicon-based gas, an impurity-containing organic gas, and an oxidizing gas. As a material gas, a first CVD process for forming a silicon oxide film containing impurities at a high concentration, and an impurity-containing organic gas are controlled to be lower than those in the first CVD process, so that a small amount of impurities can be removed. It is characterized by comprising the second CVD step of forming the contained silicon oxide film.

  The impurity-containing silicon oxide film is formed in a pressure region of 15000 Pa to 100,000 Pa. This is because the reflow property generally depends on the impurity concentration and the film forming pressure, and the reflow property of the film formed in the pressure region of 150,000 Pa to 100,000 Pa becomes high.

  The impurity-containing organic gas is one or more of organic gases containing at least one of boron and phosphorus, and the impurity-containing silicon oxide film formed in the second CVD process is formed on the surface. The allowable value of the dissolution amount of boron and phosphorus dissolved in the water in contact with each other is determined, and the concentration in the film forming tank of the impurity-containing organic gas that is equal to or lower than the allowable value is obtained in advance and becomes the concentration in the film forming tank. Thus, the flow rate of the impurity-containing organic gas is controlled.

The impurity-containing silicon oxide film formed in the second CVD process has a film thickness of 10 nm or less, and is less than 0.0020 μg / cm ^{2 of} boron or 0.010 μg / cm of phosphorus with respect to water in contact with the surface. ^The impurity content is ² or less, or boron and phosphorus of 0.01 μg / cm ² or less. Good reflow properties can be obtained in the above-described film thickness range, and foreign matter precipitation can be avoided in the above-described impurity content range.

  The semiconductor device manufacturing apparatus of the present invention has a pipe for supplying each of an organic silicon-based gas, an impurity-containing organic gas, and an oxidizing gas to a film forming tank, and the pipe of the impurity-containing organic gas is an organic silicon-based gas Compared to this pipe, the pipe length from the flow control device interposed to control the gas flow rate to a desired amount to the film formation tank is short.

  The semiconductor device of the present invention is a semiconductor device having a multilayer wiring structure in which an impurity-containing silicon oxide film is arranged as an interlayer insulating film between a lower layer wiring and an upper layer wiring, and the impurity-containing silicon oxide film is generated by the lower layer wiring. An organic silicon gas, an impurity-containing organic gas, and an oxidizing gas are formed as material gases on the stepped portion, and a high concentration of impurities are contained on the lower wiring side and a small amount of impurities are contained on the upper wiring side. Features.

  The method of manufacturing a semiconductor device according to the present invention forms an impurity-containing silicon oxide film as an interlayer insulating film in two stages, and improves the reflow property by controlling the impurity to a high concentration in the first stage. The problem of moisture absorption and deposited foreign matter is avoided by controlling the amount of impurities in the second stage, and also by controlling the film thickness. An interlayer insulating film having a multilayer wiring structure such as a transistor having a wiring layer for transmission can be formed with high flatness without a problem of precipitated foreign matter and without impairing electrical characteristics. Therefore, a semiconductor device in which element spacing is miniaturized can be obtained with a high yield.

  Since it is sufficient to perform reflow after film formation in two stages, temperature control is easy and productivity does not decrease. The CMP (chemical mechanical polishing) processing time performed after the formation of the interlayer insulating film to alleviate the global step can be shortened, which greatly contributes to the improvement of the productivity of the CMP apparatus.

  The semiconductor device manufacturing apparatus of the present invention that implements this method can be realized by making a slight modification to the conventional device, and does not require any additional investment, extending the life of the conventional semiconductor device manufacturing apparatus and semiconductor manufacturing line. Is possible.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view showing a part of a semiconductor device, specifically a gate structure of a transistor, more specifically a polymetal gate structure.

  In FIG. 1, a polysilicon electrode 2 (70 nm), a titanium nitride film 3 (15 nm), a tungsten film 4 (100 nm), and a titanium nitride film 5 (15 nm) are formed on a semiconductor substrate (wafer) 1. A silicon nitride film 6 (100 nm) and a SiON film 7 (50 nm) are formed. In order to form the gate electrode, predetermined resist patterning and dry etching are performed.

  Further, a silicon nitride film 8 (40 nm) is formed as a spacer film for SAC (Self Alien Contact). Since the LP-CVD method is used for forming the silicon nitride film 8, 400 ° C. or lower is provided prior to the silicon nitride film 8 for the purpose of preventing the tungsten 4 in the gate electrode portion from being oxidized by the entanglement oxidation. An insulating film 9 (about 20 nm) with good coverage that can be formed at the film forming temperature is formed as an antioxidant film. The embedding size in such a structure is about 150 nm.

  Then, a BPSG film 10 which is an impurity-containing silicon oxide film is formed on the silicon nitride film 8 and annealed in a nitrogen, oxygen or hydrogen atmosphere in order to improve the embedding property. The film thickness of the BPSG film 10 is determined in accordance with the pattern, the region to be embedded, the depth, etc., but here it is formed to a thickness of about 500 nm. The BPSG film 10 contains impurities at a very high concentration of boron 4.0 wt% and phosphorus 6.0 wt%.

On the high-concentration impurity-containing BPSG film 10, a BPSG film 11 which is a silicon oxide film containing a small amount of impurities is formed. The BPSG film 11 desirably has a thickness of 10 nm or less in order to ensure high reflow properties, and is formed here with a thickness of 5 nm. BPSG film 11, to the water in contact with the surface at a predetermined condition, boron 0.00020μg / cm ² or less, or, phosphorus 0.010 / cm ² or less, or, boron and phosphorus 0.01 [mu] g / cm ² or less Is an impurity content to dissolve.

  When the above-described polymetal gate structure portion was observed with an operation electron microscope, the BPSG film 11 showed good reflow properties, and no void was observed in the space between the gate electrodes. Before the observation, a wet etching process of BHF 1:10 for 10 seconds is performed as a decoration process.

  This observation result shows that the film structure having a high impurity concentration on the Bulk side, as described above, does not cause deterioration in reflow characteristics, so that foreign matter is precipitated due to moisture in the atmosphere and moisture in the cleaning treatment atmosphere after film formation. It is shown that can be avoided. This will be further described with reference to FIG.

FIG. 2 shows the correlation between the number of defects in the insulating film (PMD film) and the amount of impurities deposited.
The sample is a silicon oxide film (impurity high concentration layer 800 nm, low concentration layer 5.0 nm) formed on a semiconductor substrate (200 mm substrate) and exposed to the atmosphere. The film formation conditions are a substrate temperature of 450 ° C. and a film formation pressure of 25000 Pa.

The number of defects (au) shown on the vertical axis indicates the amount of defects of 0.20 μm or more present per sample, that is, phosphorus and boron in the atmosphere using a defect evaluation apparatus equipped with an optical system such as a laser. This is a result of detecting precipitates of P ₂ O ₅ and B ₂ O ₃ produced by reacting with the above.

  The amount of precipitated impurities (μg) shown on the horizontal axis is quantitatively analyzed by inductively coupled plasma mass spectrometry (ICP-MS) using 2 ml of pure water dropped on the sample and allowed to stand for 2 minutes and then recovered. The result shows the dissolved amount of each sample of boron and phosphorus dissolved in pure water. The pure water dropped on the sample spreads over the entire sample surface because the surface is hydrophilic.

  In FIG. 2, when the precipitation amount of boron exceeds 0.05 μg, and the precipitation amount of phosphorus exceeds 3.0 μg, the number of defects increases rapidly. In other words, precipitated foreign matter is suppressed when boron is 0.05 μg or less and phosphorus is 3.0 μg or less.

Accordingly, the amount dissolved in water contacting the surface is 0.05 μg or less of boron (about 0.0020 μg / cm ² ) or less than 3.0 μg of phosphorus (about 0.010 μg / cm ² ) or 0.01 μg of boron and phosphorus. By forming an insulating film having an impurity content of not more than / cm ^2, it can be said that the problem of moisture in the atmosphere and the deposit foreign matter due to the cleaning treatment after film formation can be avoided, and excellent heat treatment reflow characteristics can be realized. Although this result was obtained with a film thickness of 5.0 nm as described above, the reflow property is not impaired if the film thickness is 10 nm or less.

The semiconductor device manufacturing apparatus of the present invention will be described.
The semiconductor device manufacturing apparatus shown in FIG. 3 is a CVD apparatus for forming an insulating film (PMD film) as described above.

  In the chamber 101, a susceptor 103 for installing a semiconductor substrate 102 to be processed and a shower head 104 for uniformly supplying a material gas to the semiconductor substrate 102 are installed. The susceptor 103 incorporates a heating mechanism such as a heater for heating the semiconductor substrate 102. However, for the PMD film, a resistance heating method using a heating mechanism in the susceptor 103 may be used, or a lamp heating method in which a lamp (not shown) is provided in the vicinity of the susceptor 103 to directly heat the PMD film may be used. .

  Outside the chamber 101, a vacuum pump 106 that controls the pressure in the chamber 101 through a vacuum pipe 105 is installed. A throttle valve 107 and a main valve 108 are interposed in the vacuum pipe 105. The throttle valve 107 is for controlling the pressure during film formation, but there is no problem even if any of the various types of throttle valves is used.

A first material gas supply system 109 and a second material gas supply system 110 that supply material gas to the shower head 104 are also provided outside the chamber 101.
The first material gas supply system 109 has an O ₃ pipe 111 connected to an O ₃ supply source. The second material gas supply system 110 includes a TEOS pipe 112 connected to the TEOS supply source, a TEB pipe 113 connected to the TEB supply source, and a TEPO pipe 114 connected to the TEPO supply source. Main pipe 115. The second material gas supply system 110 is provided with only three systems of pipes 112, 113, and 114, but may be added according to the type of material gas required.

  A main valve 116 is installed in the main pipe 115. In other piping, a first valve 117 for opening and closing the pipe line is installed, a mass flow controller 118 for controlling the gas flow rate is installed upstream thereof, and a second valve 119 is installed immediately upstream of the mass flow controller 118. Is provided. The main valve 116 and the first and second valves 117 and 119 are used as emergency shut-off valves as part of particle gas reduction, material gas supply stabilization, and safety measures.

  The controllability and responsiveness of the material gas amount are important factors for improving the controllability of the impurity content in the film. Therefore, the pipe length from the mass flow controller 118 to the chamber 101 in the second material gas supply system 110 is set so that the impurity pipes 113 and 114 are shorter than the pipe 112 for TEOS. The effect of the amount of impurities inside is reduced. This can be said to be a particularly useful configuration when the diameter of the semiconductor substrate 102 is further increased and management in units of single wafers becomes necessary.

  The mass flow controller 118 is provided with a logging system (control system) 120 for monitoring an actual flow rate, a control signal, and signals for opening and closing the valves 116, 117, and 119. By providing this logging system 120, it is possible to manage the state of the semiconductor substrate 102 on a single wafer, to detect abnormal film formation at an early stage, and to select a semiconductor substrate on which abnormal film formation has occurred. At the same time, it is possible to detect an apparatus abnormality at an early stage.

  A degassing analyzer 121 is also installed in the chamber 101 for the same purpose. By providing the degassing analyzer 121, it is possible to control the impurity concentration in the chamber 101 at the initial stage of film formation, and to feed back the analysis result to the mass flow controller 118.

  The logging system 120 and the degassing analyzer 121 are installed because it is necessary to strictly control the impurity concentration. However, the mass flow controller 118 has high performance or the response time and control of the film forming program. These monitoring systems are not necessarily required if the performance is excellent.

An insulating film forming method will be described with reference to the film forming profile shown in FIG. The horizontal axis indicates time, and the vertical axis indicates whether or not each component gas is supplied.
(Step 1)
A semiconductor substrate 102 to be processed is placed on a susceptor 103 and heated to a desired substrate temperature.

  At this time, the atmosphere in the chamber 101 may be either vacuum or air. However, since the insulating film (PMD film) is formed in the quasi-atmospheric pressure region of 100 to 80,000 Pa, the semiconductor is used in this film forming pressure region. It is desirable to heat the substrate 102.

  Here, it is assumed that the TEOS gas is flowed at 500 sccm, and in that case, it is desirable to control the pressure so that a desired process pressure becomes, for example, 25000 Pa, and to set the substrate temperature to 400 ° C. or higher. To do. When the substrate temperature reaches 450 ° C., the process proceeds to the next step.

(Step 2)
Next, a TEB gas for doping boron into the film formed of TEOS is flowed at 160 sccm. Thereby, the boron concentration on the Bulk side is increased. Only TEB gas is flown because the flow rate controllability of TEB is poor, and when TEPO and O ₃ which is an oxidizing agent are flowed in the next step, the boron of the dopant reacts with TEPO and TEOS and the concentration on the Bulk side of the film Therefore, the supply starts slightly before TEPO and TEOS. Depending on the size of the chamber 101 and the flow rate of each component gas, this step 2 requires about 20 seconds.

(Step 3)
Next, TEPO and O ₃ gas are flowed at 5000 Sccm. Step 3 is a time for obtaining a desired film thickness.
(Step 4)
Then, the supply of TEB and TEPO is stopped. In step 4, the formation of the silicon oxide film (high concentration BPSG film) containing boron and phosphorus at a high concentration is completed.

(Step 5)
TEOS and O ₃ gas are stopped by adjusting the film formation time in advance so that the film thickness of the film to be formed is 5 nm. While the TEOS and O ₃ gas are supplied, TEB and TEPO remaining in the pipes 113, 114, and 115 are also supplied, so that a silicon oxide film containing minute boron and phosphorus is formed. The If it is known in advance that appropriate amounts of TEB and TEPO do not remain in the pipes 113, 114, and 115, a very small amount of TEB and TEPO may be allowed to flow while continuing to supply TEOS and O ₃ gas. After film formation, the chamber 101 is evacuated and the semiconductor substrate 102 is taken out.

  The semiconductor device of the present invention is formed to have a multilayer structure including the insulating film (PMD film) as described above. Insulating film has excellent heat treatment reflow characteristics and flatness due to the film quality of the film formed in the last step, free from moisture in the atmosphere and deposited foreign matter due to cleaning treatment after film formation. .

Note that the flow rates of the above-described TEOS, TEB, TEPO, and O ₃ gases are examples of suitable flow rates set to achieve the above-described desired boron and phosphorus concentrations, and are not limited thereto.

  The method and apparatus for manufacturing a semiconductor device according to the present invention can form an interlayer insulating film having a multilayer wiring structure with high flatness without a problem of deposited foreign matter, and particularly for manufacturing a semiconductor device in which element spacing is miniaturized. Useful.

Sectional view showing the polymetal gate structure of a semiconductor device A graph showing the correlation between the amount of deposited impurities and the number of defects in an insulating film 1 is a schematic configuration diagram of a semiconductor device manufacturing apparatus according to an embodiment of the present invention. The conceptual diagram which shows the film-forming profile of the semiconductor device manufacturing method in one Embodiment of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Polysilicon electrode 3 Titanium nitride film 4 Tungsten film 5 Titanium nitride film 6 Silicon nitride film 7 SiON film 8 Silicon nitride film 9 Insulating film 10 BPSG film 11 BPSG film 101 Chamber 102 Semiconductor substrate 104 Shower head 112 TEOS piping 113 TEB piping 114 TEPO piping 118 Mass flow controller

Claims (6)

A method for manufacturing a semiconductor device having a multilayer wiring structure in which an impurity-containing silicon oxide film is disposed as an interlayer insulating film between a lower layer wiring and an upper layer wiring,
A CVD step of forming the impurity-containing silicon oxide film by a CVD method;
Reflow process of reflowing the formed impurity-containing silicon oxide film,
The CVD process includes
A first CVD step of forming a silicon oxide film containing impurities at a high concentration using an organic silicon-based gas, an impurity-containing organic gas, and an oxidizing gas as a material gas;
A method of manufacturing a semiconductor device comprising: a second CVD step of forming a silicon oxide film containing a trace amount of impurities by controlling an impurity-containing organic gas to a lower amount than in the first CVD step.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity-containing silicon oxide film is formed in a pressure region of 15000 Pa to 100000 Pa.   The impurity-containing organic gas is one or a plurality of organic gases containing at least one of boron and phosphorus, and the impurity-containing silicon oxide film formed in the second CVD process is formed on the surface. The allowable value of the dissolution amount of boron and phosphorus dissolved in the water in contact with each other is determined, and the concentration in the film forming tank of the impurity-containing organic gas that is equal to or lower than the allowable value is obtained in advance and becomes the concentration in the film forming tank. The method of manufacturing a semiconductor device according to claim 1, wherein the flow rate of the impurity-containing organic gas is controlled as described above. The impurity-containing silicon oxide film formed in the second CVD process has a film thickness of 10 nm or less, and is less than 0.0020 μg / cm ^{2 of} boron or 0.010 μg / cm ^{2 of} phosphorus with respect to water in contact with the surface. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the impurity content is such that boron or phosphorus is dissolved in an amount of 0.01 μg / cm ² or less. A semiconductor device manufacturing apparatus for forming an interlayer insulating film according to claim 1,
A pipe for supplying each of the organic silicon-based gas, the impurity-containing organic gas, and the oxidizing gas to the film formation tank, and the impurity-containing organic gas pipe has a gas flow rate that is higher than that of the organic silicon-based gas pipe. A semiconductor device manufacturing apparatus having a short pipe length from a flow control device interposed to control a desired amount to a film formation tank. A semiconductor device having a multilayer wiring structure in which an impurity-containing silicon oxide film is disposed as an interlayer insulating film between a lower layer wiring and an upper layer wiring,
The impurity-containing silicon oxide film is formed using organic silicon-based gas, impurity-containing organic gas, and oxidizing gas as material gas on the step generated by the lower-layer wiring, and contains impurities at a high concentration on the lower-layer wiring side, A semiconductor device containing a small amount of impurities on the upper wiring side.

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