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JP2006121008A - Semiconductor component mounted structure and manufacturing method thereof - Google Patents

Semiconductor component mounted structure and manufacturing method thereof Download PDF

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Publication number
JP2006121008A
JP2006121008A JP2004309968A JP2004309968A JP2006121008A JP 2006121008 A JP2006121008 A JP 2006121008A JP 2004309968 A JP2004309968 A JP 2004309968A JP 2004309968 A JP2004309968 A JP 2004309968A JP 2006121008 A JP2006121008 A JP 2006121008A
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Japan
Prior art keywords
semiconductor
wiring pattern
substrate
organic film
component mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004309968A
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Japanese (ja)
Inventor
Takashi Kitae
孝史 北江
Yasuharu Karashima
靖治 辛島
Takashi Ichiyanagi
貴志 一柳
Seiichi Nakatani
誠一 中谷
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2004309968A priority Critical patent/JP2006121008A/en
Publication of JP2006121008A publication Critical patent/JP2006121008A/en
Withdrawn legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/1624Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor component mounted structure which is easy to manufacture, adaptive to narrow pitches, and improved in insulation reliability and connection reliability, and to provide a manufacturing method thereof. <P>SOLUTION: The mounting method of electrically connecting a semiconductor (101) to a substrate is disclosed including an insulating layer (1201) and wiring patterns (501 and 502). The method comprises a step of forming metal projections (200) in nearly identical shapes on the semiconductor (101), positioning and mounting the semiconductor (101) on the substrate, applying pressure to crush the metal projections (200), connecting the metal projections (200) to a wiring pattern (501) formed on the top surface of the substrate, and connecting the metal projections (200) to a wiring pattern (502) formed on the reverse surface of the substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体部品実装体及びその製造方法に関するものである。   The present invention relates to a semiconductor component mounting body and a manufacturing method thereof.

近年、電子機器の高性能化、小型化の要求に伴い、回路基板、モジュール、半導体パッケージなどの電子部品実装体の高密度、高機能化に対する要求がますます厳しくなっている。半導体においても高密度化、高集積化に伴い電極端子が多ピン化、狭ピッチ化しているが、一方で半導体を実装する基板の配線ピッチそれに追いつかなくなってきている。半導体を実装する方法としては、ワイヤーボンディング実装とフリップチップ実装に大別できるが、多ピン化、狭ピッチ化への対応、配線遅延の減少などの目的でフリップチップ実装が注目を集めている。   In recent years, with the demand for higher performance and miniaturization of electronic devices, demands for higher density and higher functionality of electronic component mounting bodies such as circuit boards, modules, and semiconductor packages have become increasingly severe. Also in semiconductors, electrode terminals have become multi-pin and narrow pitched with higher density and higher integration, but on the other hand, it has become difficult to keep up with the wiring pitch of the substrate on which the semiconductor is mounted. As a method for mounting a semiconductor, it can be broadly divided into wire bonding mounting and flip chip mounting, but flip chip mounting has been attracting attention for the purpose of increasing the number of pins, reducing the pitch, and reducing wiring delay.

図15は多層基板へ半導体チップをフリップチップ実装した半導体部品実装体の構造である。半導体のアクティブ面に形成された金属突起物は基板の表層に設けられた配線パターンに電気的に接続されている。表層の配線パターンから層間接続部として設けられたビアやスルーホールを介して配線が引き回されている。従来のこの構成では、半導体の電極端子の多ピン化、狭ピッチ化への対応が困難になってきており、ビア、スルーホール、配線パターンの引き回しにより、多くの基板面積が必要である。   FIG. 15 shows a structure of a semiconductor component mounting body in which a semiconductor chip is flip-chip mounted on a multilayer substrate. The metal protrusion formed on the active surface of the semiconductor is electrically connected to a wiring pattern provided on the surface layer of the substrate. Wiring is routed from the surface wiring pattern through vias and through holes provided as interlayer connection portions. In this conventional configuration, it is difficult to cope with the increase in the number of pins and the narrow pitch of semiconductor electrode terminals, and a large substrate area is required due to the routing of vias, through holes, and wiring patterns.

この課題を解決する手段として、半導体のアクティブ面に表層配線パターン用と内層配線パターン用の異なる高さの金属突起物をそれぞれ形成し、異なる層の配線パターンに金属突起物を介して直接接続する方法が下記特許文献1に提案されている。この構成により、ビアやスルーホールの削減など基板の設計自由度が向上する。
特開2002−246415号公報
As means for solving this problem, metal projections having different heights for the surface layer wiring pattern and the inner layer wiring pattern are formed on the active surface of the semiconductor, respectively, and directly connected to the wiring patterns of different layers via the metal projections. A method is proposed in Patent Document 1 below. With this configuration, the degree of freedom in designing the substrate such as the reduction of vias and through holes is improved.
JP 2002-246415 A

しかし、前記特許文献1の実装方法では、以下のような問題点が挙げられる。
(1) 各層に合わせて異なる高さの金属突起物を予め形成する必要があり、金属突起物を形成する工程が煩雑になる。
(2) 金属突起物を形成する際の高さばらつきを厳密に制御する必要がある。
(3) 基板の同一層内の厚みにばらつきがある場合、そのばらつきを吸収できない。
(4) 異なる高さの金属突起物を形成することで半導体の上下左右の向きが発生する。そのため、実装時に向きを規定しなくてはならず、上下反転などの不良が発生する可能性がある。
(5) 金属突起物を表層配線パターンと内層配線パターンに接続する場合、樹脂層などの絶縁層が薄いことが必須となってくるが、その場合、表層配線パターンと内層配線パターンの絶縁性確保が難しい。
However, the mounting method disclosed in Patent Document 1 has the following problems.
(1) It is necessary to previously form metal protrusions having different heights for each layer, and the process of forming the metal protrusions becomes complicated.
(2) It is necessary to strictly control the height variation when forming the metal protrusion.
(3) When there is a variation in the thickness of the same layer of the substrate, the variation cannot be absorbed.
(4) By forming metal protrusions with different heights, the vertical and horizontal orientations of the semiconductor occur. Therefore, the direction must be specified at the time of mounting, and defects such as upside down may occur.
(5) When connecting metal protrusions to the surface layer wiring pattern and the inner layer wiring pattern, it is essential that the insulating layer such as the resin layer is thin. In that case, ensuring insulation between the surface layer wiring pattern and the inner layer wiring pattern Is difficult.

本発明は、前記従来の課題を解決するための半導体部品実装体及び半導体部品実装体の製造方法であって、新たな実装方法を提案する。   The present invention proposes a new mounting method, which is a semiconductor component mounting body and a method for manufacturing the semiconductor component mounting body, for solving the conventional problems.

本発明の半導体部品実装体の製造方法は、絶縁層と配線パターンを含む基板に半導体を電気的に接続する実装方法であって、前記半導体に略同形状の金属突起物を形成し、前記半導体を前記基板に位置決めして搭載し、圧力をかけて前記金属突起物を押し潰し、前記金属突起物と前記基板の表面に形成された前記配線パターンとを接続し、前記金属突起物と前記基板の裏面に形成された前記配線パターンとを接続する工程を含むことを特徴とする。   The method for manufacturing a semiconductor component mounting body according to the present invention is a mounting method in which a semiconductor is electrically connected to a substrate including an insulating layer and a wiring pattern, wherein a metal protrusion having substantially the same shape is formed on the semiconductor, and the semiconductor Is positioned and mounted on the substrate, and the metal protrusions are crushed by applying pressure to connect the metal protrusions and the wiring pattern formed on the surface of the substrate. The metal protrusions and the substrate And a step of connecting the wiring pattern formed on the back surface of the substrate.

本発明の別の半導体部品実装体の製造方法は、絶縁層と配線パターンからなる多層基板に半導体を電気的に接続する実装方法であって、前記半導体に略同形状の金属突起物を形成し、前記半導体を前記基板に位置決めして搭載し、前記半導体の前記金属突起物に圧力をかけて押し潰し、少なくとも前記基板の内層に形成された配線パターンと、前記内層とは異なる層に形成された前記配線パターンに接続させる工程を含むことを特徴とする。   Another method of manufacturing a semiconductor component mounting body according to the present invention is a mounting method in which a semiconductor is electrically connected to a multilayer substrate composed of an insulating layer and a wiring pattern, and a metal protrusion having substantially the same shape is formed on the semiconductor. The semiconductor is positioned and mounted on the substrate, the metal protrusions of the semiconductor are pressed and crushed, and the wiring pattern formed at least on the inner layer of the substrate is formed on a layer different from the inner layer. And a step of connecting to the wiring pattern.

本発明の半導体部品実装体は、フレキシブル基板に半導体を、前記半導体に設けられた金属突起物を介して電気的に接続した半導体部品実装体であって、前記フレキシブル基板は、有機フィルムと、前記有機フィルムの両面に形成された樹脂層と、前記樹脂層に埋め込まれた配線パターンを含み、前記半導体の前記金属突起物の少なくとも一つは、前記フレキシブル基板の表面に形成された前記配線パターンに接続されており、かつ、前記半導体の前記金属突起物の少なくとも一つは、前記有機フィルムを貫通し、前記フレキシブル基板の裏面に形成された前記配線パターンに接続されていることを特徴とする。   The semiconductor component mounting body of the present invention is a semiconductor component mounting body in which a semiconductor is electrically connected to a flexible substrate via a metal protrusion provided on the semiconductor, and the flexible substrate includes an organic film, A resin layer formed on both sides of the organic film; and a wiring pattern embedded in the resin layer, wherein at least one of the metal protrusions of the semiconductor is formed on the wiring pattern formed on the surface of the flexible substrate. It is connected, and at least one of the metal protrusions of the semiconductor penetrates the organic film and is connected to the wiring pattern formed on the back surface of the flexible substrate.

本発明の別の半導体部品実装体は、フレキシブル基板に半導体を、前記半導体に設けられた金属突起物を介して電気的に接続した半導体部品実装体であって、前記フレキシブル基板は、有機フィルムと、前記有機フィルムの両面に形成された樹脂層と、前記樹脂層に埋め込まれた配線パターンを含むフレキシブル基板が複数積層された多層フレキシブル基板であり、前記半導体の前記金属突起物の少なくとも一つは、前記有機フィルムを貫通し、前記フレキシブル基板の内層に形成された前記配線パターンに接続されており、かつ、前記半導体の前記金属突起物の少なくとも一つは、前記金属突起物が接続した層とは異なる層の配線パターンに接続されていることを特徴とする。   Another semiconductor component mounting body of the present invention is a semiconductor component mounting body in which a semiconductor is electrically connected to a flexible substrate via a metal protrusion provided on the semiconductor, and the flexible substrate includes an organic film and A multilayer flexible substrate in which a plurality of flexible substrates including a resin layer formed on both surfaces of the organic film and a wiring pattern embedded in the resin layer are laminated, and at least one of the metal protrusions of the semiconductor is , Penetrating the organic film, connected to the wiring pattern formed in the inner layer of the flexible substrate, and at least one of the metal protrusions of the semiconductor is a layer connected to the metal protrusions Are connected to wiring patterns of different layers.

本発明の半導体部品実装体の製造方法によれば、従来までの表層配線パターンに金属突起物を介して半導体を電気的に接続していた場合に比べて、内層配線パターンに直接電気的に接続でき、ビアやスルーホールの削減できる。また、半導体の狭ピッチに対応可能であり、基板の設計自由度も増す。   According to the method for manufacturing a semiconductor component mounting body of the present invention, compared to the conventional case where the semiconductor is electrically connected to the surface layer wiring pattern via the metal protrusion, the semiconductor component mounting body is directly electrically connected to the inner layer wiring pattern. It is possible to reduce vias and through holes. In addition, it is possible to cope with a narrow pitch of the semiconductor, and the degree of freedom in designing the substrate is increased.

また、本発明の半導体部品実装体においては、基板としてこのフレキシブル基板を用いることにより、金属突起物を貫通させて各層の配線パターンに直接電気的に接続しつつ、かつ各層の絶縁信頼性が確保できる。   Further, in the semiconductor component mounting body of the present invention, by using this flexible substrate as a substrate, the metal protrusions are penetrated and directly connected to the wiring pattern of each layer, and the insulation reliability of each layer is ensured. it can.

本発明の半導体部品実装体の製造方法は、半導体のアクティブ面に略同形状(略同高さ)の金属突起物を形成する。基板に半導体を実装する際に圧力をかけて金属突起物を押し潰し、異なる層に設けられた配線パターン(表面配線パターンと裏面配線パターン、表層配線パターンと内層配線パターンなど)に同時に電気的に接続する。   In the method for manufacturing a semiconductor component mounting body according to the present invention, metal protrusions having substantially the same shape (substantially the same height) are formed on the active surface of the semiconductor. When mounting a semiconductor on a substrate, pressure is applied to crush the metal protrusions, and the wiring patterns (surface wiring pattern and back wiring pattern, surface wiring pattern and inner wiring pattern, etc.) provided in different layers are electrically connected simultaneously. Connecting.

本発明は、特開2002−246415号公報に提案されている従来例に比べ、以下のような利点がある。
(1) 各層に合わせて異なる高さの金属突起物を形成する必要がなく、略同形状の金属突起物を半導体のアクティブ面に形成すれば良く、工程が容易である。
(2) 金属突起物を形成する際の高さばらつきの範囲が緩やかである。
(3) 基板の同一層内の厚みにばらつきに対しても、金属突起物が押し潰されることにより吸収することができる。
(4) 略同じ高さの金属突起物を形成しているため、半導体の上下左右の区別がなく、実装時に向きを気にしなくても良い。上下反転などの不良が発生することもない。
The present invention has the following advantages over the conventional example proposed in Japanese Patent Laid-Open No. 2002-246415.
(1) It is not necessary to form metal protrusions having different heights for each layer, and metal protrusions having substantially the same shape may be formed on the active surface of the semiconductor, and the process is easy.
(2) The range of height variation when forming the metal protrusions is moderate.
(3) Variations in the thickness of the same layer of the substrate can be absorbed by the metal protrusion being crushed.
(4) Since the metal protrusions having substantially the same height are formed, there is no distinction between the upper and lower sides and the right and left sides of the semiconductor, and it is not necessary to worry about the orientation during mounting. Defects such as upside down do not occur.

以下、本発明の実施の形態について、図面を参照しながら説明する。以下の図面においては、説明の簡略化のため実質的に同一の機能を有する構成要素を同一の参照符号で示す。なお、本発明は以下の実施形態に限定されない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of simplicity. In addition, this invention is not limited to the following embodiment.

(実施の形態1)
図1A−Cは本発明の実施の形態1における半導体部品実装体の製造方法である。まず、半導体101に略同形状の金属突起物200を形成する(図1A)。絶縁層1201と配線パターン501、502からなる基板(図1B)に、この半導体を位置決めして、圧力をかけながら実装する。この際、金属突起物200は押し潰ぶされ、基板表面に設けられた配線パターン501に接続される金属突起物201と絶縁層を貫通して基板裏面に設けられた配線パターン502に接続される金属突起物202が形成される(図1C)。
(Embodiment 1)
1A to 1C show a method for manufacturing a semiconductor component mounting body according to the first embodiment of the present invention. First, a metal protrusion 200 having substantially the same shape is formed on the semiconductor 101 (FIG. 1A). This semiconductor is positioned on a substrate (FIG. 1B) composed of an insulating layer 1201 and wiring patterns 501 and 502, and mounted while applying pressure. At this time, the metal protrusion 200 is crushed and connected to the metal protrusion 201 connected to the wiring pattern 501 provided on the substrate surface and the wiring pattern 502 provided on the back surface of the substrate through the insulating layer. A metal protrusion 202 is formed (FIG. 1C).

(実施の形態2)
図2A−Cは本発明の実施の形態2における半導体部品実装体の製造方法である。実施の形態2では実施の形態1と比べ、基板として有機フィルム401と、有機フィルム401の両面に形成された樹脂層301と、樹脂層301に埋め込まれた配線パターン501、502とからなるフレキシブル基板1401を用いている。まず、半導体101に略同形状の金属突起物200を形成する(図2A)。有機フィルム401と、有機フィルム401の両面に形成された樹脂層301と、樹脂層301に埋め込まれた配線パターン501、502とからなるフレキシブル基板1401(図2B)に、この半導体を位置決めして、圧力をかけながら実装する。この際、金属突起物200は押し潰ぶされ、基板表面に設けられた配線パターン501に接続される金属突起物201と樹脂層301、302と有機フィルム401を貫通して基板裏面に設けられた配線パターン502に接続される金属突起物202が形成される(図2C)。
(Embodiment 2)
2A to 2C show a method for manufacturing a semiconductor component mounting body according to the second embodiment of the present invention. In the second embodiment, as compared with the first embodiment, a flexible substrate including an organic film 401 as a substrate, a resin layer 301 formed on both surfaces of the organic film 401, and wiring patterns 501 and 502 embedded in the resin layer 301. 1401 is used. First, a metal protrusion 200 having substantially the same shape is formed on the semiconductor 101 (FIG. 2A). The semiconductor is positioned on a flexible substrate 1401 (FIG. 2B) including an organic film 401, a resin layer 301 formed on both surfaces of the organic film 401, and wiring patterns 501 and 502 embedded in the resin layer 301. Mount with pressure. At this time, the metal protrusion 200 was crushed and provided on the back surface of the substrate through the metal protrusion 201, the resin layers 301 and 302, and the organic film 401 connected to the wiring pattern 501 provided on the substrate surface. A metal protrusion 202 connected to the wiring pattern 502 is formed (FIG. 2C).

(実施の形態3)
図3A−Cは本発明の実施の形態3における半導体部品実装体の製造方法である。実施の形態3では実施の形態1と比べ、基板として絶縁層1201と配線パターン501、502、503からなる多層基板を用いている。まず、半導体101に略同形状の金属突起物200を形成する(図3A)。基板(図3B)に、この半導体を位置決めして、圧力をかけながら実装する。この際、金属突起物200は押し潰ぶされ、基板表面に設けられた配線パターン501に接続される金属突起物201と絶縁層1201を貫通して基板内層に設けられた配線パターン502に接続される金属突起物202が形成される(図3C)。
(Embodiment 3)
3A to 3C show a method for manufacturing a semiconductor component mounting body according to Embodiment 3 of the present invention. In the third embodiment, as compared with the first embodiment, a multilayer substrate including an insulating layer 1201 and wiring patterns 501, 502, and 503 is used as a substrate. First, a metal protrusion 200 having substantially the same shape is formed on the semiconductor 101 (FIG. 3A). The semiconductor is positioned on a substrate (FIG. 3B) and mounted while applying pressure. At this time, the metal protrusions 200 are crushed and connected to the metal protrusions 201 connected to the wiring patterns 501 provided on the substrate surface and the wiring patterns 502 provided on the inner layer of the substrate through the insulating layer 1201. A metal protrusion 202 is formed (FIG. 3C).

(実施の形態4)
図4A−Cは本発明の実施の形態4における半導体部品実装体の製造方法である。実施の形態4では実施の形態3と比べ、基板として有機フィルム401、402と、有機フィルム401、402の両面に形成された樹脂層301、302、303と、樹脂層に埋め込まれた配線パターン501、502、503とからなる多層フレキシブル基板1402を用いている。まず、半導体101に略同形状の金属突起物200を形成する(図4A)。多層フレキシブル基板1402(図4B)に、この半導体を位置決めして圧力をかけながら実装する。この際、金属突起物200は押し潰され、基板表面に設けられた配線パターン501に接続される金属突起物201と樹脂層301、樹脂層302の一部、有機フィルム401を貫通して基板内層に設けられた配線パターン502に接続される金属突起物202が形成される(図4C)。
(Embodiment 4)
4A to 4C show a method for manufacturing a semiconductor component mounting body according to the fourth embodiment of the present invention. In Embodiment 4, compared with Embodiment 3, organic films 401 and 402 as substrates, resin layers 301, 302, and 303 formed on both surfaces of organic films 401 and 402, and wiring pattern 501 embedded in the resin layer , 502, and 503 are used. First, a metal protrusion 200 having substantially the same shape is formed on the semiconductor 101 (FIG. 4A). The semiconductor is positioned and mounted on a multilayer flexible substrate 1402 (FIG. 4B) while applying pressure. At this time, the metal protrusion 200 is crushed and penetrates through the metal protrusion 201 connected to the wiring pattern 501 provided on the substrate surface, the resin layer 301, a part of the resin layer 302, and the organic film 401. A metal protrusion 202 connected to the wiring pattern 502 provided on the substrate is formed (FIG. 4C).

実施の形態4では、図5A−Cのように表層に設けられた配線パターン501、内層に設けられた配線パターン502、基板裏面に設けられた配線パターン503、それぞれに金属突起物が接続されるような形態も可能である。   In the fourth embodiment, as shown in FIGS. 5A to 5C, metal projections are connected to the wiring pattern 501 provided on the surface layer, the wiring pattern 502 provided on the inner layer, and the wiring pattern 503 provided on the back surface of the substrate. Such a form is also possible.

実施の形態1から実施の形態4には本発明の半導体部品実装体の製造方法を示したが、以下に、それぞれの部材や条件について述べる。   Although the manufacturing method of the semiconductor component mounting body of the present invention is shown in the first to fourth embodiments, each member and conditions will be described below.

金属突起物が押し潰される工程と金属突起物が各層の配線パターンに接続される工程は、基本的に同一工程である。すなわち、配線パターンと半導体に挟まれながら金属突起物に圧力がかかり、押し潰されると同時に接続が完了する。なお、金属突起物を押し潰して配線パターンに物理的に接続したのち、熱などにより金属突起物あるいは配線パターンを溶融し、金属突起物と配線パターンを電気的に接続する方法なども利用できる。このような方法としては、金属突起物をハンダで形成したり配線パターンにハンダメッキしておく例が挙げられる。   The process of crushing the metal protrusion and the process of connecting the metal protrusion to the wiring pattern of each layer are basically the same process. That is, pressure is applied to the metal protrusion while being sandwiched between the wiring pattern and the semiconductor, and the connection is completed at the same time that the metal protrusion is crushed. In addition, after the metal protrusions are crushed and physically connected to the wiring pattern, the metal protrusions or the wiring pattern are melted by heat or the like, and the metal protrusions and the wiring pattern are electrically connected. Examples of such a method include forming metal protrusions with solder or solder plating on a wiring pattern.

金属突起物としては、金ワイヤーにより形成される金バンプが最も一般的に利用可能である。また、その他の金属ワイヤーにより形成されたバンプやメッキバンプ、ハンダバンプ、金属粉と樹脂を混合した導電性ペーストにより形成されたバンプなどが利用可能である。金属突起物の形状は特に問わないが、画鋲形状のバンプが好ましく利用できる。   As the metal protrusion, a gold bump formed by a gold wire is most commonly used. Further, bumps formed by other metal wires, plating bumps, solder bumps, bumps formed by conductive paste in which metal powder and resin are mixed, and the like can be used. The shape of the metal protrusion is not particularly limited, but a thumbtack-shaped bump can be preferably used.

金属突起物の形状や高さは厳密に同じである必要はなく、機械精度のばらつきなどにより、通常ばらつく範囲で略同形状であれば良い。また、どの層に接続するかによって金属突起物の形状や高さを変える必要はない。基本的には遠い方の層に接続する金属突起物に合わせて、長さを決めれば良い。   The shape and height of the metal protrusions do not have to be exactly the same, and may be approximately the same shape as long as they usually vary due to variations in mechanical accuracy. Further, it is not necessary to change the shape and height of the metal protrusion depending on which layer is connected. Basically, the length may be determined according to the metal protrusion connected to the far layer.

金属突起物の押し潰す圧力は、半導体や基板、配線パターンの厚み、材質、実装温度、実装時間などにより、最適な値を用いる必要がある。また、圧力は半導体上部から治具等で押す方法が好ましく利用できるが、その方法などは特に問わない。金属突起物はどの層に接続される場合でも、少なくとも押し潰されて実装される必要がある。なお、押し潰して接続した後に、熱や超音波を加えて更に接続を強化することも可能である。例えば、配線パターンをハンダメッキしておき、実装後に熱を加えて金属突起物と配線パターンをハンダを介して接続する形態も利用できる。また、圧力プロファイルとして、必要圧力を一気にかける工法、半導体を位置決めして基板に仮固定してから、再度圧力をかける工法、圧力を数回に分けてかける工法などが利用できる。圧力プロファイルと温度プロファイルを制御することで、より好ましい条件が設定できる。   It is necessary to use an optimum value for the crushing pressure of the metal projection depending on the thickness, material, mounting temperature, mounting time, etc. of the semiconductor, the substrate, and the wiring pattern. Moreover, although the method of pressing a pressure with a jig | tool etc. from a semiconductor upper part can be utilized preferably, the method etc. do not ask | require especially. When the metal protrusion is connected to any layer, it must be at least crushed and mounted. In addition, after squeezing and connecting, it is possible to further strengthen the connection by applying heat or ultrasonic waves. For example, it is possible to use a form in which the wiring pattern is solder-plated, and heat is applied after mounting to connect the metal protrusion and the wiring pattern via the solder. Further, as a pressure profile, a method of applying necessary pressure at once, a method of applying pressure again after positioning and temporarily fixing a semiconductor to a substrate, a method of applying pressure in several times, or the like can be used. More favorable conditions can be set by controlling the pressure profile and the temperature profile.

実装温度は基板材料(絶縁層、有機フィルム)が軟化するガラス転移点(Tg)以上の温度で行うのが好ましい。基板材料が軟化していることで、金属突起物が貫通しやすく、実装時間や圧力などの範囲設定が容易になるという利点がある。   The mounting temperature is preferably a temperature equal to or higher than the glass transition point (Tg) at which the substrate material (insulating layer, organic film) softens. Since the substrate material is softened, there is an advantage that the metal protrusions can easily penetrate and the setting of ranges such as mounting time and pressure becomes easy.

図6A−Cに示したように有機フィルム401に金属突起物201が貫通する箇所に予め穴1301、1302を開けておくことで、金属突起物が貫通しやすくなるという利点がある。その際、有機フィルムに設ける穴は小さめにしておき、金属突起物が貫通後に拡大することが好ましい。このような構成にすることで、金属突起物と有機フィルムの間が隙間なく埋まり、各層の絶縁信頼性がより確保される。なお、穴は樹脂層で埋められていても良い。   As shown in FIGS. 6A to 6C, there is an advantage that the metal protrusions can be easily penetrated by opening holes 1301 and 1302 in advance at the locations where the metal protrusions 201 penetrate the organic film 401. In that case, it is preferable that the hole provided in the organic film is made small and the metal protrusion expands after penetration. By setting it as such a structure, between a metal protrusion and an organic film is filled without a gap, and the insulation reliability of each layer is ensured more. The hole may be filled with a resin layer.

また、本発明では金属突起物を押し潰して配線パターンと電気的に接続するため、基板の同一層内の厚みにばらつきがある場合や基板が反ったりしている場合においても、そのばらつきを吸収することが可能である(図7A−C)。   Further, in the present invention, the metal protrusions are crushed and electrically connected to the wiring pattern, so that even when the thickness of the same layer of the substrate is uneven or the substrate is warped, the variation is absorbed. (FIGS. 7A-C).

なお、基板には電子部品が実装されていてもよく、電子部品としては抵抗やコンデンサ、インダクタなどの受動部品、モジュールなど、その種類や形状は特に問わない。また、半導体を実装した後に、電子部品を実装することも可能である。同様に、基板内に電子部品が内蔵されていてもよく、内蔵部品としてはチップ形状やシート状のコンデンサ、抵抗体、インダクタなど、その種類や形状は特に問わない。   Note that electronic components may be mounted on the substrate, and the types and shapes of electronic components such as resistors, capacitors, passive components such as inductors, modules, etc. are not particularly limited. It is also possible to mount electronic components after mounting the semiconductor. Similarly, an electronic component may be built in the substrate, and the type and shape of the built-in component are not particularly limited, such as a chip shape, a sheet-like capacitor, a resistor, and an inductor.

なお、これらの製造方法で半導体部品実装体を製造した後、半導体と基板間にアンダーフィルを挿入する工程を入れてもよい。また、アンダーフィルを予め基板に設置してから、これらの工程を行うことも十分可能である。アンダーフィルとしては液状のもの、シート状のものなどが好ましく利用できる。   In addition, after manufacturing a semiconductor component mounting body by these manufacturing methods, you may put the process of inserting an underfill between a semiconductor and a board | substrate. It is also possible to perform these steps after the underfill is previously installed on the substrate. As the underfill, liquid or sheet-like materials can be preferably used.

なお、基板の絶縁層あるいは樹脂層、有機フィルムはBステージであっても、Cステージであっても構わない。Bステージであれば、金属突起物が貫通しやすく、半導体を実装した後に硬化してCステージにすることが可能である。また、Cステージであれば、実装時の圧力や温度を制御することにより、金属突起物を貫通させて本発明の半導体部品実装体を作製できる。ここでBステージとは半硬化又は部分硬化状態をいい、Cステージとは硬化が完了した状態をいう。   The insulating layer or resin layer of the substrate and the organic film may be B stage or C stage. If it is a B stage, a metal protrusion can penetrate easily, and after mounting a semiconductor, it can harden | cure and can be set as a C stage. Moreover, if it is a C stage, the semiconductor component mounting body of this invention can be produced by penetrating a metal protrusion by controlling the pressure and temperature at the time of mounting. Here, the B stage refers to a semi-cured or partially cured state, and the C stage refers to a state where curing has been completed.

(実施の形態5)
次に半導体部品実装体について、可能な実施の形態を述べる。なお、以下の半導体部品実装体の実施の形態において、上述の実施の形態と同様のものについては同様の符号を記した。また、特に記述がない限り、上述した実施の形態と同様であり、その詳細な説明は省略する。
(Embodiment 5)
Next, possible embodiments of the semiconductor component mounting body will be described. In the following embodiments of the semiconductor component mounting body, the same reference numerals are given to the same components as those in the above-described embodiment. Further, unless otherwise specified, it is the same as the above-described embodiment, and detailed description thereof is omitted.

図8は本発明の実施の形態5における半導体部品実装体である。有機フィルム401と、その両面に形成された樹脂層301、302と、樹脂層に埋め込まれた配線パターン501、502からなるフレキシブル基板1403の両面板に、半導体101が実装されている。半導体101のアクティブ面に形成された金属突起物201はフレキシブル基板1403の表面に設けられた配線パターン501と電気的に接続しており、かつ、金属突起物202は樹脂層301、302及び有機フィルム401を貫通し、フレキシブル基板1403の裏面に設けられた配線パターン502と電気的に接続している構成である。   FIG. 8 shows a semiconductor component mounting body according to the fifth embodiment of the present invention. The semiconductor 101 is mounted on a double-sided board of a flexible substrate 1403 including an organic film 401, resin layers 301 and 302 formed on both sides thereof, and wiring patterns 501 and 502 embedded in the resin layer. The metal protrusion 201 formed on the active surface of the semiconductor 101 is electrically connected to the wiring pattern 501 provided on the surface of the flexible substrate 1403, and the metal protrusion 202 includes the resin layers 301 and 302 and the organic film. In this configuration, the wiring pattern 502 is provided so as to penetrate through 401 and be provided on the back surface of the flexible substrate 1403.

(実施の形態6)
図9は本発明の実施の形態6における半導体部品実装体である。実施の形態6では実施の形態5と比べ、基板として有機フィルム401、402と、有機フィルム401、402の両面に形成された樹脂層301、302、303と、樹脂層に埋め込まれた配線パターン501、502、503とからなる多層フレキシブル基板1404を用いており、この多層フレキシブル基板1404に半導体101が実装されている。半導体101のアクティブ面に形成された金属突起物201はフレキシブル基板1404の表面に設けられた配線パターン501と電気的に接続しており、かつ、金属突起物202は樹脂層301、302の一部及び有機フィルム401を貫通し、フレキシブル基板1404の内層に設けられた配線パターン502と電気的に接続している構成である。
(Embodiment 6)
FIG. 9 shows a semiconductor component mounting body according to the sixth embodiment of the present invention. In Embodiment 6, compared with Embodiment 5, organic films 401 and 402 as substrates, resin layers 301, 302, and 303 formed on both surfaces of organic films 401 and 402, and wiring pattern 501 embedded in the resin layer , 502, and 503 are used, and the semiconductor 101 is mounted on the multilayer flexible substrate 1404. The metal protrusion 201 formed on the active surface of the semiconductor 101 is electrically connected to the wiring pattern 501 provided on the surface of the flexible substrate 1404, and the metal protrusion 202 is part of the resin layers 301 and 302. In addition, the organic film 401 penetrates and is electrically connected to the wiring pattern 502 provided in the inner layer of the flexible substrate 1404.

(実施の形態7)
図10は本発明の実施の形態7における半導体部品実装体である。実施の形態7では実施の形態6と同様、多層フレキシブル基板1405に半導体101が実装されている。半導体101のアクティブ面に形成された金属突起物201はフレキシブル基板1405の表面に設けられた配線パターン501と電気的に接続し、金属突起物202は樹脂層301、302の一部及び有機フィルム401を貫通し、フレキシブル基板1405の内層に設けられた配線パターン502と電気的に接続している。また、金属突起物203は樹脂層301、302、303及び有機フィルム401、402を貫通し、フレキシブル基板1405の裏面に設けられた配線パターン503と電気的に接続している構成である。
(Embodiment 7)
FIG. 10 shows a semiconductor component mounting body according to the seventh embodiment of the present invention. In the seventh embodiment, as in the sixth embodiment, the semiconductor 101 is mounted on the multilayer flexible substrate 1405. The metal protrusion 201 formed on the active surface of the semiconductor 101 is electrically connected to the wiring pattern 501 provided on the surface of the flexible substrate 1405, and the metal protrusion 202 includes part of the resin layers 301 and 302 and the organic film 401. Are electrically connected to the wiring pattern 502 provided in the inner layer of the flexible substrate 1405. Further, the metal protrusion 203 is configured to penetrate the resin layers 301, 302, and 303 and the organic films 401 and 402 and to be electrically connected to the wiring pattern 503 provided on the back surface of the flexible substrate 1405.

これらの構成により、従来までの表層配線パターンに金属突起物を介して半導体を電気的に接続していた場合に比べて、内層あるいは裏面の配線パターンに金属突起物を介して直接電気的に接続でき、ビアやスルーホールの削減できる。また、半導体の狭ピッチに対応可能であり、基板の設計自由度も増す。   With these configurations, compared to the conventional case where the semiconductor is electrically connected to the surface layer wiring pattern via the metal protrusion, it is directly electrically connected to the wiring pattern on the inner layer or the back surface via the metal protrusion. It is possible to reduce vias and through holes. In addition, it is possible to cope with a narrow pitch of the semiconductor, and the degree of freedom in designing the substrate is increased.

また、基板の内層あるいは裏面側に設けられた配線パターンまで金属突起物が貫通するためには、金属突起物に対して基板自体が薄い必要がある。近年、半導体の端子電極は狭ピッチ化しており、125μmピッチや80μmピッチが現在のトップ水準である。このような条件では、金属突起物の台座径は50μm〜100μm程度、長さは40μm〜百数十μm程度である。本発明においても基板厚みが薄い方が好ましく、基板厚みより実装前の金属突起物の長さが長い方が好ましい。また、基板が薄くなると各層の絶縁信頼性が懸念される。本実施の形態における半導体部品実装体では、基板として有機フィルムと、その両面に形成された樹脂層と、樹脂層に埋め込まれた配線パターンとからなるフレキシブル基板を用いており、金属突起物を貫通させて各層の配線パターンに電気的に接続した場合においても、基板内に設けられた有機フィルムの絶縁性により各層の絶縁信頼性が確保できる。   Further, in order for the metal protrusion to penetrate to the wiring pattern provided on the inner layer or the back side of the substrate, the substrate itself needs to be thin relative to the metal protrusion. In recent years, semiconductor terminal electrodes have been narrowed in pitch, and 125 μm pitch and 80 μm pitch are the current top level. Under such conditions, the base diameter of the metal protrusion is about 50 μm to 100 μm, and the length is about 40 μm to several hundreds of μm. Also in this invention, the one where a board | substrate thickness is thin is preferable, and the one where the length of the metal protrusion before mounting is longer than board | substrate thickness is preferable. In addition, when the substrate becomes thin, there is a concern about the insulation reliability of each layer. In the semiconductor component mounting body according to the present embodiment, a flexible substrate including an organic film, a resin layer formed on both sides of the organic film, and a wiring pattern embedded in the resin layer is used as a substrate, and the metal protrusion is penetrated. Even when electrically connected to the wiring pattern of each layer, the insulation reliability of each layer can be ensured by the insulating property of the organic film provided in the substrate.

なお、樹脂層の厚みは有機フィルムの厚みより厚いことが好ましく、また、有機フィルムの厚みは5μm以下であることが好ましい。このような構成であれば、基板厚みを薄くすることができ、かつ、基板の絶縁信頼性が確保できる。また、配線パターンの厚みが樹脂層厚みの80%以上である方が好ましい。この構成であれば、基板の表面側では実装時の配線パターンの沈み込みが少なく、接続しやすい。逆に基板の内層や裏面側では樹脂層が少なく金属突起物が配線パターンに接続されやすい。このような形態に用いる有機フィルムとしては、アラミドフィルムやポリイミドフィルムなどが好ましく利用できる。   In addition, it is preferable that the thickness of a resin layer is thicker than the thickness of an organic film, and it is preferable that the thickness of an organic film is 5 micrometers or less. With such a configuration, the thickness of the substrate can be reduced, and the insulation reliability of the substrate can be ensured. Moreover, it is preferable that the thickness of the wiring pattern is 80% or more of the resin layer thickness. With this configuration, on the surface side of the substrate, there is little sinking of the wiring pattern during mounting, and connection is easy. Conversely, there are few resin layers on the inner layer and the back side of the substrate, and the metal protrusions are easily connected to the wiring pattern. As the organic film used in such a form, an aramid film or a polyimide film can be preferably used.

なお、金属突起物が接続された配線パターンの形状が略凹形状であることが好ましい(図11)。この様な形状により、金属突起物との接触面積が増加し、接続信頼性が向上する。実装プロセス(実装圧力、実装温度など)、基板(樹脂層、有機フィルム、電極の厚み、材料特性など)、金属突起物の材料、太さなどの条件を最適化することで、配線パターンの形状を略凹形状の形状にすることが可能である。   In addition, it is preferable that the shape of the wiring pattern to which the metal protrusion is connected is a substantially concave shape (FIG. 11). With such a shape, the contact area with the metal protrusion is increased, and the connection reliability is improved. By optimizing conditions such as mounting process (mounting pressure, mounting temperature, etc.), substrate (resin layer, organic film, electrode thickness, material properties, etc.), metal projection material, thickness, etc., the shape of the wiring pattern Can be made into a substantially concave shape.

また、金属突起物と配線パターンの接続断面積は、半導体の実装面側に近い層の配線パターンに接続されている方が、遠い層の配線パターンに接続されているものより大きいことが好ましい。一般的に基板より半導体の方が熱膨張係数は小さく、半導体に近い層に接続している金属突起物の方が熱膨張係数による応力が掛かりやすい。また、半導体から遠い層の配線パターンに接続している金属突起物の方が樹脂層に多く接触しており、樹脂層が補強剤の役割を果たすため、熱応力が緩和される。そのため、半導体の実装面側に近い層の配線パターンに接続されている部分の金属突起物と配線パターンの接続断面積を大きくすることで、接続信頼性を保てる利点がある。   Further, the connection cross-sectional area between the metal protrusion and the wiring pattern is preferably larger when connected to the wiring pattern of the layer closer to the mounting surface side of the semiconductor than when connected to the wiring pattern of the far layer. In general, a semiconductor has a smaller thermal expansion coefficient than a substrate, and a metal protrusion connected to a layer closer to the semiconductor is more likely to be stressed by the thermal expansion coefficient. Further, the metal protrusions connected to the wiring pattern of the layer far from the semiconductor are in contact with the resin layer more, and the resin layer serves as a reinforcing agent, so that the thermal stress is relieved. Therefore, there is an advantage that the connection reliability can be maintained by increasing the connection cross-sectional area of the metal projection and the wiring pattern in the portion connected to the wiring pattern of the layer close to the semiconductor mounting surface side.

また、本発明の半導体部品実装体においては、配線パターン間を電気的に接続する層間接続部位が設けられていても良い(図12)。層間接続部位としては、スルーホールや導電性ペーストで作製されたビアなどが好ましく利用できる。また、配線パターンを加圧などにより変形させて有機フィルムを貫通し、断面形状を略X字形あるいは略U字形にした層間接続部位も好ましく利用できる(図13)。   Moreover, in the semiconductor component mounting body of the present invention, an interlayer connection portion for electrically connecting the wiring patterns may be provided (FIG. 12). As the interlayer connection site, a through hole or a via made of a conductive paste can be preferably used. Further, an interlayer connection portion having a wiring pattern deformed by pressurization or the like and penetrating the organic film and having a cross-sectional shape substantially X-shaped or U-shaped can be preferably used (FIG. 13).

なお、金属突起物としては上述したように、金ワイヤーにより形成される金バンプが最も一般的に利用可能である。また、その他の金属ワイヤーにより形成されたバンプやメッキバンプ、ハンダバンプ、金属粉と樹脂を混合した導電性ペーストにより形成されたバンプなどが利用可能である。   In addition, as above-mentioned as a metal protrusion, the gold bump formed with a gold wire is most generally available. Further, bumps formed by other metal wires, plating bumps, solder bumps, bumps formed by conductive paste in which metal powder and resin are mixed, and the like can be used.

また、半導体部品実装体においても、半導体と基板間にアンダーフィルが設けられていることが好ましく利用できる。この様な構成を取ることでより接続信頼性の高い半導体部品実装体を提供できる。   Also in the semiconductor component mounting body, it is preferable to use an underfill provided between the semiconductor and the substrate. By adopting such a configuration, a semiconductor component mounting body with higher connection reliability can be provided.

なお、本発明の半導体部品実装体においては、電子部品が実装されていてもよく、電子部品としては抵抗やコンデンサ、インダクタなどの受動部品、モジュールなど、その種類や形状は特に問わない。同様に、基板内に電子部品が内蔵されていてもよく、内蔵部品としてはチップ形状やシート状のコンデンサ、抵抗体、インダクタなど、その種類や形状は特に問わない。また、本発明の半導体部品実装体をモジュールと考え、他のマザー基板に実装するなど、その形態は特に問わない。   In the semiconductor component mounting body of the present invention, electronic components may be mounted, and the types and shapes of the electronic components are not particularly limited, such as resistors, capacitors, passive components such as inductors, modules, and the like. Similarly, an electronic component may be built in the substrate, and the type and shape of the built-in component are not particularly limited, such as a chip shape, a sheet-like capacitor, a resistor, and an inductor. Also, the form of the semiconductor component mounting body of the present invention is not particularly limited, such as considering it as a module and mounting it on another mother board.

なお、本発明の半導体部品実装体においては、有機フィルムと樹脂層と配線パターンとからなるフレキシブル基板について説明したが、他の基板にこのフレキシブル基板を貼り付けた状態のものを基板として用いても良く、半導体実装部分がこのフレキシブル基板であれば、その形態は特に問わない。   In addition, in the semiconductor component mounting body of the present invention, the flexible substrate composed of the organic film, the resin layer, and the wiring pattern has been described. However, a substrate in which the flexible substrate is attached to another substrate may be used. If the semiconductor mounting part is this flexible substrate, the form is not particularly limited.

図14には上述の実施の形態を盛り込んだ一例を示す。このような構成により、従来例よりも狭ピッチに対応し、より絶縁信頼性、接続信頼性の向上した半導体部品実装体を提供することができる。   FIG. 14 shows an example incorporating the above-described embodiment. With such a configuration, it is possible to provide a semiconductor component mounting body that can handle a narrower pitch than the conventional example, and that has further improved insulation reliability and connection reliability.

以下、本発明の実施例について説明する。   Examples of the present invention will be described below.

(実施例1)
本実施例では、実施の形態2に記載の半導体部品実装体の製造方法に従い、図2A−Cに示した半導体部品実装体を作製した。部材として、次のものを用いた。シリコン半導体は5x5mm角、100μm厚み、125μmピッチの端子電極が144ピンのペリフェラル配置(36ピンx4辺)のものを用意した。半導体のアクティブ面に略同形状の金属突起物として、画鋲形状の金バンプを形成した。作製方法としては、従来から知られている方法であり、バンプボンダーにより金ワイヤー(直径25μm)に加熱(300℃)及び超音波を加えて半導体のアクティブ面に設けられている電極端子上に画鋲形状バンプを形成した。今回行ったバンプ形成条件はすべてのバンプに対して同条件で行っており、機械誤差によるばらつきはあるものの略同形状のバンプが形成できた。バンプの台座部分の直径は70±5μm、台座高さは20±3μm、台座を含めたバンプの高さは65〜95μmの範囲であった。基板としては、フレキシブル基板の両面板(30x30mm角)を用意し、有機フィルムの厚み4μm、樹脂層の厚み14μm、配線パターンの厚み12μm、半導体実装部分の配線ピッチが250μm、基板厚みが総厚32μm(14μm+4μm+14μm)であった。
Example 1
In this example, the semiconductor component mounting body shown in FIGS. 2A to 2C was manufactured according to the method for manufacturing a semiconductor component mounting body described in the second embodiment. The following were used as members. A silicon semiconductor having a 5 × 5 mm square, 100 μm thickness, and 125 μm pitch terminal electrodes having a 144 pin peripheral arrangement (36 pins × 4 sides) was prepared. A thumbtack-shaped gold bump was formed as a metal protrusion having substantially the same shape on the active surface of the semiconductor. The manufacturing method is a conventionally known method, in which a gold wire (diameter 25 μm) is heated (300 ° C.) and ultrasonic waves are applied to a gold wire (25 μm) by a bump bonder on an electrode terminal provided on the active surface of the semiconductor. Shape bumps were formed. The bump formation conditions performed this time were the same for all bumps, and bumps with almost the same shape could be formed although there were variations due to mechanical errors. The diameter of the base portion of the bump was 70 ± 5 μm, the height of the base was 20 ± 3 μm, and the height of the bump including the base was in the range of 65 to 95 μm. As the substrate, a flexible double-sided board (30 x 30 mm square) is prepared, the organic film thickness is 4 μm, the resin layer thickness is 14 μm, the wiring pattern thickness is 12 μm, the wiring pitch of the semiconductor mounting portion is 250 μm, and the total thickness of the substrate is 32 μm. (14 μm + 4 μm + 14 μm).

このフレキシブル基板に上記半導体をフリップチップ実装した。今回は、実装工法としてNCF工法を用いた。市販のNCFフィルム(5x5mm角、厚み40μm、エポキシ系樹脂+無機フィラー)を用意し、予め基板の半導体実装部分に貼り付けた。半導体実装機を用いて半導体を位置決めし、バンプを押し潰しながら各層へ電気的に接続した。実装条件は加圧30kgf(1バンプあたり約200g)、温度200℃、60秒で行い、半導体を実装するのと同時に、アンダーフィルであるNCFシートを硬化した。   The semiconductor was flip-chip mounted on this flexible substrate. This time, the NCF method was used as the mounting method. A commercially available NCF film (5 × 5 mm square, thickness 40 μm, epoxy resin + inorganic filler) was prepared and pasted on the semiconductor mounting portion of the substrate in advance. The semiconductor was positioned using a semiconductor mounting machine and electrically connected to each layer while crushing the bumps. The mounting conditions were a pressure of 30 kgf (about 200 g per bump), a temperature of 200 ° C. and 60 seconds. At the same time as mounting the semiconductor, the NCF sheet as an underfill was cured.

作製した半導体部品実装体を断面観察し、各バンプの高さ(半導体のアクティブ面から配線パターンまで)を測定したところ表層の配線パターン501に接続されたバンプ(金属突起物201)は平均30μm、裏面の配線パターン502に接続されたバンプ(金属突起物202)は平均50μmであった。   The prepared semiconductor component mounting body was observed in cross section, and the height of each bump (from the active surface of the semiconductor to the wiring pattern) was measured. As a result, the bumps (metal protrusions 201) connected to the wiring pattern 501 on the surface layer had an average of 30 μm Bumps (metal protrusions 202) connected to the wiring pattern 502 on the back surface had an average of 50 μm.

また、半導体部品実装体の初期導通が配線パターンの表層側、裏面側ともに確認され、各層の絶縁信頼性も問題なかった。また、85℃/85%RH(RHは相対湿度)の吸湿試験500時間後においても、その導通、絶縁信頼性ともに不良は確認されず、良好であった。   Moreover, the initial conduction of the semiconductor component mounting body was confirmed on both the surface layer side and the back surface side of the wiring pattern, and there was no problem in the insulation reliability of each layer. Even after a moisture absorption test at 85 ° C./85% RH (RH is relative humidity) for 500 hours, neither conduction nor insulation reliability was confirmed, and it was good.

以上の様に、この本発明の実装方法を用いることで、125μmピッチの半導体を250μmピッチの基板配線パターンを設けた基板に実装することができ、かつ、接続信頼性、絶縁信頼性の良好な半導体部品実装体を得ることができた。   As described above, by using the mounting method of the present invention, a 125 μm pitch semiconductor can be mounted on a substrate provided with a 250 μm pitch substrate wiring pattern, and the connection reliability and insulation reliability are excellent. A semiconductor component mounting body was obtained.

(実施例2)
本実施例では、実施の形態4に記載の半導体部品実装体の製造方法に従い、図5A−Cに示した半導体部品実装体を作製した。
(Example 2)
In this example, the semiconductor component mounting body shown in FIGS. 5A to 5C was manufactured according to the method for manufacturing a semiconductor component mounting body described in the fourth embodiment.

部材として、半導体は実施例1と同じものを用いた。半導体の金属突起物も同様の部材、機械を用いて、実施例1とは異なる作製条件で画鋲形状の金バンプを作製した。バンプの台座部分の直径は65±5μm、台座高さは17±3μm、台座を含めたバンプの高さは85〜110μmの範囲であった。実施例2においてもバンプ形成条件はすべてのバンプに対して同条件で行っており、機械誤差によるばらつきはあるものの略同形状のバンプが形成できた。基板としては、多層フレキシブル基板の(30x30mm角)を用意し、有機フィルム401、402の厚みが4μm、樹脂層301、303の厚み14μm、樹脂層302の厚み28μm、配線パターンの厚み12μm、半導体実装部分の配線ピッチが250μm、基板厚みが総厚64μm(14μm+4μm+28μm+4μm+14μm)である。この多層フレキシブル基板に半導体をNCF実装した。実装条件は加圧を45kgf(1バンプあたり約300g)にした以外は実施例1と同様の条件で行った。   As the member, the same semiconductor as in Example 1 was used. For the semiconductor metal protrusions, thumbtack-shaped gold bumps were produced under the production conditions different from those of Example 1 using the same members and machines. The diameter of the base portion of the bump was 65 ± 5 μm, the height of the base was 17 ± 3 μm, and the height of the bump including the base was in the range of 85-110 μm. In Example 2 as well, bump formation conditions were the same for all bumps, and bumps having substantially the same shape could be formed although there were variations due to mechanical errors. As a substrate, a multilayer flexible substrate (30 × 30 mm square) is prepared, the thickness of the organic films 401 and 402 is 4 μm, the thickness of the resin layers 301 and 303 is 14 μm, the thickness of the resin layer 302 is 28 μm, the thickness of the wiring pattern is 12 μm, and the semiconductor mounting The wiring pitch of the part is 250 μm, and the substrate thickness is 64 μm in total (14 μm + 4 μm + 28 μm + 4 μm + 14 μm). A semiconductor was mounted on the multilayer flexible substrate by NCF. The mounting conditions were the same as in Example 1 except that the pressure was 45 kgf (about 300 g per bump).

作製した半導体部品実装体を断面観察し、各バンプの高さ(半導体のアクティブ面から配線パターンまで)を測定したところ表層の配線パターン501に接続されたバンプ(金属突起物201)は平均20μm、内面の配線パターン502に接続されたバンプ(金属突起物202)は平均40μm、裏面の配線パターン503に接続されたバンプ(金属突起物203)は平均72μmであった。   A cross-section of the produced semiconductor component mounting body was observed, and the height of each bump (from the active surface of the semiconductor to the wiring pattern) was measured. As a result, the bump (metal protrusion 201) connected to the surface wiring pattern 501 had an average of 20 μm. Bumps (metal protrusions 202) connected to the wiring pattern 502 on the inner surface averaged 40 μm, and bumps (metal protrusions 203) connected to the wiring pattern 503 on the back surface averaged 72 μm.

また、半導体部品実装体の初期導通が配線パターンの表層、内層、裏面ともに確認され、各層の絶縁信頼性も問題なかった。また、85℃/85%RHの吸湿試験500時間後においても、その導通、絶縁信頼性ともに不良は確認されず、良好であった。   Further, initial conduction of the semiconductor component mounting body was confirmed on the surface layer, inner layer, and back surface of the wiring pattern, and there was no problem with the insulation reliability of each layer. Further, even after 500 hours of a moisture absorption test at 85 ° C./85% RH, neither conduction nor insulation reliability was confirmed and it was good.

以上の様に、この本発明の実装方法を用いることで、125μmピッチの半導体を250μmピッチの基板配線パターンを設けた基板に実装することができ、かつ、接続信頼性、絶縁信頼性の良好な半導体部品実装体を得ることができた。   As described above, by using the mounting method of the present invention, a 125 μm pitch semiconductor can be mounted on a substrate provided with a 250 μm pitch substrate wiring pattern, and the connection reliability and insulation reliability are excellent. A semiconductor component mounting body was obtained.

なお、ここに示した実施例は一例であって、本発明は以上の実施例に限定されない。   In addition, the Example shown here is an example, Comprising: This invention is not limited to the above Example.

[産業上の利用可能性]
本発明によれば、狭ピッチの半導体が実装可能であり、かつ、絶縁信頼性や接続信頼性の向上した半導体部品実装体及びその製造方法を提供できる。
[Industrial applicability]
ADVANTAGE OF THE INVENTION According to this invention, the semiconductor component mounting body which can mount the semiconductor of a narrow pitch, and the insulation reliability and connection reliability improved, and its manufacturing method can be provided.

A−Cは本発明の実施の形態1における半導体部品実装体の製造方法を示す断面図。FIGS. 8A to 8C are cross-sectional views illustrating a method for manufacturing a semiconductor component mounting body according to the first embodiment of the present invention. FIGS. A−Cは本発明の実施の形態2における半導体部品実装体の製造方法を示す断面図。AC is sectional drawing which shows the manufacturing method of the semiconductor component mounting body in Embodiment 2 of this invention. A−Cは本発明の実施の形態3における半導体部品実装体の製造方法を示す断面図。AC is sectional drawing which shows the manufacturing method of the semiconductor component mounting body in Embodiment 3 of this invention. A−Cは本発明の実施の形態4における半導体部品実装体の製造方法(1)を示す断面図。AC is sectional drawing which shows the manufacturing method (1) of the semiconductor component mounting body in Embodiment 4 of this invention. A−Cは本発明の実施の形態4における半導体部品実装体の製造方法(2)を示す断面図。AC is sectional drawing which shows the manufacturing method (2) of the semiconductor component mounting body in Embodiment 4 of this invention. A−Cは本発明の一実施形態における有機フィルムに金属突起物が貫通する箇所に予め穴を開けておいた場合の製造方法を示す断面図。AC is sectional drawing which shows the manufacturing method when the hole is previously opened in the location where a metal protrusion penetrates the organic film in one Embodiment of this invention. A−Cは本発明の別の一実施形態における基板の同一層内の厚みにばらつきがある場合の利点を示す断面図。AC is sectional drawing which shows an advantage in case the thickness in the same layer of the board | substrate in another one Embodiment of this invention has dispersion | variation. 本発明の実施の形態5における半導体部品実装体の断面図。Sectional drawing of the semiconductor component mounting body in Embodiment 5 of this invention. 本発明の実施の形態6における半導体部品実装体の断面図。Sectional drawing of the semiconductor component mounting body in Embodiment 6 of this invention. 本発明の実施の形態7における半導体部品実装体の断面図。Sectional drawing of the semiconductor component mounting body in Embodiment 7 of this invention. 本発明の一実施形態における金属突起物が接続された配線パターンの形状が略凹形状である半導体部品実装体の断面図。Sectional drawing of the semiconductor component mounting body whose shape of the wiring pattern to which the metal protrusion in one Embodiment of this invention was connected is a substantially concave shape. 本発明の別の実施形態における層間接続部位が設けられている半導体部品実装体の断面図。Sectional drawing of the semiconductor component mounting body in which the interlayer connection site | part in another embodiment of this invention is provided. 本発明の別の実施形態における層間接続部位が略X字形あるいは略U字形である半導体部品実装体の断面図。Sectional drawing of the semiconductor component mounting body whose interlayer connection site | part in another embodiment of this invention is a substantially X shape or a substantially U shape. 本発明の別の実施形態における半導体部品実装体の断面図。Sectional drawing of the semiconductor component mounting body in another embodiment of this invention. 従来の半導体部品実装体の構造を示す一例An example showing the structure of a conventional semiconductor component mounting body

符号の説明Explanation of symbols

101 半導体
200,201,202,203,204 金属突起物
301 樹脂層
401,402,403 有機フィルム
501,502,503,504 配線パターン
601,602 ビア
701,702,703 略凹形状の配線パターン
801 略X形状の層間接続部
901 略U形状の層間接続部
1001 アンダーフィル
1101 スルーホール
1201 絶縁層
1301,1302 有機フィルムに設けられた穴
1401,1402,1403,1404,1405 フレキシブル基板

101 semiconductor
200,201,202,203,204 Metal projection
301 resin layer
401,402,403 Organic film
501,502,503,504 Wiring pattern
601,602 beer
701,702,703 Wiring pattern with substantially concave shape
801 Almost X-shaped interlayer connection
901 Almost U-shaped interlayer connection
1001 Underfill
1101 Through hole
1201 Insulation layer
1301,1302 Holes in the organic film
1401,1402,1403,1404,1405 Flexible substrate

Claims (14)

絶縁層と配線パターンを含む基板に半導体を電気的に接続する実装方法であって、
前記半導体に略同形状の金属突起物を形成し、
前記半導体を前記基板に位置決めして搭載し、
圧力をかけて前記金属突起物を押し潰し、前記金属突起物と前記基板の表面に形成された前記配線パターンとを接続し、
前記金属突起物と前記基板の裏面に形成された前記配線パターンとを接続する工程を含むことを特徴とする半導体部品実装体の製造方法。
A mounting method for electrically connecting a semiconductor to a substrate including an insulating layer and a wiring pattern,
Forming a metal protrusion having substantially the same shape on the semiconductor;
Positioning and mounting the semiconductor on the substrate;
Crushing the metal protrusion by applying pressure, connecting the metal protrusion and the wiring pattern formed on the surface of the substrate;
The manufacturing method of the semiconductor component mounting body characterized by including the process of connecting the said metal protrusion and the said wiring pattern formed in the back surface of the said board | substrate.
前記基板は有機フィルムと、前記有機フィルムの両面に形成された樹脂層と、前記樹脂層に埋め込まれた配線パターンとからなるフレキシブル基板であり、
前記金属突起物と前記基板の裏面に形成された前記配線パターンとを接続する工程において、前記有機フィルムを貫通する請求項1に記載の半導体部品実装体の製造方法。
The substrate is a flexible substrate comprising an organic film, a resin layer formed on both sides of the organic film, and a wiring pattern embedded in the resin layer,
The manufacturing method of the semiconductor component mounting body of Claim 1 which penetrates the said organic film in the process of connecting the said metal protrusion and the said wiring pattern formed in the back surface of the said board | substrate.
絶縁層と配線パターンからなる多層基板に半導体を電気的に接続する実装方法であって、
前記半導体に略同形状の金属突起物を形成し、
前記半導体を前記基板に位置決めして搭載し、
前記半導体の前記金属突起物に圧力をかけて押し潰し、少なくとも前記基板の内層に形成された配線パターンと、前記内層とは異なる層に形成された前記配線パターンに接続させる工程を含むことを特徴とする半導体部品実装体の製造方法。
A mounting method for electrically connecting a semiconductor to a multilayer substrate comprising an insulating layer and a wiring pattern,
Forming a metal protrusion having substantially the same shape on the semiconductor;
Positioning and mounting the semiconductor on the substrate;
Crushing the metal protrusions of the semiconductor by applying pressure to connect the wiring pattern formed at least on the inner layer of the substrate and the wiring pattern formed on a layer different from the inner layer. A method for manufacturing a semiconductor component mounting body.
前記基板は有機フィルムと、前記有機フィルムの両面に形成された樹脂層と、前記樹脂層に埋め込まれた配線パターンを含むフレキシブル基板が複数積層された多層フレキシブル基板であり、
前記半導体の前記金属突起物に圧力をかけて押し潰し、前記基板の内層に形成された前記配線パターンに接続させる工程において、前記有機フィルムを貫通する請求項3に記載の半導体部品実装体の製造方法。
The substrate is a multilayer flexible substrate in which a plurality of flexible substrates including an organic film, a resin layer formed on both surfaces of the organic film, and a wiring pattern embedded in the resin layer are laminated,
4. The manufacturing of a semiconductor component mounting body according to claim 3, wherein in the step of crushing the metal protrusions of the semiconductor by applying pressure to connect to the wiring pattern formed on the inner layer of the substrate, the semiconductor film is penetrated through the organic film. Method.
前記金属突起物が前記有機フィルムを貫通する箇所に予め穴を開けおいたフレキシブル基板を用いる請求項2又は4に記載の半導体部品実装体の製造方法。   The manufacturing method of the semiconductor component mounting body of Claim 2 or 4 using the flexible substrate which opened the hole previously in the location where the said metal protrusion penetrates the said organic film. 前記金属突起物が前記有機フィルムを貫通した際に、前記穴が拡大する請求項5に記載の半導体部品実装体の製造方法。   The manufacturing method of the semiconductor component mounting body according to claim 5, wherein the hole expands when the metal protrusion penetrates the organic film. フレキシブル基板に半導体を、前記半導体に設けられた金属突起物を介して電気的に接続した半導体部品実装体であって、
前記フレキシブル基板は、有機フィルムと、前記有機フィルムの両面に形成された樹脂層と、前記樹脂層に埋め込まれた配線パターンを含み、
前記半導体の前記金属突起物の少なくとも一つは、前記フレキシブル基板の表面に形成された前記配線パターンに接続されており、
かつ、前記半導体の前記金属突起物の少なくとも一つは、前記有機フィルムを貫通し、前記フレキシブル基板の裏面に形成された前記配線パターンに接続されていることを特徴とする半導体部品実装体。
A semiconductor component mounting body in which a semiconductor is electrically connected to a flexible substrate via a metal protrusion provided on the semiconductor,
The flexible substrate includes an organic film, a resin layer formed on both surfaces of the organic film, and a wiring pattern embedded in the resin layer,
At least one of the metal protrusions of the semiconductor is connected to the wiring pattern formed on the surface of the flexible substrate,
In addition, at least one of the metal protrusions of the semiconductor penetrates the organic film and is connected to the wiring pattern formed on the back surface of the flexible substrate.
フレキシブル基板に半導体を、前記半導体に設けられた金属突起物を介して電気的に接続した半導体部品実装体であって、
前記フレキシブル基板は、有機フィルムと、前記有機フィルムの両面に形成された樹脂層と、前記樹脂層に埋め込まれた配線パターンとからなるフレキシブル基板が複数積層された多層フレキシブル基板であり、
前記半導体の前記金属突起物の少なくとも一つは、前記有機フィルムを貫通し、前記フレキシブル基板の内層に形成された前記配線パターンに接続されており、
かつ、前記半導体の前記金属突起物の少なくとも一つは、前記金属突起物が接続した層とは異なる層の配線パターンに接続されていることを特徴とする半導体部品実装体。
A semiconductor component mounting body in which a semiconductor is electrically connected to a flexible substrate via a metal protrusion provided on the semiconductor,
The flexible substrate is a multilayer flexible substrate in which a plurality of flexible substrates composed of an organic film, a resin layer formed on both surfaces of the organic film, and a wiring pattern embedded in the resin layer are laminated,
At least one of the metal protrusions of the semiconductor penetrates the organic film and is connected to the wiring pattern formed in the inner layer of the flexible substrate,
In addition, at least one of the metal protrusions of the semiconductor is connected to a wiring pattern in a layer different from the layer to which the metal protrusions are connected.
前記樹脂層の厚みが前記有機フィルムの厚みより厚い請求項7又は8に記載の半導体部品実装体。   The semiconductor component mounting body according to claim 7 or 8, wherein a thickness of the resin layer is thicker than a thickness of the organic film. 前記有機フィルムの厚みが5μm以下である請求項7〜9のいずれかに記載の半導体部品実装体。   The thickness of the said organic film is 5 micrometers or less, The semiconductor component mounting body in any one of Claims 7-9. 前記金属突起物が接続された前記配線パターンの形状が略凹形状である請求項7又は8に記載の半導体部品実装体。   The semiconductor component mounting body according to claim 7 or 8, wherein a shape of the wiring pattern to which the metal protrusion is connected is a substantially concave shape. 前記金属突起物と前記配線パターンの接続断面積が、前記半導体の実装面側に近い層の前記配線パターンに接続されている方が、遠い層の前記配線パターンに接続されている方より大きい請求項7又8に記載の半導体部品実装体。   The connection cross-sectional area between the metal protrusion and the wiring pattern is larger when the connection to the wiring pattern in the layer near the semiconductor mounting surface is larger than the connection with the wiring pattern in the far layer. Item 9. The semiconductor component package according to Item 7 or 8. 前記フレキシブル基板に設けられている前記配線パターン間を電気的に接続する層間接続部位が設けられている請求項7〜12のいずれかに記載の半導体部品実装体。   The semiconductor component mounting body according to any one of claims 7 to 12, wherein an interlayer connection portion for electrically connecting the wiring patterns provided on the flexible substrate is provided. 前記層間接続部位は、前記配線パターンが前記有機フィルムを貫通し、断面形状が略X字形又は略U字形である請求項13に記載の半導体部品実装体。

The semiconductor component mounting body according to claim 13, wherein the interlayer connection portion has the wiring pattern that penetrates the organic film and has a cross-sectional shape that is substantially X-shaped or substantially U-shaped.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008034562A (en) * 2006-07-27 2008-02-14 Yamaha Corp Method for forming bump for electric connection
US7605075B2 (en) 2004-12-06 2009-10-20 International Business Machines Corporation Multilayer circuit board and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7605075B2 (en) 2004-12-06 2009-10-20 International Business Machines Corporation Multilayer circuit board and method of manufacturing the same
JP2008034562A (en) * 2006-07-27 2008-02-14 Yamaha Corp Method for forming bump for electric connection

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