JP2006105841A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily detect faults other than a leakage current occurring in the short-channel effect in a probe test. <P>SOLUTION: In a standby test before a screening test, a consumption current is measured at each test point, and when the consumption current value exceeds a first consumption current threshold, the semiconductor device is regarded as faulty. As a result of judgment whether the measured consumption current value is within the criterion limits or not, the semiconductor device outside the limits is regarded as faulty. In a standby test after the screening test, as a result of the calculation of the difference between the consumption current measured at each test point and the consumption current measured before the screening test, the semiconductor device of which the difference exceeds a second consumption current threshold is regarded as faulty. Thereafter, as a result of judgment whether the consumption current value measured after the screening test is less than the first consumption current threshold or not, the semiconductor device with a larger consumption current value is regarded as faulty. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to defect detection of a semiconductor device in a probe test.

  In a probe test for inspecting electrical characteristics of a semiconductor device, a so-called standby test is known as an effective test technique for identifying a semiconductor device having a minor defect that cannot be determined as a defective product by a logic test (functional test). .

  In this standby test, for example, when all functions of the semiconductor device are stopped (standby mode), the current consumption of the semiconductor device is measured at a plurality of test points in which the internal logic circuit is fixed in various states, and these measurements are performed. The non-defective product / defective product is determined by determining whether the measured current value is higher or lower than an arbitrary threshold (absolute value determination).

In this type of semiconductor integrated circuit device, a static current test technique includes measuring the power supply current in a static state in the state of two or more logical combinations of the semiconductor integrated circuit device, and determining the maximum value of the power supply current and the power supply The minimum value of current is measured by the current measuring device of the semiconductor integrated circuit device, the difference between the maximum value and the minimum value of the power supply current is calculated, and the difference exceeds a certain value stored in advance in the memory. If the semiconductor integrated circuit device is defective in screening (see Patent Document 1), the logic state of the plurality of elements constituting the semiconductor integrated circuit device is sequentially changed and set, and the quiescent power supply current through the plurality of elements Is measured multiple times, the maximum value and the minimum value are extracted from the measured current values, and the semiconductor integrated circuit device is determined to be defective when the difference exceeds a predetermined difference value. The current value output from the current value output means for outputting the power supply current value given to the semiconductor integrated circuit and the semiconductor integrated circuit is held at an arbitrary point in time, and the current between the current value and the held current value There is one that compares a value difference with a determination reference value and determines the quality of the semiconductor integrated circuit device based on the difference in the power supply current value (see Patent Document 3).
JP 2000-88914 A Japanese Patent Laid-Open No. 2001-21609 JP 2003-84048 A

  However, the present inventors have found that the standby test technology in the semiconductor device as described above has the following problems.

  In recent years, with the miniaturization of semiconductor devices in semiconductor integrated circuit devices, leakage current due to the short channel effect of MOS transistors tends to increase. Since the leakage current due to the short channel effect is greatly affected by the manufacturing variation of the process, when the absolute determination is performed in consideration of the manufacturing variation, the current value serving as a determination criterion becomes large.

  Therefore, it is difficult to determine whether the leakage current is due to the short channel effect or the leakage current, and it is difficult to determine a defective semiconductor device.

  An object of the present invention is to provide a test technique capable of easily detecting a defect other than a leakage current generated due to a short channel effect or the like in a probe test.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the semiconductor device manufacturing method of the present invention, in a standby state in which all functions of the internal logic circuit provided in the semiconductor device are stopped, the test point for changing the fixed state in the node of the internal logic circuit is arbitrarily changed. In the first test process for measuring a plurality of consumption current values and in a standby state in which all the functions of the internal logic circuit are stopped, a plurality of consumption currents are changed while arbitrarily changing the fixed state at the node of the internal logic circuit. A difference between each of the current consumption values measured in the second test step for measuring the value, each of the current consumption values measured in the first test step and each of the current consumption values measured in the second test step, and the calculated current consumption And a step of determining that the semiconductor device is defective when the value is outside the first determination range value.

  The method for manufacturing a semiconductor device according to the present invention includes a third test step for operating at least the semiconductor device at a high temperature / high voltage between the first test step and the second test step. is there.

  Furthermore, in the method for manufacturing a semiconductor device according to the present invention, the first test step is performed when the current consumption value measured at each test point in the first test step is outside the second determination range value. A step of determining a semiconductor device as a defective product, wherein the second test step includes a current consumption value measured at each test point in the second test step outside a second determination range value; And a step of determining the semiconductor device as a defective product.

  In the semiconductor device manufacturing method according to the present invention, the test point of the semiconductor device is at least the first test point at which all nodes are fixed by the internal logic circuit, and the register of the semiconductor device is set to “0” from the start address. A second test point for alternately writing “1”, a third test point for alternately writing “1” and “0” from the start address to the register of the semiconductor device, and “1” from the external port of the semiconductor device And “0” are output alternately, and a fifth test point is output where “0” and “1” are alternately output from the external port of the semiconductor device.

  Furthermore, the semiconductor device manufacturing method according to the present invention supplies the internal operating power supply voltage of the semiconductor device from the outside in the first and second test steps.

  Furthermore, in the method for manufacturing a semiconductor device according to the present invention, the back bias control of the transistor of the semiconductor device is performed in the first and second test steps.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  According to the semiconductor device manufacturing method of the present invention, in a standby state in which all functions of the internal logic circuit provided in the semiconductor device are stopped, the test point for changing the fixed state in the node of the internal logic circuit is arbitrarily changed. However, a test process for measuring a plurality of consumption current values was performed n times, and each consumption current value measured in an arbitrary test process and any test process was performed either before or after the test process. A step of calculating a difference from each current consumption value measured in the test process, and determining the semiconductor device as defective when the calculated current consumption value is outside the first determination range value. is there.

  In addition, the method for manufacturing a semiconductor device according to the present invention includes a third test step in which at least the semiconductor device is operated at a high temperature / high voltage between the arbitrary test steps.

  Furthermore, in the method of manufacturing a semiconductor device according to the present invention, the test process determines that the semiconductor device is defective when the current consumption value measured at each test point in the test process is outside the second determination range value. Having a step of determining.

  In the semiconductor device manufacturing method according to the present invention, the test point of the semiconductor device is at least a first test point at which all nodes are fixed by the internal logic circuit, and a register of the semiconductor device is set to “0” from the start address. The second test point for alternately writing “1” and “1”, the third test point for alternately writing “1” and “0” from the start address to the register of the semiconductor device, and “1” from the external port of the semiconductor device It has a fourth test point where “and“ 0 ”are output alternately, and a fifth test point where“ 0 ”and“ 1 ”are output alternately from the external port of the semiconductor device. .

  Furthermore, the semiconductor device manufacturing method according to the present invention supplies the internal operating power supply voltage of the semiconductor device from the outside in the test step.

  In the semiconductor device manufacturing method according to the present invention, the back bias control of the transistor of the semiconductor device is performed in the n test steps.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) A defective semiconductor device can be easily detected while accurately discriminating from a leakage current due to a single channel effect or the like.

  (2) According to the above (1), the reliability of the semiconductor device can be greatly improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is an explanatory diagram showing a configuration of a semiconductor inspection apparatus according to an embodiment of the present invention, FIG. 2 is a flowchart showing a probe test process by the semiconductor inspection apparatus of FIG. 1, and FIG. 3 is a probe of FIG. FIG. 4 is an explanatory diagram showing an example of an internal logic unit in a semiconductor device to be inspected by the semiconductor inspection device of FIG. 1, and FIG. 5 is a diagram showing standby mode test points and the semiconductor device. FIG. 6 is an explanatory diagram showing an example of coverage of a combination with a node of an internal logic circuit. FIG. 6 is an explanatory diagram showing an example of a current consumption value in a standby test between a non-defective semiconductor device and a defective semiconductor device. FIG. 8 is an explanatory diagram showing an example of increase / decrease in current consumption caused by a defect in a semiconductor device, and FIG. 8 is a flowchart showing an example of a standby test performed after the logic test in FIG. FIG. 9 is a flowchart illustrating an example of a standby test performed after the screening test of FIG. 2 is completed. FIG. 10 is a flowchart illustrating another example of the standby test performed after the logic test of FIG. 11 is a flowchart showing another example of the standby test performed after the screening test of FIG. 2 is completed.

  In the present embodiment, the semiconductor inspection apparatus 1 performs an electrical test of each semiconductor chip by applying a probe needle to an electrode formed on each semiconductor chip in the semiconductor wafer. As shown in the upper part of FIG. 1, the semiconductor inspection apparatus 1 includes a tester 2, a control device 3, and a tester terminal 4.

  The tester 2 connects each electrode of each semiconductor chip formed on the semiconductor wafer and a test circuit to test the semiconductor chip. The control device 3 is composed of, for example, a workstation or a personal computer, and controls all the control in the test system. The control device 3 is provided with a built-in memory 3a, and the built-in memory 3a stores various data such as test programs, test patterns, and variables.

As shown in the lower part of FIG. 1, the tester 2 includes a probe card 2a and a test head 2b. The probe card 2a is a card in which a plurality of conductive probe needles 2a ₁ are arranged in accordance with the arrangement of the electrode portions of the semiconductor chip formed on the semiconductor wafer W. Connect electrically.

  A test head 2b is connected to the probe card 2a. The test head 2b includes a power supply circuit that generates a DC power supply to be applied to a semiconductor chip that is a device under test, a timing generator output, a pattern generator output unit, and an input unit for taking the device output into the measurement unit. The semiconductor chip is evaluated.

  FIG. 2 is a flowchart showing a probe test process performed by the semiconductor inspection apparatus 1.

  First, a logic test is performed on individual semiconductor chips formed on the semiconductor wafer (step S101). When the logic test is completed, a standby test (first test process) is performed (step S102). Subsequently, after performing a screening test (third test process) (step S103), a standby test (second test process) is performed again (step S104). Thereafter, a DC test is performed (step S105), and then a logic test is performed again (step S106).

  The logic test is a test for confirming all functions installed in the semiconductor device. For example, the semiconductor device is determined to be non-defective if the signal state output when the function of the semiconductor device operates does not differ from the ideal value.

  The standby test is a test in which the semiconductor device is set to a standby mode (all functions are stopped) and the current consumption is measured. In the screening test, a semiconductor device is operated at a high temperature and a high voltage.

  The DC test is a test for confirming whether or not the DC characteristics described in the hardware manual can be guaranteed, and is roughly a test other than the standby test such as a consumption current test and a leakage current test.

  Next, the types of standby tests in the processes of steps S102 and S104 will be described.

  As shown in FIG. 3, for example, the type of standby test includes one type of hardware standby and 10 types of software standby.

  Hardware standby is a test point (test point a) mode in which all nodes are fixed by the internal logic circuit of the semiconductor device, and software standby is performed by executing a specific instruction, except for RAM, registers, and ports. This is a test point mode (test points b to k) for fixing all the nodes.

  In software standby, all internal registers write “55” test point (test point b), all internal registers write “AA” test point (test point c), and all external ports set to “55”. Test point (test point d) that outputs, test point (test point e) where all external ports output 'AA', and six test points added so that the coverage described later (FIG. 5) almost converges (Test points f to k).

  FIG. 4 is a diagram illustrating an example of an internal logic unit in the semiconductor device.

  In the semiconductor device, as shown in the figure, a node of each logic circuit LG is determined by a signal input via an external port and an internal register R. That is, there are as many node types as there are combinations of the state of the external input signal and the state of the register R. However, reproducing all combinations of the state of the input signal and the state of the register R is not practical because it requires a large amount of test patterns. Therefore, the number of test points in software standby is determined from the test pattern coverage.

  FIG. 5 is an explanatory diagram showing coverage of combinations of standby mode test points and internal nodes of a semiconductor device.

  As shown in the figure, in the case of this semiconductor device, the coverage converges from 11 test points, and even if the test points are increased, the coverage hardly increases after 12 test points. Therefore, here, the standby test is performed at 11 test points.

  FIG. 5 shows an example of the coverage of a certain semiconductor device, and the test points added so that the coverage shown in FIG. 3 almost converges depend on the number of coverage convergence different for each semiconductor device. Will increase or decrease.

  For example, in the case of a semiconductor device in which coverage converges from 15 test points, there are 11 additional test points. In the case of a semiconductor device in which coverage converges from 8 test points, the additional test points are There will be four.

  The difference between hardware standby and software standby will be described.

  As shown in the figure, the hardware standby is a state in which all nodes of the logic circuit are fixed to “1” (or “0”) by setting the standby terminal provided in the semiconductor device to “0”. . At this time, the bit values stored in all the registers are “1” (or “0”).

  In software standby, the internal node is fixed by setting the standby bit for setting the standby mode provided in the register to “0”. However, unlike the hardware standby, the state of the node of the logic circuit is determined by the set value of the register and the state of the signal input from the outside.

  Further, a test point where the register in software standby shown in FIG. 3 writes '55' (55 write) and a test point where the register writes 'AA' (AA write) will be described. Here, an example is shown in which the register R is composed of, for example, an 8-bit register.

  The 55 write is a state in which “01010101” is written from the top register to the register R composed of an 8-bit register. The AA write is a state in which '10101010' is written from the head register to the register R composed of an 8-bit register.

  The test point at which the external port shown in FIG. 3 outputs '55' (ALL'55 'output) and the test point at which the external port outputs' AA '(ALL'AA' output) will be described. Here, an example in which the external port is an 8-bit port is shown.

  The ALL'55 'output is a state in which a signal of "01010101" is output from the head at the 8-bit port. The ALL′AA ′ output is a state in which a signal “10101010” is output from the head of the 8-bit port.

  FIG. 6 is an explanatory diagram showing current consumption values in a standby test between a non-defective semiconductor device and a defective semiconductor device.

  In FIG. 6, the horizontal axis indicates standby test types (test points a to k), and the vertical axis indicates the current consumption value of the semiconductor device in each standby test type.

  As shown in the figure, in the non-defective semiconductor devices (normal products 1 and 2 in the figure), the current consumption value is substantially constant at each of the test points a to k if they are the same semiconductor device. However, in defective semiconductor devices (defective products 1 and 2), the current consumption value is not substantially constant and the current difference is large depending on the type of standby test (test points g and d).

  An example of an increase in current consumption value in the semiconductor device of the defective product 1 will be described.

  As shown in the upper part of FIG. 7, for example, if two inverters Iv1 and Iv2 are connected in series and there is a leak path to the reference potential VSS between the inverters Iv1 and Iv2, the lower right part of FIG. In addition, when the node of the input part of the inverter Iv1 becomes “0”, a large leak current flows (test point g) and a large leak current flows.

  In the other standby test types, as shown in the lower left part of FIG. 7, “1” is input to the inverter Iv 1, and there is no potential difference from the reference potential VSS. There will be no significant change in value.

  Since the semiconductor devices of the defective products 1 and 2 are both below the absolute determination value, they become samples that do not pose a problem in the absolute determination of determining the non-defective product / defective product based on the standby current value in each semiconductor device. Thus, by performing current relative value determination according to the present embodiment, defective semiconductor devices that cannot be detected by absolute determination can be easily detected.

  Next, the standby test and the current difference determination process in the probe test performed by the semiconductor inspection apparatus 1 in the present embodiment will be described.

  FIG. 8 is a flowchart showing an example of the standby test (the process of FIG. 2, step S102) performed after the logic test is completed.

  First, a standby test is performed using the test points a to k shown in FIG. 3, and current consumption (standby current) at each of the test points a to k is measured (step S201). In the control device 3 of the semiconductor inspection apparatus 1, the current consumption measured at the test points a to k is assigned to the variables A 1 to K 1 and stored in the built-in memory 3 a provided in the control device 3.

  Thereafter, the control device 3 has a current consumption value measured at each of the test points a to k larger than a first current consumption threshold value (for example, about 90 μA) preset in the built-in memory 3a and the like. Whether or not each is determined (step S202).

  In the process of step S202, if there is a consumption current value larger than the first consumption current threshold value among the measured consumption current values, the semiconductor device is determined as a defective product (step S203).

  Subsequently, in the semiconductor device that has become non-defective in the process of step S203, when the measured current consumption value is smaller than the first current consumption threshold value, the consumption measured at each test point a to k. It is determined whether or not the current value is within the determination reference range value (second determination range value) stored in advance in the built-in memory 3a or the like (for example, about ± 5 μA) and is substantially the same (step S204). .

  In the process of step S204, when the current consumption values measured at the respective test points a to k are within the determination reference range value and are approximately the same value, the screening test of the subsequent process (FIG. 2, S103). If the measured current consumption value is not substantially the same outside the determination reference range value, the semiconductor device is determined to be defective (step S205).

  Next, an example of the standby test performed after the screening test is completed will be described with reference to the flowchart of FIG.

  First, similarly to the process of step S201, a standby test is performed using the test points a to k shown in FIG. 3, and current consumption at each of the test points a to k is measured (step S301).

  Similarly in this case, the control device 3 of the semiconductor inspection apparatus 1 substitutes the current consumption measured at the test points a to k into the variables A2 to K2, respectively, and stores them in the built-in memory 3a provided in the control device 3. To do.

  Subsequently, the difference between the current consumption by the test points a to k (variables A2 to K2) measured in the process of step S301 and the current consumption value (variables A1 to K1) by the test points a to k measured in the process of step S201. Is calculated for each of the test points a to k (for example, (variable A2−variable A1) = A3) (step S302), and the calculated consumption current values (A3 to K3) and the built-in memory 3a are stored in advance. The set second consumption current threshold value (first determination range value) is compared (step S303).

  If there is a consumption current value larger than the second consumption current threshold value (for example, about 5 μA) among the calculated consumption current values, the semiconductor device is determined as a defective product (step S304).

  Further, in the semiconductor device that has become non-defective in the process of step S304, when all the calculated current consumption values are smaller than the second consumption current threshold value, the consumption current value measured in step S301 is the first. It is determined whether or not the current consumption threshold is smaller than (step S305).

  If there is a current consumption value larger than the first current consumption threshold value among the current consumption values measured at the respective test points a to k, the semiconductor device is determined as a defective product (step S306).

  When the current consumption values measured at the test points a to k are smaller than the second current consumption threshold value, the current consumption values (A2 to A2) measured at the respective test points a to k measured in step S301. K2) is within a judgment reference range value (for example, about ± 5 μA), and it is determined whether or not the values are approximately the same (step S307). (FIG. 2, step 105) is executed, and if the degree is not the same, the semiconductor device is determined to be defective (step S308).

  Further, in the standby test shown in FIGS. 8 and 9, the internal operation power supply voltage of the semiconductor device may be supplied from the outside through an external port such as a power supply circuit external capacitor terminal.

  As a result, the internal operating power supply voltage in the semiconductor device is stabilized, so that more accurate current consumption can be measured in the standby test.

  Here, the first consumption current threshold value, the second consumption current threshold value, and the determination reference range value are examples, and these values increase and decrease for each type of semiconductor device.

  In addition, other processing examples in the standby test (FIG. 2, step S102) performed after completion of the logic test and the standby test performed after completion of the screening test (FIG. 2, step S103) are illustrated in FIG. Each will be described with reference to the flowchart of FIG.

  First, in FIG. 10, a standby test is performed at the test points a to k shown in FIG. 3, and current consumption at each of the test points a to k is measured (step S401). The control device 3 assigns the current consumption measured at the test points a to k to the variables A1 to K1, and stores them in the built-in memory 3a.

  Thereafter, the control device 3 determines whether or not the current consumption values measured at the respective test points a to k are larger than a preset first current consumption threshold value (step S402).

  In the process of step S402, if there is a consumption current value larger than the first consumption current threshold value among the measured consumption current values, the semiconductor device is determined to be defective (step S403), and all measurements are performed. If the measured current consumption value is smaller than the first current consumption threshold value, it is determined whether or not the current consumption values measured at the respective test points a to k are substantially the same (step S404). ).

  In the process of step S404, if the current consumption values measured at the respective test points a to k are substantially the same value, a screening test (process of FIG. 2, S103) in the subsequent process is performed and the measured consumption is measured. If the current values are not substantially the same, the semiconductor device is determined as a defective product (step S205).

  Next, in the standby test performed after the screening test is completed, as shown in FIG. 11, the standby test is performed by the test points a to k shown in FIG. Current consumption at a to k is measured (step S501).

  Similarly, in the control device 3 of the semiconductor inspection apparatus 1, the current consumption measured at the test points a to k is substituted for the variables A 2 to K 2 and stored in the built-in memory 3 a provided in the control device 3. The

  Subsequently, the difference between the current consumption by the test points a to k (variables A2 to K2) measured in the process of step S501 and the current consumption value (variables A1 to K1) by the test points a to k measured in the process of step S201. Is calculated for each of the test points a to k (for example, (variable A2−variable A1) = A3) (step S502), and whether the calculated current consumption values (A3 to K3) are approximately the same. Whether or not is compared (step S503). If the calculated current consumption values are not substantially the same, the semiconductor device is determined as a defective product (step S504).

  If the calculated current consumption values are approximately the same, it is determined whether or not the current consumption value measured in step S501 is smaller than the first current consumption threshold value (step S505). If there is a current consumption value that is larger than the first current consumption threshold value among the current consumption values measured at the respective test points a to k, the semiconductor device is determined to be defective (step S506).

  In the semiconductor device that has become non-defective in the process of step S506, when the current consumption value measured at the test points a to k is smaller than the first current consumption threshold value, the test point a measured in the process of step S401. Are compared with the power consumption of the test points a to k measured in step S501 (steps S507 to S517).

  In the processes in steps S507 to S517, if the compared current consumption values are not the same, the semiconductor device is determined to be defective (step S518).

  Thus, according to the present embodiment, it is possible to easily determine the leakage current of the semiconductor device due to a single channel effect or the like, and it is possible to easily determine a defect that could not be selected in the logic test. Can do.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the standby test is performed before and after the screening test has been described. However, the standby test may be performed in a plurality of standby tests of two or more times in an arbitrary process. It may be.

  The method for manufacturing a semiconductor device according to the present invention is suitable for a defect determination technique for a semiconductor device in a probe test.

It is explanatory drawing which shows the structure of the semiconductor inspection apparatus by one embodiment of this invention. 2 is a flowchart showing a probe test process by the semiconductor inspection apparatus of FIG. 1. It is explanatory drawing of the standby test shown to the probe test of FIG. FIG. 2 is an explanatory diagram showing an example of an internal logic unit in a semiconductor device inspected by the semiconductor inspection device of FIG. 1. It is explanatory drawing which showed an example of the coverage of the combination of the test point of a standby mode, and the node of the internal logic circuit of a semiconductor device. It is explanatory drawing which showed an example of the consumption current value in the standby test of a non-defective semiconductor device and a defective semiconductor device. It is explanatory drawing which shows the example of increase / decrease in the consumption current which generate | occur | produces by the defect of a semiconductor device. It is a flowchart which shows an example of the standby test implemented after completion | finish of the logic test of FIG. It is a flowchart which shows an example of the standby test implemented after completion | finish of the screening test of FIG. 5 is a flowchart showing another example of a standby test performed after the logic test of FIG. 2 is completed. It is a flowchart which shows the other example of the standby test implemented after completion | finish of the screening test of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor inspection apparatus 2 Tester 2a Probe card 2a ₁ Probe needle 2b Test head 3 Control apparatus 3a Built-in memory 4 Tester terminal W Semiconductor wafer

Claims (12)

In a standby state where all functions of the internal logic circuit provided in the semiconductor device are stopped, a plurality of consumption current values are measured while arbitrarily changing the test point for changing the fixed state in the node of the internal logic circuit. 1 test process,
A second test step of measuring a plurality of consumption current values while arbitrarily changing a fixed state at a node of the internal logic circuit in a standby state in which all the functions of the internal logic circuit are stopped;
A difference between each consumption current value measured in the first test step and each consumption current value measured in the second test step is calculated, and the calculated consumption current value is a first determination range value. And a step of determining that the semiconductor device is defective when outside. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, comprising: a third test step for operating at least the semiconductor device at a high temperature / high voltage between the first test step and the second test step. In the manufacturing method of the semiconductor device of Claim 1 or 2,
The first test step includes a step of determining the semiconductor device as a defective product when a current consumption value measured at each test point in the first test step is outside a second determination range value. And
The second test step includes a step of determining the semiconductor device as a defective product when a current consumption value measured at each test point in the second test step is outside a second determination range value. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device of any one of Claims 1-3,
The test point of the semiconductor device is at least a first test point at which all nodes are fixed by the internal logic circuit, and a first test point in which “0” and “1” are alternately written from the start address to the register of the semiconductor device. 2 test points, a third test point that alternately writes “1” and “0” from the start address to the register of the semiconductor device, and “1” and “0” alternately from the external port of the semiconductor device And a fifth test point in which “0” and “1” are alternately output from an external port of the semiconductor device, and a method of manufacturing a semiconductor device, comprising: . In the manufacturing method of the semiconductor device given in any 1 paragraph of Claims 1-4,
In the first and second test steps, an internal operating power supply voltage of the semiconductor device is supplied from the outside. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
In the semiconductor device manufacturing method, the first and second test steps perform back bias control of the transistor of the semiconductor device. A test that measures a plurality of current consumption values while arbitrarily changing a test point for changing a fixed state in a node of the internal logic circuit in a standby state in which all functions of the internal logic circuit provided in the semiconductor device are stopped A test process of performing n times,
Calculate the difference between each current consumption value measured in any of the test processes and each current consumption value measured in the test process performed in either the pre-process or the post-process of the optional test process. A method of manufacturing a semiconductor device, comprising: a determination step of determining that the semiconductor device is defective when the calculated current consumption value is outside a first determination range value. The method of manufacturing a semiconductor device according to claim 7.
A method for manufacturing a semiconductor device, comprising: a third test step for operating at least the semiconductor device at a high temperature / high voltage between the arbitrary test steps. In the manufacturing method of the semiconductor device according to claim 7 or 8,
The test step includes a step of determining the semiconductor device as a defective product when a current consumption value measured at each test point in the test step is outside a second determination range value. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device of any one of Claims 7-9,
The test point of the semiconductor device is at least a first test point at which all nodes are fixed by the internal logic circuit, and a first test point in which “0” and “1” are alternately written from the start address to the register of the semiconductor device. 2 test points, a third test point that alternately writes “1” and “0” from the start address to the register of the semiconductor device, and “1” and “0” alternately from the external port of the semiconductor device And a fifth test point in which “0” and “1” are alternately output from an external port of the semiconductor device, and a method of manufacturing a semiconductor device, comprising: . In the manufacturing method of the semiconductor device of any one of Claims 7-10,
The method of manufacturing a semiconductor device, wherein the test step supplies an internal operating power supply voltage of the semiconductor device from the outside. In the manufacturing method of the semiconductor device of any one of Claims 7-11,
The method of manufacturing a semiconductor device, wherein the n test steps include back bias control of a transistor of the semiconductor device.

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