JP2006181742A - Driving circuit, led array driving circuit, wiring substrate for driving circuit, printing head and printing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit capable of improving reliability by transmitting a differential clock signal under a good signal transmitting condition, and attempting to reduce a cost by reducing a scale of a circuit. <P>SOLUTION: An LED head in a printing apparatus connects a plurality of driving IC DRV supplying a driving electric current to an LED element constituting an LED array chip CHP in a cascade, and transmits printing data to each driving IC DRV based on the differential clock signals HD-CLK-P and HD-CLK-N. On this instance, each driving IC DRV transmits printing data on both rising-up edge and falling-down edge of the inputted differential clock signals HD-CLK-P and HD-CLK-N. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a driving circuit for connecting a plurality of driving ICs for supplying a driving current to recording elements constituting an array in a cascade and transferring print data to each driving IC based on a differential clock signal, and The present invention relates to an LED array driving circuit in which a recording element in the driving circuit is an LED element. The present invention also relates to a drive circuit wiring board on which the drive circuit is mounted, a print head including the drive circuit, and a printing apparatus including the print head.

  In a conventional electrophotographic recording system printing apparatus, an electrostatic latent image is formed by selectively irradiating a charged photosensitive drum according to print information, and then toner is attached to the electrostatic latent image. Then, development is performed to form a toner image, and the toner image is transferred and fixed on a sheet as a recording medium, thereby forming an image on the sheet.

  As such a printing apparatus, one using a light emitting diode (hereinafter referred to as an LED) as a light source for irradiating a photosensitive drum with light for exposure is known. An LED head used in such a printing apparatus includes an LED array chip in which a plurality of LED elements are arranged, and a drive circuit for driving each LED array chip. The driving circuit includes a plurality of driving ICs (Integrated Circuits) each having a shift register. In the drive circuit, the input / output of the shift register of each drive IC is cascade-connected to the adjacent drive IC, and a common clock signal is supplied to these shift registers, whereby print data is serially transferred to each drive IC. .

  In addition, LED heads that use high-speed data transfer using a differential clock signal as a clock signal for driving the shift register of each drive IC have been proposed.

In order to supply such a differential clock signal, the two signal lines provided on the substrate on which the LED array chip and the driving IC are mounted are reduced in noise by avoiding wiring portions for other driving ICs. For example, there is an example of a wiring configuration as shown in FIG. 45 in order to minimize the influence of the above and to suppress the wiring length of the entire signal line. That is, in this LED head, a plurality of LED array chips CHP ₁ , CHP ₂ , CHP ₃ ,... Are printed, as shown in the plan view in FIG. A plurality of drive ICs DRV ₁ , DRV ₂ , DRV ₃ that drive the LED array chips CHP ₁ , CHP ₂ , CHP ₃ ,... By inputting / outputting data signals HD-DATA 3,. ,... Are arranged in a row on the substrate 2000, and two signal lines for supplying clock signals HD-CLK-P and HD-CLK-N are connected to driving ICs DRV ₁ , DRV ₂ , DRV _3. ..,... Meandering to form a crank shape, narrowing the width while avoiding wiring portions for other drive ICs and suppressing the wiring length of the entire signal lines.

  In addition, as an LED head, the input terminals of the differential clock signal at the odd and even stages of the driving IC can be inverted and input, and the clock signal is inverted to match the polarity of the input differential clock. There is also an example in which a possible circuit is provided in a driving IC (for example, see Patent Document 1).

Japanese Patent Laid-Open No. 2001-199096

  Specifically, the internal configuration of the LED head is as shown in FIG. Here, an LED head that can print on A4 size paper with a resolution of 600 dots per inch is illustrated.

That is, the LED head 26 of the LED array chip _{CHP 1,} CHP 2, · · ·, a _{CHP 26,} 26 for driving each of these LED array chip _{CHP 1, CHP 2, ···,} CHP 26 drive _{IC DRV 1, DRV 2, ···} , DRV 26 and is configured to be arranged in a predetermined printed circuit board so that each faces. In this LED head, each drive IC DRV ₁ , DRV ₂ ,..., DRV ₂₆ configured by the same circuit is cascade-connected to the adjacent drive IC, and the print data signal HD-DATA input from the outside is serialized. Can be transferred to. Further, in this LED head, four data lines are provided to input four lines of print data signals HD-DATA3,..., HD-DATA0, and based on the one-pulse clock signal HD-CLK. It is possible to transfer data for four adjacent pixels at a time.

Each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ is a clock that converts the clock signals HD-CLK-P and HD-CLK-N made up of differential signals into single-ended signals used inside the driving IC. An input circuit 2001, an exclusive OR circuit 2002 for setting the logic of a signal output from the clock input circuit 2001, and printing in synchronization with the clock signal output from the exclusive OR circuit 2002 A shift register circuit 2003 that performs shift transfer of the data signals HD-DATA3,..., HD-DATA0, a latch circuit 2004 that holds the output signal of the shift register circuit 2003 based on the latch signal HD-LOAD, and negative logic A strobe signal that is a signal (hereinafter referred to as a print drive signal HD-STB-N) is input. Inverter circuit 2005, logical product circuit 2006 that takes the logical product of the output signal of latch circuit 2004 and the output signal of inverter circuit 2005, and power supplied from a predetermined power supply VDD based on the output signal of logical product circuit 2006 An LED drive circuit 2007 that supplies a drive current based on power to the LED element, and a control voltage generation circuit 2008 that gives a command voltage to the LED drive circuit 2007 so that the drive current is constant.

In such drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ , the shift register circuit 2003 is composed of 48 × 4 sets = 192 flip-flop circuits, and the print data signal HD-DATA 3,. , HD-DATA0 are shifted in synchronization with the differential clock signals HD-CLK-P and HD-CLK-N, and a print data signal for 192 dots is transferred by clock input of 24 pulses.

Further, in the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ , the exclusive OR circuit 2002 has one input terminal connected to the output of the clock input circuit 2001 and the other input terminal connected to the other. The select terminal is connected to a pull-up resistor (not shown). This select terminal is opened in the odd-numbered drive ICs connected in cascade, and is connected to the ground in the even-numbered drive ICs.

In the LED head including such driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ , the differential clock signals HD-CLK-P and HD-CLK-N are placed on the printed wiring board in the LED head. It is transmitted through a transmission line having a transmission characteristic of the formed differential characteristic impedance Z _0. This end of the transmission line, the terminating resistor 2010 is equal resistance to the differential characteristic impedance Z ₀ is connected.

Thereby, in the LED head, the transmission of the differential clock signals HD-CLK-P and HD-CLK-N in the printed wiring board is configured to be non-reflective terminated by the terminating resistor 2010. _{IC DRV 1, DRV 2, ···} , differential clock signal HD-CLK-P inputted to _{DRV 26,} between the HD-CLK-N, although very small delay due to signal propagation occurs, the respective Signal transmission can be performed without causing a difference in the transmission waveform between the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ . In other words, in the LED head, the exclusive OR circuit 2002 inverts and connects the input terminals of the differential clock signals at the odd-numbered stage and the even-numbered stage of the drive IC. Even if there is a difference in the terminal impedance of DRV ₁ , DRV ₂ ,..., DRV ₂₆ , the load impedance to the positive and negative clock signals will not be biased. It is possible to prevent disturbance of signal waveforms of CLK-P and HD-CLK-N.

By the way, in the conventional LED head described in Patent Document 1 described above, in order to reduce the influence of noise on the printed wiring board, as described above, each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ are supplied, but the signal lines for transmitting these differential clock signals HD-CLK-P and HD-CLK-N are connected to the cascaded drive ICs DRV ₁ , DRV _2. ,..., DRV ₂₆ are arranged across four signal lines for transmitting print data signals HD-DATA3,..., HD-DATA0.

Therefore, in the conventional LED head, in order to obtain a good signal transmission state, the drive _{IC DRV 1, DRV 2, ···} , differential for each _{DRV 26} clock signal HD-CLK-P, HD- CLK-N Therefore, in order to match the polarities of the input differential clocks, the exclusive OR circuit 2002 in which one input terminal is a select terminal is used. and inverts the logic of the clock signal in the odd-numbered stages and the even-numbered stage cascaded driver _{IC DRV 1, DRV 2, ···} , DRV 26 Te.

Thus, in the conventional LED head, necessary to provide a circuit for inverting the logic of the clock signal cascaded driver _{IC DRV 1, DRV 2, ···} , odd of _{DRV 26} and the even-numbered stage in In these drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ , a select terminal for instructing that it is an odd-numbered stage or an even-numbered stage and a bonding for setting the logic level of the select terminal Wire was needed.

Therefore, in the conventional LED head, driving IC _DRV 1 by providing such a select _terminal, DRV 2, · · ·, the occupation of chip area of _{DRV 26,} and lead to increased costs, also, the bonding wire There was a problem that the assembly and mounting cost for laying was also increased.

  The present invention has been made in view of such circumstances, and can improve the reliability by transmitting a differential clock signal under a good signal transmission state and reduce the circuit scale. An object is to provide a drive circuit and an LED array drive circuit capable of reducing costs, a drive circuit wiring board on which the drive circuit is mounted, a print head including the drive circuit, and a printing apparatus including the print head. And

  A drive circuit according to the present invention that achieves the above-described object is configured to connect a plurality of drive ICs that supply drive current to recording elements constituting an array to a cascade, and to print data based on a differential clock signal. In the drive circuit for transferring data to each drive IC, the drive IC transfers the print data both at the rising edge and the falling edge of the input differential clock signal.

  In such a drive circuit according to the present invention, even if the connection between the differential clock signal and the clock input terminal of the drive IC is switched between adjacent drive ICs, the rising edge and the falling edge of the differential clock signal are switched. Since the print data is transferred by both, the operation can be performed without any trouble. Therefore, in the drive circuit according to the present invention, the differential clock signal lines can be arranged on the same surface without crossing on the printed circuit board, and the differential clock is provided for each adjacent drive IC on the circuit diagram. Even though the signal lines cross each other alternately, the difference in operation timing due to the signal lines does not appear, and it is not necessary to provide a circuit for correcting the influence of the crossing of the differential clock signal lines for each driving IC.

  Further, in the drive circuit according to the present invention, since it is not necessary to provide a select terminal that has been unavoidable in the past, the wiring area on the printed wiring board can be reduced and the number of bonding wires can also be reduced. Therefore, it is possible to reduce the size of the printed wiring board and to reduce the cost accordingly.

  Furthermore, in the drive circuit according to the present invention, the frequency of the differential clock signal can be substantially reduced to ½ times that of the prior art, so that the influence of electromagnetic radiation can also be suppressed.

  Specifically, in the drive circuit according to the present invention, the signal line for transmitting one of the differential clock signals is connected to the first clock input terminal and the even-numbered stage of the odd-numbered stage drive ICs connected in cascade. A signal line that is connected to the second clock input terminal of the driving IC and transmits the other of the differential clock signals is connected to the second clock input terminal of the odd-numbered driving IC connected in cascade and an even number. It is connected to the first clock input terminal of the stage driving IC.

  As a result, in the drive circuit according to the present invention, even if the capacitances at the two clock input terminals are slightly different due to variations in design or manufacture of the drive IC, Since the same number of clock input terminals are connected, the difference in load capacitance between the differential clock signal lines is averaged and becomes substantially negligible. Therefore, in the drive circuit according to the present invention, it is possible to avoid a situation in which the operating frequency cannot be increased due to a difference in rising time or falling time between the differential clock signals. Quality can be improved and reliability at the time of data transfer can be improved.

  Here, each of the driving ICs captures and outputs an input logical value when the input differential clock signal is at a low level, while the differential clock signal is at a high level. In addition, when the input differential clock signal is at a high level, the first latch element that continues to hold the logical value that was output immediately before, and the input logical value is captured and output, When the differential clock signal is at a low level, a second latch element that continues to hold the logical value that was output immediately before, and when the differential clock signal is at a high level, the first latch A selector circuit that outputs a logical value output from the second latch element when the differential clock signal is at a low level while outputting a logical value output from the element. It can be configured as.

  In the driving circuit according to the present invention, terminations having a resistance value substantially equal to a characteristic impedance of a signal line for transmitting the print data at the signal transmission end of the print data and the signal reception end of the drive circuit. A resistor is preferably connected.

  As a result, in the drive circuit according to the present invention, the waveform shape changes so that the logic of the print data is reflected at the input portion of the drive circuit and the logic determination becomes difficult, or the print data is multiplexed with the output source of the print data. It can be prevented that it takes a long time to converge by repeating signal reflection. In the driving circuit according to the present invention, the input print data can be remarkably reduced in amplitude, and EMI noise can be reduced. Furthermore, in the drive circuit according to the present invention, assuming that the slope of the rising waveform and falling waveform of the input print data is constant, the waveform rise time and fall time can be shortened by reducing the amplitude. Since it can also be achieved, the amount of data that can be transmitted within the same time can be remarkably increased, and the printing speed can be increased.

  The drive circuit according to the present invention includes a comparator circuit that converts the potential of the print data into a voltage value corresponding to the signal level of the drive IC based on a predetermined reference voltage value. The comparator circuit can be provided in each of the plurality of driving ICs. As a result, in the drive circuit according to the present invention, it is not necessary to externally attach a comparator circuit to the input of print data in the first-stage drive IC, the size of the drive circuit can be further reduced, and the cost can be further reduced. Can be achieved. In this case, the comparator circuit provided in the first-stage driving IC among the plurality of driving ICs converts the potential of the print data based on the first reference voltage value, and 2 out of the plurality of driving ICs. The comparator circuit provided in the driver ICs after the stage converts the potential of the print data based on the second reference voltage value.

  Furthermore, in the drive circuit according to the present invention, a termination resistor having a resistance value substantially equal to the characteristic impedance of the signal line is connected to the end of the signal line commonly connected to each of the drive ICs. Is desirable. As a result, in the drive circuit according to the present invention, a phenomenon in which the malfunction of the drive IC due to the fact that a waveform that should originally have only one edge is recognized as having two edges is prevented. be able to. Further, in the drive circuit according to the present invention, it is not necessary to sufficiently dull the signal input waveform, so that the signal transition time can be shortened and the pulse width can be increased, and excellent data transmission reliability can be achieved. It can be provided, and high-speed operation can be performed.

  In the driving circuit according to the present invention, a terminal resistor having a resistance value substantially equal to the differential characteristic impedance of the signal line may be connected to the end of the signal line that transmits the differential clock signal. .

  Furthermore, in the driving circuit according to the present invention, the driving IC generates a two-phase clock signal composed of a first clock signal and a second clock signal that do not overlap each other for each input of the differential clock signal. And a flip-flop circuit to which the two-phase clock signal output from the phase conversion circuit is input. In this case, the flip-flop circuit has two data transmission paths, the inputs of the two data transmission paths are connected to each other, and the outputs of the two data transmission paths are connected to each other. It will be connected.

  The flip-flop circuit includes a first transmission gate that operates on the first data transmission path of the two systems of data transmission paths based on the second clock signal, and the first transmission gate. A first inverter that receives an output; and a second transmission gate that operates based on the first clock signal when the output of the first inverter is input. Of these, a third transmission gate that operates on the second data transmission path based on the first clock signal, a second inverter that receives the output of the third transmission gate, and the second inverter And a fourth transmission gate that operates based on the second clock signal. It can be constructed as provided.

  The flip-flop circuit includes a first clocked CMOS inverter that operates on the first data transmission path of the two systems of data transmission paths based on the second clock signal, and the first clock. A second clocked CMOS inverter that receives the output of the CMOS inverter and operates based on the first clock signal, and the second data transmission path of the two data transmission paths includes the second data transmission path. A third clocked CMOS inverter that operates based on the first clock signal, and a fourth clocked CMOS inverter that operates based on the second clock signal by receiving the output of the third clocked CMOS inverter It can also comprise as what provides.

  Thus, in the drive circuit according to the present invention, it is possible to further reduce the chip size of the drive IC by having a flip-flop circuit composed of a transmission gate and an inverter and a flip-flop circuit composed of a clocked CMOS inverter. Further cost reduction can be achieved.

  In the drive circuit according to the present invention, the phase conversion circuit includes a transmission gate to which the differential clock signal is input, an inverter to which the differential clock signal is input, and an output from the inverter. 1 negative-OR circuit, a second negative-OR circuit to which the output of the transmission gate is input, and an output of the first negative-OR circuit to which the first of the two-phase clock signals is input A first buffer circuit that outputs a clock signal; and a second buffer circuit that receives the output of the second NOR circuit and outputs a second clock signal of the two-phase clock signals. The first NOR circuit is supplied with the output of the inverter and the second clock signal output from the second buffer circuit, and the second NOT signal. The OR circuit can be configured as the first clock signal output and an output of the transmission gate from said first buffer circuit and are input.

  In the drive circuit according to the present invention, the delay time by the inverter and the delay time by the transmission gate can be set to the same level by using the phase conversion circuit having such a configuration. Therefore, in the drive circuit according to the present invention, the circuit operation can be speeded up.

  Furthermore, in the drive circuit according to the present invention, the phase conversion circuit includes a transmission gate to which the differential clock signal is input, an inverter to which the differential clock signal is input, and an output from the inverter. 1 negative-OR circuit, a second negative-OR circuit to which the output of the transmission gate is input, and an output of the first negative-OR circuit to which the first of the two-phase clock signals is input A first buffer circuit that outputs a clock signal; a second buffer circuit that receives the output of the second NOR circuit and outputs a second clock signal of the two-phase clock signals; and A circuit for generating a first complement signal for the first clock signal output from one buffer circuit, and an output from the second buffer circuit Generating a second complement signal for the second clock signal, and delaying the output of the inverter and the second complement signal in the first NOR circuit The second negative OR circuit may be configured to receive an output of the transmission gate and a signal obtained by delaying the first complement signal. it can.

  In the drive circuit according to the present invention, by using a phase conversion circuit having such a configuration, it is possible to avoid data skipping in the flip-flop circuit. Therefore, in the driving circuit according to the present invention, it is not necessary to set an excessive timing margin in the pause time between the two-phase clock signals, and the operating frequency can be easily increased.

  Furthermore, in the driving circuit according to the present invention, the flip-flop circuit includes a first MOS transistor that operates on a first data transmission path of the two systems of data transmission paths based on the second clock signal. And a first inverter that receives the output of the first MOS transistor, and a second MOS transistor that receives the output of the first inverter and operates based on the first clock signal. A second MOS transmission transistor that operates based on the first clock signal and an output of the third MOS transistor are input to a second data transmission path of the two data transmission paths. Inverter and a fourth MOS transistor that receives the output of the second inverter and operates based on the second clock signal It can be constructed as provided.

  Thereby, in the drive circuit according to the present invention, the number of elements constituting the flip-flop circuit can be reduced, the chip size of the drive IC can be further reduced, and the cost can be further reduced.

  In the driving circuit according to the present invention, the flip-flop circuit includes an output of the second MOS transistor in the first data transmission path and an output of the fourth MOS transistor in the second data transmission path. When a third inverter to which a signal after connection is input is provided, the drive circuit has input potentials of each of the first inverter, the second inverter, and the third inverter. There may be provided means for pulling down or pulling up.

  As a result, in the drive circuit according to the present invention, since no through current is generated in the flip-flop, it may interfere with detection of a short circuit or an open state caused by a defect in a semiconductor manufacturing process when performing an IDDq test. Can be reliably eliminated.

  Further, the LED array driving circuit according to the present invention for achieving the above-described object has a plurality of driving ICs for supplying a driving current to the LED elements constituting the LED array connected to the cascade, and based on the differential clock signal. In the LED array drive circuit for transferring print data to each drive IC, the drive IC transfers the print data at both the rising edge and the falling edge of the input differential clock signal. It is characterized by doing.

  Furthermore, a wiring board for a driving circuit according to the present invention that achieves the above-described object comprises a cascade connecting a recording element constituting an array and a plurality of driving ICs for supplying a driving current to the recording element. And a driving circuit for transferring print data to each driving IC based on a clock signal, and the driving IC has both a rising edge and a falling edge of the input differential clock signal. The print data is transferred.

  Furthermore, a print head according to the present invention that achieves the above-described object includes a recording element that constitutes an array and a plurality of driving ICs that supply a driving current to the recording element are connected to a cascade, and a differential clock signal is provided. And a substrate on which the recording element and the drive circuit are mounted, each of the drive ICs receiving the differential clock signal input thereto. The print data is transferred at both the rising edge and the falling edge.

  Further, the printing apparatus according to the present invention that achieves the above-described object includes a recording element that constitutes an array and a plurality of driving ICs that supply a driving current to the recording element are connected to a cascade to generate a differential clock signal. Based on this, a print head having a drive circuit for transferring print data to each drive IC, a recording head and a substrate on which the drive circuit is mounted, and image formation on a predetermined recording medium using the print head. And an image forming unit that performs the transfer of the print data on both the rising edge and the falling edge of the input differential clock signal.

  In such an LED array drive circuit, drive circuit wiring board, print head, and printing apparatus according to the present invention, the connection between the differential clock signal and the clock input terminal of the drive IC is between adjacent drive ICs. Even if they are switched, the print data is transferred at both the rising edge and the falling edge of the differential clock signal, so that the operation can be performed without any trouble. Therefore, in the LED array drive circuit, the drive circuit wiring board, the print head, and the printing apparatus according to the present invention, the differential clock signal lines can be arranged on the same surface on the printed wiring board without crossing each other. In spite of the differential clock signal lines alternately crossing each adjacent driving IC on the circuit diagram, the difference in the operation timing due to the crossing of the differential clock signal lines does not surface. There is no need to provide a circuit for correcting the influence of the above.

  In addition, in the LED array drive circuit, the drive circuit wiring board, the print head, and the printing apparatus according to the present invention, it is not necessary to provide a select terminal that has been unavoidable in the past. The area can be reduced, the number of bonding wires can be reduced, the printed wiring board can be reduced in size, and the cost can be reduced accordingly.

  Further, in the LED array driving circuit, the driving circuit wiring board, the print head, and the printing apparatus according to the present invention, the frequency of the differential clock signal may be substantially reduced to ½ times compared to the conventional case. Since it can do, the influence of electromagnetic radiation can also be suppressed.

  In the present invention, the differential clock signal is brought into a good signal transmission state by transferring the print data at both the rising edge and the falling edge of the differential clock signal input to each driving IC. The transmission can improve the reliability, and the circuit scale can be reduced to reduce the cost.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  In this embodiment, charging and exposure of a photosensitive drum as an electrostatic latent image carrier, development of the electrostatic latent image formed on the photosensitive drum with toner, and onto the recording medium of the obtained toner image The electrophotographic recording type printing apparatus performs image formation through a process such as transfer of toner and fixing of a toner image on the recording medium. In the following description, for convenience of explanation, a printing apparatus including a row of a plurality of light emitting diodes (hereinafter referred to as LEDs) as a light source (recording element) for irradiating the photosensitive drum with light for exposure. The case where the present invention is applied using these LED elements as driven elements will be described.

  First, a printing apparatus shown as the first embodiment of the present invention will be described.

  The printing apparatus includes a control circuit as shown in FIG. That is, the printing apparatus includes a print control unit 1 that controls the printing apparatus in an integrated manner. The print control unit 1 includes, for example, a microprocessor, a ROM (Read Only Memory), a RAM (Random Access Memory), an input / output port, a timer, and the like, and is disposed inside the printing unit in the printing apparatus. The print control unit 1 performs a printing operation by performing sequence control on the entire printing apparatus based on a control signal SG1 transmitted from a host controller (not shown), a video signal SG2 in which dot map data is arranged one-dimensionally, and the like.

  More specifically, when the printing control unit 1 receives a printing instruction included in the control signal SG1, first, the printing control unit 1 detects the temperature detected by the fixing device temperature sensor 23 that detects the temperature of the fixing device 22 including the heater 22a. Reading is performed to determine whether or not the fixing device 22 is within a usable temperature range. When it is determined that the fixing device 22 is not within the usable temperature range, the print control unit 1 energizes the heater 22a to heat the fixing device 22 to a usable temperature. On the other hand, when the print controller 1 determines that the fixing device 22 is within the usable temperature range, the print controller 1 rotates the development / transfer process motor 3 via the driver 2 and also supplies the charge signal SGC for charging. By supplying the high voltage power supply 25, the charging high voltage power supply 25 is turned on, and the developing device 27 is charged.

  The print control unit 1 detects the presence or absence of a sheet as a recording medium in a sheet feeding tray (not shown) through the sheet remaining amount sensor 8 and detects the type of the sheet set in the sheet feeding tray. 9, and feeding of a sheet corresponding to the sheet is started. Here, the paper feed motor 5 can be rotated in both directions via the driver 4, and the print control unit 1 first rotates the paper feed motor 5 in the reverse direction and is detected by the paper inlet sensor 6. Until then, the paper set in the paper feed tray is fed by a preset amount. Then, the print controller 1 rotates the paper feed motor 5 forward via the driver 4 and conveys the paper to the printing mechanism inside the printing apparatus.

  Subsequently, when the print control unit 1 reaches a printable position, the print control unit 1 transmits a timing signal SG3 including a main scanning synchronization signal and a sub-scanning synchronization signal to the host controller as shown in FIG. In response, the video signal SG2 edited for each page is received from the host controller. Then, the print control unit 1 transfers the received video signal SG2 to the LED head 19 as a print data signal HD-DATA based on a predetermined clock signal HD-CLK composed of a differential signal described later. Note that. As will be described in detail later, the LED head 19 is formed by arraying a plurality of LED elements provided for printing one dot (pixel).

  Such transmission / reception of the video signal SG2 is performed for each print line. Upon receiving the video signal SG2 for one line, the print control unit 1 transmits a latch signal HD-LOAD to the LED head 19 and holds the print data signal HD-DATA in the LED head 19. The print control unit 1 can cause the print data signal HD-DATA held in the LED head 19 to perform printing even while the video signal SG2 of the next line is being received from the host controller. .

  Information printed by the LED head 19 is formed into a latent image as a dot with an increased potential on a photosensitive drum (not shown) charged to a predetermined negative potential. Then, the printing control unit 1 controls the developing device 27 to suck the image forming toner charged to a predetermined negative potential to each dot carried on the photosensitive drum by an electric suction force. To form a toner image. The formed toner image is supplied to the transfer device 28. The printing control unit 1 supplies the transfer signal SG4 to the transfer high-voltage power supply 26 to turn on the transfer high-voltage power supply 26 and apply a predetermined positive potential to the transfer device 28. At this time, based on the detection by the paper size sensor 9 and the paper inlet sensor 6, the print control unit 1 applies the voltage from the transfer high-voltage power supply 26 only while the paper passes through the transfer device 28. 28 is applied. In response to this, the transfer unit 28 transfers the toner image onto a sheet passing between the photosensitive drum and the transfer unit 28.

  The sheet on which the toner image is transferred in this way is conveyed to the fixing device 22. The fixing device 22 fixes the toner image on the paper by the heat from the heater 22a. The sheet on which the image is fixed is further conveyed and discharged from the printing mechanism to the outside. At this time, the print control unit 1 detects that the sheet has been discharged via the sheet discharge port sensor 7 provided in the vicinity of the discharge port. When the printing is completed and the sheet passes through the position where the sheet discharge sensor 7 is provided, the printing control unit 1 terminates the application of the voltage to the developing device 27 by the charging high-voltage power supply 25 and the driver 2. Then, the rotation of the motor 3 for development / transfer process is stopped.

  The printing apparatus can perform image formation on a plurality of sheets by repeatedly performing such a series of operations under the control of the print control unit 1.

Now, such a printing apparatus includes the LED head 19 as described above. LED head 19, for example, as shown in FIG. 3, a plurality of LED array chip _CHP which a plurality of LED elements arranged 1, _CHP 2, · · · and these LED array chip _CHP 1, _CHP 2, · · · A plurality of driving ICs (Integrated Circuits) DRV ₁ , DRV ₂ ,... For driving each of these are arranged on a predetermined printed wiring board 100 so as to face each other. Here, 26 LED array chips CHP ₁ , CHP ₂ ,..., CHP ₂₆ and 26 drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ are provided. Show.

  As long as the printed wiring board 100 is generally used as a so-called copper-clad laminate for printed wiring, it can be configured by using any type. Specifically, the printed wiring board 100 is a paper phenol board specified as symbols XPP, XPC, etc. by the National Electrical Manufacturers Association (NEMA), and paper specified as FR-2. Polyester substrate, paper epoxy substrate specified as FR-3, glass paper composite epoxy substrate specified as CEM-1, glass nonwoven paper composite epoxy substrate specified as CHE-3 The glass cloth epoxy substrate defined as G-10 and the glass cloth epoxy substrate defined as FR-4 are so-called rigid substrates having copper foil on one side or both sides. Of these, a glass cloth epoxy substrate (FR-4) having a low hygroscopic property and dimensional change and having a self-extinguishing property is most suitable.

The drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ are arranged on the printed wiring board 100 at an equal pitch with respect to the main scanning direction of the LED head 19. Each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ is configured by the same circuit and is cascade-connected to adjacent driving ICs. On the other hand, LED array chip _{CHP 1, CHP 2, ···,} CHP 26 is driven _{IC DRV 1, DRV 2, ···} , it is disposed to face the respective _{DRV 26} to the printed wiring board 100 on. These LED array chip _{CHP 1, CHP 2, ···,} CHP 26 and the drive _{IC DRV 1, DRV 2, ···} , is between the electrode pads of the dots of _{DRV 26,} directly by the wire bonding method using a gold wire (not shown) It is connected.

A differential clock signal line 101 for transmitting a differential clock signal is disposed on the printed wiring board 100. A terminal resistor 102 is connected to the end of the differential clock signal line 101, and the resistance value of the terminal resistor 102 is set to a value that does not cause signal reflection in the differential clock signal line 101. That is, the termination resistor 102 has a resistance value equal to the differential characteristic impedance Z ₀ included in the differential clock signal line 101.

  Such an LED head 19 is connected to the above-described print control unit 1 via a predetermined connection cable connected to the connector 103 formed on the printed wiring board 100.

In such an LED head 19, as will be described later in detail, the differential clock signal line 101 meanders between the drive ICs DRV ₁ , DRV ₂ ,... On the printed wiring board 100 as shown in FIG. However, it is wired to the terminating resistor 102 while drawing a crank-like path. At this time, in the LED head 19, in order to reduce the ratio of the differential clock signal line 101 occupying the printed wiring board 100, the pitch of the crank shape is set to the length of the drive ICs DRV ₁ , DRV ₂ ,. The length is 2 chips in the direction. Therefore, in the LED head 19, the connection between the differential clock signal line 101 and the terminals of the drive ICs DRV ₁ , DRV ₂ ,... Differs between adjacent drive ICs.

Accordingly, the LED head 19, as shown in FIG. 4 in the circuit diagram, driving _{IC DRV 1, DRV 2, ···} , DRV 26 and LED array chip _{CHP 1,} CHP 2, · · ·, the _{CHP 26} Connecting. In the figure, only the first-stage and second-stage drive ICs DRV ₁ and DRV ₂ and the LED array chips CHP ₁ and CHP ₂ connected in cascade are shown. That is, in the LED head 19, the differential clock signals HD-CLK-P and HD-CLK-N and the drive ICs are connected between the cascade-connected first and second stage drive ICs DRV ₁ and DRV _2. The connection with the clock input terminals CLKP and CLKN is switched. In the LED head 19, the differential clock signals HD-CLK-P and HD-CLK-N and the clocks in the driver ICs are similarly applied to the cascaded drive ICs DRV ₃ ,. The connection with the input terminals CLKP and CLKN is switched. More specifically, the differential clock signal HD-CLK-P is connected to the clock input terminal CLKP in the odd-numbered stage driving IC, and is connected to the clock input terminal CLKN in the even-numbered stage driving IC. On the other hand, the differential clock signal HD-CLK-N is connected to the clock input terminal CLKN in the odd-numbered stage driving IC, and is connected to the clock input terminal CLKP in the even-numbered stage driving IC.

  The internal configuration of the LED head 19 is as shown in FIG. 5, for example. Here, the LED head 19 capable of printing on A4 size paper with a resolution of 600 dots per inch is illustrated.

That is, in this LED head 19, the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ are single signals that use the differential clock signals HD-CLK-P and HD-CLK-N, respectively, inside the drive IC. A clock input circuit 151 for converting to an end signal, a shift register circuit 152 for performing shift transfer of the print data signals HD-DATA3,..., HD-DATA0 in synchronization with the clock signal output from the clock input circuit 151; A latch circuit 153 that holds the output signal of the shift register circuit 152 based on the latch signal HD-LOAD, and a strobe signal (hereinafter referred to as a print drive signal) that is a negative logic signal for controlling light emission or non-light emission of the LED element. HD-STB-N) is input to the inverter circuit 154 and the latch circuit An AND circuit 155 that takes the logical product of the output signal of 153 and the output signal of the inverter circuit 154, and based on the output signal of this AND circuit 155, the drive current based on the power supplied from a predetermined power supply VDD is LED An LED drive circuit 156 supplied to the element, and a control voltage generation circuit 157 that gives a command voltage to the LED drive circuit 156 so that the drive current is constant.

Further, the LED head 19 has a reference voltage generation circuit 158. In the LED head 19, the reference voltage V _ref generated by the reference voltage generation circuit 158 is supplied to the control voltage generation circuit 157 to generate a reference current for driving the LED element.

In such an LED head 19, the shift register circuit 152 in the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ is composed of 48 × 4 sets = 192 flip-flop circuits, and the print data signal HD-DATA3. ,..., HD-DATA0 is shifted in synchronization with the differential clock signals HD-CLK-P and HD-CLK-N, and a print data signal for 192 dots is transferred by clock input of 24 pulses.

Specifically, each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ includes 48 flip-flop circuits DFA ₁ , DFA ₂ ,. and DFA _48, cascaded 48 flip-flop circuits _{DFB 1, DFB 2, ···,} a _{DFB 48,} 48 flip-flop circuits connected in cascade _{DFC 1, DFC 2, ···,} DFC 48 When, 48 flip-flop circuits connected in cascade _{DFD 1,} DFD 2, · · ·, which has a _{DFD 48,} these 192 flip-flop circuit _{DFA 1, ···, DFA 48,} DFB 1, · _{··, DFB 48, DFC 1,} ···, DFC 48, DFD 1, ···, corresponding to each of the _{DFD 48} A plurality of latch circuits _LTA 1 _{provided, ···, LTA 48, LTB 1} , ···, LTB 48, LTC 1, ···, LTC 48, LTD 1, ···, LTD 48 ( above the latch Equivalent to the circuit 153). Further, the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ respectively output 192 drive current output terminals DO1, DO2,..., Which output drive currents for driving 192 LED elements. .., DO192, corresponding to each of these drive current output terminals DO1, DO2,..., DO192. Equivalent to.) These drive current output terminals DO1, DO2,..., DO192 are respectively connected to the terminal DO in the LED drive circuit DRV and connected to LED elements at corresponding dot positions by wire bonding.

The flip-flop circuits DFA ₁ , ..., DFA ₄₈ , DFB ₁ , ..., DFB ₄₈ , DFC ₁ , ..., DFC ₄₈ , DFD ₁ , ..., DFD ₄₈ will be described in detail later. However, unlike the conventional flip-flop circuit, the differential clock signal HD-CLK is not transferred at the falling edge of the input differential clock signals HD-CLK-P and HD-CLK-N. It is configured to operate based on both rising and falling edges of -P and HD-CLK-N and to transfer data. The data input terminal D of the flip-flop circuit DFA ₁ is connected to the data input terminal DATAI0 of the driving IC, and the output from the flip-flop circuit DFA ₄₈ is connected to the data output terminal DATAO0 of the driving IC. Similarly, the data input terminals D of the flip-flop circuits DFB ₁ , DFC ₁ , and DFD ₁ are respectively connected to the data input terminals DATAI 1, DATAI 2, and DATAI 3 of the driving IC, and the flip-flop circuits DFB ₄₈ , DFC ₄₈ , and DFD ₄₈ Are connected to the data output terminals DATAO1, DATAO2, and DATAO3 of the driving IC, respectively. Accordingly, the flip-flop circuit _{DFA 1, ···, DFA 48,} DFB 1, ···, DFB 48, DFC 1, ···, DFC 48, DFD 1, ···, DFD 48 , respectively, 48-stage The shift register circuit is configured.

Data output terminal DATAO0 drive IC DRV _m, · · ·, DATAO3 each next stage of the drive IC _{DRV m + 1} data input terminals DATAI0, · · ·, are connected to DATAI3. Therefore, the drive IC _{DRV 1,} DRV 2, · · ·, the flip-flop circuit _DFA 1 in _{DRV 26,} · · ·, _{DFA 48} are respectively inputted from the print control unit 1 to the drive IC DRV ₁ of the first stage A 48 × 26 stage shift register circuit is configured to shift the print data signal HD-DATA3 in synchronization with the differential clock signal HD-CLK-P. Similarly, the drive _{IC DRV 1, DRV 2, ···} , the flip-flop circuit _DFB 1 in _{DRV 26, ···, DFB 48,} DFC 1, ···, DFC 48, DFD 1, ···, DFD 48 Respectively, the print data signals HD-DATA2, HD-DATA1, and HD-DATA0 input from the print control unit 1 to the first-stage driving IC DRV ₁ are synchronized with the differential clock signal HD-CLK-P. A shift register circuit of 48 × 26 stages to be shifted is configured.

As described above, each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ includes a 4-bit parallel input shift register circuit, and transfers data for four adjacent pixels in a single clock. With this configuration, the data transfer clock frequency, that is, the frequency of the differential clock signal HD-CLK can be reduced.

The latch circuit _{LTA 1, ···, LTA 48,} LTB 1, ···, LTB 48, LTC 1, ···, LTC 48, LTD 1, ···, LTD 48 , respectively, from the terminal LOADI It operates based on the input latch signal LOAD-P. Latch circuits _LTA 1, · · ·, _{LTA 48,} respectively, the flip-flop circuit _DFA 1, · · ·, latches the print data signal HD-DATA0 held in the _{DFA 48.} Similarly, the latch circuit _{LTB 1, ···, LTB 48,} LTC 1, ···, LTC 48, LTD 1, ···, LTD 48 , respectively, the flip-flop circuit _DFB 1, · · ·, _{DFB 48} , DFC ₁ ,..., DFC ₄₈ , DFD ₁ ,..., Latch the print data signals HD-DATA 1, HD-DATA 2, and HD-DATA 3 held in the DFD ₄₈ .

In such a drive _{IC DRV 1, DRV 2, ···} , DRV 26, differences were upon the prior art, these drive _{IC DRV 1, DRV 2, ···} , odd or even-numbered stages in the _{DRV 26} That is, there is no select terminal for instructing the eyes.

7, the driving IC _{DRV 1,} DRV 2, shown · · ·, _{DRV 26} and the LED array chip _{CHP 1,} CHP 2, · · ·, the wiring of the _{CHP 26} and the printed wiring board 100. In the drawing, only the first to third stage driving ICs DRV ₁ , DRV ₂ , DRV ₃ and LED array chips CHP ₁ , CHP ₂ , CHP ₃ connected in cascade are shown.

The drive ICs DRV ₁ , DRV ₂ , DRV ₃ ,... And the LED array chips CHP ₁ , CHP ₂ , CHP ₃ ,... Are connected by bonding wires as shown by broken lines in FIG. DRV ₁ , DRV ₂ , DRV ₃ ,... And the printed wiring board 100 are also connected by bonding wires as indicated by broken lines in FIG.

The print data signals HD-DATA3,..., HD-DATA0 output from the print control unit 1 are input to the drive IC DRV ₁ via bonding pads indicated by “□” in FIG. The terminals DATAI3,..., DATAI0 are connected by wire bonding. The cascade output from the driving IC DRV ₁ is connected to a bonding pad once formed on the printed wiring board 100 from the data output terminals DATAO3,. It is connected to the adjacent bonding pad via the wiring formed on 100, and is again connected to the data input terminals DATAI3,..., DATAI0 of the driving IC DRV ₂ via wire bonding. Similarly, other drive ICs are also cascade-connected to adjacent drive ICs via wire bonding.

On the other hand, the differential clock signals HD-CLK-P and HD-CLK-N output from the print control unit 1 are respectively supplied to the driving ICs DRV ₁ , DRV ₂ , DRV ₃ ,. The signal is transmitted through a pair of signal lines formed by drawing a crank-shaped path while meandering between them, that is, the differential clock signal line 101 shown in FIG. Differential clock signal HD-CLK-P differential clock signal line 101 _N for transmitting the differential clock signal lines 101 _P and the differential clock signal HD-CLK-N for transmitting, respectively, drive a terminal cascaded It is formed up to the position of the IC DRV ₂₆ and is terminated by the termination resistor 102 shown in FIG.

Here, the differential clock signal lines 101 _P and 101 _N are arranged meandering while avoiding wiring portions for the print data signals HD-DATA 3,..., HD-DATA 0. Each of the driving ICs DRV ₁ , DRV ₂ , DRV ₃ ,... Drives 192 LED elements, as described above, and the arrangement pitch of each dot corresponding to each LED element is 1/600 inch. Thus, the drive _{IC DRV 1, DRV 2, DRV} 3, the arrangement pitch of ..., since it is about 8.1 mm, a crank-like arrangement pitch of the differential clock signal lines ₁₀₁ P, 101 _N, the drive This is twice the arrangement pitch of IC DRV ₁ , DRV ₂ , DRV ₃ ,.

As is clear from FIG. 7, each of the differential clock signal lines 101 _P and 101 _N becomes one continuous signal trace, and no discontinuity occurs in the middle. The intervals between the pair of differential clock signal lines 101 _P and 101 _N are configured to be equal.

Thus, the crank-like arrangement pitch of the differential clock signal lines 101 _P and 101 _N is twice the arrangement pitch of the drive ICs DRV ₁ , DRV ₂ , DRV ₃ ,. As described above, the connection between the differential clock signals HD-CLK-P and HD-CLK-N and the clock input terminals CLKP and CLKN in the drive IC is switched between adjacent drive ICs. As a result, in the LED head 19, in reality, the differential clock signal lines 101 _P and 101 _N do not cross each other, as shown in FIG. A circuit in which the differential clock signal lines 101 _P and 101 _N alternately intersect is realized.

As described above, in the LED head 19, the connection between the differential clock signals HD-CLK-P and HD-CLK-N and the clock input terminals CLKP and CLKN in the drive IC is switched between adjacent drive ICs. Therefore, even if the capacitances at the two clock input terminals CLKP and CLKN are slightly different due to variations in the design or manufacture of the driving IC, the same number is provided for each of the differential clock signal lines 101 _P and 101 _N. Since the clock input terminals CLKP and CLKN are connected, the difference in load capacitance between the differential clock signal lines 101 _P and 101 _N is averaged and becomes substantially negligible. Since this is a configuration similar to a so-called twisted pair wiring, it is a preferable characteristic from the viewpoint of the symmetry of the differential signal.

  Now, such an LED head 19 has a flip-flop circuit having the following configuration and operation, so that, conventionally, differential clock signals HD-CLK-P, HD-CLK between adjacent drive ICs. In order to reverse the logical inversion of the positive logic state and the negative logic state by switching the connection between −N and the clock input terminals CLKP and CLKN in the driving IC to return to the original operation logic. There is no need to provide a select terminal that was unavoidable.

FIG. 8 shows a circuit diagram showing the configuration of the above-described flip-flop circuit in comparison with the circuit symbol. FIG. 6A shows circuit symbols, which are flip-flop circuits DFA ₁ ,..., DFA ₄₈ , DFB ₁ ,..., DFB ₄₈ , DFC ₁ ,. ₄₈ , DFD ₁ ,..., DFD ₄₈ . FIG. 2B shows the internal configuration.

  That is, the flip-flop circuit DF includes two latch elements 201 and 202 and a selector circuit 203.

  The latch element 201 has a data input terminal D, a gate input terminal G, and a data output terminal Q. The latch element 201 receives the above-described differential clock signals HD-CLK-P and HD-CLK-N to the gate input terminal G through the clock input circuit 151, so that the level of the gate input terminal G is low. When the level is reached, the logic value of the data input terminal D is fetched and output from the data output terminal Q. On the other hand, when the level of the gate input terminal G becomes high level, the logic value output immediately before is held. Keep doing.

  The latch element 202 has a data input terminal D, a gate input terminal G, and a data output terminal Q. In the latch element 202, when the differential clock signals HD-CLK-P and HD-CLK-N are input to the gate input terminal G via the clock input circuit 151, the level of the gate input terminal G becomes high. In this case, the logic value of the data input terminal D is captured and output from the data output terminal Q. On the other hand, when the level of the gate input terminal G becomes a low level, the logic value output immediately before is continuously held. .

  The selector circuit 203 has a select terminal S, data input terminals A and B, and a data output terminal Y. In the selector circuit 203, when the differential clock signals HD-CLK-P and HD-CLK-N are input to the select terminal S via the clock input circuit 151, the level of the select terminal S becomes high level. When the logic value input to the data input terminal B is output from the data output terminal Y while the level of the select terminal S is low, the logic value input to the data input terminal A is The data is output from the data output terminal Y.

  Specifically, such a flip-flop circuit DF can be configured as shown in FIG. 9 or FIG. That is, as shown in FIG. 9, the flip-flop circuit DF includes latch elements 201 and 202 using an inverter composed of a clocked CMOS (Complementary Metal-Oxide Semiconductor) and a selector circuit 203 as a transmission. It can be configured by a combination of gates. In the flip-flop circuit DF, as shown in FIG. 10, the latch elements 201 and 202 are configured using an inverter configured from a clocked CMOS, and the selector circuit 203 is configured from an AND-OR inverter circuit. It can also be configured by a combination of selectors. Further, the flip-flop circuit DF is not particularly shown, but the latch elements 201 and 202 can also be configured by a combination of a transmission gate and an inverter, and the selector circuit 203 is composed of an AND circuit and an OR circuit. A combination or a combination of NAND circuits may be used.

  In such a flip-flop circuit DF, according to the level of the differential clock signals HD-CLK-P and HD-CLK-N inputted to the clock input terminal CK in the latch elements 201 and 202, the latch elements 201 and 202 The data output terminal 202 is switched, and the data input terminal to be output according to the levels of the differential clock signals HD-CLK-P and HD-CLK-N input to the select terminal S in the selector circuit 203. A and B are switched.

  Specifically, the flip-flop circuit DF operates according to the timing as shown in FIG. The first stage of FIG. 2 shows the signal waveform at the data input terminal D, the second stage of FIG. 2 shows the signal waveform at the clock input terminal CK, and the third stage of FIG. The signal waveform at the data output terminal Q is shown. The fourth stage in FIG. 4 shows the signal waveform at the data output terminal Q of the latch element 202. The fifth stage in FIG. 5 shows the signal waveform at the data output terminal Y of the selector circuit 203. The waveform is shown. In the figure, a data string composed of a, b, c, d, and e is input to the data input terminal D, and a clock signal CK (differential clock signal HD-CLK-P is synchronized with each data input. , HD-CLK-N) shows that the rising from the low level to the high level and the falling from the high level to the low level are repeated.

  That is, the flip-flop circuit DF selects the output of the latch element 201 when the level of the clock input terminal CK is high, while latching when the level of the clock input terminal CK is low. The output of the element 202 is selected and output from the data output terminal Y in the selector circuit 203.

  As a result, in the flip-flop circuit DF, when the data strings a, b, c, d, and e are input to the data input terminal D, the rise of the differential clock signals HD-CLK-P and HD-CLK-N and At both falling edges, the data strings a, b, c, d, and e are sequentially switched and output. In other words, in the flip-flop circuit DF, data transfer can be performed at both rising and falling edges of the differential clock signals HD-CLK-P and HD-CLK-N.

  Here, in the LED head 19, as described above, between the adjacent drive ICs, the differential clock signals HD-CLK-P and HD-CLK-N and the clock input terminals CLKP and CLKN in the drive ICs. The connection is switched, but the effect of this is that the rising and falling of the differential clock signals HD-CLK-P and HD-CLK-N change when the connection is switched. Therefore, the LED head 19 is configured to be operable at both rising and falling edges of the differential clock signals HD-CLK-P and HD-CLK-N as the flip-flop circuit DF. It can be operated.

  When the operation of the LED head 19 is compared with the conventional circuit operation, it is as shown in FIG. FIG. 4A shows the timing of the conventional print data signals HD-DATA3,..., HD-DATA0 and the clock signal HD-CLK (differential clock signals HD-CLK-P, HD-CLK-N). FIG. 4B shows the timing of the print data signals HD-DATA3,..., HD-DATA0 and the clock signal HD-CLK in the LED head 19.

  First, as shown in FIG. 2A, the print data signals HD-DATA3,..., HD-DATA0 are shifted at the falling edge of the clock signal HD-CLK input to the flip-flop circuit. Is done. That is, in the prior art, if the cycle of the clock signal HD-CLK is T, even if the print data signals HD-DATA3,..., HD-DATA0 change most frequently, the cycle is at most 2T. Become.

  On the other hand, in the LED head 19, as shown in FIG. 5B, the print data signal HD- is detected at both rising and falling edges of the clock signal HD-CLK input to the flip-flop circuit DF. DATA3,..., HD-DATA0 are shifted. Therefore, in the LED head 19, if both the high level pulse width and the low level pulse width of the clock signal HD-CLK are T1 (= T / 2), the print data signal HD-DATA3,. .. Even if HD-DATA0 changes most frequently, its period is at most T1. That is, the LED head 19 can perform data transfer at a rate twice that of the prior art.

As described above, in the LED head 19 of the printing apparatus shown as the first embodiment of the present invention, the differential clock signal lines 101 _P and 101 _N are not crossed on the printed circuit board 100 on the same plane. In other words, it is possible to realize a circuit that can be arranged on the same wiring layer and in which a pair of differential clock signal lines 101 _P and 101 _N alternately cross every adjacent driving IC on the circuit diagram. . At this time, in the LED head 19, although the differential clock signal lines 101 _P and 101 _N cross each other alternately for each driving IC on the circuit diagram, the difference in operation timing does not surface, There is no need to provide a circuit for correcting the influence of the intersection of the differential clock signal lines 101 _P and 101 _N for each driving IC.

In the LED head 19, the differential clock signal lines 101 _P and 101 _N can be arranged at equal intervals so as to obtain a predetermined characteristic impedance, and due to variations in design or manufacturing of the driving IC. Even if the capacitances at the two clock input terminals CLKP and CLKN are slightly different, the same number of clock input terminals CLKP and CLKN are connected to the differential clock signal lines 101 _P and 101 _N. The difference in load capacitance between the differential clock signal lines 101 _P and 101 _N is averaged and becomes substantially negligible. As a result, in the LED head 19, the rise time and the fall time are different between the differential clock signals HD-CLK-P and HD-CLK-N, and the operating frequency of the shift register circuit cannot be increased. It can be avoided. Therefore, in the LED head 19, the signal quality of the differential clock signals HD-CLK-P and HD-CLK-N can be improved, and the reliability during data transfer can be improved.

  Furthermore, in the LED head 19, since it is not necessary to provide a select terminal that has been unavoidable in the past, the wiring area on the printed wiring board 100 can be reduced, and the number of bonding wires can be reduced. In addition, the printed wiring board 100 can be reduced in size, and the cost can be reduced accordingly.

  Furthermore, in the LED head 19, the frequency of the differential clock signals HD-CLK-P and HD-CLK-N can be substantially reduced to ½ times that of the conventional case. The influence can also be suppressed.

  Hereinafter, advantages of the case where the clock signal is reduced in amplitude and configured as a pair of differential signals will be described.

  Generally, when a signal line wiring formed on a printed wiring board undergoes a logical change, a high-frequency current is generated in each part of the signal line, and electromagnetic radiation is generated in the external space. Such electromagnetic radiation may interfere with reception of radio waves by a receiving device such as a radio or television arranged around the printed wiring board, and is known as a so-called EMC (ElectroMagnetic Compatibility) problem. For example, “C. R. Paul.,“ Introduction to Electromagnetic Compatibility ”” (Japanese translation “EMC introduction”), which describes EMC technology, describes such a phenomenon as follows.

FIG. 13A shows a model circuit in the case where a load is connected to a signal source that generates a signal V _s (t) that changes with time, and a loop is formed via a signal line that connects the two. A high-frequency current flowing in the signal line is I, and an area of a loop formed by the signal source, the signal line, and the load is S. Here, the signal generated by the signal source _V s (t), as shown in FIG. (B), period T, the pulse width _{T w,} rise time _{T r,} the fall time _{T f,} the amplitude _{A m} A clock waveform composed of a repetitive waveform approximated by a trapezoidal wave is assumed.

  Here, FIG. 2C shows the electric field strength of the electromagnetic wave radiated by the current I obtained from the theory of the linear antenna. In the figure, the horizontal axis indicates the frequency f, and the vertical axis indicates the electric field E radiated to the outside normalized by the current I, which is displayed as a log-log graph. From the figure, as the frequency of the signal source increases, the radiation electric field strength generated due to this increases, and the electric field strength increases by 40 dB (40 dB / decade) every time the frequency is increased by 10 times. It can be seen that the electric field strength increases by 6 dB (6 dB / octave) every time the value of the signal becomes twice.

FIG. 4D shows an outline of an envelope created by a harmonic spectrum of the fundamental frequency 1 / T having a period T as the frequency spectrum of the waveform shown in FIG. In the figure, the vertical axis corresponds to the current I. From the figure, in the frequency region A from the low frequency region to the frequency 1 / (πT _w ), the frequency characteristic is approximated flatly because the number of harmonic components is small, and the frequency is from 1 / (πT _w ). In the frequency region B up to 1 / (πT _r ), it can be seen that the high-frequency current component decreases at a rate of −20 dB / decade with respect to the increase in frequency. In addition, it can be seen from the figure that in the frequency region C where the frequency is 1 / (πT _r ) or more, the high-frequency current component decreases at a rate of −40 dB / decade with respect to the increase in frequency. That is, in order to reduce the frequency spectrum in this high frequency region, it is effective to increase the rise time and fall time of the signal waveform, that is, to increase the signal period.

Furthermore, the same figure (e) shows the electric field strength radiated | emitted outside with the waveform shown in the figure (b). This graph is obtained by adding the graph shown in FIG. 5C and the graph shown in FIG. From the figure, in the frequency region A from the low frequency region to the frequency 1 / (πT _w ), the electric field strength increases at a rate of +40 dB / decade with respect to the frequency increase, and the frequency becomes 1 / (πT _w ). In the frequency domain B from 1 to (πT _r ), the electric field strength increases at a rate of +20 dB / decade with respect to the increase in frequency, and in the frequency domain C in which the frequency is 1 / (πT _r ) or more. It can be seen that the electric field strength is at a constant level regardless of the frequency.

  Thus, it is also quantitatively clear that the EMI (Electro Magnetic Interference) noise level is remarkably increased by increasing the frequency and the signal amplitude.

  On the other hand, in the LED head 19, the differential clock signal HD-CLK-P can be obtained without reducing the signal amplitude or increasing the signal waveform by increasing the rise time and fall time of the signal waveform. Since the frequency of HD-CLK-N can be substantially reduced, the influence of electromagnetic radiation can be suppressed without reducing the data processing capability.

  Next, a printing apparatus shown as the second embodiment will be described.

  In the printing apparatus shown as the second embodiment, a phase conversion circuit that generates a two-phase clock signal that does not overlap each other for each input of the clock signal is provided in the driving IC in the printing apparatus shown as the first embodiment. It is provided. Therefore, in the description of the second embodiment, the same components as those in the description of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

In the printing apparatus shown as the second embodiment, an LED head 19 having an internal configuration as shown in FIG. 14 is used. That is, in the LED head 19, the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ are respectively the clock input circuit 151, the latch circuit 153, the inverter circuit 154, the AND circuit 155, the LED driving circuit 156, In addition to the control voltage generation circuit 157, the shift register circuit 301 and the phase conversion circuit 302 having a configuration different from that of the shift register circuit 152 described above are included.

In such an LED head 19, the shift register circuit 301 in the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ has 48 × 4 sets = 192 flip-flops, similar to the shift register circuit 152 described above. The print data signals HD-DATA3,..., HD-DATA0 are shifted in synchronization with the differential clock signals HD-CLK-P and HD-CLK-N, and 192 by clock input of 24 pulses. Transfer print data signal for dots.

Specifically, each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ includes 48 flip-flop circuits EFA ₁ , EFA ₂ ,. and EFA _48, 48 pieces of flip-flop circuits connected in cascade _{EFB 1, EFB 2, ···,} and _{EFB 48,} 48 pieces of flip-flop circuits connected in cascade _{EFC 1, EFC 2, ···,} EFC 48 And 48 flip-flop circuits EFD ₁ , EFD ₂ ,..., EFD ₄₈ connected in cascade.

Flip-flop circuit _{EFA 1, ···, EFA 48,} EFB 1, ···, EFB 48, EFC 1, ···, EFC 48, EFD 1, ···, EFD 48 , respectively, flip-flops described above circuit _{DFA 1, ···, DFA 48,} DFB 1, ···, DFB 48, DFC 1, ···, DFC 48, DFD 1, ···, like the _{DFD 48,} a differential clock signal HD- It operates based on both rising and falling edges of CLK-P and HD-CLK-N, and is configured to be able to transfer data. The data input terminal D of the flip-flop circuit EFA ₁ is connected to the data input terminal DATAI 0 of the drive IC, and the output from the flip-flop circuit EFA ₄₈ is connected to the data output terminal DATAO 0 of the drive IC. Similarly, the data input terminals D of the flip-flop circuits EFB ₁ , EFC ₁ , EFD ₁ are respectively connected to the data input terminals DATAI 1, DATAI 2, DATAI 3 of the drive IC, and the flip-flop circuits EFB ₄₈ , EFC ₄₈ , EFD ₄₈ Are connected to the data output terminals DATAO1, DATAO2, and DATAO3 of the driving IC, respectively. Accordingly, the flip-flop circuit _{EFA 1, ···, EFA 48,} EFB 1, ···, EFB 48, EFC 1, ···, EFC 48, EFD 1, ···, EFD 48 , respectively, 48-stage The shift register circuit is configured.

Data output terminal DATAO0 drive IC DRV _m, · · ·, DATAO3 each next stage of the drive IC _{DRV m + 1} data input terminals DATAI0, · · ·, are connected to DATAI3. Therefore, the drive IC _{DRV 1,} DRV 2, · · ·, the flip-flop circuit _EFA 1 in _{DRV 26,} · · ·, _{EFA 48} are respectively inputted from the print control unit 1 to the drive IC DRV ₁ of the first stage A 48 × 26 stage shift register circuit is configured to shift the print data signal HD-DATA3 in synchronization with the differential clock signal HD-CLK-P. Similarly, the drive _{IC DRV 1, DRV 2, ···} , the flip-flop circuit _EFB 1 in _{DRV 26, ···, EFB 48,} EFC 1, ···, EFC 48, EFD 1, ···, EFD 48 Respectively, the print data signals HD-DATA2, HD-DATA1, and HD-DATA0 input from the print control unit 1 to the first-stage driving IC DRV ₁ are synchronized with the differential clock signal HD-CLK-P. A shift register circuit of 48 × 26 stages to be shifted is configured.

As described above, each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ includes a 4-bit parallel input shift register circuit, and transfers data for four adjacent pixels in a single clock. With this configuration, the data transfer clock frequency, that is, the frequency of the differential clock signal HD-CLK can be reduced.

In such a drive _{IC DRV 1, DRV 2, ···} , DRV 26, differences were upon the prior art, these drive _{IC DRV 1, DRV 2, ···} , odd or even-numbered stages in the _{DRV 26} That is, there is no select terminal for instructing the eyes.

The drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ are connected to the LED array chips CHP ₁ , CHP ₂ , CHP ₃ ,. Connected by.

Therefore, in the LED head 19, as described above, the differential clock signal lines 101 _P and 101 _N are not actually crossed, and as shown in FIG. A circuit is realized in which a pair of differential clock signal lines 101 _P and 101 _N alternately cross each time.

In the LED head 19, as described above, the connection between the differential clock signals HD-CLK-P and HD-CLK-N and the clock input terminals CLKP and CLKN in the drive IC is switched between adjacent drive ICs. Thus, even if the capacitances at the two clock input terminals CLKP and CLKN are slightly different due to variations in the design or manufacture of the driving IC, the differential clock signal lines 101 _P and 101 _N Since the same number of clock input terminals CLKP and CLKN are connected, the difference in load capacitance between the differential clock signal lines 101 _P and 101 _N is averaged and becomes substantially negligible. Since this is a configuration similar to a so-called twisted pair wiring, it is a preferable characteristic from the viewpoint of the symmetry of the differential signal.

  Now, such an LED head 19 has a flip-flop circuit and a phase conversion circuit having the following configurations and operations, so that, conventionally, a differential clock signal HD-CLK-P between adjacent drive ICs. , HD-CLK-N and the clock input terminals CLKP and CLKN in the driving IC are switched, so that the positive logic state and the negative logic state are inverted, and the logic is inverted again to return to the original operation logic. Therefore, there is no need to provide a select terminal, which is inevitable to install.

FIG. 16 is a circuit diagram showing the configuration of the above-described flip-flop circuit in comparison with the circuit symbol. FIG. 6A shows circuit symbols, and the flip-flop circuits EFA ₁ ,..., EFA ₄₈ , EFB ₁ ,..., EFB ₄₈ , EFC ₁ ,. ₄₈ , EFD ₁ ,..., EFD ₄₈ . FIG. 2B shows the internal configuration.

  That is, the flip-flop circuit EF includes seven N-channel MOS transistors 351, 352, 353, 354, 359, 361, 363 and seven P-channel MOS transistors 355, 356, 357, 358, 360, 362, 364. Composed.

  Among these, the source terminal of the N channel MOS transistor 351 is connected to the drain terminal of the P channel MOS transistor 355, the source terminal of the N channel MOS transistor 352 is connected to the drain terminal of the P channel MOS transistor 356, and the N channel MOS transistor 356 is connected. The source terminal of transistor 353 is connected to the drain terminal of P channel MOS transistor 357, and the source terminal of N channel MOS transistor 354 is connected to the drain terminal of P channel MOS transistor 358. That is, N channel MOS transistor 351 and P channel MOS transistor 355, N channel MOS transistor 352 and P channel MOS transistor 356, N channel MOS transistor 353 and P channel MOS transistor 357, and N channel MOS transistor 354 and P channel MOS transistor 358. Each constitutes a transmission gate.

  N channel MOS transistor 359 and P channel MOS transistor 360, N channel MOS transistor 361 and P channel MOS transistor 362, and N channel MOS transistor 363 and P channel MOS transistor 364 constitute an inverter, respectively.

  The input of the transmission gate constituted by the N channel MOS transistor 351 and the P channel MOS transistor 355 and the input of the transmission gate constituted by the N channel MOS transistor 353 and the P channel MOS transistor 357 are respectively shown in FIG. It is connected to the data input terminal D shown in (a).

  The output of the transmission gate constituted by N channel MOS transistor 351 and P channel MOS transistor 355 is connected to the input of an inverter constituted by N channel MOS transistor 359 and P channel MOS transistor 360, and N channel MOS transistor The output of the transmission gate constituted by transistor 353 and P channel MOS transistor 357 is connected to the input of an inverter constituted by N channel MOS transistor 361 and P channel MOS transistor 362.

  Further, the output of the inverter constituted by N channel MOS transistor 359 and P channel MOS transistor 360 is connected to the input of the transmission gate constituted by N channel MOS transistor 352 and P channel MOS transistor 356, and N channel MOS transistor The output of the inverter constituted by transistor 361 and P channel MOS transistor 362 is connected to the input of the transmission gate constituted by N channel MOS transistor 354 and P channel MOS transistor 358.

  Furthermore, the output of the transmission gate constituted by N channel MOS transistor 352 and P channel MOS transistor 356 and the output of the transmission gate constituted by N channel MOS transistor 354 and P channel MOS transistor 358 are mutually wired. ORed and connected to the input of an inverter constituted by an N channel MOS transistor 363 and a P channel MOS transistor 364. The output of the inverter constituted by the N channel MOS transistor 363 and the P channel MOS transistor 364 is connected to the data output terminal Q shown in FIG.

  Such a flip-flop circuit EF inputs non-overlapping two-phase clock signals φ1 and φ2 output from a phase conversion circuit 302 described later, and operates according to timing described later. Note that φ1N and φ2N shown in the figure are complement signals obtained by logically inverting the two-phase clock signals φ1 and φ2 by a logic inversion circuit (not shown).

  On the other hand, as shown in FIG. 17, the phase conversion circuit 302 includes an inverter 370, two negative OR circuits 371 and 372, and two buffer circuits 373 and 374.

  In such a phase conversion circuit 302, the differential clock signals HD-CLK-P and HD-CLK-N input to the clock input terminal CK are input to one input terminal of the NOR circuit 372, Input to the input terminal of the inverter 370. In addition, the output of the inverter 370 is input to one input terminal of the NOR circuit 371.

  Further, the output of the negative logical sum circuit 372 is input to the buffer circuit 373, while the output of the negative logical sum circuit 371 is input to the buffer circuit 374. The output of the buffer circuit 373 is output to the flip-flop circuit EF as one clock signal φ2 of the two-phase clock signals, and is input to the other input terminal of the NOR circuit 371. The output of the buffer circuit 374 is output to the flip-flop circuit EF as the other clock signal φ1 of the two-phase clock signals, and is also input to the other input terminal of the negative OR circuit 372.

  Such a phase conversion circuit 302 operates according to the timing shown in FIG. The first stage of the figure shows signal waveforms of the differential clock signals HD-CLK-P and HD-CLK-N inputted to the clock input terminal CK, and the second stage of FIG. FIG. 3 shows the signal waveform output from the NOR circuit 372. FIG. 4 shows the signal waveform of the two-phase clock signal φ2. FIG. 5 shows the signal waveform output from the NOR circuit 371, and FIG. 6 shows the signal waveform of the two-phase clock signal φ1.

  First, in the phase conversion circuit 302, when the differential clock signals HD-CLK-P and HD-CLK-N are input to the clock input terminal CK, the clock signal CK1 logically inverted by the inverter 370 is generated. Therefore, in the phase conversion circuit 302, when the level of the clock input terminal CK is high, the low-level signal NOR2 is output from the negative OR circuit 372, and is the output of the buffer circuit 373 that receives this signal. The two-phase clock signal φ2 is also at a low level. At this time, in the phase conversion circuit 302, the clock signal CK1 output from the inverter 370 transits from the high level to the low level, and the clock signal CK1 is input to the negative OR circuit 371. In the phase conversion circuit 302, since the two-phase clock signal φ2 is input to the negative OR circuit 371, after waiting for the two-phase clock signal φ2 to become low level, A high level signal NOR1 is output. In the phase conversion circuit 302, the signal NOR1 output from the NOR circuit 371 is input to the buffer circuit 374, and the two-phase clock signal φ1 transitions from the low level to the high level.

  Subsequently, in the phase conversion circuit 302, when the level of the clock input terminal CK transitions from a high level to a low level, a high level clock signal CK1 logically inverted by the inverter 370 is generated. As a result, in the phase conversion circuit 302, the signal NOR1 output from the NOR circuit 371 transits from the high level to the low level, and the two-phase clock signal φ1 that is the output of the buffer circuit 374 to which the signal NOR1 is input is high. Transition from level to low level. At this time, in the phase conversion circuit 302, the differential clock signals HD-CLK-P and HD-CLK-N that have previously transitioned to the low level are input to one input terminal of the NOR circuit 372. In response to the transition of the high-level two-phase clock signal φ1 input to the other input terminal to the low level, the signal NOR2 output from the NOR circuit 372 changes to the high level. The two-phase clock signal φ2 that is the output of the input buffer circuit 373 is also at a high level.

The phase conversion circuit 302 generates the two-phase clock signals φ1 and φ2 that do not overlap each other for each input of the differential clock signals HD-CLK-P and HD-CLK-N by performing such an operation. It will be. Here, the pulse widths T _w1 and T _w2 of the two-phase clock signals φ 1 and φ ₂ are slightly different, reflecting the influence of the delay time by the inverter 370. In the same figure, the rising and falling timings of the differential clock signals HD-CLK-P and HD-CLK-N are indicated by vertical broken lines, and these differential clock signals HD-CLK-P and HD- Although the delay times from the rising and falling edges of CLK-N to the output of the two-phase clock signals φ1 and φ2 are shown as T _d1 and T _d2 , these delay times T _d1 and T _d2 are also shown. Further, it is slightly different reflecting the influence of delay time by the inverter 370.

  On the other hand, the flip-flop circuit EF that receives the two-phase clock signals φ1 and φ2 output from the phase conversion circuit 302 that performs such an operation operates according to the timing shown in FIG.

  The first stage of FIG. 1 shows the signal waveform at the data input terminal D shown in FIG. 16A, and the second stage of FIG. 2 shows the signal waveform at the clock input terminal CK of the phase conversion circuit 302. FIG. 14 shows the signal waveform at the data output terminal Q shown in FIG. In the figure, a data string composed of a, b, c, d, and e is input to the data input terminal D, and a clock signal CK (differential clock signal HD-CLK-P is synchronized with each data input. , HD-CLK-N) shows that the rising from the low level to the high level and the falling from the high level to the low level are repeated.

  The third stage of FIG. 3 shows the signal waveform of the two-phase clock signal φ1 output from the phase conversion circuit 302. The fourth stage of FIG. 4 shows the two-phase clock signal φ2 output from the phase conversion circuit 302. 5 shows the signal waveform of the complement signal φ1N obtained by logically inverting the two-phase clock signal φ1, and the sixth row shows the logical waveform of the two-phase clock signal φ2. The signal waveform of the completed complement signal φ2N is shown.

  Furthermore, the 7th to 13th stages of FIG. 7 show signal waveforms output from the respective transmission gates and inverters shown in FIG. 7 shows the signal waveform of the signal D1A output from the transmission gate composed of the N-channel MOS transistor 351 and the P-channel MOS transistor 355, and the eighth stage in FIG. The signal waveform of the signal D1B output from the inverter constituted by the MOS transistor 359 and the P-channel MOS transistor 360 is shown. In FIG. 9, the signal waveform is constituted by the N-channel MOS transistor 352 and the P-channel MOS transistor 356. The signal waveform of the signal D1C output from the transmission gate is shown. In FIG. 10, the signal D0 output from the transmission gate constituted by the N-channel MOS transistor 353 and the P-channel MOS transistor 357 is shown. 11 shows the signal waveform of the signal D0B output from the inverter constituted by the N-channel MOS transistor 361 and the P-channel MOS transistor 362. The 12th stage of FIG. The signal waveform of the signal D0C output from the transmission gate formed by the N channel MOS transistor 354 and the P channel MOS transistor 358 is shown. Actually, the signals D1C and D0C are wired-or connected as described above, but are distinguished here for convenience. 13 shows the signal waveform of the signal DC after wired OR input to the inverter constituted by the N channel MOS transistor 363 and the P channel MOS transistor 364.

  First, in the flip-flop circuit EF, a data string composed of a, b, c, d, and e is input to the data input terminal D, and the level of the clock signal CK transitions in synchronization therewith. At this time, in the flip-flop circuit EF, the two-phase clock signals φ1 and φ2 and the complement signals φ1N and φ2N are input.

  Here, in the flip-flop circuit EF, when the data signal a is applied to the data input terminal D when the clock signal CK is at the low level, the two-phase clock signal φ2 is active, so that the N-channel MOS transistor 351 is active. Since data a is transmitted to the output of the transmission gate constituted by the P channel MOS transistor 355 and this signal is logically inverted by the inverter constituted by the N channel MOS transistor 359 and the P channel MOS transistor 360. Data a is output as the signal D1B. In FIG. 19, “a” is simply described in the signal waveform of the signal D1B. However, the data a as the signal D1A is logically inverted, and the signal is similarly applied in the following description. This is a logically inverted version of the data as D1A.

  Subsequently, in the flip-flop circuit EF, when the clock signal CK becomes high level, the two-phase clock signal φ2 becomes low level, and further, the two-phase clock signal φ1 changes to high level. In the flip-flop circuit EF, when the two-phase clock signal φ2 becomes low level, the transmission gate constituted by the N channel MOS transistor 351 and the P channel MOS transistor 355 is turned off. Since there is a capacitance component at the input, the transmission gate maintains the previously output potential level due to the electric charge stored therein. In FIG. 19, this state is indicated by a one-dot chain line in the signal waveform, indicating that the signal is in a high impedance state and the potential level output before that is held by the accumulated charge. .

  Thus, in the flip-flop circuit EF, when a data string composed of a, b, c, d, e is input to the data input terminal D, the signals D1A, D1B are also a, b, c, A data string consisting of d and e is obtained.

  Similarly, in the flip-flop circuit EF, when the two-phase clock signal φ1 is at the high level, the transmission gate constituted by the N channel MOS transistor 353 and the P channel MOS transistor 357 is turned on, and the data input terminal D The data string composed of a, b, c, d, and e inputted to is transmitted to the next stage. In the flip-flop circuit EF, when the two-phase clock signal φ1 becomes low level, the transmission gate constituted by the N-channel MOS transistor 353 and the P-channel MOS transistor 357 is turned off. Since there is a capacitance component at the input of the inverter, the electric potential stored in the transmission gate maintains the potential level output previously.

  Thus, in the flip-flop circuit EF, when the data string composed of a, b, c, d, and e is input to the data input terminal D, the signal D0A is different in timing from the signals D1A and D1B. , D0B, a data string composed of a, b, c, d, and e is obtained.

  Here, as is apparent from FIG. 19, the signals D1C and D0C do not become active at the same time, and when one is active, the other is in a charge accumulation state due to a high impedance state. Therefore, in the flip-flop circuit EF, a data string composed of a, b, c, d and e synchronized with the clock signal CK is generated as a signal DC obtained by wired-OR connection of these signals D1C and D0C. become. In the flip-flop circuit EF, the signal DC is logically inverted by an inverter constituted by an N-channel MOS transistor 363 and a P-channel MOS transistor 364, so that a, b, c inputted to the data input terminal D are obtained. , D, e, a data string consisting of a, b, c, d, e, which has the same logic as the data string, is obtained.

  As described above, in the flip-flop circuit EF, when the data strings a, b, c, d, and e are input to the data input terminal D, the rising edges of the differential clock signals HD-CLK-P and HD-CLK-N. The data strings a, b, c, d, and e are sequentially switched and output at both the falling and falling edges. In other words, in the flip-flop circuit EF, it is possible to transfer data at both rising and falling edges of the differential clock signals HD-CLK-P and HD-CLK-N.

  At this time, in the LED head 19, as described above, between the adjacent driving ICs, the differential clock signals HD-CLK-P and HD-CLK-N and the clock input terminals CLKP and CLKN in the driving ICs. The connection is switched, but the effect of this is that the rising and falling of the differential clock signals HD-CLK-P and HD-CLK-N change when the connection is switched. Accordingly, the LED head 19 is configured to be operable at both the rising and falling edges of the differential clock signals HD-CLK-P and HD-CLK-N as the flip-flop circuit EF. It can be operated.

  When the operation of the LED head 19 is compared with the conventional circuit operation, it is the same as that shown in FIG.

  That is, in the prior art, if the cycle of the clock signal HD-CLK is T, even if the print data signals HD-DATA3,..., HD-DATA0 change most frequently, the cycle is at most 2T. On the other hand, in the LED head 19, if both the high level pulse width and the low level pulse width of the clock signal HD-CLK are T1 (= T / 2), the print data signal HD- Even if DATA3,..., HD-DATA0 changes most frequently, the period is at most T1. That is, the LED head 19 can perform data transfer at a rate twice that of the prior art.

As described above, in the LED head 19 of the printing apparatus shown as the second embodiment of the present invention, the differential clock signal lines 101 _P and 101 _N are not crossed on the printed circuit board 100 on the same plane. In other words, a circuit in which a pair of differential clock signal lines 101 _P and 101 _N are alternately crossed for each adjacent driving IC can be realized on the circuit diagram. . At this time, in the LED head 19, although the differential clock signal lines 101 _P and 101 _N cross each other alternately for each driving IC on the circuit diagram, the difference in operation timing does not surface, There is no need to provide a circuit for correcting the influence of the intersection of the differential clock signal lines 101 _P and 101 _N for each driving IC.

In the LED head 19, the differential clock signal lines 101 _P and 101 _N can be arranged at equal intervals so as to obtain a predetermined characteristic impedance, and due to variations in design or manufacturing of the driving IC. Even if the capacitances at the two clock input terminals CLKP and CLKN are slightly different, the same number of clock input terminals CLKP and CLKN are connected to the differential clock signal lines 101 _P and 101 _N. The difference in load capacitance between the differential clock signal lines 101 _P and 101 _N is averaged and becomes substantially negligible. As a result, in the LED head 19, the rise time and the fall time are different between the differential clock signals HD-CLK-P and HD-CLK-N, and the operating frequency of the shift register circuit cannot be increased. It can be avoided. Therefore, in the LED head 19, the signal quality of the differential clock signals HD-CLK-P and HD-CLK-N can be improved, and the reliability during data transfer can be improved.

  Furthermore, in the LED head 19, since it is not necessary to provide a select terminal that has been unavoidable in the past, the wiring area on the printed wiring board 100 can be reduced, and the number of bonding wires can be reduced. In addition, the printed wiring board 100 can be reduced in size, and the cost can be reduced accordingly.

  Furthermore, the LED head 19 includes a flip-flop circuit EF composed of a transmission gate and an inverter configured by combining an N-channel MOS transistor and a P-channel MOS transistor, and a phase conversion circuit 302, thereby providing a flip-flop circuit EF. Since there is no need to provide a selector circuit unlike the flip-flop circuit DF shown as the first embodiment, the chip size of the drive IC can be further reduced, and the cost can be further reduced.

  Further, in the LED head 19, the frequency of the differential clock signals HD-CLK-P and HD-CLK-N can be substantially reduced to ½ times as compared with the conventional case. Can also be suppressed.

  Next, a printing apparatus shown as the third embodiment will be described.

  The printing apparatus shown as the third embodiment is different from the flip-flop circuit EF in the printing apparatus shown as the second embodiment. Accordingly, in the description of the third embodiment, the same reference numerals are given to the same configurations as those in the first embodiment and the second embodiment, and the detailed description thereof is omitted. To do.

In the printing apparatus shown as the third embodiment, a flip-flop circuit EF constituting a shift register circuit provided in the LED head 19 is used as shown in FIG. FIG. 6A shows circuit symbols, and the flip-flop circuits EFA ₁ ,..., EFA ₄₈ , EFB ₁ ,..., EFB ₄₈ , EFC ₁ ,. ₄₈ , EFD ₁ ,..., EFD ₄₈ . FIG. 2B shows the internal configuration.

  That is, the flip-flop circuit EF includes eight N channel MOS transistors 401, 402, 403, 404, 405, 406, 407, 408 and eight P channel MOS transistors 409, 410, 411, 412, 413, 414, 415. , 416.

  Among these, N channel MOS transistors 401 and 402 and P channel MOS transistors 409 and 410, N channel MOS transistors 405 and 406, P channel MOS transistors 413 and 414, N channel MOS transistors 403 and 404, and P channel MOS transistors 411 and 412 , And N channel MOS transistors 407 and 408 and P channel MOS transistors 415 and 416 constitute a clocked CMOS inverter, respectively.

  The gate terminals of the N-channel MOS transistors 401 and 405 and the P-channel MOS transistors 410 and 414 are connected to the data input terminal D shown in FIG. A complement signal φ2N obtained by logically inverting the two-phase clock signal φ2 output from the phase conversion circuit 302 by a logic inverting circuit (not shown) is input to the gate terminal of the P channel MOS transistor 409, and the N channel MOS A two-phase clock signal φ 2 output from the phase conversion circuit 302 is input to the gate terminal of the transistor 402. Similarly, a complement signal φ1N obtained by logically inverting the two-phase clock signal φ1 output from the phase conversion circuit 302 by a logic inverting circuit (not shown) is input to the gate terminal of the P-channel MOS transistor 413, and N-channel A two-phase clock signal φ 1 output from the phase conversion circuit 302 is input to the gate terminal of the MOS transistor 406.

  A signal D1B output from a clocked CMOS inverter composed of N-channel MOS transistors 401 and 402 and P-channel MOS transistors 409 and 410 is connected to the gate terminals of the N-channel MOS transistor 403 and the P-channel MOS transistor 412. The signal D0B output from the clocked CMOS inverter constituted by the N channel MOS transistors 405 and 406 and the P channel MOS transistors 413 and 414 is input to the gate terminals of the N channel MOS transistor 407 and the P channel MOS transistor 416. Is entered.

  Further, a complement signal φ1N is input to the gate terminal of P channel MOS transistor 411, and a two-phase clock signal φ1 is input to the gate terminal of N channel MOS transistor 404. Complement signal φ2N is input to the terminal, and two-phase clock signal φ2 is input to the gate terminal of N-channel MOS transistor 408.

  A signal D1C output from a clocked CMOS inverter constituted by N channel MOS transistors 403 and 404 and P channel MOS transistors 411 and 412; N channel MOS transistors 407 and 408; P channel MOS transistors 415 and 416; The signal D0C output from the clocked CMOS inverter constituted by is wired-or connected to each other and is input to the data output terminal Q shown in FIG.

  Such a flip-flop circuit EF receives the non-overlapping two-phase clock signals φ1 and φ2 output from the phase conversion circuit 302 and operates according to the timing as shown in FIG.

  The first stage of FIG. 2 shows the signal waveform at the data input terminal D shown in FIG. 20A, and the second stage of FIG. 2 shows the signal waveform at the clock input terminal CK of the phase conversion circuit 302. FIG. 11 shows the signal waveform at the data output terminal Q shown in FIG. In the figure, a data string composed of a, b, c, d, and e is input to the data input terminal D, and a clock signal CK (differential clock signal HD-CLK-P is synchronized with each data input. , HD-CLK-N) shows that the rising from the low level to the high level and the falling from the high level to the low level are repeated.

  The third stage of FIG. 3 shows the signal waveform of the two-phase clock signal φ1 output from the phase conversion circuit 302. The fourth stage of FIG. 4 shows the two-phase clock signal φ2 output from the phase conversion circuit 302. 5 shows the signal waveform of the complement signal φ1N obtained by logically inverting the two-phase clock signal φ1, and the sixth row shows the logical waveform of the two-phase clock signal φ2. The signal waveform of the completed complement signal φ2N is shown.

  Furthermore, the 7th to 10th stages of FIG. 7 show signal waveforms output from the clocked CMOS inverters shown in FIG. 7 shows the signal waveform of the signal D1B output from the clocked CMOS inverter composed of the N-channel MOS transistors 401 and 402 and the P-channel MOS transistors 409 and 410. The eye shows the signal waveform of the signal D1C output from the clocked CMOS inverter constituted by the N-channel MOS transistors 403 and 404 and the P-channel MOS transistors 411 and 412. The signal waveform of the signal D0B output from the clocked CMOS inverter constituted by the MOS transistors 405 and 406 and the P-channel MOS transistors 413 and 414 is shown. In the 10th stage of the figure, the N-channel MOS transistors 407 and 408 and P channel MOS transistor Shows a signal waveform of the signal D0C output from the clocked CMOS inverters configured by the Njisuta 415, 416. Actually, the signals D1C and D0C are wired-or connected as described above, but are distinguished here for convenience.

  First, in the flip-flop circuit EF, a data string composed of a, b, c, d, and e is input to the data input terminal D, and the level of the clock signal CK transitions in synchronization therewith. At this time, in the flip-flop circuit EF, the two-phase clock signals φ1 and φ2 and the complement signals φ1N and φ2N are input.

  Here, in the flip-flop circuit EF, when the data signal a is applied to the data input terminal D when the clock signal CK is at the low level, the two-phase clock signal φ2 is active, so that the N-channel MOS transistor 401 , 402 and the P channel MOS transistors 409, 410, the data a is transmitted to the output of the clocked CMOS inverter and is output as the signal D1B. In FIG. 21, “a” is simply described in the signal waveform of the signal D1B. However, the data “a” input to the data input terminal D is logically inverted. Similarly, the data as the signal input to the data input terminal D is logically inverted.

  Subsequently, in the flip-flop circuit EF, when the clock signal CK becomes high level, the two-phase clock signal φ2 becomes low level, and further, the two-phase clock signal φ1 changes to high level. In the flip-flop circuit EF, when the two-phase clock signal φ2 becomes low level, the output of the clocked CMOS inverter formed by the N-channel MOS transistors 401 and 402 and the P-channel MOS transistors 409 and 410 is turned off. Since there is a capacitance component at the output or the input of the next-stage inverter, the clocked CMOS inverter maintains the previously output potential level by the electric charge stored therein. In FIG. 21, this state is indicated by a one-dot chain line in the signal waveform, indicating that the signal is in a high impedance state and the potential level output before that is held by the accumulated charge. .

  Thus, in the flip-flop circuit EF, when a data string composed of a, b, c, d, e is input to the data input terminal D, the signal D1B is also a, b, c, d, A data string consisting of e is obtained.

  Similarly, in the flip-flop circuit EF, when the two-phase clock signal φ1 is at the high level, the output of the clocked CMOS inverter constituted by the N channel MOS transistors 405 and 406 and the P channel MOS transistors 413 and 414 is obtained. The data string consisting of a, b, c, d, and e input to the data input terminal D is transmitted to the next stage. In the flip-flop circuit EF, when the two-phase clock signal φ1 becomes low level, the output of the clocked CMOS inverter constituted by the N channel MOS transistors 405 and 406 and the P channel MOS transistors 413 and 414 is turned off. However, since there is a capacitance component at the output or the input of the inverter at the next stage, the clocked CMOS inverter maintains the previously output potential level by the electric charge stored therein.

  As described above, in the flip-flop circuit EF, when a data string composed of a, b, c, d, and e is input to the data input terminal D, the signal D0B has a timing different from that of the signal D1B. A data string composed of a, b, c, d, and e is obtained.

  Further, in flip-flop circuit EF, similarly, signal D1C output from the clocked CMOS inverter constituted by N-channel MOS transistors 403 and 404 and P-channel MOS transistors 411 and 412 and N-channel MOS transistor 407 408 and P channel MOS transistors 415 and 416, a signal D0C output from the clocked CMOS inverter is obtained.

  Here, as is clear from FIG. 21, the signals D1C and D0C are not active at the same time, and when one is active, the other is in a charge storage state due to a high impedance state. Therefore, in the flip-flop circuit EF, a data string composed of a, b, c, d, and e synchronized with the clock signal CK is obtained as a signal at the data output terminal Q obtained by wired OR connection of these signals D1C and D0C. Will be generated.

  As described above, in the flip-flop circuit EF, when the data strings a, b, c, d, and e are input to the data input terminal D, the rising edges of the differential clock signals HD-CLK-P and HD-CLK-N. The data strings a, b, c, d, and e are sequentially switched and output at both the falling and falling edges. In other words, in the flip-flop circuit EF, it is possible to transfer data at both rising and falling edges of the differential clock signals HD-CLK-P and HD-CLK-N.

  At this time, in the LED head 19, as described above, between the adjacent driving ICs, the differential clock signals HD-CLK-P and HD-CLK-N and the clock input terminals CLKP and CLKN in the driving ICs. The connection is switched, but the effect of this is that the rising and falling of the differential clock signals HD-CLK-P and HD-CLK-N change when the connection is switched. Accordingly, the LED head 19 is configured to be operable at both the rising and falling edges of the differential clock signals HD-CLK-P and HD-CLK-N as the flip-flop circuit EF. It can be operated.

As described above, in the LED head 19 of the printing apparatus shown as the third embodiment of the present invention, the differential clock signal lines 101 _P and 101 _N are not crossed on the printed circuit board 100 on the same plane. In other words, a circuit in which a pair of differential clock signal lines 101 _P and 101 _N are alternately crossed for each adjacent driving IC can be realized on the circuit diagram. . At this time, in the LED head 19, although the differential clock signal lines 101 _P and 101 _N cross each other alternately for each driving IC on the circuit diagram, the difference in operation timing does not surface, There is no need to provide a circuit for correcting the influence of the intersection of the differential clock signal lines 101 _P and 101 _N for each driving IC.

In the LED head 19, the differential clock signal lines 101 _P and 101 _N can be arranged at equal intervals so as to obtain a predetermined characteristic impedance, and due to variations in design or manufacturing of the driving IC. Even if the capacitances at the two clock input terminals CLKP and CLKN are slightly different, the same number of clock input terminals CLKP and CLKN are connected to the differential clock signal lines 101 _P and 101 _N. The difference in load capacitance between the differential clock signal lines 101 _P and 101 _N is averaged and becomes substantially negligible. As a result, in the LED head 19, the rise time and the fall time are different between the differential clock signals HD-CLK-P and HD-CLK-N, and the operating frequency of the shift register circuit cannot be increased. It can be avoided. Therefore, in the LED head 19, the signal quality of the differential clock signals HD-CLK-P and HD-CLK-N can be improved, and the reliability during data transfer can be improved.

  Furthermore, in the LED head 19, since it is not necessary to provide a select terminal that has been unavoidable in the past, the wiring area on the printed wiring board 100 can be reduced, and the number of bonding wires can be reduced. In addition, the printed wiring board 100 can be reduced in size, and the cost can be reduced accordingly.

  Furthermore, the LED head 19 includes a flip-flop circuit EF composed of a clocked CMOS inverter configured by combining an N-channel MOS transistor and a P-channel MOS transistor, and a phase conversion circuit 302, thereby providing a flip-flop circuit EF. Since there is no need to provide a selector circuit unlike the flip-flop circuit DF shown as the first embodiment, the chip size of the drive IC can be further reduced, and the cost can be further reduced.

  Furthermore, in the LED head 19, the frequency of the differential clock signals HD-CLK-P and HD-CLK-N can be substantially reduced to ½ times that of the conventional case. The influence can also be suppressed.

  Next, a printing apparatus shown as the fourth embodiment will be described.

  In the printing apparatus shown as the fourth embodiment, the phase conversion circuit 302 in the printing apparatus shown as the second embodiment or the third embodiment is configured differently. Therefore, in the description of the fourth embodiment, the same components as those in the first to third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. To do.

  In the printing apparatus shown as the fourth embodiment, the phase conversion circuit 302 provided in the LED head 19 is as shown in FIG.

  That is, the phase conversion circuit 302 includes an N-channel MOS transistor 451 and a P in front of the negative OR circuit 372, in addition to the inverter 370, the two NOR circuits 371 and 372, and the two buffer circuits 373 and 374. The transmission gate is formed of a channel MOS transistor 452. In this transmission gate, the power supply voltage VDD is applied to the gate terminal of the N channel MOS transistor 451, and the gate terminal of the P channel MOS transistor 452 is connected to the ground.

  In such a phase conversion circuit 302, the differential clock signals HD-CLK-P and HD-CLK-N input to the clock input terminal CK are transmitted to the transmission gate composed of the N-channel MOS transistor 451 and the P-channel MOS transistor 452. While being input, it is input to the input terminal of the inverter 370. Further, the output of the transmission gate is input to one input terminal of the negative OR circuit 372, and the output of the inverter 370 is input to one input terminal of the negative OR circuit 371.

  Further, the output of the negative logical sum circuit 372 is input to the buffer circuit 373, while the output of the negative logical sum circuit 371 is input to the buffer circuit 374. The output of the buffer circuit 373 is output to the flip-flop circuit EF as one clock signal φ2 of the two-phase clock signals, and is input to the other input terminal of the NOR circuit 371. The output of the buffer circuit 374 is output to the flip-flop circuit EF as the other clock signal φ1 of the two-phase clock signals, and is also input to the other input terminal of the negative OR circuit 372.

  Such a phase conversion circuit 302 operates according to the timing shown in FIG. The first stage of the figure shows the signal waveforms of the differential clock signals HD-CLK-P and HD-CLK-N inputted to the clock input terminal CK. The second stage of FIG. FIG. 3 shows the signal waveform output from the inverter 370, and FIG. 4 shows the signal waveform output from the negative OR circuit 372. FIG. 5 shows the signal waveform of the two-phase clock signal φ2, FIG. 6 shows the signal waveform output from the NOR circuit 371, and FIG. The signal waveform of the clock signal φ1 is shown.

  First, in the phase conversion circuit 302, when the differential clock signals HD-CLK-P and HD-CLK-N are input to the clock input terminal CK, the clock signal CK1 logically inverted by the inverter 370 is generated. Therefore, in the phase conversion circuit 302, when the level of the clock input terminal CK is high, the low-level signal NOR2 is output from the negative OR circuit 372, and is the output of the buffer circuit 373 that receives this signal. The two-phase clock signal φ2 is also at a low level. At this time, in the phase conversion circuit 302, the clock signal CK1 output from the inverter 370 transits from the high level to the low level, and the clock signal CK1 is input to the negative OR circuit 371. In the phase conversion circuit 302, since the two-phase clock signal φ2 is input to the negative OR circuit 371, after waiting for the two-phase clock signal φ2 to become low level, A high level signal NOR1 is output. In the phase conversion circuit 302, the signal NOR1 output from the NOR circuit 371 is input to the buffer circuit 374, and the two-phase clock signal φ1 transitions from the low level to the high level.

  Subsequently, in the phase conversion circuit 302, when the level of the clock input terminal CK transitions from a high level to a low level, a high level clock signal CK1 logically inverted by the inverter 370 is generated. As a result, in the phase conversion circuit 302, the signal NOR1 output from the NOR circuit 371 transits from the high level to the low level, and the two-phase clock signal φ1 that is the output of the buffer circuit 374 to which the signal NOR1 is input is high. Transition from level to low level. At this time, in the phase conversion circuit 302, the differential clock signals HD-CLK-P and HD-CLK-N are delayed by the transmission gate, and the clock signal CK2 that has previously transitioned to the low level is the negative OR circuit 372. Since the signal is input to one input terminal, the signal output from the NOR circuit 372 in response to the transition of the high-level two-phase clock signal φ1 input to the other input terminal to the low level. NOR2 changes to a high level, and the two-phase clock signal φ2 that is the output of the buffer circuit 373 that receives this NOR2 also goes to a high level.

The phase conversion circuit 302 generates the two-phase clock signals φ1 and φ2 that do not overlap each other for each input of the differential clock signals HD-CLK-P and HD-CLK-N by performing such an operation. It will be. Here, the pulse widths T _w1 and T _w2 of the two-phase clock signals φ1 and φ2 can be made equal by setting the delay time by the inverter 370 and the delay time by the transmission gate to the same level. In the same figure, the rising and falling timings of the differential clock signals HD-CLK-P and HD-CLK-N are indicated by vertical broken lines, and these differential clock signals HD-CLK-P and HD- Although the delay times from the rising and falling edges of CLK-N to the output of the two-phase clock signals φ1 and φ2 are shown as T _d1 and T _d2 , these delay times T _d1 and T _d2 are Further, the delay time by the inverter 370 and the delay time by the transmission gate can be set to be equal to each other.

  In such a phase conversion circuit 302, the difference in phase difference between the generated two-phase clock signals φ1 and φ2 with respect to the input differential clock signals HD-CLK-P and HD-CLK-N is reduced. be able to. That is, in the phase conversion circuit 302, there is no difference in timing due to the difference between the rising timing and falling timing of the differential clock signals HD-CLK-P and HD-CLK-N, and 2 for the flip-flop circuit EF. It is not necessary to give excessive setup time and hold time to the input of the phase clock signals φ1 and φ2, and the circuit operation can be speeded up.

  As described above, in the LED head 19 of the printing apparatus shown as the fourth embodiment of the present invention, the delay time by the inverter 370 and the delay time by the transmission gate are set to the same level, so that the second In addition to the effects described in the embodiment and the third embodiment, an effect that the circuit operation can be speeded up can be realized.

  Next, a printing apparatus shown as the fifth embodiment will be described.

  In the printing apparatus shown as the fifth embodiment, the phase conversion circuit 302 in the printing apparatus shown as the second to fourth embodiments has a different configuration. Therefore, in the description of the fifth embodiment, the same reference numerals are given to the same configurations as those in the first to fourth embodiments, and the detailed description thereof will be omitted. To do.

  In the printing apparatus shown as the fifth embodiment, the phase conversion circuit 302 provided in the LED head 19 is as shown in FIG.

  That is, the phase conversion circuit 302 includes the inverter 370, the two NAND circuits 371 and 372, the two buffer circuits 373 and 374, and the transmission gate including the N-channel MOS transistor 451 and the P-channel MOS transistor 452. It is composed of four inverters 501, 502, 503, and 504 and two NAND circuits 505 and 506.

  In such a phase conversion circuit 302, the differential clock signals HD-CLK-P and HD-CLK-N input to the clock input terminal CK are transmitted to the transmission gate composed of the N-channel MOS transistor 451 and the P-channel MOS transistor 452. While being input, it is input to the input terminal of the inverter 370. Further, the output of the transmission gate is input to one input terminal of the negative OR circuit 372, and the output of the inverter 370 is input to one input terminal of the negative OR circuit 371.

  Further, the output of the negative logical sum circuit 372 is input to the buffer circuit 373, while the output of the negative logical sum circuit 371 is input to the buffer circuit 374. The output of the buffer circuit 373 is output to the flip-flop circuit EF as one clock signal φ2 of the two-phase clock signals, and also input to the input terminals of the inverters 501 and 504, respectively. The output of the buffer circuit 374 is output to the flip-flop circuit EF as the other clock signal φ1 of the two-phase clock signals, and is also input to the input terminals of the inverters 502 and 503, respectively.

  Furthermore, the output of the inverter 501 is output to the flip-flop circuit EF as a complement signal φ2N obtained by logically inverting the two-phase clock signal φ2, and also input to one input terminal of the negative AND circuit 506. Further, the output of the inverter 502 is output to the flip-flop circuit EF as a complement signal φ1N obtained by logically inverting the two-phase clock signal φ1 and also input to one input terminal of the NAND circuit 505.

  Further, the output of the inverter 503 is input to the other input terminal of the negative logical product circuit 505, while the output of the inverter 504 is input to the other input terminal of the negative logical product circuit 506. The output of the negative logical product circuit 505 is input to the other input terminal of the negative logical sum circuit 372, while the output of the negative logical product circuit 506 is input to the other input terminal of the negative logical sum circuit 371. The

  Such a phase conversion circuit 302 operates according to the timing shown in FIG. The first stage of the figure shows the signal waveforms of the differential clock signals HD-CLK-P and HD-CLK-N inputted to the clock input terminal CK. The second stage of FIG. FIG. 3 shows the signal waveform output from the inverter 370, and FIG. 4 shows the signal waveform output from the negative OR circuit 372. The 5th stage shows the signal waveform of the two-phase clock signal φ2, the 6th stage shows the signal waveform of the complement signal φ2N, and the 7th stage is outputted from the inverter 504. FIG. 8 shows the signal waveform output from the negative logical product circuit 506, and FIG. 9 shows the signal waveform output from the negative logical sum circuit 371. In FIG. 10, the signal of the two-phase clock signal φ1 is shown. 11 shows the signal waveform of the complement signal φ1N, FIG. 12 shows the signal waveform output from the inverter 503, and FIG. 13 shows the negative waveform. The signal waveform output from the AND circuit 505 is shown.

  First, in the phase conversion circuit 302, when the differential clock signals HD-CLK-P and HD-CLK-N are input to the clock input terminal CK, the clock signal CK1 logically inverted by the inverter 370 is generated. Therefore, in the phase conversion circuit 302, when the level of the clock input terminal CK is high, the low-level signal NOR2 is output from the negative OR circuit 372, and is the output of the buffer circuit 373 that receives this signal. The two-phase clock signal φ2 is also at a low level. At this time, in the phase conversion circuit 302, the two-phase clock signal φ2 is logically inverted by the inverter 501 and output as a complement signal φ2N. At this time, in the phase conversion circuit 302, the signal IV2 output from the inverter 504 and the complement signal φ2N are input to the NAND circuit 506, and the signal change of the two-phase clock signal φ2 and the complement signal φ2N is caused. A delayed signal NAND2 is generated. In the phase conversion circuit 302, the signal NAND2 is input to the NAND circuit 371, and transits from the high level to the low level.

  At this time, in the phase conversion circuit 302, since the two-phase clock signal φ2 that is the output of the buffer circuit 373 transitions from a high level to a low level, after waiting for the complement signal φ2N to become a high level, A high level signal NOR1 is output from the NOR circuit 371. In the phase conversion circuit 302, the signal NOR1 output from the NOR circuit 371 is input to the buffer circuit 374, the two-phase clock signal φ1 transitions from the low level to the high level, and the two-phase clock signal φ1 is logically inverted by the inverter 502 and output as a complement signal φ1N. At this time, in the phase conversion circuit 302, the signal IV1 and the complement signal φ1N output from the inverter 503 are input to the NAND circuit 505, and the signal change of the two-phase clock signal φ1 and the complement signal φ1N is caused. A delayed signal NAND1 is generated. In the phase conversion circuit 302, the signal NAND1 is input to the NOR circuit 372, and transits from the high level to the low level.

  Subsequently, in the phase conversion circuit 302, when the level of the clock input terminal CK transitions from a high level to a low level, a high level clock signal CK1 logically inverted by the inverter 370 is generated. As a result, in the phase conversion circuit 302, the signal NOR1 output from the NOR circuit 371 transits from the high level to the low level, and the two-phase clock signal φ1 that is the output of the buffer circuit 374 to which the signal NOR1 is input is high. Transition from level to low level. At this time, in the phase conversion circuit 302, the differential clock signals HD-CLK-P and HD-CLK-N are delayed by the transmission gate, and the clock signal CK2 that has previously transitioned to the low level is the negative OR circuit 372. Since the signal is input to one input terminal, the signal output from the NOR circuit 372 in response to the transition of the high-level two-phase clock signal φ1 input to the other input terminal to the low level. NOR2 changes to a high level, and the two-phase clock signal φ2 that is the output of the buffer circuit 373 that receives this NOR2 also goes to a high level.

  The phase conversion circuit 302 generates the two-phase clock signals φ1 and φ2 that do not overlap each other for each input of the differential clock signals HD-CLK-P and HD-CLK-N by performing such an operation. It will be. Here, in the figure, the region in which either the two-phase clock signal φ1 or the complement signal φ1N, or the two-phase clock signal φ2 or the complement signal φ2N is active is indicated by a gray band. From the figure, it can be seen that in the transition process of the clock signal, a region in which both the two-phase clock signal φ1 or the complement signal φ1N, or the two-phase clock signal φ2 or the complement signal φ2N is inactive is inserted.

  Here, in the second to fourth embodiments described above, the two-phase clock signals φ1 and φ2 are generated, and the complement signals φ1N and φ2N for the two-phase clock signals φ1 and φ2 are generated. When the delay time due to the logic inversion means increases, for example, when the timing when the complement signal φ1N is active and the timing when the two-phase clock signal φ2 is active overlap, There is a possibility of data slipping between the first-stage latch circuit and the second-stage latch circuit in the flip-flop circuit EF to which the two-phase clock signal φ2 and the complement signal φ1N are input. Such slip-through of data may occur similarly when, for example, the timing at which the complement signal φ2N is active overlaps with the timing at which the two-phase clock signal φ1 is active.

  In the phase conversion circuit, in order to avoid such an undesirable phenomenon, it is necessary to increase the pause time between the two-phase clock signals φ1 and φ2, but on the other hand, by setting an excessive timing margin, The overall delay time may become too large, and the operating frequency may not be increased.

  On the other hand, in the phase conversion circuit 302, the two-phase clock signal φ1 or the complement signal φ1N, or the two-phase clock signal φ2 or An area in which any of the complement signals φ2N is inactive can be inserted, and data slipping through the flip-flop circuit EF can be avoided.

  As described above, in the LED head 19 of the printing apparatus shown as the fifth embodiment of the present invention, it is possible to avoid data passing through the flip-flop circuit EF. Therefore, in this LED head 19, in addition to the effects shown in the second to fourth embodiments, it is necessary to set an excessive timing margin in the pause time between the two-phase clock signals φ1 and φ2. The effect that it becomes easy to raise the operating frequency is also realizable.

  Next, a printing apparatus shown as the sixth embodiment will be described.

  The printing apparatus shown as the sixth embodiment is different from the flip-flop circuit EF in the printing apparatus shown as the second to fifth embodiments. Accordingly, in the description of the sixth embodiment, the same components as those in the first to fifth embodiments will be denoted by the same reference numerals, and detailed description thereof will be omitted. To do.

In the printing apparatus shown as the sixth embodiment, the flip-flop circuit EF provided in the LED head 19 is as shown in FIG. FIG. 6A shows circuit symbols, and the flip-flop circuits EFA ₁ ,..., EFA ₄₈ , EFB ₁ ,..., EFB ₄₈ , EFC ₁ ,. ₄₈ , EFD ₁ ,..., EFD ₄₈ . FIG. 2B shows the internal configuration.

  That is, the flip-flop circuit EF includes seven N-channel MOS transistors 551, 552, 553, 554, 555, 557, and 559 and three P-channel MOS transistors 556, 558, and 560.

  Among these, N channel MOS transistor 555 and P channel MOS transistor 556, N channel MOS transistor 557 and P channel MOS transistor 558, and N channel MOS transistor 559 and P channel MOS transistor 560 each constitute an inverter.

  The gate terminals of the N channel MOS transistors 551 and 553 are connected to the data input terminal D shown in FIG. The two-phase clock signal φ2 output from the phase conversion circuit 302 is input to the gate terminals of the N-channel MOS transistors 551 and 554, respectively, and the gate terminals of the N-channel MOS transistors 552 and 553 are respectively input to the gate terminals. The two-phase clock signal φ1 output from the phase conversion circuit 302 is input.

  Signal D1A output from N-channel MOS transistor 551 is input to an inverter constituted by N-channel MOS transistor 555 and P-channel MOS transistor 556, and signal D1B output from this inverter is an N-channel MOS transistor. 552 is input. Further, signal D0A output from N channel MOS transistor 553 is input to an inverter constituted by N channel MOS transistor 557 and P channel MOS transistor 558, and signal D0B output from this inverter is an N channel MOS transistor. It is input to 554.

  Furthermore, the signal D1C output from the N channel MOS transistor 552 and the signal D0C output from the N channel MOS transistor 554 are connected to each other by a wired OR connection, and are configured by the N channel MOS transistor 559 and the P channel MOS transistor 560. Input to the inverter. The output of the inverter formed by N channel MOS transistor 559 and P channel MOS transistor 560 is connected to data output terminal Q shown in FIG.

  Such a flip-flop circuit EF receives the non-overlapping two-phase clock signals φ1 and φ2 output from the phase conversion circuit 302 and operates according to the timing as shown in FIG.

  The first stage of FIG. 2 shows the signal waveform at the data input terminal D shown in FIG. 26A, and the second stage of FIG. 2 shows the signal waveform at the clock input terminal CK of the phase conversion circuit 302. FIG. 12 shows the signal waveform at the data output terminal Q shown in FIG. In the figure, a data string composed of a, b, c, d, and e is input to the data input terminal D, and a clock signal CK (differential clock signal HD-CLK-P is synchronized with each data input. , HD-CLK-N) shows that the rising from the low level to the high level and the falling from the high level to the low level are repeated.

  The third stage of FIG. 3 shows the signal waveform of the two-phase clock signal φ1 output from the phase conversion circuit 302. The fourth stage of FIG. 4 shows the two-phase clock signal φ2 output from the phase conversion circuit 302. The signal waveform is shown.

  Further, the fifth to eleventh stages of FIG. 5 show signal waveforms output from the respective N-channel MOS transistors and inverters shown in FIG. That is, the fifth stage of FIG. 5 shows the signal waveform of the signal D1A output from the N-channel MOS transistor 551, and the sixth stage of FIG. 6 is composed of an N-channel MOS transistor 555 and a P-channel MOS transistor 556. The signal waveform of the signal D1B output from the inverter is shown. The signal waveform of the signal D1C output from the N channel MOS transistor 552 is shown in the seventh row of FIG. The signal waveform of the signal D0A output from the transistor 553 is shown. The signal waveform of the signal D0B output from the inverter constituted by the N-channel MOS transistor 557 and the P-channel MOS transistor 558 is shown in the ninth stage of FIG. In the 10th stage of the figure, the output is from the N channel MOS transistor 554. It shows a signal waveform of the signal DOC. Actually, the signals D1C and D0C are wired-or connected as described above, but are distinguished here for convenience. 11 shows the signal waveform of the signal DC after wired OR input to the inverter constituted by the N channel MOS transistor 559 and the P channel MOS transistor 560.

  First, in the flip-flop circuit EF, a data string composed of a, b, c, d, and e is input to the data input terminal D, and the level of the clock signal CK transitions in synchronization therewith. At this time, the two-phase clock signals φ1 and φ2 are input to the flip-flop circuit EF.

  Here, in the flip-flop circuit EF, when the data signal a is applied to the data input terminal D when the clock signal CK is at a low level, the two-phase clock signal φ2 is active. Since data a is transmitted to the output of, and this signal is logically inverted by an inverter constituted by N channel MOS transistor 555 and P channel MOS transistor 556, data a is output as signal D1B. Become. In FIG. 27, “a” is simply described in the signal waveform of the signal D1B, but it is precisely the logical inversion of the data a as the signal D1A. This is a logically inverted version of the data as D1A.

  Subsequently, in the flip-flop circuit EF, when the clock signal CK becomes high level, the two-phase clock signal φ2 becomes low level, and further, the two-phase clock signal φ1 changes to high level. In the flip-flop circuit EF, when the two-phase clock signal φ2 becomes low level, the N-channel MOS transistor 551 is turned off. However, since there is a capacitance component at the output or the input of the next-stage inverter, The N channel MOS transistor 551 maintains the previously outputted potential level by the electric charge stored in. In FIG. 27, such a state is indicated by a one-dot chain line in the signal waveform, indicating that the signal is in a high impedance state and the potential level output before that is held by the accumulated charge. .

  Thus, in the flip-flop circuit EF, when a data string composed of a, b, c, d, e is input to the data input terminal D, the signals D1A, D1B are also a, b, c, A data string consisting of d and e is obtained.

  Similarly, in the flip-flop circuit EF, when the two-phase clock signal φ1 is at a high level, the N-channel MOS transistor 553 is turned on and a, b, c, d, e inputted to the data input terminal D are turned on. Is transmitted to the next stage. In the flip-flop circuit EF, when the two-phase clock signal φ1 becomes low level, the N-channel MOS transistor 553 is turned off, but there is a capacitance component at the output or the input of the next-stage inverter. The N channel MOS transistor 553 maintains the previously output potential level due to the electric charge stored therein.

  Thus, in the flip-flop circuit EF, when a data string composed of a, b, c, d, and e is input to the data input terminal D, the timing is different from that of the signals D1A, D1B, and D1C. As the signals D0A, D0B, and D0C, a data string composed of a, b, c, d, and e is obtained.

  Here, as is apparent from FIG. 27, the signals D1C and D0C do not become active at the same time. When one of them is active, the other becomes a charge accumulation state due to a high impedance state. Therefore, in the flip-flop circuit EF, a data string composed of a, b, c, d and e synchronized with the clock signal CK is generated as a signal DC obtained by wired-OR connection of these signals D1C and D0C. become. In the flip-flop circuit EF, this signal DC is logically inverted by an inverter constituted by an N-channel MOS transistor 559 and a P-channel MOS transistor 560, so that a, b, c inputted to the data input terminal D are obtained. , D, and e, the data string consisting of a, b, c, d, and e, whose logic is the same, is output from the data output terminal Q.

  As described above, in the flip-flop circuit EF, when the data strings a, b, c, d, and e are input to the data input terminal D, the rising edges of the differential clock signals HD-CLK-P and HD-CLK-N. The data strings a, b, c, d, and e are sequentially switched and output at both the falling and falling edges. In other words, in the flip-flop circuit EF, it is possible to transfer data at both rising and falling edges of the differential clock signals HD-CLK-P and HD-CLK-N.

  At this time, in the LED head 19, as described above, between the adjacent driving ICs, the differential clock signals HD-CLK-P and HD-CLK-N and the clock input terminals CLKP and CLKN in the driving ICs. The connection is switched, but the effect of this is that the rising and falling of the differential clock signals HD-CLK-P and HD-CLK-N change when the connection is switched. Accordingly, the LED head 19 is configured to be operable at both the rising and falling edges of the differential clock signals HD-CLK-P and HD-CLK-N as the flip-flop circuit EF. It can be operated.

  As described above, in the LED head 19 of the printing apparatus shown as the sixth embodiment of the present invention, the number of elements can be reduced compared to the flip-flop circuit EF shown as the second embodiment, In addition to the effect shown as the second embodiment, the chip size of the driving IC can be further reduced, and the effect of contributing to further cost reduction can be realized.

  Next, a printing apparatus shown as the seventh embodiment will be described.

  In the printing apparatus shown as the seventh embodiment, the flip-flop circuit EF and the phase conversion circuit 302 in the printing apparatus shown as the second to sixth embodiments are configured differently. Therefore, in the description of the seventh embodiment, the same reference numerals are given to the same configurations as those in the first to sixth embodiments, and the detailed description thereof is omitted. To do.

FIG. 28 shows the configuration of the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ in the LED head 19. That is, 48 drive _{IC DRV 1, DRV 2, ···} , DRV 26 are respectively, 48 flip-flop circuits connected in cascade _{EFA 1,} EFA 2, · · ·, and _{EFA 48,} cascaded , EFB ₄₈ , 48 flip-flop circuits EFC ₁ , EFC ₂ ,..., EFC _48, and ₄₈ flip-flops cascade-connected to the flip-flop circuit EFB ₁ , EFB ₂ ,. flop circuit _{EFD 1, EFD 2, ···,} and an _{EFD 48.}

Flip-flop circuit _{EFA 1, ···, EFA 48,} EFB 1, ···, EFB 48, EFC 1, ···, EFC 48, EFD 1, ···, EFD 48 , respectively, as described above The differential clock signals HD-CLK-P and HD-CLK-N operate based on both rising and falling edges, and are configured to be able to transfer data. The data input terminal D of the flip-flop circuit EFA ₁ is connected to the data input terminal DATAI 0 of the drive IC, and the output from the flip-flop circuit EFA ₄₈ is connected to the data output terminal DATAO 0 of the drive IC. Similarly, the data input terminals D of the flip-flop circuits EFB ₁ , EFC ₁ , EFD ₁ are respectively connected to the data input terminals DATAI 1, DATAI 2, DATAI 3 of the drive IC, and the flip-flop circuits EFB ₄₈ , EFC ₄₈ , EFD ₄₈ Are connected to the data output terminals DATAO1, DATAO2, and DATAO3 of the driving IC, respectively. Accordingly, the flip-flop circuit _{EFA 1, ···, EFA 48,} EFB 1, ···, EFB 48, EFC 1, ···, EFC 48, EFD 1, ···, EFD 48 , respectively, 48-stage The shift register circuit is configured.

In addition, the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ are disclosed in Japanese Patent Application Laid-Open No. 2000-108407 previously filed by the applicant of the present application in place of the control voltage generation circuit 157 described above. A control voltage generation circuit 603 provided with the above circuit means. That is, the control voltage generation circuit 603 has a signal input terminal STBY for inputting a standby mode instruction signal STBY-P supplied from an external control circuit, and a quiescent current path based on the standby mode instruction signal STBY-P. Switching circuit means for shutting off or short-circuiting is provided.

  This standby mode is for reducing the power consumption of the LED head 19 during standby, but the function of switching to the standby mode can also be used in the IDDq test during the manufacturing test of the drive IC. In other words, in the IDDq test, failure factors that are difficult to find only with a digital circuit function test such as disconnection of wiring in an IC chip and short-circuiting between adjacent wirings, which are defects peculiar to the semiconductor manufacturing process, are transferred to the standby mode. By detecting a minute increase in the power supply current using the switching function, it can be found efficiently.

The drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ each have a function of switching to the standby mode, the clock input circuit 601 replacing the clock input circuit 151 and the phase conversion circuit 602 replacing the phase conversion circuit 302. Also provided. That is, each of the clock input circuit 601 and the phase conversion circuit 602 has a signal input terminal STBY that inputs a standby mode instruction signal STBY-P. Phase conversion circuit 602 is configured to be able to control the signal values of two-phase clock signals φ1 and φ2 that are the outputs when the standby mode is set.

  Specifically, as shown in FIG. 29, the phase conversion circuit 602 includes an inverter 370, two negative OR circuits 371 and 372, and a transmission gate composed of an N-channel MOS transistor 451 and a P-channel MOS transistor 452. In addition, it is composed of two OR circuits 611 and 612 to which a standby mode instruction signal STBY-P is input to one input terminal.

  In such a phase conversion circuit 602, the differential clock signals HD-CLK-P and HD-CLK-N input to the clock input terminal CK are transmitted to the transmission gate composed of the N-channel MOS transistor 451 and the P-channel MOS transistor 452. While being input, it is input to the input terminal of the inverter 370. Further, the output of the transmission gate is input to one input terminal of the negative OR circuit 372, and the output of the inverter 370 is input to one input terminal of the negative OR circuit 371.

  Further, the output of the negative OR circuit 372 is input to one input terminal of the logical sum circuit 612, while the output of the negative OR circuit 371 is input to one input terminal of the logical sum circuit 611. The output of the OR circuit 612 is output to the flip-flop circuit EF as one clock signal φ2 of the two-phase clock signals, and is input to the other input terminal of the NOR circuit 371. The output of the OR circuit 611 is output to the flip-flop circuit EF as the other clock signal φ1 of the two-phase clock signals, and is also input to the other input terminal of the NOT OR circuit 372.

The flip-flop circuit EF is configured as shown in FIG. FIG. 5A shows circuit symbols, which are flip-flop circuits EFA ₁ ,..., EFA ₄₈ , EFB ₁ ,..., EFB ₄₈ , EFC ₁ ,. ₄₈ , EFD ₁ ,..., EFD ₄₈ . FIG. 2B shows the internal configuration.

  That is, flip-flop circuit EF includes an inverter constituted by N channel MOS transistor 359 and P channel MOS transistor 360 shown in FIG. 16, and an inverter constituted by N channel MOS transistor 361 and P channel MOS transistor 362. , And an N channel MOS transistor 363 and a P channel MOS transistor 364, and four N channel MOS transistors 621, 622, 623, 624 and one P channel MOS transistor 625.

  One terminal of each of the N-channel MOS transistors 621 and 623 is connected to a data input terminal D shown in FIG. The two-phase clock signal φ2 output from the phase conversion circuit 602 is input to the gate terminals of the N-channel MOS transistors 621 and 624, respectively, and the gate terminals of the N-channel MOS transistors 622 and 623 are respectively connected to the gate terminals. The two-phase clock signal φ1 output from the phase conversion circuit 302 is input.

  The signal D1A output from the N-channel MOS transistor 621 is input to an inverter constituted by the N-channel MOS transistor 359 and the P-channel MOS transistor 360. The signal D1B output from the inverter is an N-channel MOS transistor. It is input to 622. Further, signal D0A output from N channel MOS transistor 623 is input to an inverter constituted by N channel MOS transistor 361 and P channel MOS transistor 362, and signal D0B output from this inverter is an N channel MOS transistor. 624 is input.

  Furthermore, the signal D1C output from the N-channel MOS transistor 622 and the signal D0C output from the N-channel MOS transistor 624 are connected to each other by a wired OR connection, and are configured by the N-channel MOS transistor 363 and the P-channel MOS transistor 364. Input to the inverter. The output of the inverter constituted by the N channel MOS transistor 363 and the P channel MOS transistor 364 is connected to the data output terminal Q shown in FIG. The signal DC after wired-or connection input to the inverter constituted by the N-channel MOS transistor 363 and the P-channel MOS transistor 364 is also input to the drain terminal of the P-channel MOS transistor 625. The power supply voltage VDD is applied to the source terminal of the P-channel MOS transistor 625, and the output of the inverter constituted by the N-channel MOS transistor 363 and the P-channel MOS transistor 364 is input to the gate terminal.

  Here, FIG. 31 shows a structure obtained by removing the P-channel MOS transistor 625 from the flip-flop circuit EF. In the figure, it is assumed that the voltage value of the signal input from the data input terminal D is the ground potential (0 V), the two-phase clock signal φ1 is active, the two-phase clock signal φ2 is inactive, The potential of each part of the circuit after being left still is shown in parentheses.

  In flip-flop circuit EF, since two-phase clock signal φ2 is inactive, N-channel MOS transistors 621 and 624 are turned off, and the nodes through which signals D1A and D0C flow are in a high impedance state. In the flip-flop circuit EF, since the two-phase clock signal φ1 is active, the N-channel MOS transistors 622 and 623 are turned on, and the input potential to the N-channel MOS transistor 623 is 0V. The potential of the signal D0A is about 0V.

  On the other hand, in flip-flop circuit EF, N channel MOS transistor 621 is in an OFF state, and an input of an inverter constituted by N channel MOS transistor 359 and P channel MOS transistor 360 connected thereto is in an undefined state. Therefore, a through current IDDq that flows from the power supply VDD to the ground is generated in the inverter.

  Here, since the output of the inverter constituted by the N-channel MOS transistor 359 and the P-channel MOS transistor 360 is in an indefinite state, it is difficult to determine the output potential as a whole, but it is assumed that it is 5V. Then, the potential of the node through which the signal D1C output from the N channel MOS transistor 622 in the on state flows is a value obtained by subtracting the gate threshold voltage of the N channel MOS transistor 622 from the input potential of the N channel MOS transistor 622. Therefore, it is about 4V.

  At this time, in the flip-flop circuit EF, since the N-channel MOS transistor 624 is in the OFF state, the input potential of the inverter constituted by the N-channel MOS transistor 363 and the P-channel MOS transistor 364 is about 4V, A through current IDDq that flows from the power supply VDD to the ground is generated in the inverter.

  As described above, it is assumed that the two-phase clock signal φ1 is active and the two-phase clock signal φ2 is inactive, and the circuit operation after being left in a stationary state has been studied. However, the flip-flop circuit EF is symmetrical with this state. In the case where the two-phase clock signal φ1 is inactive and the two-phase clock signal φ2 is active, the output from the inverter whose input is in a high impedance state and the output of the previous stage are also similar. A through current is generated in the inverter which becomes high level.

  As described above, in the flip-flop circuit EF shown in FIG. 31, a through current at the time of IDDq current measurement cannot be prevented, and a short circuit or an open due to a defect in a semiconductor manufacturing process which is an original purpose of the IDDq test. It was difficult to detect the condition.

  On the other hand, in the LED head 19 shown as the seventh embodiment, as the phase conversion circuit 602, two buffer circuits 373 and 374 that send out the two-phase clock signals φ1 and φ2 in the phase conversion circuit 302 described above. Instead of these, two OR circuits 611 and 612 are provided.

  In the phase conversion circuit 602 previously shown in FIG. 29, when the standby mode instruction signal STBY-P is set to the low level, an operation similar to the logical operation of the phase conversion circuit 302 shown in FIG. 22 is performed. . On the other hand, in phase conversion circuit 602, when standby mode instruction signal STBY-P is at a high level, both of two-phase clock signals φ1 and φ2 are at a high level.

  Therefore, in the flip-flop circuit EF previously shown in FIG. 30, N channel MOS transistor 621 to which two-phase clock signals φ1 and φ2 are input is set in the standby mode in order to perform the IDDq test of the driving IC. , 622, 623, 624 are all turned on.

  Here, the potential of each part of the circuit in the flip-flop circuit EF is shown in FIG. In the figure, it is assumed that the two-phase clock signals φ1 and φ2 are both active, and the voltage value of the signal input from the data input terminal D is set to the ground potential (0 V) so that it can be compared with FIG. The potential of each part of the circuit after being left still is shown in parentheses.

  In the flip-flop circuit EF shown in FIG. 32, the IDDq test is performed by setting the signal input from the data input terminal D to the low level. At this time, in the flip-flop circuit EF, the potentials of the nodes through which the signals D1A and D0A flow are both 0 V, and the signal D1B output from the inverter formed by the N-channel MOS transistor 359 and the P-channel MOS transistor 360, The potentials of the nodes through which the signal D0B output from the inverter constituted by the channel MOS transistor 361 and the P channel MOS transistor 362 flows are both 5V.

  Here, in the flip-flop circuit EF, as described above, when the input potential to the N-channel MOS transistors 622 and 624 is 5 V, the signal D1C output from each of the N-channel MOS transistors 622 and 624 in the ON state. , D0C flows through a potential obtained by subtracting the gate threshold voltage of the N-channel MOS transistors 622 and 624 from the input potential of the N-channel MOS transistors 622 and 624, and is about 4V.

  In flip-flop circuit EF, signals D1C and D0C output from N-channel MOS transistors 622 and 624, respectively, are input to an inverter constituted by N-channel MOS transistor 363 and P-channel MOS transistor 364. Since the logic is inverted, the output potential of the inverter becomes 0V. In the flip-flop circuit EF, the output potential of 0 V is applied to the gate terminal of the P channel MOS transistor 625, so that the P channel MOS transistor 625 is turned on.

  Thus, flip-flop circuit EF is configured by the potential of the node through which signals D1C and D0C output from N channel MOS transistors 622 and 624 flow, and N channel MOS transistor 363 and P channel MOS transistor 364, respectively. The input potential of the inverter is raised from about 4V to 5V equal to the power supply voltage VDD.

  As described above, in the flip-flop circuit EF, since the input potential of each inverter is pulled down or pulled up to either 0 V or 5 V, no through current can be generated in each inverter.

  As described above, in the LED head 19 of the printing apparatus shown as the seventh embodiment of the present invention, the two-phase clock signals φ1 and φ2 are set when the standby mode is set in order to perform the IDDq test of the driving IC. N channel MOS transistors 621, 622, 623, 624 are all turned on. At this time, in the LED head 19, by performing an IDDq test with the signal input from the data input terminal D in the flip-flop EF shown in FIG. 30 as a low level, no through current is generated in the flip-flop EF. Therefore, in the LED head 19, in addition to the effects shown in the second to sixth embodiments, a short circuit or an open state caused by a defect in the semiconductor manufacturing process, which is an original purpose of the IDDq test, is achieved. It is also possible to realize the effect that it is possible to reliably eliminate the obstacle to detection.

  Next, a printing apparatus shown as the eighth embodiment will be described.

  The printing apparatus shown as the eighth embodiment is different from the LED head 19 in the printing apparatus shown as the first embodiment. Therefore, in the description of the eighth embodiment, the same reference numerals are given to the same components as those in the description of the first embodiment, and the detailed description thereof will be omitted.

In the printing apparatus shown as the eighth embodiment, an LED head 19 having an internal configuration as shown in FIG. 33 is used. That is, the LED head 19 inputs the print data signals HD-DATA3,..., HD-DATA0 in the first-stage driving IC DRV ₁ cascaded to the LED head 19 shown in FIG. Further, a comparator circuit 700 for converting the signal level and a termination resistor 701 are added. Further, the LED head 19 includes a reference voltage generation circuit 702 that generates the reference voltage V _ref1 in addition to the reference voltage generation circuit 158 described above.

The comparator circuit 700 includes a potential of the print data signals HD-DATA3,. comparing the V _ref1, converts the print data signals HD-DATA3, ···, the potential of the HD-DATA0, driving _{IC DRV 1, DRV 2, ···} , a voltage corresponding to the data signal level of the _{DRV 26} To do.

The termination resistor 701 is provided for each of the signal lines that transmit the print data signals HD-DATA3,..., HD-DATA0. One end of the termination resistor 701 is connected to a signal line for transmitting the print data signals HD-DATA3,..., HD-DATA0, and the other end is _supplied with a potential V _tt generated by a termination voltage generation circuit (not shown). Applied. The resistance value of the termination resistor 701 is a resistance value substantially equal to the characteristic impedance of the signal line that transmits the print data signals HD-DATA3,..., HD-DATA0. Therefore, in the LED head 19, by providing the termination resistor 701, the waveform shape changes so that the signal output from the print control unit 1 is reflected at the input portion of the LED head 19 and the logical determination becomes difficult. In addition, it is possible to prevent a long time from being repeatedly converged by repeating signal reflection with the print control unit 1.

In such an LED head 19, the amplitudes of the print data signals HD-DATA3,..., HD-DATA0 are based on a so-called GTL (Gunning Transceiver Logic) interface. The potential V _tt generated by the voltage generation circuit is set to 1.2V, and the reference voltage V _ref1 generated by the reference voltage generation circuit 702 is set to 0.8V. Therefore, the potentials of the print data signals HD-DATA3,..., HD-DATA0 are 1.2V at the highest and 0V at the lowest, and the amplitude is 1.2V or less.

  On the other hand, the amplitude of the conventional print data signal is about 5 V in the case of a CMOS interface, and about 3.3 V in the case of a TTL (Transistor-Transistor Logic) interface. The print data signals HD-DATA3,..., HD-DATA0 input to 19 are remarkably reduced in amplitude.

Such an LED head 19 performs data transfer according to the timing shown in FIG. 2A shows signal waveforms of conventional print data signals HD-DATA3,..., HD-DATA0, and FIG. 2B shows the print data signal HD-DATA3 in the LED head 19. ,..., shows a signal waveform of HD-DATA0, in FIG. (c) shows a signal waveform of the data signal output from the comparator circuit 700, in FIG. (d) is from the drive IC DRV ₁ The signal waveform of the output data signal is shown.

First, in the signal waveforms of the conventional print data signals HD-DATA3,..., HD-DATA0, the low-level potential ViL shown in FIG. The potential ViH is ideally about 5V. At this time, in the drive IC to which the print data signals HD-DATA3,..., HD-DATA0 are inputted, the signal _V.sub.cmos is about VDD / 2 based on the power supply voltage VDD of the drive IC. The logical value will be determined.

Here, in a conventional LED head, for example, when performing printing such as solid black coating, since a large number of LED elements are driven all at once, a power supply current having a large peak value is repeatedly generated. As a result, the power supply voltage VDD may vary every time the LED element is driven. In the conventional LED head, the potential of the input print data signals HD-DATA3,..., HD-DATA0 is determined based on the potential V _cmos based on the power supply voltage VDD of the drive IC itself. Since noise due to potential fluctuation is superimposed on VDD, it is difficult to determine the potential of the input print data signals HD-DATA3,..., HD-DATA0. An erroneous printing due to a mistake may occur.

On the other hand, in the LED head 19, small-amplitude print data signals HD-DATA 3,. DATA0 is input. In the signal waveform of the print data signals HD-DATA3,..., HD-DATA0, the low-level potential ViL shown in FIG. Ideally, it is about 1.2V. Further, the reference voltage V _ref1 generated by the reference voltage generation circuit 702 is set to 0.8 V as described above. Therefore, as described above, the potential of the print data signals HD-DATA3,... 2V or less.

At this time, in the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ to which the print data signals HD-DATA 3,. The logical value of the signal is determined using V _ref1 as a reference. Therefore, the LED head 19 is not affected by the fluctuation of the power supply voltage VDD unlike the conventional LED head.

The signal waveform of the data signal output from the comparator circuit 700 is as shown in FIG. In this signal waveform, the low-level potential ViL is ideally 0V, and the high-level potential ViH is ideally about 5V. At this time, according the print data signals HD-DATA3, · · ·, in the driving IC DRV ₁ to HD-DATA0 is inputted, the reference about VDD / 2 becomes the potential _{V cmos} based on the power supply voltage VDD of the drive IC DRV ₁ As a result, the logical value of the signal is determined. Here, since the comparator circuit 700 is provided in the LED head 19, its power supply is connected in common with the power supply VDD of the drive IC DRV ₁ .

  Therefore, the LED head 19 has a large peak value because a large number of LED elements are driven at the same time, for example, when performing printing such as solid black coating, as in the conventional LED head. Although the power supply current may repeatedly occur, even if the power supply voltage VDD fluctuates every time the LED element is driven, the power supply potential of the comparator circuit 700 also fluctuates. The potential on the high level side also fluctuates.

Here, since the LED head 19 determines the potential of the data output from the comparator circuit 700 with reference to a threshold potential of about VDD / 2 based on the power supply voltage VDD of the drive IC DRV ₁ itself, the power supply voltage Even when the potential on the high level side in the output of the comparator circuit 700 is caused by the potential variation of VDD, the threshold potential on the side of the driving IC DRV ₁ to which this signal is input also varies at the same rate. become.

  Therefore, the LED head 19 has no influence on the potential determination of the input print data signals HD-DATA3,..., HD-DATA0, and no erroneous printing due to a data input error occurs.

Further, the signal waveform of the data signal output from the driving IC DRV ₁ is as shown in FIG. The signal waveform, the signal shown in FIG. (C) is shifted transmitted through the shift register circuit 152 in the drive IC DRV _1, the drive IC DRV ₁ data output terminals DATAO3, · · ·, outputted from DATAO0 It has been done. In this signal waveform, the low-level potential ViL is ideally 0V, and the high-level potential ViH is ideally about 5V. At this time, in the next-stage driving IC DRV ₂ to which the data signal is input, the logical value of the signal is determined with reference to the potential V _cmos of about VDD / 2 based on the power supply voltage VDD of the driving IC DRV _2. It will be.

In the LED head 19, similarly for the subsequent drive ICs DRV ₃ ,..., The logical value of the input signal with reference to the potential V _cmos of about VDD / 2 based on the power supply voltage VDD of the drive IC. Will be determined.

Accordingly, the LED head 19, as described above, all the driving _{IC DRV 1, DRV 2, ···} , any effect is not given to the potential discrimination of data signals input to _{DRV 26,} the data input error No erroneous printing will occur.

  As described above, in the LED head 19 of the printing apparatus shown as the eighth embodiment of the present invention, in addition to the effects shown as the first embodiment, the print data signal HD-DATA3,. Printing is performed by disposing a terminating resistor 701 having a resistance value substantially equal to the characteristic impedance of the signal line transmitting HD-DATA0 at the signal transmitting end of the print control unit 1 and the signal receiving end of the LED head 19. The waveform output changes so that the signal output from the control unit 1 is reflected at the input part of the LED head 19 and the logical determination becomes difficult, or the signal is converged repeatedly with the print control unit 1 repeatedly. It is also possible to realize an effect that it is possible to prevent a long time from being taken.

  Further, in the LED head 19, the print data signals HD-DATA3,..., HD-DATA0 inputted can be remarkably reduced in amplitude, and EMI noise can be reduced.

  Further, in the LED head 19, if the rising waveform or falling waveform slope of the input print data signals HD-DATA3,... Since the rise time and the fall time can be shortened, the amount of data that can be transmitted within the same time can be remarkably increased, and the printing speed can be increased.

  Next, a printing apparatus shown as the ninth embodiment will be described.

  In the printing apparatus shown as the ninth embodiment, the LED head 19 in the printing apparatus shown as the eighth embodiment has a different configuration. Therefore, in the description of the ninth embodiment, the same reference numerals are given to the same configurations as those in the description of the eighth embodiment, and the detailed description thereof will be omitted.

In the printing apparatus shown as the ninth embodiment, an LED head 19 having an internal configuration as shown in FIG. 35 is used. That is, the LED head 19 receives a signal for inputting a print data signal in each of the cascaded drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ with respect to the LED head 19 shown in FIG. A comparator circuit 750 for converting the level is added. The LED head 19 includes a reference voltage generation circuit 751 that generates reference voltages V _ref1 and V _ref2 in addition to the above-described reference voltage generation circuit 158. Furthermore, LED head 19, printing of the drive IC DRV ₁ of the first stage data signals HD-DATA3, · · ·, to the input of the HD-DATA0, with a terminating resistor 701 as described above.

Unlike the comparator circuit 700 described above, the comparator circuit 750 is provided in each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ . The comparator circuit 750 in the first-stage driving IC DRV ₁ includes the potential of the print data signals HD-DATA3,... It compares the reference voltage _{V ref1} generated by the generation circuit 751, converts the print data signals HD-DATA3, · · ·, the potential of the HD-DATA0, a voltage corresponding to the data signal level of the drive IC DRV ₁ To do.

The termination resistor 701 is provided for each of the signal lines that transmit the print data signals HD-DATA3,..., HD-DATA0. One end of the termination resistor 701, the print data signals HD-DATA3, · · ·, are connected to a signal line for transmitting the HD-DATA0, the other end, the potential _{V tt} generated by an unillustrated termination voltage generating circuit Applied. The resistance value of the termination resistor 701 is a resistance value substantially equal to the characteristic impedance of the signal line that transmits the print data signals HD-DATA3,..., HD-DATA0. Therefore, in the LED head 19, by providing this termination resistor 701, the waveform shape changes so that the signal output from the print control unit 1 is reflected at the input portion of the LED head 19 and the logical determination becomes difficult. It is possible to prevent a long time from being repeatedly converged by repeating signal reflection with the print control unit 1.

More specifically, each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ includes four comparators corresponding to the data input terminals DATAI 0,. Circuits 750A, 750B, 750C, and 750D are included. One end of each of the comparator circuits 750A, 750B, 750C, and 750D is connected to the data input terminals DATAI0,. The The reference voltage V _ref1 generated by the reference voltage generation circuit 751 is applied to the input terminal VT in the first-stage driving IC DRV _{1, and} the input terminals in the second-stage and subsequent driving ICs DRV ₂ ,. The reference voltage V _ref2 generated by the reference voltage generation circuit 751 is applied to each VT.

In such an LED head 19, the amplitude of the print data signals HD-DATA3,..., HD-DATA0 conforms to the GTL interface as described above. The potential V _tt generated by the generation circuit is set to 1.2V, and the reference voltage V _ref1 generated by the reference voltage generation circuit 751 is set to 0.8V. Therefore, the potentials of the print data signals HD-DATA3,..., HD-DATA0 are 1.2V at the highest and 0V at the lowest, and the amplitude is 1.2V or less. Compared with the print data signal, the amplitude is remarkably reduced.

Such an LED head 19 performs data transfer according to the timing shown in FIG. 2A shows signal waveforms of conventional print data signals HD-DATA3,..., HD-DATA0, and FIG. 2B shows the print data signal HD-DATA3 in the LED head 19. ,..., shows a signal waveform of HD-DATA0, in FIG. (c) shows a signal waveform of the data signal outputted from the drive IC DRV _1.

First, in the signal waveforms of the conventional print data signals HD-DATA3,..., HD-DATA0, the low-level potential ViL shown in FIG. The potential ViH is ideally about 5V. At this time, in the drive IC to which the print data signals HD-DATA3,..., HD-DATA0 are inputted, the signal _V.sub.cmos is about VDD / 2 based on the power supply voltage VDD of the drive IC. The logical value will be determined.

  Therefore, in the conventional LED head, as described above, the noise caused by the potential fluctuation is superimposed on the power supply voltage VDD, so that the input print data signals HD-DATA3,. It becomes difficult to determine the potential of DATA0, and as a result, erroneous printing due to a data input error may occur.

On the other hand, in the LED head 19, small-amplitude print data signals HD-DATA 3,. DATA0 is input. In the signal waveform of the print data signals HD-DATA3,..., HD-DATA0, the low-level potential ViL shown in FIG. Ideally, it is about 1.2V. Further, the reference voltage V _ref1 generated by the reference voltage generation circuit 751 is set to 0.8 V as described above. Therefore, as described above, the potential of the print data signals HD-DATA3,... 2V or less.

At this time, in the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ to which the print data signals HD-DATA 3,. The logical value of the signal is determined using V _ref1 as a reference. Therefore, the LED head 19 is not affected by the fluctuation of the power supply voltage VDD unlike the conventional LED head.

The signal waveform of the data signal output from the driving IC DRV ₁ is as shown in FIG. The signal waveform, the print data signals HD-DATA3 shown in FIG. (B), ···, HD- DATA0 are shifted transmitted through the shift register circuit 152 in the drive IC DRV _1, the drive IC DRV ₁ Are output from the data output terminals DATAO3,..., DATAO0. In this signal waveform, the low-level potential ViL is ideally 0V, and the high-level potential ViH is ideally about 5V. At this time, according the print data signals HD-DATA3, · · ·, in the next stage of the drive IC DRV ₂ to HD-DATA0 is inputted, at approximately VDD / 2 becomes the potential based on the power supply voltage VDD of the drive IC DRV ₂ Instead, the logical value of the signal is determined based on the reference voltage V _ref2 generated by the reference voltage generation circuit 751. This reference voltage V _ref2 is typically set to about VDD / 2.

In the LED head 19, similarly for subsequent drive ICs DRV ₃ ,..., The logical value of the input signal is determined based on the reference voltage V _ref2 generated by the reference voltage generation circuit 751. become.

Accordingly, the LED head 19, as shown as the eighth embodiment, the print data signals HD-DATA3 of the drive IC DRV ₁ of the first stage, ..., external comparator circuit to an input of HD-DATA0 The size of the LED head 19 can be further reduced, and the cost can be further reduced.

  As described above, in the LED head 19 of the printing apparatus shown as the ninth embodiment of the present invention, in addition to the effects shown as the first embodiment, the print data signal HD-DATA3,. Printing is performed by disposing a terminating resistor 701 having a resistance value substantially equal to the characteristic impedance of the signal line transmitting HD-DATA0 at the signal transmitting end of the print control unit 1 and the signal receiving end of the LED head 19. The waveform output changes so that the signal output from the control unit 1 is reflected at the input part of the LED head 19 and the logical determination becomes difficult, or the signal is converged repeatedly with the print control unit 1 repeatedly. It is also possible to realize an effect that it is possible to prevent a long time from being taken.

  Further, in the LED head 19, the print data signals HD-DATA3,..., HD-DATA0 inputted can be remarkably reduced in amplitude, and EMI noise can be reduced.

  Furthermore, in the LED head 19, assuming that the slope of the rising waveform or falling waveform of the input print data signal HD-DATA 3,..., HD-DATA 0 is constant, the waveform is reduced by reducing the amplitude. Since the rise time and the fall time can be shortened, the amount of data that can be transmitted within the same time can be remarkably increased, and the printing speed can be increased.

Furthermore, in the LED head 19, it is not necessary to externally connect a comparator circuit to the input of the print data signals HD-DATA 3,..., HD-DATA 0 in the first stage driving IC DRV ₁ . The size of 19 can be further reduced, and further cost reduction can be achieved.

  Finally, a printing apparatus shown as the tenth embodiment will be described.

  The printing apparatus shown as the tenth embodiment is different from the LED head 19 in the printing apparatus shown as the ninth embodiment. Therefore, in the description of the tenth embodiment, the same reference numerals are given to the same components as those in the description of the ninth embodiment, and the detailed description thereof will be omitted.

  First, prior to the description of the printing apparatus shown as the tenth embodiment, problems in the case of configuring an LED head will be described.

  In general, LED elements have a large variation in light emission power due to the semiconductor manufacturing process, which appears as unevenness in the amount of light. Therefore, in the conventional LED head, as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2000-108407, a correction memory storing correction data for each dot is driven in order to correct the variation in the light amount of the LED element. It is provided in the IC, and based on this correction data, the drive current value of the LED element is adjusted to correct the variation in light quantity.

  In such an LED head, the latch signal HD-LOAD, the print drive signal HD-STB-N, etc. are corrected in addition to the function for simply holding the signal by the latch circuit and controlling the light emission or non-light emission of the LED element. It also has a function of controlling data writing to the memory and a function as a clock signal for sequence control of various control circuits.

  Here, problems in transmitting the latch signal HD-LOAD and the print drive signal HD-STB-N will be described with reference to FIGS.

  In FIG. 38, a vertical broken line A indicates the boundary between the LED head and the external device. A modeled LED head is shown on the right side of the broken line A, and a predetermined value is shown on the left side of the broken line A. A model of the connection cable, the print control unit, and the like is shown.

In FIG. (A), the driving _{IC DRV 1, DRV 2, ···} , for example, a latch signal is supplied to the _{DRV 26} HD-LOAD and the print drive signal signal lines for transmitting signals, such as HD-STB-N 1000 a plurality of signal lines T1, T2, · · ·, and T26, the signal lines T1, T2, · · ·, IC driven from _{T26 DRV 1, DRV 2, ···} , stub line which branches to _{DRV 26} TS1, TS2,..., TS26. The signal line T1 is a signal line extending from the head boundary corresponding to the connector formed on the printed wiring board to connect the LED head and the print control unit to the branch point to the driving IC DRV ₁ , and the stub wiring. TS1 is a signal line that branches from the signal line 1000 to the driving IC DRV ₁ , and includes a bonding wire indicated by a one-dot chain line in FIG. Similarly, the signal line T2 is a signal line from the branch point of the stub wiring TS1 in the signal line 1000 to the branch point to the driving IC DRV ₂ , and the stub wiring TS2 branches from the signal line 1000 to the driving IC DRV ₂ . Including a bonding wire indicated by a one-dot chain line in FIG. Thus, in the LED head, the signal line 1000 is branched for each driving IC, and the branching is interrupted at the position of the driving IC DRV ₂₆ that is the terminal.

An equivalent circuit of such an LED head is as shown in FIG. In this equivalent circuit, a signal generated from a signal source V _s having a driving impedance R _s is transmitted to the LED head via a transmission line T ₀ having a characteristic impedance Z ₀ . In other words, here, the characteristic impedance of the connecting wires of the LED head is assumed to be Z _0. In the figure, T1 is modeled as a signal line on the printed circuit board from the head connector to the branch point to the drive IC DRV ₁ as a transmission line, and TS1 branches to the drive IC DRV ₁ The signal line to be modeled as a transmission line. Further, in the figure, C1 is a model of the input capacitance of the terminal in the driving IC DRV ₁ , and typically, the stray capacitance of the pad of the IC terminal or the ESD (electro-static) on the IC. discharge) is a combination of the protective element and the capacitance of the input buffer. Similarly, in the figure, T2 is a model of a signal line on the printed circuit board from the branch point of the drive IC DRV _{1 to} the branch point to the drive IC DRV ₂ as a transmission line, and TS2 is a drive line. A signal line branched to the IC DRV ₂ is modeled as a transmission line, and C2 is a model of an input capacitance of a terminal in the driving IC DRV ₂ . Since the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ have the same configuration, their input capacitances C1,.

The arrangement intervals of the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ are the same as the arrangement intervals of the LED array chips. Therefore, the line length of T2 is about 8.1 mm, and similarly, T3,..., T26 are also periodically arranged with a line length of about 8.1 mm.

Thus, in the LED head, the transmission line is modeled for the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ . Here, these transmission lines TS1, · · ·, TS26 and T1, · · ·, T26, and the input capacitance C1, · · ·, the characteristic impedance of the system constituted by C26, the transmission line _{T 0} as described above it can be made equal to the characteristic impedance Z ₀ at. Specifically, this characteristic impedance is calculated using the well-known relationship described in “HW Johnson, M. Graham,“ High-Speed Digital Design: A Handbook of Black Magic ”(Prentice Hall)”. It is set as equation (1).

Incidentally, _{Z 0} 'is in the above formula (1), the transmission line T2, · · ·, a characteristic impedance of T26, _{C D} is the input capacitance C1, · · ·, input drive IC corresponding to C26 Capacitance. Further, C ₀ is a characteristic capacitance of the transmission lines T2,..., T26, which is obtained by multiplying the capacity per unit length of the transmission line by the line length. Here, the characteristic impedance Z ₀ is known as the characteristic impedance of the connecting cable of the LED head, an input capacitance C _D is also known. Therefore, the characteristic impedance Z ₀ ′ can be calculated by giving the cross-sectional shape of the wiring pattern on the printed wiring board, and the characteristic capacitance C ₀ is also uniquely determined.

FIG. 39 shows the signal waveform of the drive IC obtained based on the model shown in FIG. In the figure, the signal source V _s generates a pulse signal, the drive impedance R _s is matched with the characteristic impedance Z ₀ of the transmission line T ₀ , and the signal that returns to the signal transmission end by signal reflection is shown. It is assumed that re-reflection is suppressed and multiple reflection does not occur. FIG. 4A shows a signal waveform in the drive IC DRV ₁ , FIG. 2B shows a signal waveform in the drive IC DRV ₁₃ located at the midpoint of the LED head substrate, and FIG. Shows a signal waveform in the drive IC DRV ₂₆ located at the end of the LED head substrate.

Here, the propagation delay time t13 generated by the propagation of the signal on the transmission line from the driving IC DRV ₁ to the driving IC DRV ₁₃ is t13 = 13 × t1 using the line delay time t1 between the driving ICs. It is represented by

The signal waveform that drives the driving IC DRV ₁ shown in FIG. 6A propagates through the transmission line, and after the propagation delay time t13 has elapsed, transitions as shown in FIG. After the propagation delay time t13 elapses, the transition is made as shown in FIG. Here, in the driving IC DRV ₂₆ located at the end of the LED head substrate, the signal line is cut off to become an open end, and as a result of the signal reflection at that position, the signal waveform is shown in FIG. As shown in (), it rises monotonously and steeply. In the LED head, when the signal waveform reflected at the position of the driving IC DRV ₂₆ returns to the driving IC DRV ₁ and reaches the position of the driving IC DRV ₁₃ after the propagation delay time t13 has elapsed, The waveform rises. As a result, the signal waveform has a terrace-shaped step in the middle of the rising waveform as shown in FIG. Further, in the LED head, when the position of the driving IC DRV ₁ is reached after the propagation delay time t13 has elapsed, the waveform further rises, and as shown in FIG. Thus, a signal waveform with the occurrence of is obtained. Further, in the LED head, a signal waveform in which a terrace-shaped step is generated in the middle of the falling waveform is obtained at the falling edge of the signal waveform, similarly to the rising time.

In the LED head, as is apparent from FIGS. 9A, 9B, and 9C, a substantially ideal digital waveform is obtained by the position of the driving IC DRV ₂₆ located at the end of the signal line. Only when it reaches The shape of the signal waveform differs depending on the position of each drive IC, and is notably different from the shape in which a wide terrace-shaped step occurs in the middle of the signal transition as when returning to the position of the drive IC DRV _1. Become.

FIG. 40 shows a signal waveform expressed using more realistic conditions than the signal waveform shown in FIG. 39. Specifically, a predetermined capacitor is connected to the output of the digital drive element which is a signal source. Is shown, and the signal waveform from the signal source is blunted. FIG. 40A shows a signal waveform in the drive IC DRV ₁ , FIG. 40B shows a signal waveform in the drive IC DRV ₁₃ located at the midpoint of the LED head substrate, and FIG. Shows a signal waveform in the drive IC DRV ₂₆ located at the end of the LED head substrate.

  As shown in the figure, this signal has a waveform shape in which a terrace-shaped step occurs in the middle of signal transition, but ringing of the waveform has occurred, and undulation occurs in the middle of the signal transition. It matches the input threshold voltage level of the input driving IC.

  In the LED head, when such a signal is input to the drive IC, a waveform that should originally have only one edge is recognized as having two edges at the rise and fall. As a result, the drive IC malfunctions.

  As described above, in the LED head, there is a problem inducing a malfunction of the drive IC even when the latch signal HD-LOAD and the print drive signal HD-STB-N are transmitted.

Therefore, in the printing apparatus shown as the tenth embodiment, in order to solve such a problem, an LED head 19 having an internal configuration as shown in FIG. 41 is used. That is, the LED head 19 is connected to the print head signal HD-STB-N in each of the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ cascade-connected to the LED head 19 previously shown in FIG. the input, conversion with adding a comparator circuit 800 for converting a signal level, the drive _{IC DRV 1, DRV 2, ···} , to the input of the latch signal HD-LOAD at each _{DRV 26,} the signal level A comparator circuit 801 is added. Further, the LED head 19 has the above-described termination resistor 701 at the input of the print data signals HD-DATA3,..., HD-DATA0 in the first-stage drive IC DRV ₁ , and the print drive signal HD-STB-. Terminal resistors 802 and 803 are provided at the ends of signal lines for transmitting N and the latch signal HD-LOAD. Further, the LED head 19 includes a reference voltage generation circuit 804 that generates reference voltages V _ref1 and V _ref2 in addition to the above-described reference voltage generation circuit 158.

As described above, the comparator circuit 750 is provided in each of the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ . The comparator circuit 750 in the first-stage driving IC DRV ₁ includes the potentials of the print data signals HD-DATA3,..., HD-DATA0, which are single-ended signals having a small amplitude output from the print control unit 1, and the reference voltage. It compares the reference voltage _{V ref1} generated by the generation circuit 804, converts the print data signals HD-DATA3, · · ·, the potential of the HD-DATA0, a voltage corresponding to the data signal level of the drive IC DRV ₁ To do.

The comparator circuit 800 is provided in each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ . The comparator circuit 800 in the first-stage drive IC DRV ₁ compares the potential of the print drive signal HD-STB-N output from the print control unit 1 with the reference voltage V _ref1 generated by the reference voltage generation circuit 804. Then, the potential of the print drive signal HD-STB-N is converted into a voltage value corresponding to the signal level of the drive IC DRV ₁ .

The comparator circuit 801 is provided in each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ . The comparator circuit 801 in the first stage drive IC DRV ₁ compares the potential of the latch signal HD-LOAD output from the print control unit 1 with the reference voltage V _ref1 generated by the reference voltage generation circuit 804, and latches it. The potential of the signal HD-LOAD is converted into a voltage value corresponding to the signal level of the driving IC DRV ₁ .

The termination resistor 701 is provided for each of the signal lines that transmit the print data signals HD-DATA3,..., HD-DATA0. One end of the termination resistor 701, the print data signals HD-DATA3, · · ·, are connected to a signal line for transmitting the HD-DATA0, the other end, the potential _{V tt} generated by an unillustrated termination voltage generating circuit Applied. The resistance value of the termination resistor 701 is a resistance value substantially equal to the characteristic impedance of the signal line that transmits the print data signals HD-DATA3,..., HD-DATA0. Therefore, in the LED head 19, by providing this termination resistor 701, the waveform shape changes so that the signal output from the print control unit 1 is reflected at the input portion of the LED head 19 and the logical determination becomes difficult. It is possible to prevent a long time from being repeatedly converged by repeating signal reflection with the print control unit 1.

Termination resistors 802 and 803 are provided at the ends of signal lines that transmit the print drive signal HD-STB-N and the latch signal HD-LOAD, respectively. One end of each of the termination resistors 802 and 803 is connected to a signal line that transmits the print drive signal HD-STB-N and the latch signal HD-LOAD, and the other end is generated by a termination voltage generation circuit (not shown). A potential V _tt is applied. The resistance values of these termination resistors 802 and 803 are set to resistance values substantially equal to the characteristic impedances of the signal lines that transmit the print drive signal HD-STB-N and the latch signal HD-LOAD, respectively. Therefore, in the LED head 19, by providing these termination resistors 802 and 803, the waveform shape is such that the signal output from the print control unit 1 is reflected at the input portion of the LED head 19 and the logical determination becomes difficult. It is possible to prevent a change or a long time from being repeatedly reflected and converged with the print control unit 1 to converge.

More specifically, each of the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ includes four comparators corresponding to the data input terminals DATAI 0,. Circuits 750A, 750B, 750C, and 750D are included. One end of each of the comparator circuits 750A, 750B, 750C, and 750D is connected to the data input terminals DATAI0,. The Further, the driving ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ have comparator circuits 800 and 801, respectively. One end of the comparator circuit 800 is connected to the input terminal STB in the drive IC that inputs the print drive signal HD-STB-N, and the other end is connected to the input terminal VREF1 in the drive IC. One end of the comparator circuit 801 is connected to the input terminal LOADI in the driving IC that inputs the latch signal HD-LOAD, and the other end is connected to the input terminal VREF1 in the driving IC. Note that the input terminal VREF1, VREF2 in the drive IC DRV ₁ of the first stage, the reference voltage _{V ref1} that are both generated by the reference voltage generating circuit 804 is applied. Further, the second and subsequent stages of the drive IC _DRV 2, the input terminal VREF1 at ..., respectively, the reference voltage the reference voltage _{V ref1} generated by generator 804 is applied, the second and subsequent stages driving IC DRV ₂ The reference voltage V _ref2 generated by the reference voltage generation circuit 804 is applied to the input terminals VREF2 of.

In such an LED head 19, the amplitudes of the print data signal HD-DATA3,..., HD-DATA0, the print drive signal HD-STB-N, and the latch signal HD-LOAD are respectively compliant with the GTL interface. As a typical example, the potential V _tt generated by a termination voltage generation circuit (not shown) is set to 1.2 V, and the reference voltage V _ref1 generated by the reference voltage generation circuit 751 is set to 0.8 V. The Therefore, the potentials of the print data signals HD-DATA3,..., HD-DATA0, the print drive signal HD-STB-N, and the latch signal HD-LOAD are 1.2 V at most, respectively, Even if it is low, it is 0 V, and its amplitude is 1.2 V or less, which is significantly smaller than the conventional signal.

  FIG. 43 shows an equivalent circuit of the wiring configuration of the print drive signal HD-STB-N or the latch signal HD-LOAD. In the drawing, a vertical broken line A indicates a boundary between the LED head 19 and an external device, and the right side of the broken line A shows a model of the LED head 19, and on the left side of the broken line A. 1 shows a model of a predetermined connection cable, the print control unit 1 and the like.

In FIG. (A), the driving _{IC DRV 1, DRV 2, ···} , the print drive signal is supplied to the _{DRV 26} HD-STB-N or the signal line 900 for transmitting the latch signal HD-STB-N is a plurality of signal lines T1, T2, ..., and T27, the signal lines T1, T2, ..., IC driven from T26 _{DRV 1,} DRV 2, stub line TS1 branching., to _{DRV 26,} TS2,..., TS26. In the LED head 19, the signal line 900 is branched for each driving IC, but the branching is not interrupted at the position of the driving IC DRV ₂₆ which is the terminal as in the equivalent circuit previously shown in FIG. Further, the signal line T27 extends from the branch point of the stub wiring TS26 in the signal line 900 to the resistance corresponding to the termination resistors 802 and 803 indicated by the resistance value RL.

An equivalent circuit of such an LED head is as shown in FIG. In this equivalent circuit, a signal generated from a signal source V _s having a driving impedance R _s is transmitted to the LED head 19 via a transmission line T ₀ having a characteristic impedance Z ₀ . In other words, here, the characteristic impedance of the connecting wires of the LED head 19 is assumed to be Z _0. In the figure, T1 is a model of a signal line on the printed wiring board 100 from the connector 103 formed on the printed wiring board 100 to the branch point to the driving IC DRV ₁ as a transmission line. TS1 is a model in which a signal line branched to the drive IC DRV ₁ is modeled as a transmission line. Further, in the figure, C1 is obtained by modeling the input capacitance of the terminals of the drive IC DRV _1. Similarly, in the figure, T2 is a signal line on the printed circuit board 100 from the branch point of the driving IC DRV _{1 to} the branch point to the driving IC DRV ₂ , which is modeled as a transmission line. A signal line branched to the drive IC DRV ₂ is modeled as a transmission line, and C2 is a model of an input capacitance of a terminal in the drive IC DRV ₂ . Since the drive ICs DRV ₁ , DRV ₂ ,..., DRV ₂₆ have the same configuration, their input capacitances C1,.

Here, the characteristic impedance of the system constituted by these transmission lines TS1,..., TS26 and T1,..., T26 and the input capacitances C1,. Is set as follows. Accordingly, the transmission line T2, · · ·, the characteristic impedance Z ₀ of the T26 _'can be calculated by giving the cross-sectional shape of the wiring pattern on the printed circuit board 100, the characteristic capacitance C ₀ to be uniquely determined Become. The resistance RL of the terminating resistor 802 and 803 is set to be equal to the characteristic impedance _{Z 0.}

When the signal waveform of the driving IC is obtained based on the model shown in FIG. 43, it is as shown in FIG. In the figure, the signal source V _s generates a pulse signal, the drive impedance R _s is matched with the characteristic impedance Z ₀ of the transmission line T ₀ , and the signal that returns to the signal transmission end by signal reflection is shown. It is assumed that re-reflection is suppressed and multiple reflection does not occur. FIG. 4A shows a signal waveform in the drive IC DRV ₁ , FIG. 2B shows a signal waveform in the drive IC DRV ₁₃ located at the midpoint of the LED head substrate, and FIG. Shows a signal waveform in the drive IC DRV ₂₆ located at the end of the LED head substrate. Further, in FIGS. 9A, 9B, and 9C, a reference voltage V _ref1 that is an input threshold voltage of each driving IC is indicated by a one-dot chain line.

Here, as described above, the propagation delay time t13 generated by the signal propagating on the transmission line from the driving IC DRV ₁ to the driving IC DRV ₁₃ is obtained by using the line delay time t1 between the driving ICs. t13 = 13 × t1.

Since the LED head 19 is terminated by the terminating resistors 802 and 803 at the position of the driving IC DRV ₂₆ , the print driving signal HD-STB-N or the latch signal HD-LOAD reaching the end of the signal line is reached. Will not be reflected. Thus, in the LED head 19, since each signal line input from the outside is terminated at the end, signal reflection does not occur. Therefore, in the LED head 19, as shown in FIG. 39, a signal waveform having a shape in which a terrace-shaped step is generated in the middle of signal transition does not occur.

  Therefore, in the LED head 19, a predetermined capacitor is connected to the output of the digital drive element that is a signal source to blunt the signal waveform from the signal source, and the signal passes through the surface of the connection cable or the printed wiring board 100. There is no need to provide additional circuit means such as providing a sufficiently large rise time or fall time for the reciprocating time.

Further, in the conventional LED head, the shape of the signal waveform differs depending on the position of each driving IC, and the pulse width may vary, but in the LED 19, the pulse in the first stage driving IC DRV ₁ There is no difference between the width tw1 and the pulse width tw26 in the driving IC DRV ₂₆ in the 26th stage, and no malfunction occurs even if a signal having a pulse width smaller than the conventional one is used.

  Further, in the LED head 19, since the signal waveform rises monotonously and falls monotonously, as in the prior art, undulation occurs in the middle of signal transition, and there is a waveform that should originally have only one edge. It is possible to prevent a phenomenon in which a drive IC malfunctions due to being recognized as having two edges.

  As described above, in the LED head 19 of the printing apparatus shown as the tenth embodiment of the present invention, like the signal line for transmitting the print drive signal HD-STB-N or the latch signal HD-LOAD, By providing the terminating resistors 802 and 803 having resistance values substantially equal to the characteristic impedance of the signal line commonly connected to each driving IC, in addition to the effect shown as the ninth embodiment, It is also possible to realize an effect that it is possible to prevent a phenomenon in which the malfunction of the driving IC due to the fact that a waveform that should have only one edge is recognized as having two edges.

  Further, in the conventional LED head, in order to prevent malfunction due to signal reflection, it is necessary to sufficiently dull the input waveforms such as the print drive signal HD-STB-N and the latch signal HD-LOAD. There is a problem that the signal transition time increases or the pulse width cannot be reduced, and the clock signal needs to be stopped during the signal transition, so that the data transmission is substantially delayed. It was happening.

  On the other hand, the LED head 19 can eliminate such problems, can provide excellent data transmission reliability, and can perform high-speed operation.

  The present invention is not limited to the embodiment described above. For example, in the above-described embodiment, the LED head in the electrophotographic recording method printing apparatus using the LED element as the light source for irradiating the photosensitive drum with light has been described. The present invention can also be applied to an organic EL head using an organic EL (ElectroLuminescent) element.

  Further, in the above-described embodiment, the light source is used as the driven element. However, the present invention is not limited to, for example, a column of heating resistors in a thermal printer or a column of display elements in a display device. Any device can be applied as long as the row of driven elements is selectively and periodically driven.

  Thus, it goes without saying that the present invention can be modified as appropriate without departing from the spirit of the present invention.

3 is a block diagram illustrating a configuration of a control circuit included in the printing apparatus illustrated as the first embodiment of the present invention. FIG. 3 is a timing chart for explaining transmission / reception timings of various signals used in the printing apparatus shown as the first embodiment of the present invention. It is a top view explaining the circuit wiring structure of the LED head in the printing apparatus shown as the 1st Embodiment of this invention. It is a figure explaining the principal part circuit structure of the LED head shown as the 1st Embodiment of this invention. It is a block diagram explaining the internal structure of the LED head shown as the 1st Embodiment of this invention. It is a figure explaining the circuit structure of the drive IC in the LED head shown as the 1st Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure explaining the mode of connection with the drive IC in the LED head shown as the 1st Embodiment of this invention, an LED array chip, and a printed wiring board, Comprising: (a) is a top view of the LED head (B) is sectional drawing of the LED head. 2A and 2B are diagrams illustrating a circuit configuration of a flip-flop circuit in the driving IC shown as the first embodiment of the present invention, where FIG. 1A shows a circuit symbol, and FIG. 2B shows an internal configuration of the flip-flop circuit; FIG. FIG. 9 illustrates a specific configuration of the flip-flop circuit illustrated in FIG. 8. FIG. 10 is a diagram illustrating a specific configuration of the flip-flop circuit illustrated in FIG. 8, and illustrates a configuration different from the configuration illustrated in FIG. 9. 3 is a timing chart illustrating operation timings of the flip-flop circuit in the driving IC shown as the first embodiment of the present invention. 2 is a timing chart for explaining the timing of a print data signal and a clock signal, wherein (a) shows the timing of the print data signal and the clock signal in a conventional LED head, and (b) shows the first of the present invention. It is a figure which shows the timing of the print data signal and clock signal in the LED head shown as this embodiment. It is a figure for demonstrating electromagnetic radiation, Comprising: (a) shows a model circuit, (b) shows the signal generated by the signal source of the model circuit shown in (a), (c), (D) shows an outline of the frequency spectrum of the waveform shown in (b), and (e) is radiated to the outside by the waveform shown in (b). FIG. It is a block diagram explaining the internal structure of the LED head in the printing apparatus shown as the 2nd Embodiment of this invention. It is a figure explaining the circuit structure of the drive IC in the LED head shown as the 2nd Embodiment of this invention. 4A and 4B are diagrams for explaining a circuit configuration of a flip-flop circuit in a driving IC shown as a second embodiment of the present invention, in which FIG. 5A shows a circuit symbol, and FIG. 5B shows an internal configuration of the flip-flop circuit; FIG. It is a figure explaining the circuit structure of the phase conversion circuit in the drive IC shown as the 2nd Embodiment of this invention. 7 is a timing chart for explaining the operation timing of the phase conversion circuit in the drive IC shown as the second embodiment of the present invention. 6 is a timing chart illustrating operation timings of the flip-flop circuit in the driving IC shown as the second embodiment of the present invention. 4A and 4B are diagrams for explaining a circuit configuration of a flip-flop circuit in a driving IC shown as a third embodiment of the present invention, where FIG. 5A shows a circuit symbol, and FIG. 4B shows an internal configuration of the flip-flop circuit; FIG. 10 is a timing chart illustrating operation timings of the flip-flop circuit in the driving IC shown as the third embodiment of the present invention. It is a figure explaining the circuit structure of the phase conversion circuit in the drive IC shown as the 4th Embodiment of this invention. It is a timing chart explaining the operation | movement timing of the phase conversion circuit in the drive IC shown as the 4th Embodiment of this invention. It is a figure explaining the circuit structure of the phase conversion circuit in the drive IC shown as the 5th Embodiment of this invention. It is a timing chart explaining the operation | movement timing of the phase conversion circuit in the drive IC shown as the 5th Embodiment of this invention. FIG. 10 is a diagram for explaining a circuit configuration of a flip-flop circuit in a driving IC shown as a sixth embodiment of the present invention, where (a) shows a circuit symbol and (b) shows an internal configuration of the flip-flop circuit. FIG. 16 is a timing chart illustrating operation timings of the flip-flop circuit in the driving IC shown as the sixth embodiment of the present invention. It is a figure explaining the circuit structure of the drive IC in the LED head shown as the 7th Embodiment of this invention. It is a figure explaining the circuit structure of the phase conversion circuit in the drive IC shown as the 7th Embodiment of this invention. FIG. 10 is a diagram illustrating a circuit configuration of a flip-flop circuit in a driving IC shown as a seventh embodiment of the present invention, where (a) shows a circuit symbol and (b) shows an internal configuration of the flip-flop circuit. FIG. FIG. 31 is a diagram illustrating a circuit configuration of a circuit in which a P-channel MOS transistor is removed from the flip-flop circuit shown in FIG. 30. It is a figure explaining the circuit structure of the flip-flop circuit in the drive IC shown as the 7th Embodiment of this invention, Comprising: It is a figure for demonstrating the electric potential of each part of a circuit. It is a block diagram explaining the internal structure of the LED head in the printing apparatus shown as the 8th Embodiment of this invention. It is a timing chart explaining the operation timing of the LED head shown as 8th Embodiment of this invention, Comprising: (a) shows the signal waveform of the conventional print data signal, (b) is the LED head. The signal waveform of the print data signal is shown, (c) shows the signal waveform of the data signal output from the comparator circuit in the LED head, and FIG. (D) is output from the first stage driving IC in the LED head. It is a figure which shows the signal waveform of the data signal to be performed. It is a block diagram explaining the internal structure of the LED head in the printing apparatus shown as the 9th Embodiment of this invention. It is a figure explaining the circuit structure of the drive IC in the LED head shown as the 9th Embodiment of this invention. It is a timing chart explaining the operation timing of the LED head shown as 9th Embodiment of this invention, (a) shows the signal waveform of the conventional print data signal, (b) is in the LED head. The signal waveform of a print data signal is shown, (c) is a figure which shows the signal waveform of the data signal output from the drive IC of the 1st step | paragraph in the LED head. It is a figure for demonstrating the problem at the time of transmitting a latch signal and a printing drive signal, Comprising: (a) shows the figure which modeled the LED head and an external device, (b) shows (a). It is a figure which shows the equivalent circuit of the model shown. FIG. 39 is a diagram for explaining a signal waveform of the driving IC obtained based on the model shown in FIG. 38, in which (a) shows a signal waveform in the first stage driving IC, and (b) shows a thirteenth stage driving. The signal waveform in IC is shown, (c) is a figure which shows the signal waveform in 26th-stage drive IC. FIG. 40 is a diagram for explaining the signal waveform of the drive IC when the signal waveform shown in FIG. 39 is blunted, where (a) shows the signal waveform in the first-stage drive IC, and (b) shows the thirteenth-stage signal. The signal waveform in this drive IC is shown, (c) is a figure which shows the signal waveform in the drive IC of the 26th stage. It is a block diagram explaining the internal structure of the LED head in the printing apparatus shown as the 10th Embodiment of this invention. It is a figure explaining the circuit structure of the drive IC in the LED head shown as the 10th Embodiment of this invention. It is a figure for demonstrating the wiring structure of the printing drive signal or latch signal in the LED head shown as the 10th Embodiment of this invention, Comprising: (a) is the figure which modeled the LED head and the external device. (B) is a figure which shows the equivalent circuit of the model shown to (a). 43A and 43B are diagrams for explaining a signal waveform of a driving IC obtained based on the model shown in FIG. 43, in which FIG. 43A shows a signal waveform in the first-stage driving IC, and FIG. The signal waveform in IC is shown, (c) is a figure which shows the signal waveform in 26th-stage drive IC. It is a figure explaining the mode of connection with the drive IC in the conventional LED head, LED array chip, and a printed wiring board, Comprising: (a) is a top view of the LED head, (b) is the LED head FIG. It is a figure explaining the circuit structure of the drive IC in the conventional LED head.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Print control part 2,4 Driver 3 Development / transfer process motor 5 Paper feed motor 6 Paper inlet sensor 7 Paper discharge sensor 8 Paper remaining amount sensor 9 Paper size sensor 19 LED head 22 Fixing device 22a Heater 23 Fixing device temperature sensor 25 High Voltage Power Supply for Charging 26 High Voltage Power Supply for Transfer 27 Developer 28 Transfer Device 100 Printed Circuit Board 101, 101 _P , 101 _N Differential Clock Signal Line 102, 701, 802, 803 Termination Resistor 103 Connector 151, 601 Clock Input Circuit 152 , 301 shift register circuit _{153, LTA 1, ···, LTD} 48 latch circuit 154 inverter circuit 155 the logical product circuit 156, DRV LED drive circuit 157,603 control voltage generating circuit 158,702,751,804 reference voltage generating circuit 201 202 Latch element 203 Selector circuit 302,602 Phase conversion circuit 351,352,353,354,359,361,363,401,402,403,404,405,406,407,408,451,551,552,553 554, 555, 557, 559, 621, 622, 623, 624 N-channel MOS transistors 355, 356, 357, 358, 360, 362, 364, 409, 410, 411, 412, 413, 414, 415, 416, 452 , 556, 558, 560, 625 P-channel MOS transistors 370, 501, 502, 503, 504 Inverters 371, 372 NAND circuit 373, 374 Buffer circuit 505, 506 NAND circuit 611, 612 OR circuit 700, 75 0,750A, 750B, 750C, 750D, 800,801 comparator circuit A, B, D, DATAI1, DATAI2, DATAI3 data input terminal C ₀ characteristic capacitance C1, ···, C26, _{C D} input capacitance CK, CLKP , CLKN clock input terminal DATAO1, DATAO2, DATAO3, Q, Y data output terminal _{DFA 1, ···, DFD 48,} EFA 1, ···, EFD 48 flip-flop circuits DO terminals DO1, DO2, ···, DO192 Drive current output terminal G Gate input terminal HD-CLK clock signal HD-CLK-P, HD-CLK-N Differential clock signal HD-DATA, HD-DATA3,..., HD-DATA0 Print data signal HD-LOAD, LOAD-P Latch signal HD- STB-N print drive signal LOADI terminal S select terminal SG1 control signal SG2 video signal SG3 timing signal SG4 transfer signal SGC charge signal STBY signal input terminal STBY-P standby mode instruction signal T1,..., T27 transmission line TS1,.・, TS26 Stub wiring V _cmos potential VDD Power supply V _ref , V _ref1 , V _ref2 Reference voltage VREF1, VREF2 Input terminal V _tt potential Z ₀ Differential characteristic impedance Z ₀ 'Characteristic impedance φ1, φ2 Two-phase clock signal φ1N, φ2N Completion Signal

Claims (20)

A drive circuit for connecting a plurality of drive ICs for supplying a drive current to recording elements constituting an array in cascade and transferring print data to each drive IC based on a differential clock signal;
The driving IC transfers the print data at both a rising edge and a falling edge of the input differential clock signal. A signal line for transmitting one of the differential clock signals is connected to the first clock input terminal of the odd-numbered stage driving IC and the second clock input terminal of the even-numbered stage driving IC connected in cascade. And
The signal line for transmitting the other of the differential clock signals is connected to the second clock input terminal of the odd-numbered stage driving IC and the first clock input terminal of the even-numbered stage driving IC connected in cascade. The drive circuit according to claim 1, wherein: The drive ICs are respectively
When the input differential clock signal is at a low level, the input logical value is captured and output, while when the differential clock signal is at a high level, the logical value output immediately before A first latch element that continues to hold
When the input differential clock signal is at a high level, the input logic value is captured and output, while when the differential clock signal is at a low level, the logic value output immediately before A second latch element that continues to hold
When the differential clock signal is at a high level, the logical value output from the first latch element is output, while when the differential clock signal is at a low level, the second latch element is output. The drive circuit according to claim 2, further comprising: a selector circuit that outputs a logical value output from. A termination resistor having a resistance value substantially equal to a characteristic impedance of a signal line for transmitting the print data is connected to the signal transmission end of the print data and the signal reception end of the drive circuit. The drive circuit according to claim 2. The drive circuit according to claim 2, further comprising: a comparator circuit that converts a potential of the print data into a voltage value corresponding to a signal level of the drive IC based on a predetermined reference voltage value. The drive circuit according to claim 5, wherein the comparator circuit is provided in each of the plurality of drive ICs. The comparator circuit provided in the first stage driving IC among the plurality of driving ICs converts the potential of the print data based on a first reference voltage value,
The comparator circuit provided in the second and subsequent driver ICs of the plurality of driver ICs converts the potential of the print data based on a second reference voltage value. Driving circuit. 3. The drive according to claim 2, wherein a termination resistor having a resistance value substantially equal to a characteristic impedance of the signal line is connected to a terminal of a signal line commonly connected to each of the drive ICs. circuit. The drive circuit according to claim 2, wherein a terminal resistor having a resistance value substantially equal to a differential characteristic impedance of the signal line is connected to an end of the signal line for transmitting the differential clock signal. . The drive ICs are respectively
A phase conversion circuit that generates a two-phase clock signal composed of a first clock signal and a second clock signal that do not overlap each other for each input of the differential clock signal;
A flip-flop circuit to which the two-phase clock signal output from the phase conversion circuit is input,
The flip-flop circuit is
It has two data transmission paths, the inputs of the two data transmission paths are connected to each other, and the outputs of the two data transmission paths are connected to each other. The drive circuit according to claim 2. The flip-flop circuit is
A first transmission gate that operates based on the second clock signal and an output of the first transmission gate are input to a first data transmission path of the two systems of data transmission paths. An inverter, and a second transmission gate that receives the output of the first inverter and operates based on the first clock signal;
A third transmission gate that operates based on the first clock signal and an output of the third transmission gate are input to a second data transmission path of the two systems of data transmission paths. The drive circuit according to claim 10, further comprising: an inverter; and a fourth transmission gate that receives the output of the second inverter and operates based on the second clock signal. The flip-flop circuit is
The first clocked CMOS inverter that operates based on the second clock signal and the output of the first clocked CMOS inverter are input to the first data transmission path of the two data transmission paths. And a second clocked CMOS inverter that operates based on the first clock signal,
A third clocked CMOS inverter that operates based on the first clock signal and an output of the third clocked CMOS inverter are input to a second data transmission path of the two systems of data transmission paths. The drive circuit according to claim 10, further comprising: a fourth clocked CMOS inverter that operates based on the second clock signal. The phase conversion circuit is:
A transmission gate to which the differential clock signal is input;
An inverter to which the differential clock signal is input;
A first NOR circuit to which the output of the inverter is input;
A second NOR circuit to which the output of the transmission gate is input;
A first buffer circuit that receives an output of the first NOR circuit and outputs a first clock signal of the two-phase clock signals;
A second buffer circuit that receives the output of the second NOR circuit and outputs a second clock signal of the two-phase clock signals;
The first negative OR circuit receives the output of the inverter and the second clock signal output from the second buffer circuit,
The drive circuit according to claim 10, wherein an output of the transmission gate and the first clock signal output from the first buffer circuit are input to the second NOR circuit. . The phase conversion circuit is:
A transmission gate to which the differential clock signal is input;
An inverter to which the differential clock signal is input;
A first NOR circuit to which the output of the inverter is input;
A second NOR circuit to which the output of the transmission gate is input;
A first buffer circuit that receives an output of the first NOR circuit and outputs a first clock signal of the two-phase clock signals;
A second buffer circuit that receives the output of the second NOR circuit and outputs a second clock signal of the two-phase clock signals;
A circuit for generating a first complement signal for the first clock signal output from the first buffer circuit;
A circuit for generating a second complement signal for the second clock signal output from the second buffer circuit;
The first NOR circuit receives an output of the inverter and a signal obtained by delaying the second complement signal,
The drive circuit according to claim 10, wherein an output of the transmission gate and a signal obtained by delaying the first complement signal are input to the second NOR circuit. The flip-flop circuit is
A first MOS transistor that operates based on the second clock signal and an output of the first MOS transistor are input to a first data transmission path of the two systems of data transmission paths. An inverter and a second MOS transistor that receives the output of the first inverter and operates based on the first clock signal;
Of the two data transmission paths, a second data transmission path receives a third MOS transistor that operates based on the first clock signal and an output of the third MOS transistor. The drive circuit according to claim 10, further comprising: an inverter; and a fourth MOS transistor that receives the output of the second inverter and operates based on the second clock signal. The flip-flop circuit receives a signal after connecting the output of the second MOS transistor in the first data transmission path and the output of the fourth MOS transistor in the second data transmission path Providing a third inverter;
The drive circuit according to claim 15, further comprising means for pulling down or pulling up input potentials of the first inverter, the second inverter, and the third inverter. In an LED array driving circuit for connecting a plurality of driving ICs for supplying a driving current to LED elements constituting the LED array in a cascade and transferring print data to each driving IC based on a differential clock signal,
The LED driving circuit, wherein each of the driving ICs transfers the print data at both a rising edge and a falling edge of the input differential clock signal. Recording elements constituting the array;
A plurality of driving ICs for supplying a driving current to the recording element are connected to the cascade, and a driving circuit for transferring print data to each driving IC based on a differential clock signal is mounted;
The drive IC wiring board according to claim 1, wherein the drive IC transfers the print data at both a rising edge and a falling edge of the input differential clock signal. Recording elements constituting the array;
A drive circuit for connecting a plurality of drive ICs for supplying a drive current to the recording element in cascade, and transferring print data to each drive IC based on a differential clock signal;
A substrate on which the recording element and the drive circuit are mounted;
Each of the driving ICs transfers the print data at both a rising edge and a falling edge of the input differential clock signal. A drive circuit for connecting printing elements constituting an array and a plurality of drive ICs for supplying drive current to the print elements to the cascade and transferring print data to each drive IC based on a differential clock signal And a print head having a substrate on which the recording element and the driving circuit are mounted;
Image forming means for forming an image on a predetermined recording medium using the print head,
Each of the drive ICs transfers the print data at both a rising edge and a falling edge of the input differential clock signal.