JP2006030516A - Display device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress flicker occurring in the case of duty driving of controlling display luminance by a duty ratio of a light emission time. <P>SOLUTION: A data line driving circuit 14 supplies a video data signal supplied from a system circuit 16 per frame, to each pixel 11. A scanning line driving circuit 13 is operated in accordance with a light emission control signal DS supplied from the system circuit 16 and selects pixels 11 in line sequence per frame to cause each light emitting element 17 to emit light with luminance corresponding to the video data signal. The system circuit 16 is provided with a light emission control means Z and sets a duty ratio of the light emission time and the light non-emission time in one frame in accordance with screen luminance information and causes each light emitting element 17 to emit light in accordance with the duty ratio and divides one frame into a plurality of sub-frames and causes each light emitting element 17 to emit light only for a light emission time according with the duty ratio to suppress flicker. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active matrix type display device having a plurality of display pixels and in which display control is performed in units of pixels, and a driving method thereof, and in particular, an active matrix type in which a display element of each pixel is configured by an organic EL (Electro Luminescence) element. The present invention relates to display devices and driving methods thereof.

  In recent years, thin display devices using organic EL have attracted attention as self-luminous high-luminance displays. Because it is self-luminous, it does not require a backlight like a liquid crystal display device, and the entire display panel can be thinned to about 1 to 2 mm, so it can be made smaller and lighter. It has advantages such as high speed, high brightness, high contrast, and low power consumption, and is considered a promising candidate for next-generation displays. Organic EL displays are currently being applied to small displays for mobile devices (portable information devices) such as digital cameras and mobile phones. In the future, applications to medium and large displays such as PC monitors and televisions are considered. ing. Because mobile devices can be easily carried both indoors and outdoors, it is necessary to realize optimal display images in various usage environments from dark places such as in rooms to bright places such as outdoors in the sun. Further, since the PC monitor and the television are used in various environments by the user, it is necessary to realize an optimal display image. In such an environment, the optimal display image varies depending on the individual user, and the brightness of the display screen is set so that it can be used for everything from users who select bright display images to users who select dark display images. It must be possible.

  In a display device such as a CRT, a liquid crystal display, or an organic EL, a refresh operation is performed to rewrite a video frame to be displayed several tens of times per second, and the rewrite frequency of this frame is called a refresh rate. Flickers occur when the refresh rate is low. Therefore, the refresh rate of these display devices is normally rewritten at a frequency (60 Hz) at which no flicker occurs. By the way, the brightness of the display screen of the liquid crystal display device can be set according to the brightness of the backlight, and the brightness of the display screen can be arbitrarily set in order to optimize the usage environment and power consumption. is there. The backlight usually uses a cold cathode tube and is lit by high-speed switching drive of several tens to several hundreds KHz by an inverter circuit (lamp drive circuit), so that human eyes recognize the flashing of the backlight. Therefore, it is possible to provide a good display screen free from flicker. In addition, the liquid crystal display device inverts the polarity of the voltage applied to the pixel electrode for each frame with respect to the reference voltage, inverts the polarity for each horizontal pixel line, or inverts the polarity for each display pixel. Flicker is suppressed by the driving method.

  On the other hand, an organic EL display device uses a self-luminous display element for each pixel, and emits light by displaying a current by passing a current through each light-emitting element. The brightness of the display screen can be set according to the light emission time occupying one frame. Therefore, even if the refresh rate of the image to be displayed is displayed at 60 Hz, flickering of the display screen occurs depending on the light emission frequency and the ratio of light emission time to non-light emission time (duty ratio) in one frame. The display quality will deteriorate. Flickering (flickering) does not occur in a state where the light is constantly emitted (duty 100%), but it becomes a hold-type drive like a liquid crystal display device, so moving image blur when displaying a moving image by retinal afterimage Image quality degradation occurs. Note that the retina afterimage is a phenomenon that occurs in a hold-type drive display that continues to display an image for one frame period, and the brightness changes stepwise each time the image is switched, so that the image is always displayed without a break. Become. When the image displayed on the display is switched to the next image, a human recognizes the two images in a superimposed manner, and as a result, the outline of the image feels blurred.

  Also, flicker does not occur by increasing the refresh rate of the video to be displayed. In a general display, flicker is hardly felt when the refresh rate is set to about 72 Hz. However, the operation speed of the drive circuit has to be increased, power consumption is increased, and the use member (such as an electronic component) and the drive circuit are significantly changed accordingly. Further, with the increase in speed, energy consumption due to high-speed switching in the digital circuit portion of the drive circuit increases, and it is emitted into the air as electromagnetic waves. Electromagnetic waves emitted into the air contain various frequencies and cause various disturbances to electrical and electronic equipment.

  The conventional duty drive method for controlling the brightness of the display screen by the duty ratio of the light emission time uses a light emission time setting signal. FIG. 3 is a waveform diagram of the vertical synchronization signal and the light emission time setting signal when the refresh rate (frame rewriting frequency) of the video to be displayed is 60 Hz. It represents the turn-off time when the non-light emission period is not displayed, and the turn-on time when the light emission period is displayed. The ratio between the two in one frame is the duty ratio. Since the brightness of the image is finely brightened or darkened with a period of 1 frame (1 / 60th of a second), the brightness difference between light and dark is recognized as flicker. Working for a long time on a screen that feels flickering is very bad for your eyes, and it also affects your brain fatigue.

  FIG. 4 shows waveforms of the vertical synchronization signal and the light emission time setting signal when the refresh rate to be displayed to suppress flicker is, for example, 75 Hz. The non-emission period represents the turn-off time when no image is displayed, the emission period represents the turn-on time when the image is displayed, and the brightness of the image becomes finer or darker with a period of 1/75 second However, on a general display, flicker is hardly felt when the refresh rate is set to 72 Hz or higher. Therefore, when it is set to 75 Hz, the brightness difference between light and darkness due to non-light emission and light emission is not recognized as flicker (flicker). . However, the operation speed of the drive circuit has to be increased, power consumption is increased, and the use member (such as an electronic component) and the drive circuit are significantly changed accordingly. In addition, there is a concern about the problem of EMI due to electromagnetic wave noise generated from the digital circuit portion of the drive circuit as the speed increases.

  In this way, when the display brightness is controlled by the duty ratio of the light emission time as a display device, it is essential to maintain good display quality without recognizing flicker (flicker) on the display screen, and the function is realized. There is a problem that must be made.

  SUMMARY OF THE INVENTION In view of the above-described problems of the prior art, an object of the present invention is to easily suppress flicker (flicker) that occurs in duty driving in which display luminance is controlled by a duty ratio of light emission time in a display device such as an organic EL. To do.

  In order to achieve this purpose, the following measures were taken. That is, the present invention includes a pixel array unit, a scanning line driving circuit and a data line driving circuit for driving the pixel array unit, and a system circuit for controlling the pixel array unit. The pixel array unit includes a row-shaped scanning line, a column-shaped scanning line, and a column-shaped scanning line. A video data signal including a data line and a pixel formed of a light emitting element disposed at a crossing portion of the data line, wherein the data line driving circuit is connected to each data line and is supplied from the system circuit in units of frames. The scanning line driving circuit is connected to each scanning line and operates in accordance with the light emission control signal supplied from the system circuit, and the pixels are line-sequentially selected for each frame. In the display device that causes each light emitting element to emit light with a luminance according to a data signal, the system circuit includes a light emission control unit, and the light emission time and the non-light emission time within one frame according to the screen luminance information The light emitting element is caused to emit light according to the duty ratio, and one frame is divided into a plurality of subframes, and each light emitting element is caused to emit light for the light emission time corresponding to the duty ratio in each subframe. It is characterized by suppressing flicker.

  Preferably, the light emission control unit sets the number of subframes according to the set duty ratio. In this case, the light emission control unit increases the number of subframes as the duty ratio decreases. The light emitting element is, for example, an organic electroluminescence light emitting element.

  In addition, the present invention includes a pixel array unit constituting a screen, a scanning line driving circuit and a data line driving circuit for driving the pixel array unit, and the pixel array unit includes a row scanning line, a column data line, The data line driving circuit is connected to each data line and supplies a video data signal supplied from the outside in units of frames to each pixel. The scanning line driving circuit is connected to each scanning line and operates in accordance with a light emission control signal supplied from the outside. Each pixel is line-sequentially selected for each frame and each has a luminance corresponding to the video data signal. In a driving method of a display device that causes a light emitting element to emit light, a duty ratio between a light emitting time and a non-light emitting time in one frame is set according to luminance information of a screen, and each light emitting element is caused to emit light according to the duty ratio. When In, which comprises suppressing the flicker only emit light of each light-emitting element emitting time corresponding to the duty ratio in each sub-frame by dividing one frame into a plurality of subframes.

  According to the present invention, flicker can be suppressed by increasing the apparent frame frequency by providing subframes without changing the frame frequency. According to the present invention, in a self-luminous display device such as an organic EL, a display device capable of easily suppressing flicker (flickering) that occurs in the case of duty driving for controlling display luminance by a duty ratio of light emission time, and driving thereof The method can be realized and provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing an active matrix organic EL display device using an organic EL element which is a self-luminous element as a display element of each pixel in the display device according to the present invention. The active matrix organic EL display device according to the present embodiment includes a pixel array unit 12 in which pixels 11 are arranged in a matrix, and a scanning drive circuit 13 and a data line drive circuit 14 that drive the pixel array unit 12. It is formed on the organic EL panel unit substrate 15 and has an external system circuit 16 that drives the scanning line driving circuit 13 and the data line driving circuit 14 outside the organic EL panel unit 15.

  That is, the display device according to the present invention includes a pixel array unit 12, a scanning line driving circuit 13 and a data line driving circuit 14 for driving the pixel array unit 12, and a system circuit 16 for controlling them. The pixel array unit 12 includes a row-shaped scanning line DSL, a column-shaped data line DTL, and a pixel 11 composed of light-emitting elements 17 arranged at a portion where both intersect. The data line driving circuit 14 is connected to each data line DTL, and supplies a video data signal supplied from the system circuit 16 in units of frames to each pixel 11. The scanning line driving circuit 13 is connected to each scanning line DSL, operates in accordance with the light emission control signal DS supplied from the system circuit 16, and selects the pixels 11 line-sequentially for each frame in accordance with the video data signal. Each light emitting element 17 emits light with luminance. As a feature, the system circuit 16 includes a light emission control unit Z, sets a duty ratio between a light emission time and a non-light emission time in one frame according to the screen luminance information, and each light emission according to the duty ratio. The element 17 is caused to emit light, and one frame is divided into a plurality of subframes, and each light emitting element 17 is caused to emit light for each light emission time corresponding to the duty ratio in each subframe, thereby suppressing flicker. According to the present invention, flicker can be suppressed by increasing the apparent frame frequency by providing subframes without changing the frame frequency.

  In FIG. 1, a pixel 11 has a field effect transistor, for example, a polysilicon TFT (Thin Film Transistor) or an amorphous silicon TFT 18 as an active element for driving the organic EL element 17 to emit light, on the substrate on which these TFTs 18 are formed. In this configuration, the organic EL element 17 is formed. However, the TFT 18 in the figure is schematically displayed as a symbol, and an actual pixel circuit is composed of a plurality of TFTs and other circuit elements. The organic EL element 17 is formed by forming a plurality of first electrodes made of a transparent conductive film on a substrate and depositing a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer in order on the first electrode. A layer is formed, and a second electrode made of metal is formed on the organic layer. When a direct current voltage is applied between the first electrode and the second electrode, electrons and positive electrodes are formed in the light emitting layer. Light is emitted when the holes recombine.

  In the pixel array unit 12, scanning lines DSL-1 to DSL-n are wired in each row for a pixel array of n columns and m rows. Data lines DTL-1 to DTL-m are wired in each column. One end of each of the scanning lines DSL-1 to DSL-n is connected to the output terminal of each stage of the scanning line driving circuit 13. The scanning line driving circuit 13 is configured by, for example, a shift register or the like, and is given a light emission control signal DS generated by the external system circuit 16, and is synchronized with the vertical clock pulse VCK generated by the external system circuit 16. The light emission control sequential scanning pulses DS-1 to DS-n are output, and the scanning lines DSL-1 to DSL-n are driven.

  One end of each of the data lines DTL-1 to DTL-m is connected to an output terminal of each stage of the data line driving circuit 14. The data line driving circuit 14 has a current writing type or voltage writing type driving circuit configuration in which luminance information is written in the form of a current value or a voltage value to each of the pixels 11 through the data lines DTL-1 to DTL-m. ing.

The external system circuit 16 is formed on an external system circuit board disposed outside the organic EL panel 15. The external system circuit 16 receives a luminance setting signal from the outside, which controls the data line driving circuit 14 and the scanning line driving circuit 13, and converts the luminance setting signal into a desired digital signal to the timing generator 19. A luminance setting signal receiver 20 as an interface to be supplied is provided.

  The timing generator 19 receives an externally supplied image data signal, synchronization signal, and screen brightness setting information, and outputs a vertical clock pulse VCK, a light emission control signal DS, and a data line driving circuit 14 for controlling the scanning line driving circuit 13. A horizontal scanning control signal and a video data signal to be controlled are generated based on the synchronization signal, and are supplied to the scanning line driving circuit 13 and the data line driving circuit 14, respectively. The timing generator 19 particularly includes a light emission control means Z, generates a light emission control signal DS based on the screen luminance information, and supplies it to the scanning line drive circuit 13.

  FIG. 2 is a block diagram showing an example of the configuration of the light emission control means for generating the light emission control signal DS in the timing generator 19. The light emission control means Z according to this example is configured to include a light emission period setting circuit 21, a luminance level setting circuit 22, and a flicker suppression circuit 23.

  The luminance level setting circuit 22 sets the luminance level based on the luminance setting signal given through the luminance setting signal receiver 20. The light emission period setting circuit 21 obtains a desired luminance in each vertical scanning period in accordance with the digital luminance information set by the luminance level setting circuit 22, and emits light emission period pulses DP (light emission of one frame period T of the video signal). A duty ratio of the control pulse, that is, a ratio of the high level period to the period T, in other words, a signal defining a ratio of the high level period and the low level period) is generated and supplied as an input to the flicker suppression circuit 23. The flicker suppression circuit 23 detects the high level period in one frame period T of the light emission period pulse DP set by the light emission period setting circuit 21, converts it to a timing at which flicker can be suppressed, and generates the light emission control signal DS. Is output.

Next, the operation of the active matrix organic EL display device according to this embodiment having the above-described configuration will be described. In response to the vertical clock pulse VCK and the light emission control signal DS supplied from the timing generator 19, the scanning line driving circuit 13 sequentially applies light emission control sequential scanning pulses DS-1 to the plurality of scanning lines DSL-1 to DSL-n in each vertical period. ~ DS-n is supplied. The pixels 11 in each row are activated when the light emission control sequential scanning pulses DS-1 to DS-n supplied in common from one of the scanning lines DSL-1 to DSL-n are in a high level period. When in a low level period, it is in an inactivated state (lighted state) and is in an inactivated state (dark state).

  On the other hand, the data line driving circuit 14 samples video data in each horizontal period by a horizontal scanning control signal supplied from the timing generator 19 and supplies the video data in parallel to a plurality of data lines DTL-DTL-m. When the pixel 11 is activated, a driving current or driving voltage corresponding to the current or voltage of the video data signal supplied from the data line driving circuit 14 through the plurality of data lines DTL-1 to DTL-m is generated. It is given to the organic EL element 17.

  In the light emission control means Z of FIG. 2 constituting a part of the timing generator 19, the luminance level setting circuit 22 sets the luminance level based on the luminance setting signal supplied from the outside and processed by the receiver 20. The light emission period setting circuit 21 changes the duty ratio (ratio between the light emission period and the non-light emission period) of the light emission period pulse in accordance with the luminance level. Here, the screen luminance setting signal (dimming control signal) is a signal obtained as a result of selecting a desired luminance by a luminance adjustment switch or volume that can be controlled from an external personal computer or manually operated by a user.

  Next, a driving method capable of easily suppressing flicker (flickering) that occurs in the case of duty driving in which display luminance is controlled by the duty ratio of the light emission time will be described with reference to FIG. In the light emission control means Z, in order to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22, the light emission period setting circuit 21 generates a light emission period pulse. Control is performed by setting the duty ratio (ratio between the light emission period and the non-light emission period) to, for example, 4: 1 as illustrated. The light emission period pulse DP set by the light emission period setting circuit 21 detects a high level period in one frame (1V) period of the light emission period pulse by the flicker suppression circuit 23, and takes 1/2 frame (1/2 × V) as a period. In the subframe cycle period, a signal DS having the same duty ratio as that of the light emission period pulse DP, that is, 4: 1 is generated, and two signals are provided in one frame (1V) cycle period. That is, the light emission period pulse signal DP in one frame (1V) cycle period is apparently converted to a double speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the pulse duty ratio (ratio between the light emission period and the non-light emission period) is set to 1: 1 as shown in FIG. 6, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. The same duty ratio as the light emission period pulse DP, that is, 1: 1, is detected in the sub-frame cycle period in which the high level period in the 1-frame (1V) cycle period of the pulse is detected and the cycle is 1/2 frame (1/2 × V). Such a signal DS is generated, and two such signals are provided in one frame (1V) period. That is, the light emission period pulse signal in one frame (1V) period period is apparently converted to a double speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Similarly, in the light emission control means Z, the light emission period setting circuit 21 emits light in order to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the period pulse (ratio between the light emission period and the non-light emission period) is set to 1: 4 as shown in FIG. 7, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. The same duty ratio as that of the light emission period pulse DP, ie, 1: 4, is detected in a sub-frame cycle period in which a high-level period in one frame (1V) cycle period of the period pulse is detected and a cycle is 1/2 frame (1/2 × V). A signal DS is generated, and two such signals are provided in one frame (1V) period. That is, the light emission period pulse signal in one frame (1V) period period is apparently converted to a double speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  As described above, in the organic EL display device that controls the display luminance according to the duty ratio of the light emission time of the pixel 11, by apparently converting the light emission period pulse signal in one frame (1V) cycle period to the double speed timing, Flicker (flicker) can be easily suppressed regardless of brightness control. In the above-described embodiment, the case where the light emission period pulse signal in one frame (1V) period period is apparently set to the double speed timing has been described as an example, but the present invention is not limited to the double speed. Here, a case where the light emission period pulse signal in one frame (1V) period is apparently not at the double speed timing will be described with reference to FIG.

  In the light emission control means Z, in order to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22, the light emission period setting circuit 21 generates a light emission period pulse DP. In the control in which the duty ratio (ratio between the light emission period and the non-light emission period) is set to 4: 1 as shown in FIG. 8, the light emission period pulse DP set by the light emission period setting circuit 21 is changed to the light emission period pulse by the flicker suppression circuit 23. A high-level period in one frame (1V) period is detected, and the same duty ratio as that of the light emission period pulse DP, that is, 4: 1 is set in a sub-frame period having a period of 1/3 frame (1/3 × V). The light emission control signal DS is generated, and three such signals are provided in one frame (1V) period. That is, the light emission period pulse signal in one frame (1V) period period is apparently converted to a triple speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the pulse duty ratio (ratio between the light emission period and the non-light emission period) is set to 1: 1 as shown in FIG. 9, the light emission period pulse set by the light emission period setting circuit 21 is changed to the light emission period pulse by the flicker suppression circuit 23. A high-level period in one frame (1V) cycle period is detected, and the same duty ratio as that of the light emission period pulse is set to 1: 1 in a subframe cycle period in which 1/3 frame (1/3 × V) is a cycle. A signal is generated, and three signals are provided in one frame (1V) period. That is, the light emission period pulse signal in one frame (1V) period period is apparently converted to a triple speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Similarly, in the light emission control means, in order to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22, the light emission period setting circuit 21 emits the light emission period. In the control in which the pulse duty ratio (ratio between the light emission period and the non-light emission period) is set to 1: 4 as shown in FIG. 10, the light emission period pulse set by the light emission period setting circuit 21 is changed to the light emission period pulse by the flicker suppression circuit 23. A high level period in one frame (1V) cycle period is detected, and the same duty ratio as that of the light emission period pulse is set to 1: 4 in a sub-frame cycle period in which 1/3 frame (1/3 × V) is a cycle. A signal is generated, and three signals are provided in one frame (1V) period. That is, the light emission period pulse signal in one frame (1V) period period is apparently converted to a triple speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  As described above, in the organic EL display device that controls the display luminance according to the duty ratio of the light emission time of the pixel 11, by apparently converting the light emission period pulse signal in one frame (1V) cycle period to the timing of 3 × speed, Flicker (flicker) can be easily suppressed regardless of brightness control.

  By using the method as described above, in the organic EL display device that controls the display luminance by the duty ratio of the light emission time of the pixel 11, the light emission period pulse signal in one frame (1V) period period is apparently speeded up. By performing the conversion, the flicker of the display screen can be reduced without destroying the duty ratio of the light emission period pulse set by the light emission period setting circuit 21 in order to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside. Suppression can be performed very easily. In the above embodiment, the case where the present invention is applied to an organic EL display device using the organic EL element 17 as a display element of the pixel 11 is described as an example. However, the present invention is not limited to this. The present invention can be applied to all display devices using self-luminous elements as display elements.

  Next, a development form of the present invention will be described. FIG. 11 is a graph showing the flicker level (how the flicker looks) when one frame is 60 Hz and the duty of the light emission period and the non-light emission period is set to 0% to 100%. The flicker level increases as the duty is lowered. This is because as the non-light emission time at 1 V, that is, the time during which the black screen is displayed becomes longer, the black display on the entire display screen becomes dominant, and it becomes easier for human eyes to recognize the flashing of light emission and non-light emission. , Flicker will increase. Therefore, for example, when brightness control is performed from the outside with a brightness adjustment signal or the like for the purpose of adjusting the brightness of the display screen, the flicker level (how the flicker appears) differs depending on the set brightness. It causes deterioration of quality. As a display device, when the display brightness is increased according to the light emission time, and when the light emission time is changed by adjusting the brightness, the display screen does not recognize flicker (flicker) or flicker level (how the flicker appears) Maintaining display quality is indispensable, and its function must be realized.

  With reference to FIG. 12, a driving method that can easily suppress the difference in flicker occurrence rate (the appearance of flicker) caused by the change in the light emission time in the duty drive for controlling the display luminance according to the light emission time will be described. The circuit configuration itself is as shown in FIGS. 1 and 2, and these figures will be continuously referred to.

  In the light emission control means Z, in order to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22, the light emission period setting circuit 21 generates a light emission period pulse DP. In the control in which the duty ratio (ratio between the light emission period and the non-light emission period) is set to 9: 1 as shown in FIG. 12, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. A high-level period in one frame (1V) period is detected, and the same duty ratio as that of the light emission period pulse DP, that is, 9: 1 is obtained in a sub-frame period having a period of 1/2 frame (1/2 × V). Such a light emission control signal DS is generated, and two such signals are provided in one frame (1V) period. That is, the light emission period pulse DP signal in one frame (1V) cycle period is apparently converted to a double speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the pulse DP (ratio between the light emission period and the non-light emission period) is set to 8: 2 as shown in FIG. 13, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. In order to detect a high level period in one frame (1V) cycle period of the pulse DP and suppress a difference from the appearance of flicker in FIG. 12, the sub period with a cycle of 1/3 frame (1/3 × V) is used. Raise to frame period. In the subframe, a light emission control signal DS having the same duty ratio as that of the light emission period pulse DP, that is, 8: 2, is generated, and three signals are provided in one frame (1V) period. That is, the light emission period pulse DP signal in one frame (1V) cycle period is apparently converted to a triple speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the pulse DP (ratio between the light emission period and the non-light emission period) is set to 7: 3 as shown in FIG. 14, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. In order to detect a high level period in one frame (1V) period of the pulse DP and suppress a difference from the flicker appearance in FIGS. 12 and 13, a quarter frame (1/4 × V) is defined as a period. A light emission control signal DS having the same duty ratio as that of the light emission period pulse DP, that is, 7: 3, is generated in the subframe cycle period. It provided four in over arm (1V) period duration. That is, the light emission period pulse DP signal in one frame (1V) cycle period is apparently converted to a quadruple speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the pulse DP (ratio between the light emission period and the non-light emission period) is set to 6: 4 as shown in FIG. 15, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. In order to detect a high level period in one frame (1V) cycle period of the pulse DP and suppress a difference from the flicker appearance in FIGS. 12, 13 and 14, 1/5 frame (1/5 × V) is used. A light emission control signal DS having the same duty ratio as that of the light emission period pulse DP, that is, 6: 4, is generated in the sub-frame period period, and the signal It provided five in one frame (1V) period duration. That is, the light emission period pulse DP signal in one frame (1V) cycle period is apparently converted to a 5 × speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the pulse DP (ratio between the light emission period and the non-light emission period) is set to 5: 5 as shown in FIG. 16, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. In order to detect a high level period in one frame (1V) period of the pulse DP and suppress the difference from the flicker appearance in FIGS. 12, 13, 14, and 15, a 1/6 frame (1/6 × V ) Is generated in a sub-frame cycle period having the same duty ratio as the light emission period pulse DP, that is, 5: 5. Signal six provided in one frame (1V) period duration. That is, the light emission period pulse DP signal in one frame (1V) period period is apparently converted to 6 × speed. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the pulse DP (ratio between the light emission period and the non-light emission period) is set to 4: 6 as shown in FIG. 17, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. In order to detect a high level period in one frame (1V) period of the pulse DP and suppress a difference from the flicker appearance in FIGS. 12, 13, 14, 15, and 16, a 1/7 frame (1/7) The light emission control signal DS is generated so that the same duty ratio as that of the light emission period pulse DP, that is, 4: 6, is generated in the sub-frame period with the cycle of × V). Provided seven in the signal frame (1V) period duration. That is, the light emission period pulse DP signal in one frame (1V) cycle period is apparently converted to a 7 × speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the pulse DP (ratio between the light emission period and the non-light emission period) is set to 3: 7 as shown in FIG. 18, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. In order to detect a high level period in one frame (1V) period of the pulse DP and suppress a difference from the flicker appearance in FIGS. 12, 13, 14, 15, 16, and 17, a 1/8 frame (1 / 8 × V) in the sub-frame period, the light emission control signal DS has the same duty ratio as the light emission period pulse DP, that is, 3: 7. Produced, it provided eight in the signal frame (1V) period duration. That is, the light emission period pulse DP signal in one frame (1V) cycle period is apparently converted to a timing of 8 × speed. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the pulse DP (ratio between the light emission period and the non-light emission period) is set to 2: 8 as shown in FIG. 19, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. In order to detect a high level period in one frame (1V) period of the pulse DP and suppress a difference from the flicker appearance in FIGS. 12, 13, 14, 15, 16, 17, and 18, 1/9 frame Light emission control so that the same duty ratio as that of the light emission period pulse DP, that is, 2: 8, is obtained in the subframe period with a period of (1/9 × V). No. generates DS, provided nine in the signal frame (1V) period duration. That is, the light emission period pulse DP signal in one frame (1V) cycle period is apparently converted into 9-times speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  Further, in the light emission control means Z, the light emission period setting circuit 21 uses the light emission period setting circuit 21 to obtain a desired luminance corresponding to the luminance setting signal supplied from the outside processed by the luminance setting signal receiver 20 by the luminance level setting circuit 22. In the control in which the duty ratio of the pulse DP (ratio between the light emission period and the non-light emission period) is set to 1: 9 as shown in FIG. 20, the light emission period pulse DP set by the light emission period setting circuit 21 is emitted by the flicker suppression circuit 23. In order to detect a high level period in one frame (1V) period of the pulse DP and suppress the difference from the flicker appearance in FIGS. 12, 13, 14, 15, 16, 17, 18, and 19, The same duty ratio as the light emission period pulse DP, that is, 1: 9, in the sub-frame period with a period of 10 frames (1/10 × V) Generating a light control signal DS, provided ten in the signal frame (1V) period duration. That is, the light emission period pulse DP signal in one frame (1V) cycle period is apparently converted to a 10-times speed timing. However, since there is no change in the ratio of the light emission time to the non-light emission time in one frame (1V) period, the luminance of light emission does not change.

  As described above, in the organic EL display device that controls the display luminance according to the light emission time of the pixel 11, the subframe frequency is changed according to the duty ratio of the light emission period pulse DP signal in one frame (1V) period period, and the subframe By making the duty ratio in the frame the same as the duty ratio in one frame, flicker (flicker) and flicker Differences in level (how the flicker appears) can be easily suppressed. In the above embodiment, the case where the present invention is applied to an organic EL display device using the organic EL element 17 as a display element of the pixel 11 is described as an example. However, the present invention is not limited to this. The present invention can be applied to all display devices using self-luminous elements as display elements.

  Finally, FIG. 21 is a block diagram showing a configuration example of the organic EL display panel shown in FIG. The display panel 15 is selected by a pixel array unit 12 in which pixel circuits (PXLC) 11 are arranged in an m × n matrix, a data line driving circuit 14, scanning line driving circuits 13, 13a, and a data line driving circuit 14. Data lines DTL-1 to DTL-m to which signals corresponding to luminance information are supplied, scanning lines WSL-1 to WSL-n selectively driven by the additional scanning line driving circuit 13a, and selection by the scanning line driving circuit 13 It has scanning lines DSL-1 to DSL-n to be driven. Here, the scanning line driving circuit 13 performs duty driving, and the scanning line driving circuit 13a performs data writing driving to each pixel prior to duty driving.

  FIG. 22 is a circuit diagram showing a configuration example of the pixel circuit shown in FIG. As shown in the figure, the pixel circuit 11 is basically composed of a p-channel thin film field effect transistor (hereinafter referred to as TFT). That is, the pixel circuit 11 includes a drive TFT 111, a switching TFT 112, a sampling TFT 115, an organic EL element 17, and a storage capacitor C111. The pixel circuit 11 having such a configuration is arranged at the intersection of the data line DTL-1 and the scanning lines WSL-1 and DSL-1. The data line DTL-1 is connected to the drain of the sampling TFT 115, the scanning line WSL-1 is connected to the gate of the sampling TFT 115, and the other scanning line DSL-1 is connected to the gate of the switching TFT 112.

  The drive TFT 111, the switching TFT 112, and the organic EL element 17 are connected in series between the power supply potential Vcc and the ground potential GND. That is, the source of the drive transistor 111 is connected to the power supply potential Vcc, while the cathode of the organic EL element (light emitting element) 17 is connected to the ground potential GND. In general, the organic EL element 17 is represented by a diode symbol because of its rectifying property. On the other hand, the sampling TFT 115 and the storage capacitor C111 are connected to the gate of the drive TFT111. The gate-source voltage of the drive TFT 111 is represented by Vgs.

  The operation of the pixel circuit 11 is as follows. First, when the scanning line WSL-1 is in a selected state (low level here) and a signal is applied to the data line DTL-1, the sampling TFT 115 is turned on and the signal is written to the holding capacitor C111. It is. The signal potential written in the storage capacitor C111 becomes the gate potential of the drive transistor 111. Subsequently, when the scanning line WSL-1 is in a non-selected state (here, high level), the data line DTL-1 and the drive TFT 111 are electrically disconnected, but the gate potential Vgs of the drive TFT 111 is stabilized by the storage capacitor C111. Retained. Subsequently, when another scanning line DSL-1 is selected (here, at a low level), the switching TFT 112 becomes conductive, and a drive current flows through the TFT 111, TFT 112, and the light emitting element 17 from the power supply potential Vcc toward the ground potential GND. When DSL-1 is in a non-selected state, the switching transistor 112 is turned off and the driving current does not flow. The switching TFT 112 is inserted in order to control the light emission time of the light emitting element 17.

  The current flowing through the TFT 111 and the light emitting element 17 has a value corresponding to the gate-source voltage Vgs of the TFT 111, and the light emitting element 17 continues to emit light with a luminance corresponding to the current value. As described above, the operation of selecting the scanning line WSL-1 and transmitting the signal applied to the data line DTL-1 to the inside of the pixel circuit 11 is referred to as “writing”. As described above, once a signal is written, the light emitting element 17 continues to emit light at a constant luminance until the next rewriting.

1 is a schematic configuration diagram illustrating an active matrix organic EL display device according to an embodiment of the present invention. It is a block diagram which shows an example of a structure of the light emission control means in the display apparatus which concerns on this invention. It is a timing chart showing the waveforms of a vertical synchronization signal and a light emission time setting signal according to a conventional method. It is a timing chart showing the waveforms of a vertical synchronizing signal and a light emission time setting signal when flicker is suppressed by a conventional method. A light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 4: 1 and a light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 4: 1. It is a timing chart showing a DS signal that is apparently converted to a double speed timing. A light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 1: 1, and a light emission period pulse in one frame (1V) cycle period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 1: 1. It is a timing chart showing a DS signal that is apparently converted to a double speed timing. The light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 1: 4 and the light emission period pulse in one frame (1V) cycle period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 1: 4. It is a timing chart showing a DS signal that is apparently converted to a double speed timing. A light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 4: 1 and a light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 4: 1. FIG. 6 is a timing chart showing a DS signal obtained by apparently converting a signal to a triple speed timing. A light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 1: 1, and a light emission period pulse in one frame (1V) cycle period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 1: 1. FIG. 6 is a timing chart showing a DS signal obtained by apparently converting a signal to a triple speed timing. The light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 1: 4 and the light emission period pulse in one frame (1V) cycle period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 1: 4. FIG. 6 is a timing chart showing a DS signal obtained by apparently converting a signal to a triple speed timing. It is a figure showing the flicker level (how the flicker looks) when the duty of the light emission period and the non-light emission period is set to 0 to 100%. The light emission period pulse DP in which the ratio of the light emission / non-light emission time is set to 9: 1 and the light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of the light emission / non-light emission time at 9: 1. FIG. 4 is a timing chart showing a DS signal that is apparently converted to a double speed timing. The light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 8: 2, and the light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 8: 2. FIG. 4 is a timing chart showing a DS signal that is apparently converted to a triple speed timing. Light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 7: 3 and light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time to 7: 3 FIG. 5 is a timing chart showing a DS signal that is apparently converted to a quadruple speed timing. The light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 6: 4 and the light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 6: 4. FIG. 4 is a timing chart showing a DS signal that is apparently converted to a 5 × speed timing. The light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 5: 5 and the light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time at 5: 5. FIG. 6 is a timing chart showing a DS signal that is apparently converted to a 6 × speed timing. Light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 4: 6, and light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time to 4: 6. FIG. 5 is a timing chart showing a DS signal that is apparently converted to a 7 × speed timing. Light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 3: 7 and light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time to 3: 7 FIG. 4 is a timing chart showing a DS signal that is apparently converted to a 8 × speed timing of a DP signal. The light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 2: 8 and the light emission period pulse in one frame (1V) period period so as to suppress flicker while the ratio of light emission / non-light emission time is 2: 8. FIG. 6 is a timing chart showing a DS signal that is apparently converted to 9 × speed timing. The light emission period pulse DP in which the ratio of light emission / non-light emission time is set to 1: 9 and the light emission period pulse in one frame (1V) period period so as to suppress flicker while maintaining the ratio of light emission / non-light emission time 1: 9. FIG. 5 is a timing chart showing a DS signal that is apparently converted to a 10 × speed timing of a DP signal. It is a block diagram which shows an example of the organic electroluminescent panel shown in FIG. It is a circuit diagram which shows an example of the pixel circuit contained in the organic electroluminescent panel shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Pixel, 12 ... Pixel array part, 13 ... Scanning line drive circuit, 14 ... Data line drive circuit, 15 ... Organic EL panel part, 16 ... System circuit, 17. ..Organic EL element, 19... Timing generator, 21... Light emission period setting circuit, 22... Brightness level setting circuit, 23.

Claims (5)

A pixel array unit, a scanning line driving circuit and a data line driving circuit for driving the pixel array unit, and a system circuit for controlling them,
The pixel array unit includes a row-shaped scanning line, a column-shaped data line, and a pixel formed of a light emitting element disposed at a portion where both intersect.
The data line driving circuit is connected to each data line, and supplies a video data signal supplied in units of frames from the system circuit to each pixel.
The scanning line driving circuit is connected to each scanning line, operates in accordance with a light emission control signal supplied from the system circuit, selects pixels line by frame for each frame, and has luminance corresponding to the video data signal. In a display device that emits light from each light emitting element,
The system circuit includes light emission control means, sets a duty ratio between a light emission time and a non-light emission time in one frame according to screen luminance information, and causes each light emitting element to emit light according to the duty ratio. ,
A display device, wherein one frame is divided into a plurality of subframes, and each light emitting element emits light for a light emission time corresponding to the duty ratio in each subframe to suppress flicker.   The display device according to claim 1, wherein the light emission control unit sets the number of subframes according to a set duty ratio.   The display device according to claim 2, wherein the light emission control unit increases the number of subframes as the duty ratio decreases.   The display device according to claim 1, wherein the light emitting element is an organic electroluminescence light emitting element. A pixel array section constituting a screen, and a scanning line driving circuit and a data line driving circuit for driving the pixel array section, wherein the pixel array section is a portion where a row scanning line and a column data line cross each other The data line driving circuit is connected to each data line, and supplies a video data signal supplied from the outside in units of frames to each pixel, and drives the scanning line. The circuit is connected to each scanning line, and operates according to a light emission control signal supplied from the outside. The pixels are line-sequentially selected for each frame, and each light emitting element emits light with a luminance corresponding to the video data signal. In a method for driving a display device,
In accordance with the brightness information of the screen, the duty ratio between the light emission time and the non-light emission time in one frame is set, and each light emitting element is caused to emit light according to the duty ratio,
A display device driving method, wherein one frame is divided into a plurality of sub-frames, and each light-emitting element emits light for each sub-frame for a light emission time according to the duty ratio to suppress flicker.

Images