JP2006024754A - Wiring layer, forming method thereof, and thin-film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a specific resistance of 2.5 μΩcm or smaller, even for a thin film in which the wiring film thickness is in sub μm order of approximately 200-1,000 nm, and to provide a method for forming a wiring layer and to provide the wiring layer. <P>SOLUTION: In the wiring layer, a silicon nitride film in a substrate insulating film 2 is formed on a glass substrate 1, a substrate metal layer 3 is formed on it, a metal seed layer 4 is formed on it, and a metal wiring layer 7 is formed on the metal seed layer 4. In the wiring layer, the crystal surface of the metal seed layer 4 is orientated mainly in the (111) orientation, the average crystal particle diameter is 0.25 μm or larger, and the film thickness of the metal wiring layer is 200-1,000 nm and is formed by an electroless plating method. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming a wiring layer formed with low resistance, a wiring layer, and a thin film transistor.

  Generally, aluminum (Al) or an alloy thereof is mainly used as a material for wiring and electrodes in a semiconductor device represented by LSI or ULSI. However, due to the progress of miniaturization due to the recent improvement in integration and the improvement of the operation speed, the next generation of copper (Cu), which has lower resistance than Al and higher resistance to electromigration and stress migration, etc. Development is underway for the purpose of adopting it as a material for wiring and electrodes.

  Furthermore, in the field of display devices such as liquid crystal display devices, for example, there is a demand for increasing the wiring length by expanding the display area, and monolithic mounting with various additional functions such as a driver circuit for driving and an in-pixel memory. In addition, low-resistance wiring is required in the same manner as in the semiconductor field due to large capacity, large screen, and high-definition liquid crystal display devices suitable for the digital age.

Copper fine wiring processing, like Al wiring formation technology, masking technology using PEP (Photo Engraving Process, so-called photolithography), RIE (Reactive Ion Etching) method, etc. Even if this etching technique is simply combined, it has been difficult to realize. In other words, the vapor pressure of copper halide is very low (ie, difficult to evaporate) with respect to Al, and when an etching technique such as RIE is used, the process temperature is adjusted to 200 to 300 ° C. There are many problems such as the necessity of an etching process below. Further, it is necessary to use a mask made of SiO ₂ or SiNx instead of a normal photoresist mask. The fine wiring processing of copper is disclosed in Patent Document 1 and Patent Document 2 by a method called a damascene method, for example.

The fine wiring process of copper by this damascene method is processed through the following steps. That is, first, a wiring groove having a desired wiring pattern is formed in advance on the insulating layer on the substrate. Next, in order to prevent the diffusion of copper into the silicon oxide layer, a copper diffusion prevention layer such as TaN, Ta, TiN or the like is formed as a base layer of the thin copper layer. In this method, a thin copper layer is formed on the copper diffusion prevention layer. This copper thin layer is formed by various methods such as PVD (PHYSICAL VAPOR DEPOSITION) method such as sputtering method, plating method or CVD (CHEMICAL VAPOR DEPOSITION) method using an organic metal material so as to fill the wiring groove. Using a technique, it is embedded in the groove and formed over the entire surface of the insulating layer. After that, the thin copper layer is removed using a polishing method such as CMP (CHEMICAL MECHANICAL POLISING) or etch back until the underlying insulating layer is exposed from the substrate surface side (open end face of the groove). Then, a wiring pattern made only of copper embedded in the groove is formed. Furthermore, it is a method of covering the copper wiring layer by forming an insulating layer or a metal layer having a copper diffusion preventing ability on the copper wiring.
JP 2001-189295 A Japanese Patent Laid-Open No. 11-135504

However, the conventional techniques including the technique disclosed in the above publication have the following problems. In the damascene method, at least a groove processing step for forming a groove for embedding wiring, a metal diffusion prevention layer, a metal seed layer, a metal wiring layer, and a film formation step for forming a polishing stopper film, a photolithography step, etching A process, a grinding | polishing process, etc. are required, a manufacturing process becomes complicated and manufacturing cost becomes high.

  In order to reduce the wiring resistance, it is necessary to increase the cross-sectional area of the wiring. However, due to the limitation of integration, if a groove or via hole with a high aspect ratio (that is, a narrow width and diameter) is used, Copper embedding is reduced. In order to reduce the wiring resistance, in LSI, a film having a thickness of the order of μm is formed. However, a thin film transistor (TFT) circuit requires a thickness of the order of sub-μm, and it is difficult to obtain a copper wiring having a specific resistance of 2.5 μΩcm or less with this order of thickness. In addition, a CMP process or the like of removing unnecessary portions after forming a thin copper layer on the entire surface of the substrate requires processing time and has a problem of poor throughput.

  Furthermore, although a large-sized CMP apparatus corresponding to a large-diameter semiconductor wafer size such as 12 inches in diameter has been developed, for a display apparatus using a glass substrate having a larger area and lower flatness than the semiconductor wafer. This manufacturing apparatus has not been put into practical use. Further, in the case of manufacturing a display device using a large glass substrate having a long side of 1 m or more, the area of the copper thin layer portion used as the wiring even if the entire surface polishing by CMP or the etching method can be removed. Is very small compared to the area of the glass substrate, so that most of the deposited copper thin layer is removed and discarded. As a result, the utilization efficiency of expensive copper becomes very poor, and the product price increases due to the high cost.

  In order to improve the utilization efficiency of copper as a wiring material, the present inventors have developed a selective electroless copper plating process using a resist. In this electroless copper plating wiring formation process, a copper seed layer (hereinafter abbreviated as a sputtered copper seed layer) is formed by sputtering before forming an electroless copper plating film, and a resist groove of a wiring pattern is formed thereon. In this method, a copper wiring layer is formed in the groove by electroless plating, the resist film of the wiring pattern is removed, and then the copper seed layer is etched. This electroless copper plating film forming process can form a copper wiring thin film having a low specific resistance value even with a low wiring thickness of about 300 to 600 nm used in a display device such as a liquid crystal. However, when a wiring having a low wiring thickness of about 300 to 600 nm is formed by an electroless plating method, there is a problem that the specific resistance value of the copper wiring layer largely depends on the crystallinity of the copper seed layer. If the copper wiring has a high specific resistance value, it is meaningless to use the copper wiring. Therefore, it is necessary to realize a specific resistance value of 2.5 μΩcm or less even in a sub-μm order wiring having a film thickness of about 200 to 1000 nm. is there.

The reason why the sputtered copper seed layer is used without using the Pd catalyst nucleus normally used in the electroless plating method is that, in the electroless plating grown from the Pd catalyst nucleus, the copper grows around the Pd nucleus and centers on the Pd nucleus. Since the Cu nuclei collide with each other to form a wiring, it is difficult to apply to a thin wiring film, and it is necessary to increase the Pd nucleus density. However, it is difficult to control the density and uniformity of Pd nuclei, and there is a problem that Pd diffuses into copper by heat treatment in a later process to increase the specific resistance. For this reason, of course, the method of forming the copper seed layer by the electroless plating method using the Pd catalyst also has the same problem, and in addition, the problem of low adhesion to the underlying metal layer having barrier properties. Also have.

  The present invention has been made in response to the above problems, and a wiring layer forming method and wiring capable of obtaining a specific resistance of 2.5 μΩcm or less even with a sub-μm order thin film having a wiring film thickness of about 200 to 1000 nm. It is an object to provide a layer and a thin film transistor.

  In order to solve the above problems, the wiring layer forming method, wiring layer and thin film transistor of the present invention are provided with a metal seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more. On the seed layer, there is a film provided by electroless plating a metal wiring layer having a thickness of 200 to 1000 nm.

  The wiring layer forming method of the present invention includes a step of forming a metal seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more, and a film thickness of 200 to 1000 nm on the metal seed layer. And a step of electrolessly plating the metal wiring layer. According to this method for forming a wiring layer, a specific resistance of 2.5 μΩcm or less can be obtained even in a sub-μm order thin film having a wiring film thickness of about 200 to 1000 nm.

  The wiring layer forming method of the present invention includes a step of forming a copper seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more, and a film thickness of 200 to 1000 nm on the copper seed layer. And a step of electrolessly plating the copper wiring layer. According to this method for forming a wiring layer, a specific resistance of 2.5 μΩcm or less can be obtained even in a sub-μm order thin film having a copper wiring film thickness of about 200 to 1000 nm.

  The wiring layer forming method of the present invention includes a step of forming a base metal layer on a substrate, and a copper seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more on the base metal layer. Forming a copper wiring layer having a predetermined thickness of 200 to 1000 nm on the copper seed layer, and at least the copper other than the region bonded to the copper wiring layer And a step of removing the seed layer and the base metal layer. According to this method for forming a wiring layer, a specific resistance of 2.5 μΩcm or less can be obtained even in a sub-μm order thin film having a copper wiring film thickness of about 200 to 1000 nm. Furthermore, the average crystal grain size of the copper wiring layer can be increased by selecting the metal of the base metal layer.

  The wiring layer of the present invention is a wiring layer in which a metal wiring layer is provided on a metal seed layer, and the metal seed layer has a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more. The metal wiring layer has a thickness of 200 to 1000 nm and is an electroless plated layer. According to this wiring layer, a specific resistance of 2.5 μΩcm or less can be obtained even in a sub-μm order thin film having a wiring film thickness of about 200 to 1000 nm. Furthermore, a copper wiring layer having a low specific resistance can be formed even on a large substrate of 1 m or more.

  The thin film transistor of the present invention includes a semiconductor thin film having a crystallization region, a thin film transistor having a gate electrode provided in the crystallization region with a source region and a drain region, and a gate insulating film provided in the crystallization region. And at least one of the source electrode, drain electrode, and gate electrode of the thin film transistor has a metal seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more, and on the metal seed layer The electroless plating layer having a thickness of 200 to 1000 nm is provided on the substrate. According to this thin film transistor, it is possible to obtain at least one of an electrode and a wiring having a specific resistance of 2.5 μΩcm or less even if the wiring film thickness is a sub-μm order thin film of about 200 to 1000 nm. Furthermore, at least one of a low specific resistance electrode and a wiring layer can be formed even on a large substrate of 1 m or more.

  In the metal seed layer, the main crystal plane (111) means that the (111) peak detected by X-ray diffraction is larger than the (200) peak, and preferably its intensity ratio I (111) / I ( 200) is preferably 10 or more.

  According to the method of the present invention, a specific resistance of 2.5 μΩcm or less can be obtained even in a sub-μm order thin film having a wiring film thickness of about 200 to 1000 nm.

  Next, a method for forming a wiring layer and an embodiment of the wiring layer according to the present invention will be described with reference to the drawings. In this embodiment, a metal seed layer mainly composed of copper having a crystal plane mainly oriented to (111) and an average crystal grain size of 0.25 μm or more is provided, and a film thickness of 200 to 200 is formed on the metal seed layer. This is an example in which a metal wiring layer having a sub-μm order of 1000 nm is provided by electroless plating. Metal wiring mainly composed of copper For example, a metal wiring layer mainly composed of copper in a thin film transistor circuit has an extremely thin film thickness of 200 to 1000 nm. Even such a metal wiring mainly composed of ultra-thin copper enables a wiring having a low resistance of 2.5 μΩcm or less.

  This mechanism can be explained as follows. That is, in normal electrolytic copper plating or electroless copper plating layer formation, since the wiring thickness is as thick as about 1 to 30 μm, the plating film thickness increases and the crystal grain size increases. On the other hand, wiring such as a liquid crystal display device requires a thin film on the order of sub-μm, so that the wiring film thickness cannot be increased. Reduction of the specific resistance of the copper-plated wiring layer can be achieved by increasing the crystal grain size of the copper-plated wiring layer. It has been found that the formation of wiring with a thin copper-plated wiring layer, such as a liquid crystal display device, is greatly affected by the crystallinity of the metal seed layer. That is, in order to obtain a low specific resistance of 2.5 μΩcm or less with a thin film on the order of sub μm, the crystal grain size of the copper plating wiring layer is set by setting the crystal grain size of the metal seed layer to 0.25 μm or more. It has been found that the diameter can be increased. The ability to increase the crystal grain size of the copper-plated wiring layer makes it possible to obtain a low-resistance copper-plated wiring layer. The orientation mainly at (111) means that the (111) peak detected by X-ray diffraction is larger than the (200) peak, and preferably the intensity ratio I (111) / I (200) is 10 or more. It is desirable that

  Next, an embodiment in which the wiring layer forming method is applied to a copper (Cu) wiring layer forming method will be described in the order of steps with reference to FIGS. FIG. 1 is a cross-sectional view for explaining a preparation step for forming a Cu wiring layer in a patterned region in the order of steps. FIG. 2 is a cross-sectional view for explaining a method of forming a Cu wiring layer in a patterned region in the order of steps.

  A base insulating layer 2 such as a silicon nitride (SiN) film is formed on a substrate such as a glass substrate 1 as shown in FIG. On this SiN film, as shown in FIG. 1B, a base metal layer 3 such as a tantalum (Ta) layer that is also effective as a copper barrier film is formed by, for example, sputtering. Regarding the film thickness, for example, a Ta layer is preferably formed to 50 nm. The base metal layer 3 is preferably composed of at least one material layer among the laminated films of β-Ta, α-Ta, TaSiN, TaN, TaN and α-Ta in addition to the Ta layer. Further, a metal seed layer 4, for example, a metal seed layer mainly composed of copper is formed on the base metal layer 3 as shown in FIG. The metal seed layer mainly composed of copper is formed with a thickness of, for example, 50 nm, for example, by sputtering. The metal seed layer containing copper as a main component has a crystal orientation mainly oriented in (111) and an average crystal grain size of 0.25 μm or more.

  The Ta layer as the base metal layer 3 that is also effective as a copper barrier film is effective in forming the metal seed layer 4 having a large average crystal grain size on the laminated film. The metal seed layer 4 having an average crystal grain size of 0.25 μm or more enables a metal wiring layer 7 having a low specific resistance to be formed on the metal seed layer 4.

A photoresist layer 5 is formed on the metal seed layer 4 in order to form a wiring material only in a predetermined wiring pattern region as shown in FIG. The photoresist layer 5 is formed, for example, by a spin coating method to a film thickness of 1.2 μm, for example. The thickness of the photoresist layer 5 is selected to be greater than or equal to the thickness of the metal wiring layer 7. In this way, the preparation process for forming the wiring layer only in the wiring pattern region is completed.

  Next, a method for forming a metal wiring layer mainly composed of copper in a patterned region will be described in the order of steps with reference to FIG. A mask image of a predetermined electrode pattern or a desired wiring formation pattern is projected onto the photoresist layer 5 and exposed. After the exposure, a development process is then performed to form a groove pattern 6 in the wiring pattern region in the photoresist layer 5 as shown in FIG. In this state, the surface of the metal seed layer 4 is exposed on the bottom surface of the groove pattern 6.

  Next, a metal wiring layer 7 is formed in the groove pattern 6 as shown in FIG. In this film forming method, the metal wiring layer 7 mainly composed of copper is formed by an electroless plating method, for example, by forming an extremely thin film thickness of 200 nm to 1000 nm, for example, 300 nm. That is, a copper plating layer is epitaxially grown on a copper seed layer mainly oriented in the crystal orientation (111). At this time, the average crystal grain size of the copper seed layer and the average crystal grain size of the copper plating layer are substantially equal. The crystal grain size of the copper plating layer is larger on the copper seed layer having a larger average crystal grain size regardless of the plating conditions. Of course, as a pretreatment for forming the metal wiring layer 7 by the electroless plating method, it is desirable to add a cleaning process for removing the oxide on the surface of the metal seed layer 4.

As such an electroless plating bath for forming the metal wiring layer 7 mainly composed of extremely thin copper, it is desirable to use, for example, a neutral electroless plating bath using a cobalt salt as a reducing agent. The composition of the neutral electroless plating bath is, for example, cobalt sulfate or cobalt nitrate as a reducing agent, copper sulfate or copper nitrate as a copper salt, ethylenediamine as a complexing agent, ascorbic acid or complexing agent as a reducing agent, and the like. For example, 2,2′-bipyridyl may be used as an agent, and hydrochloric acid may be used as a reaction initiator. Since the neutral electroless plating bath using a cobalt salt as a reducing agent has a pH range of about 6 to 7, in addition to being able to use a normal photoresist, it does not contain harmful substances or alkali metals. There is an advantage that it can be applied to the manufacturing process of the thin film transistor.

Formation of the metal wiring layer 7 containing copper as a main component by electroless plating enables formation of a thin film on a glass substrate for a liquid crystal display device having a size of 1 m or more. In order to obtain a specific resistance of 2.5 μΩcm or less even in a sub-μm order thin film, it is important that the crystal grain size of the metal wiring layer 7 containing copper as a main component is an average crystal grain size of 0.25 μm or more. Further, electroless plating of the copper plating layer only on the groove pattern 6 is a manufacturing method having a resource saving effect because copper is not formed on unnecessary portions.

Next, as shown in FIG. 2C, the photoresist layer 5 is removed. As a result, the metal wiring layer 7 and the metal seed layer 4 mainly composed of copper are exposed on the surface. Next, the metal seed layer 4 is etched and removed using the metal wiring layer 7 as a mask. Further, using the metal wiring layer 7 as a mask, the base metal layer 3 is removed by etching as shown in FIG. As a result, the substrate 8 in which the pattern of the metal wiring layer 7 mainly composed of copper is formed on the surface of the SiN film can be obtained.

The metal wiring layer 7 containing copper as a main component can obtain a low specific resistance of 2.5 μΩcm or less even in a sub-μm order thin film having a wiring film thickness of about 200 to 1000 nm. In the formation of the copper wiring layer using the neutral electroless plating bath in which the cobalt salt is reduced, the crystal orientation of the copper plating layer depends on the crystal orientation of the metal seed layer 4 and the film of the metal wiring layer 7 The inventors have found that when the thickness is as thin as about 300 nm, the average crystal grain size of the copper plating layer is almost equal to that of the metal seed layer 4. That is, by selecting the crystal grain size of the metal seed layer 4 to be a crystal grain size for obtaining a low specific resistance of 2.5 μΩcm or less, a metal wiring layer 7 having a low specific resistance can be formed even with an extremely thin metal wiring layer 7. It is a thing.

Formation of a low specific resistance electroless copper-plated wiring layer of 2.5 μΩcm or less is to form a wiring layer having a large crystal grain size. In the manufacturing method of a display device such as a liquid crystal display device, the crystal grain size is increased by increasing the wiring thickness due to the unevenness before and after the metal wiring, the coverage of the insulating layer after the wiring is formed, and the demand for reducing the surface unevenness of the substrate. It is not possible. As a result of diligent development to solve this problem, it has been found that a low-resistance copper-plated wiring layer can be obtained particularly by increasing the crystal grain size of the metal seed layer 4. That is, in order to obtain a low specific resistance of 2.5 μΩcm or less with a thin film on the order of sub-μm, the crystal grain size of the metal seed layer 4 is set to an average crystal grain size of 0.25 μm or more so that the crystal of the copper plated wiring layer is crystallized. It was found that the particle size can be increased. The fact that the crystal grain size of the copper-plated wiring layer can be increased is that a low-resistance copper-plated wiring layer can be obtained. Thus, it was found that the crystallinity of the copper seed layer is important in order to obtain a copper plating layer having a low specific resistance of 2.5 μΩcm or less with a thin film of the order of sub μm.

  Next, when the copper seed layer is formed as the metal seed layer 4 and the copper plating layer is formed as the metal wiring layer 7 formed on the copper seed layer, the average crystal grain size of the copper plating layer and the specific resistance thereof are concretely shown. Specific examples are shown in Table 1. In Table 1, the copper seed layers A, B, C, and D all have a crystal orientation of mainly (111). Table 1 shows the relationship between the average crystal grain size of the copper seed layer and the average crystal grain size of the copper plating layer and the specific resistance when the copper plating layer is formed on the copper seed layer by electroless plating. Has been.

Here, the specific resistance values in Table 1 are specific resistance values of only the copper plating layer as the metal wiring layer 7 excluding the base metal layer 3 and the metal seed layer 4. The copper seed layer A is formed on a base metal layer made of TiN, and the average crystal grain size of the copper seed layer A is 0.166 μm. The average crystal grain size of the copper plating layer formed by electroless plating on the copper seed layer A is 0.160 μm.

The copper seed layers B and C are copper seed layers formed on a base metal layer made of Ta, and the average crystal grain sizes of the copper seed layers B and C are 0.284 μm and 0.462 μm. The average crystal grain sizes of the copper plating layers formed by electroless plating on the copper seed layers B and C are 0.298 μm and 0.456 μm, respectively.

The copper seed layer D is formed on a base metal layer made of TaSiN, and the average crystal grain size of the copper seed layer D is 0.425 μm. The average crystal grain size of the copper plating layer formed by electroless plating on the copper seed layer D is 0.394 μm.

As can be seen from Table 1, the average crystal grain size of the underlying copper seed layer and the average grain size of the copper plating layer are substantially the same, and the larger the average crystal grain size of the copper seed layer is, the higher the ratio of the copper plating layer. It can be seen that the resistance is low. That is, it can be seen that in order to form a copper plating layer having a low specific resistance, the average crystal grain size of the copper seed layer should be increased. In other words, in order to obtain a copper wiring layer having a desired specific resistance, it can be obtained by forming a copper seed layer having a size corresponding to the average crystal grain size. Mainly (111) means that the (111) peak detected by X-ray diffraction is larger than the (200) peak, and the intensity ratio I (111) / I (200) is preferably 10 or more. It is desirable.

In order to obtain a copper plating layer having a specific resistance of 2.2 μΩcm or less, the average crystal grain size of the copper seed layer needs to be about 0.25 μm or more. Here, the average crystal grain size is a value obtained by excluding a twin boundary of 60 ° with respect to a copper seed layer having a crystal orientation of (111) using an electron backscattering (EBSP) method. The average crystal grain size is an average value of diameters obtained by spherical approximation from the crystal grain area.

According to the above embodiment, a metal wiring layer having a large average crystal grain size can be formed by forming a metal wiring layer on the metal seed layer having a large average crystal grain size. A desired specific resistance can be obtained. Further, the metal wiring layer 7 is formed in the groove pattern 6 formed in the photoresist film 7. Therefore, according to this embodiment, only a necessary minimum amount of metal wiring material is required and resource saving is achieved.

  Next, an embodiment in which a metal seed layer having a large crystal grain size is formed will be described. An example of a copper seed layer as a metal seed layer will be described. The copper seed layer A in Table 1 was formed by forming a copper seed layer on a titanium nitride (TiN) layer, and the copper seed layer B and the copper seed layer C were formed by forming a copper seed layer on the Ta layer. The Ta layer of C is mainly composed of α-Ta. For the copper seed layer D, a copper seed layer was formed on the TaSiN layer. It is desirable to use a Ta-based layer rather than a TiN layer as the base metal layer 3 for the crystal orientation of the copper seed layer mainly to (111) and the expansion of the average crystal grain size. Ta layer and TaSiN layer The copper seed layer formed thereon has a larger average grain size. The Ta layer is also preferably a (110) body-centered cubic α-Ta layer rather than a (200) square β-Ta layer, and a TaN layer or a stacked film of a TaN layer and an α-Ta layer may be used. The stacked film of TaN layer and α-Ta layer is likely to form a β-Ta layer if only the Ta layer is formed. However, if a thin TaN layer is formed under the Ta layer, an α-Ta layer is likely to be formed. In addition to improving the crystal orientation of the copper seed layer formed on the α-Ta layer, there is an advantage that the specific resistance value of the α-Ta layer is about 1/10 of the specific resistance value of the β-Ta layer. It is.

  Next, another embodiment for forming a metal seed layer having a large crystal grain size will be described. An example of a copper seed layer as a metal seed layer will be described. The crystal grain size of the copper seed layer can be increased not only by the material of the base metal layer 3 described above but also by heat treatment after forming the copper seed layer. In this heat treatment, after the copper seed layer is formed, the average crystal grain size of the copper seed layer can be increased by heating (annealing) at a temperature, eg, 400 ° C., for a time, eg, 10 minutes, in an airtight container, eg, vacuum. . The copper plating layer plated on the copper seed layer with an enlarged average crystal grain size had a large average crystal grain size and a small specific resistance.

  Also in this heat treatment, it is desirable to use Ta or a Ta-based alloy as the base metal layer 3 because the copper seed layer is less likely to aggregate than TiN.

  Next, another embodiment for forming the metal wiring layer 5 having a large crystal grain size will be described. An example of a copper plating layer as the metal wiring layer 5 will be described. The crystal grain size of the copper plating layer can be increased by forming the copper plating layer on the copper seed layer and then heat-treating to increase the average crystal grain size and reducing the specific resistance. Using copper seeds A and B having different average crystal grain sizes, a copper plating layer formed on the copper seeds A and B is heated (annealed) at a temperature of, for example, 450 ° C. for a heating time of, for example, 10 minutes in an airtight atmosphere, for example, in a vacuum. Heat-treated.

As a result after this heat treatment, as shown in Table 1, the crystal grain size increased and the specific resistance value decreased. For example, the average crystal grain size of the copper plating layer formed on the copper seed layer A increased from 0.160 μm to 0.343 μm after annealing, and the specific resistance value decreased from 2.53 μΩcm to 2.1 μΩcm after annealing. . The average crystal grain size of the copper plating layer formed on the copper seed layer B increased from 0.298 μm to 0.506 μm after annealing, and the specific resistance value decreased from 2.18 μΩcm to 1.96 μΩcm. The average crystal grain size of the copper plating layer formed on the copper seed layer C increased from 0.456 μm to 0.616 μm after annealing, and the specific resistance value decreased from 1.97 μΩcm to 1.88 μΩcm after annealing. The average crystal grain size of the copper plating layer formed on the copper seed layer D increased from 0.394 μm to 0.555 μm after annealing, and the specific resistance value decreased from 1.99 μΩcm to 1.92 μΩcm after annealing.

Thus, the average crystal grain size of each copper plating layer formed on the copper seed layer was increased by heat treatment, and the specific resistance value was reduced. Here, the copper plating layer formed on the copper seed layer having a large average crystal grain size even with the heat treatment had a larger average crystal grain size and a smaller specific resistance value. From these results, it was found that the specific resistance value of the plating layer having a large average crystal grain size was small.

The relationship between the average crystal grain size and the specific resistance of the copper plating layer formed in this way is based on the following model formula in which the main factor of the increase in specific resistance is due to scattering at the grain boundary, and the reflection coefficient R = 0.58. It was found that the results agree well.
Specific resistance ρ = ρo (bulk specific resistance) + ρGrain boundary = ρo (1 + 3α / 2)
α = (λ / G) · R / (1-R) λ: Mean Free Path (39.3nm)
R: Reflection Coefficient (0.58) G: Crystal grain size d: Film thickness
ρo = 1.67μΩcm

  FIG. 3 is a plot of the characteristic curve showing the relationship between the specific resistance obtained from the above equation of the grain boundary scattering model of the copper plating layer and the average crystal grain size, and the measured value of the copper plating layer. In this actual measurement value, the characteristic after the copper plating layer is formed by electroless (black) and the characteristic after annealing (white) are plotted. In FIG. 3, the characteristic curve obtained from the above equation is plotted. That is, it is shown that the characteristic curve obtained from the above equation is in good agreement with the tendency of the actual measurement value. In FIG. 3, four embodiments of the characteristics (black) after the electroless copper plating layer is formed are plotted as black squares, black circles, black triangles, and black rhombuses. The characteristics (white) after annealing of the samples of these four embodiments are plotted as white squares, white circles, white triangles, and white rhombuses, respectively. That is, FIG. 3 shows that by annealing, the average crystal grain size becomes large and low specific resistance characteristics can be obtained.

  As is clear from FIG. 3, it can be seen that the copper plating layer having a large average crystal grain size exhibits low specific resistance characteristics. Furthermore, it can be seen that when the copper plating layer is annealed, the average crystal grain size of the copper plating layer becomes large, and therefore, low specific resistance characteristics can be obtained. In the characteristic curve shown in FIG. 3, the average crystal grain size of the copper plating layer having a specific resistance of 2.2 μΩcm is 0.25 μm. In other words, in order to obtain a copper plating layer having a specific resistance of 2.2 μΩcm or less, it is understood that a copper seed layer having an average crystal grain size of 0.25 μm or more may be used.

However, the expansion of the average crystal grain size by annealing is mainly due to the decrease of small crystal grains sandwiched between large crystal grains, and the average crystal grain size of the copper seed layer and the average of the copper plating layer Since the crystal grain sizes are substantially equal, it is considered that the thin film growth by the electroless plating method is performed by colliding with the crystal grains of the copper wiring layer grown on the crystal grains of the copper seed layer. It is presumed that this influences that the reflection coefficient R of the characteristic curve shown in FIG. 3 is as large as 0.58. From the above, it was found that it is important to control the crystallinity and average crystal grain size of the copper seed layer when forming a copper wiring layer having a low specific resistance value by electroless plating.

According to the above embodiment, the material thickness of the base metal layer 3 is selected, the metal seed layer 4 has a large average crystal grain size, and the metal wiring layer 7 has a large average crystal grain size, so that the film thickness is on the order of sub-μm. However, it is possible to obtain a desired low resistivity electrode or wiring. The metal wiring layer 7 of the above embodiment can obtain a low specific resistance (low resistance copper wiring) of 2.5 μΩcm or less even in a sub-μm order thin film having a wiring film thickness of about 200 to 1000 nm.

  In addition, the wiring layer of this embodiment is not only an LCD, but also an organic EL display device (OLED), for example, a signal line, a power line, a scanning line, and an electrode in a TFT formed on a substrate of an active matrix type organic OLED, In addition, the present invention can be easily applied to peripheral wiring and wiring in a peripheral driving circuit formed on the same substrate.

According to the wiring layer forming method of this embodiment, a metal wiring mainly composed of copper can be selectively formed, and a fine wiring pattern as required for the wiring of the peripheral drive circuit can be formed.
The wiring layer of this embodiment is similar in that the wiring for electrically connecting the functional elements and the electrode terminal of the functional element, for example, the thin film transistor, are similar to the current signal path. Then, it defines as a wiring layer including both.

  Next, an embodiment of a thin film transistor circuit to which the copper plated wiring layer is applied will be described. First, a method for manufacturing a crystallized semiconductor film capable of forming a thin film transistor on an arbitrary substrate will be described. In this manufacturing method, a crystallization method for forming a large silicon crystallization region capable of forming at least a channel region of one or a plurality of thin film transistors will be described with reference to FIG. FIG. 4 is a configuration diagram for explaining the crystallization apparatus.

  A laser light source 10 that outputs crystallization energy having a minimum light intensity equal to or higher than the melting temperature, for example, an XeC1 excimer laser light source having a wavelength in the ultraviolet region, for example, 308 nm is provided. The optical path of the laser light source 10 is provided with a homogenizer 11 for making the light intensity of the incident laser light uniform. The homogenizer 11 is a device that spreads incident laser light in a horizontal direction to form a linear (for example, a line length of 200 mm) laser beam, and makes the light intensity distribution uniform. For example, the homogenizer 11 arranges a plurality of X-direction cylindrical lenses in the Y direction, forms a plurality of light beams arranged in the Y direction, redistributes each light beam with another X-direction cylindrical lens, and similarly, a plurality of Y-direction cylindrical lenses. This is an optical system in which lenses are arranged in the X direction, a plurality of light beams arranged in the X direction are formed, and each light beam is redistributed by another Y-direction cylindrical lens.

In the outgoing optical path of the homogenizer 11, a phase shifter 12 is provided for forming a light intensity gradient by phase-modulating the incident laser light. The light intensity gradient is a light beam with an inverse peak-shaped light intensity minimum distribution, a continuous light intensity distribution having a substantially triangular shape, and energy light whose minimum light intensity is equal to or higher than the melting temperature. For example, the phase shifter 12 is provided with a step in a quartz base material, causes diffraction and interference of laser light at the step boundary, and gives a periodic spatial distribution to the laser light intensity. The phase shifter 12 is a case where a phase difference of 180 degrees is given on the left and right, for example, with the stepped portion x = 0 as a boundary. In general, when the wavelength of the laser beam is λ, a transparent medium having a refractive index n is formed on a transparent substrate to give a phase difference of 180 degrees. The film thickness t of the transparent medium is t = λ / 2 (n -1). If the refractive index of the quartz substrate is 1.46, the wavelength of the XeC1 excimer laser light is 308 nm. Therefore, in order to add a phase difference of 180 degrees, a step of 334.8 nm may be formed by a method such as etching. When the SiN _x film is formed as a transparent medium by PECVD, LPCVD, etc., if the refractive index of the SiN _x film is 2.0, the SiN _x film is formed on the quartz substrate at 154 nm and etched to form a step. You can add. The intensity of the laser light that has passed through the phase shift mask having a phase of 180 degrees shows a pattern of periodic strength.

An imaging optical system 13 for forming an image of the light intensity distribution formed by the phase shifter 12 is provided in the outgoing optical path of the phase shifter 12. A crystallized substrate 14 is provided at the imaging position of the imaging optical system 13. The crystallized substrate 14 is provided in alignment on an X · Y · Z · θ stage (not shown). This stage moves so that the crystallization operation is automatically performed at a predetermined position on the crystallized substrate 14 by a program stored in advance. In this way, the crystallization apparatus 15 is configured. The crystallization operation means that the stage is sequentially moved by a program in which information on which position of the crystallized substrate 14 having a size of, for example, 1 m square is irradiated with laser light for crystallization is stored in advance. Control that emits light.

  In the crystallization by the crystallization apparatus 15, the substrate 14 to be crystallized provided in the loader is aligned and transported to a predetermined position on the stage, finely aligned, and then the laser light source 10 is controlled to be irradiated. As a result, the crystallized substrate 14 is automatically crystallized. That is, the laser light source 10 is operated to emit pulsed laser light. This pulsed laser light is incident on the homogenizer 11 to make the light intensity distribution uniform and make the incident angle to the phase shifter 12 uniform.

  The laser beam made uniform by the homogenizer 11 is incident on the phase shifter 12 and is phase-modulated to be modulated into a light intensity distribution with a light intensity gradient. The phase-modulated laser light is collected by the imaging optical system 13 and enters the crystallized substrate 14. This laser light is incident on the crystallized substrate 14 and melts the irradiation region of the non-single crystal semiconductor film. When the pulse period ends and the incidence of laser light on the crystallized substrate 14 is interrupted, the temperature of the melted region rapidly decreases. In this temperature lowering process, crystallization is performed in the lateral direction according to the passage of the solid-liquid branch point along the slope of the light intensity distribution. The crystallized substrate 14 has the following structure so that the lateral crystallization continues for a long time.

  On a substrate such as a glass substrate 21, an insulator layer such as a silicon oxide film 22 is provided which has a function of preventing impurities from penetrating from the substrate 21 and storing the temperature when melted by irradiation with laser light. On the silicon oxide film 22, a non-single crystal semiconductor film such as an amorphous semiconductor film 23 is provided. On the amorphous semiconductor film 23, a cap film, for example, a silicon oxide film 24 having a function of storing a temperature when melted by irradiation with laser light is provided. The crystallized substrate 14 is configured by such a laminated structure.

  When the pulse laser light is incident on the crystallized substrate 14, the pulse laser light passes through the silicon oxide film 24 and is absorbed by the amorphous semiconductor film 23. The light-receiving area of the pulsed laser beam in the amorphous semiconductor film 23 instantaneously rises to a temperature higher than the melting point and melts instantly. This high temperature heat is stored in the silicon oxide films 22 and 24 provided on the front and back surfaces of the amorphous semiconductor film 23. When the incidence of the incident pulse laser is cut off, the melted region of the amorphous semiconductor film 23 tries to cool down at a high speed, but the temperature drop rate is lowered slowly due to the heat accumulation of the silicon oxide films 22 and 24 on the front and back surfaces. Crystallization proceeds along with the gradient of light intensity, and a crystallized region having a large grain size is formed in the lateral direction. The large grain size crystallization region allows the formation of a thin film transistor circuit consisting of one or more thin film transistors.

This crystallization process makes it possible to form a crystallization region in a wide range of the crystallized substrate 14 by moving the stage and repeating the shot of laser light.

  Next, an embodiment in which a thin film transistor circuit is formed in the large grain size crystallization region will be described with reference to FIG. The same parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted. FIG. 5 is a cross-sectional view showing a thin film transistor circuit 31 formed in alignment with a large grain size crystallization region formed in the amorphous semiconductor film 23.

  The thin film transistor circuit is formed in the crystallization region of the crystallized substrate 14 crystallized by the crystallization apparatus 15 of FIG. The silicon oxide film 24 formed on the surface of the crystallized substrate 14 is removed and used, and this state is shown in FIG.

  A source region 32, a drain region 33, and a channel region 34 are provided in the crystallization region 30 of the amorphous semiconductor film 23. On the surface of the crystallization region between the source region 32 and the drain region 33, a gate insulating film 35 such as a silicon oxide film is formed. On the silicon oxide film, a gate electrode 36 is provided above the source region 32 and the drain region 33. On the gate electrode 36 and the gate insulating film 35, a silicon nitride film 38, a silicon oxide film 39, and a silicon nitride film 40 are stacked as an interlayer insulating film 37 (the stacked structure is not shown).

In order to form the electrodes of the source region 32 and the drain region 33, a contact hole is formed in the interlayer insulating film 37. A source electrode 42 and a drain electrode 43 are embedded in each contact hole. A passivation layer 44 made of silicon nitride is provided on the source electrode 42 and the drain electrode 43. The passivation layer 40 made of the silicon nitride film 38, the silicon nitride film 39, and the silicon nitride in the interlayer insulating film 37 also functions as a copper diffusion barrier layer. The gate insulating film 35 is preferably laminated with a silicon nitride film having a barrier property of copper diffusion rather than a single layer of silicon oxide film from the viewpoint of forming a low resistance wiring layer.

  The wiring layer of this embodiment is applied to the gate electrode 36, the source electrode 42, and the drain electrode 43. In this wiring, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted because it is duplicated.

  That is, the gate electrode 36, the source electrode 42, and the drain electrode 43 all form the base metal layer 3, the metal seed layer 4 is formed on the base metal layer 3, and the metal wiring layer is formed on the metal seed layer 4. 7 is formed. The gate electrode 36 can be formed by depositing the base metal layer 3 on the gate insulating film 35, subsequently forming the metal seed layer 4 and the metal wiring layer 7, and then patterning.

In the source electrode 42 and the drain electrode 43, the base metal layer 3 is embedded in contact holes formed in alignment on the source region 32 and the drain region 33, respectively, and then the metal seed layer 4 and the metal wiring layer 7 are formed. It can be formed by film formation. Here, a silicon nitride film having a barrier property is laminated on the copper wiring layer constituting the gate electrode 36, the source electrode 42, and the drain electrode 43. However, in addition to the silicon nitride film, at least the metal seed layer 4, Needless to say, the exposed surface of the metal wiring layer 7 may be covered in advance by an electroless plating method with an alloy layer having a barrier property such as CoWB, CoB, CoWP, or CoP.

Thus, the thin film transistor circuit 31 can be formed as shown in FIG. The thin film transistor circuit 31 enables manufacture of a liquid crystal display device or an organic EL display device.

  As described above, according to the above embodiment, a low resistance copper wiring having a film thickness on the order of sub-μm and a specific resistance of 2.5 μΩcm or less can be realized. In particular, a thin film transistor or a thin film transistor circuit can be formed.

It is sectional drawing for demonstrating the intermediate process to wiring in order of process in embodiment of this invention method. FIG. 2 is a cross-sectional view for explaining a wiring process subsequent to the process of FIG. It is a characteristic curve figure which shows the relationship of the specific resistance with respect to the average crystal grain diameter of the wiring obtained at the process of FIG. FIG. 3 is an explanatory diagram of a crystallization apparatus for explaining an embodiment in which the low resistance wiring of FIG. 2 is applied to a thin film transistor circuit. FIG. 5 is a cross-sectional view for specifically explaining a configuration of a thin film transistor circuit formed in a crystallization region manufactured by the crystallization apparatus of FIG. 4.

Explanation of symbols

1: glass substrate, 2: underlying insulating layer, 3: underlying metal layer, 4: metal seed layer,
5: Photoresist layer, 6: Groove pattern, 7: Metal wiring layer, 14: Substrate to be crystallized, 15: Crystallizer, 21: Glass substrate, 22, 24: Silicon oxide film,
23: Amorphous semiconductor film, 30: Crystallized region, 31: Thin film transistor circuit,
32: source region, 33 drain region, 35: gate insulating film, 36: gate electrode, 37: interlayer insulating film, 42: source electrode, 43: drain electrode, 44: passivation layer.

Claims (12)

Forming a metal seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more;
And a step of electroless plating a metal wiring layer having a thickness of 200 to 1000 nm on the metal seed layer. Forming a copper seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more;
And a step of electrolessly plating a copper wiring layer having a thickness of 200 to 1000 nm on the copper seed layer. Forming a base metal layer on the substrate;
Forming a copper seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more on the underlying metal layer;
Electroless plating a copper wiring layer having a predetermined pattern with a film thickness of 200 to 1000 nm on the copper seed layer;
A method of forming a wiring layer, comprising: removing at least the copper seed layer and the base metal layer other than a region bonded to the copper wiring layer. 4. The method of forming a wiring layer according to claim 1, wherein the electroless plating solution is an alkali metal-free neutral electroless plating bath using a cobalt salt as a reducing agent.   4. The method for forming a wiring layer according to claim 1, wherein the seed layer is a film formed by sputtering.   4. The method for forming a wiring layer according to claim 1, wherein the wiring layer is an epitaxially grown layer.   6. The method of forming a wiring layer according to claim 1, wherein the seed layer and the wiring layer are layers annealed at a temperature of 350 ° C. or higher. A wiring layer provided with a metal wiring layer on a metal seed layer, wherein the metal seed layer has a crystal plane of (111) and an average crystal grain size of 0.25 μm or more, and the metal wiring layer has a film thickness A wiring layer having a thickness of 200 to 1000 nm and an electroless plated layer. A wiring layer in which a copper wiring layer is provided on a copper seed layer, wherein the copper seed layer and the copper wiring layer have substantially the same average grain size. The underlayer of the copper seed layer is composed of at least one material layer of a stacked film of Ta, β-Ta, α-Ta, TaSiN, TaN, TaN, and α-Ta. Item 10. The wiring layer according to Item 9. 11. The wiring layer according to claim 9, wherein an average crystal grain size of the copper seed layer is 0.25 μm or more. A semiconductor thin film having a crystallized region;
A source region and a drain region are provided in the crystallization region, and a thin film transistor having a gate electrode provided in the crystallization region via a gate insulating film,
At least one of the source electrode, the drain electrode, and the gate electrode of the thin film transistor is provided on a metal seed layer having a main crystal plane of (111) and an average crystal grain size of 0.25 μm or more, and the metal seed layer. A thin film transistor comprising an electroless plating layer having a thickness of 200 to 1000 nm.

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