JP2006013334A - Nonvolatile memory device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile memory device having improved operational characteristics by controlling the film thickness of a tunnel insulating film in a nonvolatile memory device that operates using an FN tunnel current.
A nonvolatile memory device of the present invention includes a semiconductor layer 10, and
A first trench 22a provided in the semiconductor layer 10; a second trench 20a having a smaller inclination angle on the side surface of the trench compared to the first trench 22a;
A first region 10C defined by a first isolation insulating layer 22 formed by embedding an insulating layer in the first trench 22a;
Second regions 10A and C defined by a second isolation insulating layer 20 formed by embedding an insulating layer in the second trench 20a;
An insulating layer 30 provided above the semiconductor layer 10 of the first region 10C and the second regions 10A and B;
A floating gate electrode 32 provided at least above the insulating layer 30;
And a control gate 42 for controlling a voltage applied to the floating gate electrode 32.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile memory device having a floating gate electrode and a manufacturing method thereof, and more particularly, to a nonvolatile memory device that performs writing and erasing with an FN (Fowler-Nordheim) tunnel current and a manufacturing method thereof.

  As one of nonvolatile memory devices, a floating gate electrode provided on a semiconductor layer via an insulating layer, a control gate electrode provided on the floating gate electrode via an insulating layer, and a semiconductor layer A stacked gate type nonvolatile memory device including a provided source region and drain region can be given. In such a stacked gate type nonvolatile memory device, writing and erasing are performed by applying a predetermined voltage to the control gate electrode and the drain region and injecting / emitting electrons to the floating gate electrode. .

In such a stacked gate type nonvolatile memory device, the number of steps is increased because it has two gate electrode forming steps, and it is necessary to form a thin insulating layer on the floating gate electrode. The manufacturing process becomes complicated. For this reason, a nonvolatile memory device referred to in Patent Document 1 has been proposed as a nonvolatile memory device that can be manufactured with a simple manufacturing process and at low cost as compared with a stack gate type nonvolatile memory device. In the nonvolatile memory device described in Patent Document 1, a control gate is an N-type impurity region in a semiconductor layer, and a floating gate electrode is formed of a conductive layer such as a single polysilicon layer (hereinafter referred to as “one-layer gate type”). Non-volatile storage device "). Such a single-gate nonvolatile memory device has an advantage that it can be formed in the same manner as a normal CMOS transistor process because it is not necessary to stack gate electrodes.
JP 63-166274 A

  In the various nonvolatile memory devices described above, writing or erasing is performed by injecting or extracting electrons from the floating gate electrode using CHE (Channel Hot Electron) or FN tunnel current. At the time of writing or erasing with the FN tunnel current, attempts have been made to reduce the thickness of the insulating layer (tunnel insulating film) under the floating gate electrode in order to improve the operating characteristics. On the other hand, when the thickness of the insulating layer is reduced, the operating characteristics are improved, but the resistance of the insulating layer is impaired, and the number of times that data can be written may decrease. Therefore, there is a demand for a nonvolatile memory device that improves the operation characteristics of writing and erasing while ensuring reliability.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device that operates using an FN tunnel current, and has improved operational characteristics by controlling the thickness of the tunnel insulating film, and a method for manufacturing the same. It is in.

The nonvolatile memory device of the present invention includes a semiconductor layer,
A first trench provided in the semiconductor layer, and a second trench having a smaller inclination angle of a side surface of the trench than the first trench,
A first region defined by a first isolation insulating layer formed by embedding an insulating layer in the first trench;
A second region defined by a second isolation insulating layer formed by embedding an insulating layer in the second trench;
An insulating layer provided above the semiconductor layer of the first region and the second region;
A floating gate electrode provided at least above the insulating layer in the first region;
A control gate for controlling a voltage applied to the floating gate electrode.

  According to the nonvolatile memory device of the present invention, the floating gate electrode is provided on the semiconductor layer in the first region defined by the first isolation insulating layer in which the insulating layer is embedded in the first trench. That is, in the nonvolatile memory device obtained by the manufacturing method of the present invention, the place where writing or erasing is performed is provided in a region defined by the first isolation insulating layer.

  The first region and the second region have different angles of inclination between the side surfaces of the trenches that define the respective regions, and the angle between the side surface of the semiconductor layer and the surface of the semiconductor layer in each region is also different. come. That is, since the inclination angle of the first trench is larger than the inclination angle of the second trench, the angle formed by the side surface of the semiconductor layer in the first region defined by the first isolation insulating layer and the surface of the semiconductor layer is As compared with the second region defined by the second isolation insulating layer, it becomes larger. When the angle formed between the side surface of the semiconductor layer and the surface of the semiconductor layer is large, the film thickness of the insulating layer provided at the boundary portion between the semiconductor layer and the isolation insulating layer is the film of the insulating layer provided outside the boundary portion. The insulating layer can be formed to be smaller than the thickness. Therefore, a region with a small thickness can be provided in the insulating layer under the floating gate electrode. In the portion where the thickness of the insulating layer is small, the electric field between the floating gate electrode and the semiconductor layer can be increased. As a result, the FN tunnel current easily flows as a whole, and as a result, a nonvolatile memory device with improved write and erase characteristics can be provided.

  In the present invention, the inclination angle of the side surface of the trench means an angle formed by the side surface of the trench and the surface of the semiconductor layer. Further, in the present invention, the B layer provided above a specific A layer refers to the case where the B layer is provided directly on the A layer and the B layer via another layer on the A layer. Including the case where is provided.

  The nonvolatile memory device of the present invention can further take the following aspects.

  In the nonvolatile memory device of the present invention, the film thickness of the insulating layer provided at the boundary portion between the first isolation insulating layer and the semiconductor layer is set at the boundary portion between the second isolation insulating layer and the semiconductor layer. It can be smaller than the thickness of the provided insulating layer.

  In the nonvolatile memory device of the present invention, the first trench may have a dimension according to a minimum design rule. In this aspect, since the opening pattern of the first trench is small, the inclination angle of the trench can be further increased. As a result, the thickness of the insulating layer provided at the boundary between the first isolation insulating layer and the semiconductor layer can be further reduced, and a nonvolatile memory device with improved operating characteristics can be provided.

In the nonvolatile memory device of the present invention, the control gate is an N-type impurity region provided in the second region,
The floating gate electrode may be provided over the first region and the second region. According to this aspect, it is possible to provide a single-gate nonvolatile memory device with improved operating characteristics.

  In the nonvolatile memory device of the present invention, the control gate can be provided on the floating gate electrode via an insulating layer. According to this aspect, it is possible to provide a stacked gate type nonvolatile memory device with improved operating characteristics.

A method for manufacturing a nonvolatile memory device according to the present invention includes:
(A) forming a first trench in the semiconductor layer and a second trench having a smaller inclination angle on the side surface of the trench than the first trench;
(B) embedding an insulating layer in the first trench and the second trench to form a first isolation insulating layer and a second isolation insulating layer, thereby forming a first region defined by the first isolation insulating layer; Forming a second region defined by the second isolation insulating layer;
(C) forming an insulating layer provided above the semiconductor layers of the first region and the second region;
(D) forming a floating gate electrode at least above the insulating layer in the first region;
(E) forming a control gate for controlling a voltage applied to the floating gate electrode.

  According to the method of manufacturing the nonvolatile memory device of the present invention, the floating gate electrode is formed on the semiconductor layer in the first region defined by the first isolation insulating layer formed by embedding the insulating layer in the first trench. Can be formed. That is, in the nonvolatile memory device obtained by the manufacturing method of the present invention, the place where writing or erasing is performed is provided in a region defined by the first isolation insulating layer.

  In the first region and the second region, the angle formed between the side surface of the semiconductor layer and the surface of the semiconductor layer in each region is different because the inclination angle of the side surface of the trench defining each region is different. That is, since the inclination angle of the first trench is larger than the inclination angle of the second trench, the angle formed between the side surface of the semiconductor layer in the first region defined by the first isolation insulating layer and the surface of the semiconductor layer is also large. It will be a thing. When the angle formed between the side surface of the semiconductor layer and the surface of the semiconductor layer is large, the thickness of the insulating layer formed on the semiconductor layer at the boundary portion between the semiconductor layer and the isolation insulating layer is the semiconductor layer other than the boundary portion. An insulating layer that is smaller than the thickness of the insulating layer formed thereon can be formed. As a result, the FN tunnel current can be increased, and a nonvolatile memory device with improved operating characteristics such as writing and erasing can be manufactured.

  In the present invention, the inclination angle of the side surface of the trench means an angle formed by the side surface of the trench and the surface of the semiconductor layer. In the present invention, providing the B layer above the specific A layer means that the B layer is provided directly on the A layer, and the B layer is provided on the A layer via another layer. Including meaning.

  The present invention can further take the following aspects.

In the method for manufacturing a nonvolatile memory device according to the present invention, (a)
Forming the first trench by a first etching;
Forming the second trench by a second etching under a condition different from the first etching condition. According to this aspect, by forming the first and second trenches with different etching conditions, it is possible to form the first and second trenches having different inclination angles on the side surfaces of the trenches.

In the method for manufacturing a nonvolatile memory device of the present invention, in (a),
The formation of the first trench may be performed using a mask having a pattern smaller than an opening pattern of the mask when forming the second trench.

  According to this aspect, the first trench and the second trench having different inclination angles on the side surfaces of the trench can be formed by controlling the pattern of the mask layer when forming the first trench and the second trench. In this case, since the first trench and the second trench can be separately formed with one mask, the first and second trenches can be manufactured without increasing the number of steps.

  In the non-volatile memory device manufacturing method of the present invention, the mask pattern for forming the first trench may have a dimension according to a minimum design rule. According to this aspect, the mask pattern for forming the first trench can be made smaller than the mask pattern for forming another trench. Therefore, it is possible to form the first trench having a large inclination angle of the trench.

  In the method for manufacturing a nonvolatile memory device of the present invention, the formation of the control gate in (e) can be performed by implanting impurities into the semiconductor layer serving as the second region.

  In the method for manufacturing a nonvolatile memory device of the present invention, the control gate (e) can be formed by forming a conductive layer above the floating gate electrode through an insulating layer.

  The following is a description of an embodiment of the present invention.

1. Nonvolatile Memory Device FIG. 1 is a perspective view schematically showing a nonvolatile memory device obtained by the present embodiment, and FIG. 2 is a plan view showing the arrangement of floating gate electrodes 32 and impurity regions of a memory cell C100. FIG. 3A is a cross-sectional view taken along line AA in FIG. FIG. 3B is a cross section taken along line BB in FIG. FIG. 3C is a cross-sectional view taken along the line CC in FIG. The XX line in FIG. 1 corresponds to the XX line in FIG.

  As shown in FIG. 1, the nonvolatile memory device C100 of the present embodiment is provided in a P-type semiconductor layer 10. The semiconductor layer 10 is separated and defined by a separation insulating layer 20 into a first region 10A, a second region 10B, and a third region 10C. The first region 10 </ b> A and the second region 10 </ b> B are provided in the P-type well 12. The third region 10 </ b> C is provided in the N-type well 14. As in the first embodiment, the first area 10A is a control gate section, the second area 10B is a writing section, and the third area 10C is an erasing section.

  As shown in FIG. 2, an insulating layer 30 is provided on the semiconductor layer 10 in the first region 10A to the third region 10C. On the insulating layer 30, the floating gate electrode 32 provided over the first to third regions 10A to 10C is provided. In the first region 10 </ b> A, an N-type impurity region 35 is provided so as to sandwich the floating gate electrode 32. In the second region 10B, an N-type impurity region 36 is provided so as to sandwich the floating gate electrode 32. In the third region 10 </ b> C, a P-type impurity region 38 is provided so as to sandwich the floating gate electrode 32.

  Next, the cross-sectional structure of each region will be described with reference to FIGS.

  As shown in FIG. 3A, in the first region 10A, an insulating layer 30 provided on the P-type semiconductor layer 10, a floating gate electrode 32 provided on the insulating layer 30, and a floating gate An N-type impurity region 42 provided in the semiconductor 10 below the electrode 32 and an N-type impurity region 35 provided adjacent to the impurity region 42 in the semiconductor layer 10 on the side of the floating gate electrode 32. Have. The N-type impurity region 42 serves as a control gate, and the impurity region 35 is electrically connected to the control gate line and serves as a contact portion for applying a voltage to the control gate.

  As shown in FIG. 3B, an N-channel transistor 100B for writing is provided in the second region 10B. The N-channel transistor 100B includes an insulating layer 30 provided on the P-type semiconductor layer 10, a floating gate electrode 32 provided on the insulating layer 30, and an impurity region 36 provided on the semiconductor layer 10. Have The impurity region 36 becomes a source region or a drain region. In the nonvolatile memory device of this embodiment, writing is performed by injecting electrons into the floating gate electrode 32 by CHE in the N-channel transistor 100B in the second region 10B.

  As shown in FIG. 3C, a P-channel transistor 100C is provided in the third region 10C. The P-channel transistor 100C includes an insulating layer 30 provided on the N-type well 14, a floating gate electrode 32 provided on the insulating layer 30, and an impurity region provided in the N-type well 14. 38. The impurity region 38 becomes a source region or a drain region. In the nonvolatile memory device of the present embodiment, electrons injected into the floating gate electrode 32 are extracted by flowing an FN tunnel current through the P-channel MOS transistor 100C in the third region 10C that is the erase region.

  Next, a cross-sectional structure along the length direction of the floating gate electrode 32 will be described with reference to FIG. FIG. 4 is a cross-sectional view taken along line DD in FIG. As shown in FIG. 4, the first region 10A and the second region 10B are defined by an isolation insulating layer 20 in which an insulating layer is embedded in the trench 20a. The third region 10C is defined by an isolation insulating layer 22 in which an insulating layer is embedded in the trench 22a. The trench 20a and the trench 22a have different inclination angles on the side surfaces of the trench.

  The inclination angle of the trench will be described with reference to FIG. 5A is an enlarged view of a portion A in FIG. 4, and FIG. 5B is an enlarged view of a portion B in FIG. As can be seen by comparing FIGS. 5A and 5B, the inclination angle α of the trench 22a is larger than the inclination angle β of the trench 20a. Therefore, the side surface of the semiconductor layer 10 in the third region 10C is a steeper surface compared to other regions (the first region 10A and the second region 10B). The thickness of the insulating layer 30 provided at the boundary between the isolation insulating layer 22 and the semiconductor layer 10 varies depending on the inclination of the side surface of the semiconductor layer 10. That is, the insulating layer provided in the boundary portion has a smaller thickness in the case shown in FIG.

  According to the nonvolatile memory device of the present embodiment, the first region 10A, the second region 10B, and the third region 10C have different inclination angles of the side surfaces of the trenches 20a and 22a that define the respective regions. Therefore, the angle between the side surface of the semiconductor layer 10 and the surface of the semiconductor layer 10 in each region also differs. That is, since the inclination angle of the trench 22a is larger than the inclination angle of the trench 20a, the inclination angle of the side surface of the semiconductor layer 10 in the third region 10C defined by the isolation insulating layer 22 (the side surface of the semiconductor layer 10 and the semiconductor layer). 10) is larger than that of the first region 10A and the second region 10B defined by the isolation insulating layer 20. When the inclination angle of the side surface of the semiconductor layer 10 is large, it is urged to reduce the thickness of the insulating layer provided at the boundary portion. Therefore, the thickness of the insulating layer 30 provided at the boundary portion between the semiconductor layer 10 and the isolation insulating layer 22 is smaller. Therefore, in the third region 10C in which erasing is performed using the FN tunnel current, the insulating layer 30 provided at the boundary portion can be further thinned as compared with the first region 10A and the second region 10B. . As a result, the FN tunnel current easily flows in the third region 10C, and a nonvolatile memory device with improved write and erase characteristics can be provided.

2. Method for Manufacturing Nonvolatile Memory Device Next, a method for manufacturing the nonvolatile memory device according to the present embodiment will be described with reference to FIGS. 6 and 12 are perspective views showing one step of the method of manufacturing the nonvolatile memory device according to the present embodiment, and FIGS. 7 to 11 schematically show cross sections taken along line III-III in FIG. It is sectional drawing shown.

  First, as shown in FIG. 6, isolation insulating layers 20 and 22 are formed in a predetermined region of the semiconductor layer 10. In the semiconductor device of the present embodiment, a P-type semiconductor layer 10 is used. The isolation insulating layers 20 and 22 are formed by a known STI (Shallow Trench Isolation) method. Isolation insulating layers 20 and 22 separate the first region 10A, the second region 10B, and the third region 10C.

  A method of forming the isolation insulating layers 20 and 22 will be further described with reference to FIGS. First, as shown in FIG. 7, a pad oxide film 40 is formed on the semiconductor layer 10. Thereafter, a silicon nitride film 42 serving as a CMP stopper layer is formed on the pad oxide film 40. Next, a mask layer M1 having an opening above the region where the isolation insulating layer 20 is to be formed is formed. For example, a resist layer is used as the mask layer M1.

  Next, as shown in FIG. 8, using the mask layer M1 (see FIG. 7) as a mask, the pad oxide film 40 and the silicon nitride film 42 are removed, and then the semiconductor layer 10 is removed by a known technique to form the trench 20a. Form. Thereafter, the mask layer M1 is removed. Next, as shown in FIG. 8, a mask layer M2 having an opening only above the region where the isolation insulating layer 22 is formed is formed. For example, a resist layer can be used as the mask layer M2.

Next, as shown in FIG. 9, the trench 22a is formed by etching the semiconductor layer 10 using the mask layer M2 (see FIG. 8) as a mask. In this etching of the semiconductor layer 10, the etching conditions are controlled so that the inclination angle of the side surface of the trench becomes steeper than that of the trench 20a. Etching of the semiconductor layer 10 to form the trench 20a and the trench 22a is performed with an etching gas containing oxygen (O ₂ ) and chlorine (Cl ₂ ). At this time, chlorine contained in the etching gas reacts with the silicon layer that is the semiconductor layer 10 to form a deposit (a polymer having a Si—Cl bond). Since the deposit adheres to the side surface of the etched semiconductor layer 10, the opening gradually becomes narrower as the etching progresses. The inclination angle of the side surface of the trench can be adjusted by controlling the amount of the deposit attached to the opening. For example, when the ratio of chlorine to oxygen in the etching gas is increased, the deposit in the opening increases, so that the opening becomes narrower as the etching progresses, and a trench with a small side inclination angle may be formed. it can. Conversely, by reducing the ratio of chlorine to oxygen, deposits attached to the opening can be reduced, and the opening is suppressed from becoming narrower as the etching progresses. Therefore, a trench having a large side surface inclination angle can be formed.

  Next, as shown in FIG. 10, an insulating layer is embedded in the trenches 20 a and 22 a to form isolation insulating layers 20 and 22. In forming the isolation insulating layers 20 and 22, first, an insulating layer (not shown) is formed above the semiconductor layer 10, and the insulating layer is removed until the silicon nitride film 42 is exposed. The insulating layer can be removed by, for example, a CMP method. Thereafter, the silicon nitride film 42 is selectively removed. The removal of the silicon nitride film 42 can be performed by wet etching using hot phosphoric acid. Next, portions of the insulating layer embedded in the trenches 20a and 22a that are exposed from the surface of the semiconductor layer 10 are removed. Through the above steps, the isolation insulating layer 20 is formed.

  Next, as shown in FIG. 10, a P-type well 12 is formed in the first region 10A and the second region 10B, and an N-type well 14 is formed in the third region 10C. The P-type well 12 is formed by introducing a P-type impurity after forming a mask layer (not shown) covering the third region 10C. The N-type well 14 is formed by introducing an N-type impurity after forming a mask layer (not shown) covering the first region 10A and the second region 10B. The order of forming the P-type well 12 and the N-type well 14 is not particularly limited, and any of them may be formed first.

  Next, as shown in FIG. 10, an N-type impurity region 42 serving as a control gate is formed in the first region 10A. The N-type impurity region 42 is formed by forming a mask layer having an opening above the semiconductor layer in the first region 10A and then introducing an N-type impurity by a known technique.

  Next, the insulating layer 30 is formed on the semiconductor layer 10 in the first region 10A, the second region 10B, and the third region 10C. In the formation of the insulating layer 30, first, light etching is performed in order to form the insulating layer 30 on the clean semiconductor layer surface. The light etching can be performed by wet etching using dilute hydrofluoric acid or the like. As shown in FIG. 11, the uppermost layer of the isolation insulating layers 20 and 22 is removed by this light etching, so that the upper end of the semiconductor layer 10 is at the boundary portion between the isolation insulating layers 20 and 22 and the semiconductor layer 10. Exposed.

  Next, as shown in FIG. 11, an insulating layer 30 is formed on the surface of the semiconductor layer 10. The insulating layer 30 can be formed by, for example, forming the insulating layer 30 that can be formed by a thermal oxidation method, and exposing the semiconductor layer 10 and a portion of the isolation insulating layers 20 and 22 removed in the previous step. An insulating layer 30 is formed on the side surface of the semiconductor layer 10 to be formed. Since the surface orientation of the semiconductor layer is different between the upper surface and the side surface of the semiconductor layer 10, the deposition rate of the insulating layer during thermal oxidation on the side surface becomes slow. Therefore, the thickness of the insulating layer 30 formed on the side surface of the semiconductor layer 10 is smaller than the thickness of the insulating layer 30 formed on the upper surface of the semiconductor layer 10. In addition, since the inclination angle of the side surface of the semiconductor layer 10 in the third region 10C is larger than the inclination angle of the side surface of the semiconductor layer 10 in other regions, the ratio of the surface orientation at which the film formation rate is slow is exposed. Get higher. Therefore, the film thickness of the insulating layer 30 at the boundary portion of the third region 10C is further smaller than the film thickness of the insulating layer 30 at the boundary portion of the other regions (the first region 10A and the second region 10B). Become.

  Next, as shown in FIG. 12, a floating gate electrode 32 is formed on the insulating layer 30. The floating gate electrode 32 is formed by forming a conductive layer (not shown) made of, for example, a polysilicon layer above the semiconductor layer 10 and patterning the conductive layer.

  Next, as shown in FIG. 1, impurity regions are formed in each of the first region 10A, the second region 10B, and the third region 10C using the floating gate electrode 32 as a mask. N-type impurity regions 35 and 36 are formed in the first region 10A and second region 10B, and a P-type impurity region 38 is formed in the third region 10C. First, in the formation of the P-type impurity region 38, a mask layer such as a resist layer is formed so as to cover the first region 10A and the second region 10B, and the P-type impurity region 38 is formed by a known technique using the floating gate electrode 32 as a mask. It is formed by introducing impurities. Next, in the formation of the N-type impurity regions 35 and 36, a mask layer such as a resist layer is formed so as to cover the third region 10C, and an N-type impurity is introduced by a known technique using the floating gate electrode 32 as a mask. It is formed by doing.

  Next, a modification of the manufacturing method of the present embodiment will be described. This modification is an example in which the inclination angle of the side surface of the trench 22a is different from the inclination angle of the side surface of the trench 20a by controlling the pattern in forming the isolation insulating layer 22 that defines the third region 10C. is there.

  First, as shown in FIG. 13, a pad oxide film 40 and a silicon nitride film 42 are formed on the semiconductor layer 10. Next, a mask layer M1 having an opening above the region where the isolation insulating layer 20 is to be formed is formed. For example, a resist layer can be used as the mask layer M1. In the mask layer M1, the opening a above the region where the trench for defining the third region 10C is formed is different from the opening b above the region where the trench for defining the other region is formed. Thus, the width is reduced (a <b). In this way, by reducing the mask pattern (decreasing the space), it is possible to suppress deposits generated during etching from adhering to the side surface of the opening. Therefore, it is possible to form the trench 22a having a large side surface inclination angle. The pattern of the opening a may be a pattern having a dimension according to the minimum design rule.

  Next, as shown in FIG. 14, the pad oxide film 40 and the silicon nitride film 42 are removed using the mask layer M1 (see FIG. 13) as a mask. Thereafter, the semiconductor layer 10 is removed, and trenches 20a and 22a are formed. Next, the mask layer M1 is removed.

  Next, in the same manner as in the above embodiment, the insulating layers 20 and 22 are formed by filling the trenches 20a and 22a with an insulating layer. Thereafter, the wells 12 and 14 and the insulating layer 30 and the floating gate electrode 32 can be formed in the same manner as in the above-described embodiment.

  According to the method of manufacturing the nonvolatile memory device of the present embodiment, the floating gate is formed on the semiconductor layer 10 in the third region 10C defined by the isolation insulating layer 22 formed by embedding the insulating layer in the trench 22a. A part of the electrode 32 is formed. That is, in the nonvolatile memory device obtained by the manufacturing method of the present embodiment, a place where writing or erasing is performed is provided in a region defined by the isolation insulating layer 22.

  The first region 10A, the second region 10B, and the third region 10C have different inclination angles of the side surfaces of the trenches 20a and 22a that define the respective regions. The angle between the surface and the surface will be different. That is, since the inclination angle of the trench 22a is larger than the inclination angle of the trench 20a, the angle formed between the side surface of the semiconductor layer 10 in the third region 10C defined by the isolation insulating layer 22 and the surface of the semiconductor layer 10 is large. It will be a thing. Therefore, partial thinning of the insulating layer 30 in the third region 10C (location using the FN tunnel current) can be more reliably performed as compared with the first regions 10A and 10B. As a result, the FN tunnel current can be increased, and a nonvolatile memory device with improved operating characteristics such as writing and erasing can be manufactured.

  As can be seen from the above-described steps, this one-layer gate type nonvolatile memory device can be manufactured in the same process as the manufacturing process of the CMOS transistor. Therefore, there is an advantage that it can be manufactured at a low cost and can be mixed with other MOS transistors. In particular, the following advantages can be obtained when mounting with other MOS transistors. The film thickness of the insulating layer 30 is determined by the characteristics of the MOS transistor to be embedded. Therefore, in the case of being mixed with a MOS transistor with a high breakdown voltage, the film thickness of the insulating layer 30 may be larger than the film thickness suitable for performing the function of the nonvolatile memory device. Even in such a case, for example, by partially thinning the insulating layer 30 at a location where FN tunnel current is used (write location or erase location), the characteristics are good without being affected by the mixed device. A nonvolatile memory device can be provided.

  Note that, in the nonvolatile memory device of the present embodiment, an example in which the impurity region provided immediately below the floating gate electrode 32 serves as a control gate in the single-layered nonvolatile memory device will be described as an example. However, it is not limited to this. As another example of the one-layer gate type nonvolatile memory device, an N-type well is provided in the first region 10A, and the whole well has a structure serving as a control gate.

  In addition, although the gate-type nonvolatile memory device has been described as an example, the present invention can be applied to any nonvolatile memory device that operates using an FN tunnel current. In this case, by locally reducing the thickness of the insulating layer 30, it is possible to improve the operating characteristics while suppressing deterioration of resistance due to the overall thickness of the insulating layer being reduced.

The perspective view which shows typically the non-volatile memory device obtained by this Embodiment. FIG. 2 is a plan view schematically showing a part of the nonvolatile memory device shown in FIG. 1. (A) is sectional drawing along the AA line of FIG. 2, (B) is sectional drawing along the BB line of FIG. 2, (C) is C-- line of FIG. Sectional drawing along C line. Sectional drawing along the DD line | wire of FIG. (A) is a figure which expands and shows the A section of FIG. 4, (B) is a figure which expands and shows the B section of FIG. The perspective view which shows typically 1 process of the manufacturing method concerning this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method concerning this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method concerning this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method concerning this Embodiment Sectional drawing which shows typically 1 process of the manufacturing method concerning this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method concerning this Embodiment. The perspective view which shows typically 1 process of the manufacturing method concerning this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method concerning a modification. Sectional drawing which shows typically 1 process of the manufacturing method concerning a modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Semiconductor layer, 10A 1st area | region, 10B 2nd area | region, 10C 3rd area | region 12 P-type well, 14 N-type well, 20, 22 Isolation insulation layer, 20a, 22a Trench, 30 Insulation layer, 32 Floating gate electrode , 34, 36, 38, 42 Impurity region, C100 nonvolatile memory device, 100B N-channel MOS transistor, 100C P-channel MOS transistor

Claims (11)

A semiconductor layer;
A first trench provided in the semiconductor layer, and a second trench having a smaller inclination angle of a side surface of the trench than the first trench,
A first region defined by a first isolation insulating layer formed by embedding an insulating layer in the first trench;
A second region defined by a second isolation insulating layer formed by embedding an insulating layer in the second trench;
An insulating layer provided above the semiconductor layer of the first region and the second region;
A floating gate electrode provided at least above the insulating layer in the first region;
And a control gate for controlling a voltage applied to the floating gate electrode. In claim 1,
The film thickness of the insulating layer provided at the boundary portion between the first isolation insulating layer and the semiconductor layer is the film thickness of the insulating layer provided at the boundary portion between the second isolation insulating layer and the semiconductor layer. A non-volatile memory device that is smaller than the above. In claim 1 or 2,
The first trench has a dimension according to a minimum design rule. In any one of Claims 1-3,
The control gate is an N-type impurity region provided in the second region,
The non-volatile memory device, wherein the floating gate electrode is provided over the first region and the second region. In any one of Claims 1-3,
The control gate is a nonvolatile memory device provided on the floating gate electrode via an insulating layer. (A) forming a first trench in the semiconductor layer and a second trench having a smaller inclination angle on the side surface of the trench than the first trench;
(B) by embedding an insulating layer in the first and second trenches to form a first and second isolation insulating layer, a first region defined by the first isolation insulating layer, and the second isolation insulation Forming a second region defined by the layer;
(C) forming an insulating layer provided above the semiconductor layers of the first region and the second region;
(D) forming a floating gate electrode at least above the insulating layer in the first region;
(E) forming a control gate for controlling a voltage applied to the floating gate electrode; In claim 6,
Said (a)
Forming the first trench by a first etching;
Forming a second trench by a second etching under a condition different from the first etching condition. In claim 6,
In (a) above,
The method of manufacturing a non-volatile memory device, wherein the formation of the first trench is performed using a mask having a smaller pattern than the opening pattern of the mask when forming the second trench. In claim 8,
The method of manufacturing a nonvolatile memory device, wherein a pattern of a mask for forming the first trench has a dimension according to a minimum design rule. In any one of Claims 6-9,
(E) The control gate is formed by implanting impurities into the semiconductor layer serving as the second region. In any one of Claims 6-9,
(E) The control gate is formed by forming a conductive layer having a predetermined pattern above the floating gate electrode via an insulating layer.

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