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JP2006013030A5 - - Google Patents

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Publication number
JP2006013030A5
JP2006013030A5 JP2004186007A JP2004186007A JP2006013030A5 JP 2006013030 A5 JP2006013030 A5 JP 2006013030A5 JP 2004186007 A JP2004186007 A JP 2004186007A JP 2004186007 A JP2004186007 A JP 2004186007A JP 2006013030 A5 JP2006013030 A5 JP 2006013030A5
Authority
JP
Japan
Prior art keywords
circuit board
layer
metal layer
plating resist
reinforcing plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004186007A
Other languages
Japanese (ja)
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JP2006013030A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2004186007A priority Critical patent/JP2006013030A/en
Priority claimed from JP2004186007A external-priority patent/JP2006013030A/en
Publication of JP2006013030A publication Critical patent/JP2006013030A/en
Publication of JP2006013030A5 publication Critical patent/JP2006013030A5/ja
Pending legal-status Critical Current

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Claims (4)

補強板、有機物層、可撓性フィルム、金属層がこの順に積層された回路基板用部材であって、金属層を30μmピッチ以下のパターンに形成し、得られた配線パターンの金属表面に高さが1μm以上50μm以下の突起部を設けた回路基板用部材。 A circuit board member in which a reinforcing plate, an organic material layer, a flexible film, and a metal layer are laminated in this order. The metal layer is formed into a pattern with a pitch of 30 μm or less, and the height of the obtained wiring pattern on the metal surface Is a circuit board member provided with a protrusion of 1 μm or more and 50 μm or less. 絶縁層と導体配線層が交互に複数積層され、各導体配線層が絶縁層を厚さ方向に横切ってスルーホールもしくはビアにより電気的に接続され、最表層に導体配線層が露出している多層回路基板を、有機物層を介して補強板に積層された回路基板用部材であって、多層回路基板の配線パターン表面に突起部が設けられている請求項1記載の回路基板用部材。 A multilayer in which a plurality of insulating layers and conductor wiring layers are alternately stacked, each conductor wiring layer is electrically connected by a through hole or via across the insulating layer in the thickness direction, and the conductor wiring layer is exposed on the outermost layer The circuit board member according to claim 1, wherein the circuit board is a member for circuit board laminated on a reinforcing plate via an organic layer, and a protrusion is provided on a wiring pattern surface of the multilayer circuit board. 請求項1または2記載の回路基板用部材の補強板を剥離し、得られるフレキシブル回路基板。 A flexible circuit board obtained by peeling off the reinforcing plate of the circuit board member according to claim 1. 補強板、有機物層、可撓性フィルム、金属層がこの順に積層された回路基板用部材の製造方法であって、
(1)可撓性フィルムを有機物層を介して補強板に貼り合わせる工程と、
(2)可撓性フィルムの表面に第1金属層を形成する工程と、
(3)第1金属層の表面に金属配線パターン用の第1のめっきレジスト膜(第1めっきレジスト膜)を設け、電解めっきによって第2金属層のパターンを形成する工程と、
(4)第1めっきレジスト膜及び第2金属層の上にめっきにより形成する突起部用の第2めっきレジスト膜(第2めっきレジスト膜)を設け、電解めっきによって突起部を第3金属層で形成する工程と、
(5)第1及び第2めっきレジスト膜を剥離した後、エッチング液によって露出した第1金属層を除去する工程を有することを特徴とする請求項1または2記載の回路基板用部材の製造方法。
A method for producing a circuit board member in which a reinforcing plate, an organic material layer, a flexible film, and a metal layer are laminated in this order,
(1) a step of bonding a flexible film to a reinforcing plate via an organic layer ;
(2) forming a first metal layer on the surface of the flexible film;
(3) providing a first plating resist film (first plating resist film) for a metal wiring pattern on the surface of the first metal layer, and forming a pattern of the second metal layer by electrolytic plating;
(4) Providing a second plating resist film (second plating resist film) for the protrusion formed by plating on the first plating resist film and the second metal layer, and forming the protrusion with the third metal layer by electrolytic plating Forming, and
(5) The method for manufacturing a circuit board member according to claim 1 or 2, further comprising a step of removing the first metal layer exposed by the etching solution after the first and second plating resist films are peeled off. .
JP2004186007A 2004-06-24 2004-06-24 Member for circuit board and its manufacturing method Pending JP2006013030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004186007A JP2006013030A (en) 2004-06-24 2004-06-24 Member for circuit board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004186007A JP2006013030A (en) 2004-06-24 2004-06-24 Member for circuit board and its manufacturing method

Publications (2)

Publication Number Publication Date
JP2006013030A JP2006013030A (en) 2006-01-12
JP2006013030A5 true JP2006013030A5 (en) 2007-08-02

Family

ID=35779917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004186007A Pending JP2006013030A (en) 2004-06-24 2004-06-24 Member for circuit board and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2006013030A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101232541B1 (en) * 2006-05-16 2013-02-12 엘지디스플레이 주식회사 Fabricating method of flexible substrate
JP2008270311A (en) * 2007-04-17 2008-11-06 Hitachi Cable Ltd Method of manufacturing tape carrier for semiconductor device
JP2009094128A (en) * 2007-10-04 2009-04-30 Phoenix Precision Technology Corp Circuit board, and manufacturing method thereof
KR101534849B1 (en) * 2008-08-27 2015-07-07 엘지이노텍 주식회사 Flip chip package and method for packaging the same
US20100236822A1 (en) * 2009-03-23 2010-09-23 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
JP6696128B2 (en) * 2015-08-25 2020-05-20 大日本印刷株式会社 Manufacturing method of component mounting thin film wiring substrate
TWI736695B (en) * 2017-10-24 2021-08-21 啟耀光電股份有限公司 Electronic device and manufacturing method thereof
TWM624524U (en) * 2021-11-23 2022-03-11 頎邦科技股份有限公司 Semiconductor package

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