JP2006013070A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which can miniaturize a semiconductor device. <P>SOLUTION: An LDMOSFE is formed in an epitaxial layer 22 on a substrate 21. The LDMOSFE has a gate electrode 32; a drain region composed of an n<SP>-</SP>-type offset drain region 35, an n-type offset drain region 39, and an n<SP>+</SP>-type drain region 42; a source region composed of an n<SP>-</SP>-type source region 36, and an n<SP>+</SP>-type source region 43. A plurality of Schottky electrodes 52 are formed on an n-type well 27, and a Schottky junction is formed between the Schottky electrode 52 and the n-type well 27 to form a Schottky diode element. The plurality of Schottky electrodes 52 are electrically connected to each other via a plug 63 and an anode electrode 74. Spaces between a plurality of Schottky junctions and n<SP>+</SP>-type semiconductor regions 44 provided on both sides are electrically connected to each other via the plug 63 and a cathode electrode 73. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to an RF (Radio Frequency) power module, a semiconductor device mounted on the RF power module, and a technique effective when applied to the manufacturing technique thereof.

  In recent years, mobile communication devices (so-called mobile phones) represented by communication methods such as GSM (Global System for Mobile Communications), PCS (Personal Communication Systems), PDC (Personal Digital Cellular), and CDMA (Code Division Multiple Access) Phone) is widespread worldwide.

  In general, this type of mobile communication device includes an antenna that emits and receives radio waves, a high-frequency power amplifier (RF power module) that amplifies a power-modulated high-frequency signal and supplies the signal to the antenna, A receiving unit that performs signal processing, a control unit that performs these controls, and a battery (battery) that supplies a power supply voltage thereto are configured.

  Japanese Patent Application Laid-Open No. 2003-133557 describes a technique related to a semiconductor device having a power transistor and a Schottky barrier diode element (see Patent Document 1).

Japanese Patent Application Laid-Open No. 11-154748 describes a technique related to a trench gate type MOSFET having a Schottky diode.
JP 2003-133557 A Japanese Patent Laid-Open No. 11-154748

  As amplifying elements used in the power amplifier circuit of RF power modules of mobile communication devices, compound semiconductor devices such as HBT and HEMT, silicon bipolar transistors, LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors, lateral diffusion MOSFETs) Etc. are used depending on the purpose and situation.

  Among these amplifying elements, the LDMOSFET employs a structure that ensures a high drain breakdown voltage by providing a drain region with a high impurity concentration via a low impurity concentration offset drain region on the drain side. Although the power added efficiency is lower than that of a semiconductor device, there are advantages in that bias control is easy and mass productivity is high.

  An RF power module used in a mobile communication device includes a detection circuit that detects output power of the entire RF power module. As a method for detecting the output power, a MOSFET detection method using a detection circuit using a MOSFET can be considered. FIG. 33 is a circuit diagram showing this MOSFET detection type detection circuit. By incorporating the MOSFET detection type detection circuit 209A of FIG. 33 in the RF power module, the output power amplified and output by the power amplification circuit of the RF power module can be detected by the detection circuit 209A. However, the MOSFET detection type detection circuit 209A as shown in FIG. 33 has a complicated circuit configuration and a large scale, which is disadvantageous for miniaturization of the RF power module. Further, since the MOSFET detection type detection circuit 209A is composed of a MOSFET (CMOSFET) used for signal control, it may be monolithic on the silicon substrate together with the amplifier circuit, but the circuit configuration is complicated. Since the scale is large, it occupies a relatively large area of the semiconductor chip and the semiconductor chip itself becomes large.

  As another method for detecting the output power of the RF power module, an SBD detection method using a Schottky Barrier Diode (SBD) can be considered. FIG. 2 is a circuit diagram showing a detection circuit of this SBD detection method. By incorporating detection circuits 109A and 109B of the SBD detection method as shown in FIG. 2 in the RF power module 1, the output power amplified and output by the power amplification circuits 102A and 102B of the RF power module 1 is detected. The circuits 109A and 109B can be detected with high sensitivity. The detection circuits 109A and 109B of the SBD detection system as shown in FIG. 2 are composed of a Schottky barrier diode element 121, a capacitor element 122, and a resistance element 123. These elements constituting the detection circuit of the SBD detection system Is formed by chip components (chip diodes, chip capacitors, and chip resistors) and mounted on a wiring board (module board) constituting the RF power module, the planar size of the RF power module increases, and the RF power module Will become larger.

  In the above Japanese Patent Laid-Open No. 2003-133557 (Patent Document 1), a Schottky diode and a power MISFET are connected in parallel, a cathode region of the Schottky diode is connected to a drain region of the power MISFET, and an anode region of the Schottky diode is It is connected to the source region of the power MISFET. However, the Schottky barrier diode element used in the detection circuit of the SBD detection system is not directly connected to the MISFET element, but is connected to the MISFET element via another passive element (for example, a capacitive element or a resistance element). The circuit configuration is electrically connected. For this reason, the Schottky diode disclosed in Japanese Patent Laid-Open No. 2003-133557 (Patent Document 1) cannot be applied to the Schottky diodes of the detection circuits 109A and 109B of the SBD detection method.

  There is also a demand for improving the detection sensitivity of the detection circuit of the SBD detection method. In order to improve the detection sensitivity of the detection circuit of the SBD detection method, it is effective to increase the forward current of the Schottky barrier diode. However, the junction area of the Schottky junction is simply increased to increase the forward current. This alone leads to an increase in the size of the semiconductor device.

  An object of the present invention is to provide a technique that enables a semiconductor device to be miniaturized.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the present invention, a MISFET and a Schottky diode are formed on the surface of a semiconductor substrate, and a back electrode electrically connected to the source region of the MISFET is formed on the back surface of the semiconductor substrate.

  In the present invention, a semiconductor chip in which a MISFET and a Schottky diode are formed and a back surface electrode electrically connected to the source region of the MISFET is formed on the back surface is mounted on a wiring board.

  The present invention also has a back electrode having a MISFET and a Schottky diode formed on the first main surface of the semiconductor substrate and electrically connected to the source region opposite to the first main surface of the semiconductor substrate. A method of manufacturing a semiconductor device on a second main surface, comprising: (a) a step of preparing a semiconductor substrate; (b) forming a MISFET on the first main surface of the semiconductor substrate; Forming a first semiconductor region of the first conductivity type in the first semiconductor region, and forming a plurality of second semiconductor regions of the first conductivity type having a higher impurity concentration than the first semiconductor region in the first semiconductor region; Forming a plurality of Schottky electrodes for forming a Schottky junction with each of the first semiconductor regions on the first semiconductor region between the second semiconductor regions, and (d) on the first main surface of the semiconductor substrate. MISFET and multiple shots Forming an interlayer insulating film so as to cover the electrodes; (e) a plurality of first openings that expose the Schottky electrodes at their bottoms; and a plurality of first openings that expose the second semiconductor regions at their bottoms, respectively. Forming two openings in the interlayer insulating film; and (f) filling the plurality of first openings and the plurality of second openings with a conductor to form a wiring on the interlayer insulating film, thereby forming a plurality of Schottky layers. Electrically connecting the electrodes to each other and electrically connecting the plurality of second semiconductor regions to each other.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The semiconductor device can be reduced in size.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections. However, unless otherwise specified, they are not irrelevant to each other, and one is a part of the other or All the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
The first embodiment is a semiconductor device mounted on, for example, an RF (Radio Frequency) power module used in a digital cellular phone (mobile communication device) that transmits information using a GSM network.

  FIG. 1 shows a circuit block diagram of an RF power module (high frequency power amplifier, high frequency power amplifier, semiconductor device) 1 according to the first embodiment. In this figure, for example, two frequency bands of GSM900 and DCS1800 can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) modulation system and EDGE (Enhanced Data GSM Environment) modulation system in each frequency band. The circuit block diagram (amplifier circuit) of the RF power module which can use two communication systems is shown.

  As shown in FIG. 1, the circuit configuration (amplifier circuit) of the RF power module 1 includes a power amplifier circuit 102A for GSM900 including three amplifier stages 102A1, 102A2, and 102A3, and three amplifier stages 102B1, 102B2, and 102B3. A power amplifier circuit 102B for DCS1800, a bias circuit 103A for applying a bias voltage to the amplifier stages 102A1 to 102A3 of the power amplifier circuit 102A, and a bias circuit for applying a bias voltage to the amplifier stages 102B1 to 102B3 of the power amplifier circuit 102B 103B, a power supply circuit 104A for generating a power supply voltage to be applied to the drain terminals of the output LDMOSFETs of the amplification stages 102A1 to 102A3 of the power amplification circuit 102A, and outputs for the amplification stages 102B1 to 102B3 of the power amplification circuit 102B LDM A power supply circuit 104B that generates a power supply voltage applied to the drain terminal of the SFET, a matching circuit 106A between the input terminal 105a for GSM900 and the power amplifier circuit 102A for GSM900 (first amplifier stage 102A1), and for GSM900 Matching circuit (output matching circuit) 108A between output terminal 107a of GSM900 and power amplifier circuit 102A for GSM900 (third amplifier stage 102A3), input terminal 105b for DCS1800 and power amplifier circuit 102B for DCS1800 (one stage) Matching circuit 106B between the second amplification stage 102B1), matching circuit (output matching circuit) 108B between the output terminal 107b for DCS1800 and the power amplification circuit 102B for DCS1800 (third amplification stage 102B3), and for GSM900 Output from the power amplification circuit 102A ( Detection circuit (output detection circuit) 109A for detecting a power signal and output power) and a detection circuit (output detection circuit) for detecting an output (output signal and output power) from the power amplification circuit 102B for DCS1800 109B. Among these, the power amplification circuit 102A (amplification stages 102A1 to 102A3) for GSM900, the power amplification circuit 102B (102B1 to 102B3) for DCS1800, the bias circuits 103A and 103B, and the detection circuits 109A and 109 are one. A semiconductor chip (semiconductor device, semiconductor amplification element chip, high frequency power amplification element chip) 2 is formed. Although not shown, a matching circuit (interstage matching circuit) may be provided between the amplification stages 102A1 to 102A3 and between the amplification stages 102B1 to 102B3.

  The RF input signal input to the GSM900 input terminal 105a of the RF power module 1 is input to the semiconductor chip 2 through the matching circuit 106A, and is a power amplifier circuit 102A in the semiconductor chip 2, that is, three amplifier stages 102A1 to 102A3. And is output from the semiconductor chip 2 and output as an RF output signal from the output terminal 107a for GSM900 through the matching circuit 108A. Further, the RF input signal input to the DCS 1800 input terminal 105b of the RF power module 1 is input to the semiconductor chip 2 through the matching circuit 106B, and the power amplifier circuit 102B in the semiconductor chip 2, that is, the three amplification stages 102B1. Is amplified by −102B3 and output from the semiconductor chip 2, and is output as an RF output signal from the output terminal 107b for the DCS 1800 via the matching circuit 108B. Also, the bias control signal input to the bias control signal input terminal 110a for GSM900 of the RF power module 1 is input to the bias circuit 103A, and is input to the amplification stages 102A1 to 102A3 of the power amplifier circuit 102A based on the bias control signal. The bias voltage to be applied is controlled. Also, the bias control signal input to the bias control signal input terminal 110b for DCS 1800 of the RF power module 1 is input to the bias circuit 103B, and based on the bias control signal, the bias control signal is input to the amplification stages 102B1 to 102B3 of the power amplifier circuit 102B. The bias voltage to be applied is controlled. The output (output signal, output power) from the power amplification circuit 102A for GSM900 is detected by the detection circuit 109A, and the detection signal (output power detection signal) detected by the detection circuit 109A is for GSM900 of the RF power module 1. The output detection signal is output from the output terminal 111a. The output (output signal, output power) from the power amplifier circuit 102B for DCS 1800 is detected by the detection circuit 109B, and the detection signal (output power detection signal) detected by the detection circuit 109B is for the DCS 1800 of the RF power module 1. The output detection signal is output from the output terminal 111b.

  Each of the power amplifier circuits 102A and 102B has a circuit configuration in which three n-channel LDMOSFETs are sequentially connected in cascade as the three amplification stages 102A1 to 102A3 and 102B1 to 102B3. That is, each amplification stage 102A1, 102A2, 102A3, 102B1, 102B2, and 102B3 is formed by an n-channel type LDMOSFET, and three n-channel type LDMOSFETs are sequentially connected to form a power amplification circuit 102A. The type LDMOSFETs are sequentially connected to form a power amplifier circuit 102B.

  As described above, an RF power module used in a mobile phone or the like incorporates a detection circuit that detects output power of the entire RF power module. As a method for detecting the output power, a MOSFET detection method using a detection circuit using a MOSFET can be considered. FIG. 33 is a circuit diagram showing this MOSFET detection type detection circuit. 33 is incorporated in the RF power module, the output power amplified and output by the power amplifier circuit of the RF power module can be detected by this detection circuit. However, the MOSFET detection type detection circuit 209A as shown in FIG. 33 has a complicated circuit configuration and a large scale, which is disadvantageous for miniaturization of the RF power module. Further, since the MOSFET detection type detection circuit 209A is composed of a MOSFET (CMOSFET) used for signal control, it may be monolithic on the silicon substrate together with the amplifier circuit, but the circuit configuration is complicated. Since the scale is large, it occupies a relatively large area of the semiconductor chip and the semiconductor chip itself becomes large.

  As another method for detecting the output power of the RF power module, an SBD detection method using a Schottky Barrier Diode (SBD) can be considered. FIG. 2 is a circuit diagram showing a detection circuit of this SBD detection method. In the present embodiment, the detection circuits 109A and 109B of the RF power module 1 use detection circuits of the SBD detection system as shown in FIG.

  By incorporating detection circuits 109A and 109B of the SBD detection method as shown in FIG. 2 in the RF power module 1, the output power amplified and output by the power amplification circuits 102A and 102B of the RF power module 1 is detected. The circuits 109A and 109B can be detected with high sensitivity. In addition, a Schottky barrier diode having better turn-off characteristics than a PN junction diode is preferably used because it operates in a microwave band or the like.

  The detection circuits 109A and 109B of the SBD detection system as shown in FIG. 2 are composed of a Schottky barrier diode element 121, a capacitor element 122, and a resistance element 123. If these elements constituting the detection circuit of the SBD detection method are formed by chip components (chip diodes, chip capacitors, and chip resistors) and mounted on the wiring board (module board) constituting the RF power module. Then, the planar size of the RF power module is increased, and the RF power module is increased in size.

  FIG. 3 is a top view (plan view) showing a structure of a comparative RF power module 201 examined by the present inventors. The RF power module 201 of the comparative example shown in FIG. 3 has a wiring board 203, a semiconductor chip 202 mounted on the wiring board 3, and a passive component (chip part) 204 mounted on the wiring board 203. The upper surface of the wiring board 203 including the semiconductor chip 202 and the passive component 204 is sealed with a sealing resin (not shown). The electrodes of the semiconductor chip 2 are electrically connected to the board-side terminals 212 of the wiring board 203 via bonding wires 208.

  The RF power module 201 of the comparative example of FIG. 3 has substantially the same circuit configuration as that of FIG. 1, but the detection circuit 209B of the SBD detection system as shown in FIG. 3 is a chip SBD for the detection circuit 209B. It is formed by a passive component 204 (passive component 204 mounted in a region surrounded by a dotted line indicating the detection circuit 209B in FIG. 3) mounted on the wiring board 203 including the (chip Schottky barrier diode) 204a. The semiconductor chip 202 is formed with power amplification circuits 102A and 102B, but no detection circuit is formed. For this reason, an area for mounting the passive component 204 for the detection circuit 209B of the SBD detection method is required on the wiring board 203, and accordingly, the planar size of the RF power module 201 is increased, and the RF power module 201 is increased in size. End up. Moreover, in the RF power module 201 of the comparative example of FIG. 3, the passive component 204 (chip SBD 204a) for the detection circuit 209B of the SBD detection method is separated from the semiconductor chip 202 on which the power amplification circuits 102A and 102B are formed. Since the bonding wire 216 and the wiring board 203 are electrically connected to each other, they are affected by the parasitic resistance and parasitic inductance of the bonding wire 216 and the wiring board 203, and the detection circuit 209B of the SBD detection method is used. The detection sensitivity may be reduced.

  On the other hand, in this embodiment, the detection circuit (detection circuits 109A and 109B) of the SBD detection system as shown in FIG. 2 is formed (integrated) in the same semiconductor chip 2 together with the power amplification circuits (102A and 102B). The semiconductor chip 2 is mounted on a wiring board (module board) 3 to obtain the RF power module 1.

  FIG. 4 is a top view (plan view) showing the structure of the RF power module 1 of the present embodiment, and FIG. 5 is a conceptual cross-sectional view of the RF power module 1 of the present embodiment. 4 substantially corresponds to FIG. 5, and FIG. 4 shows a state in which the sealing resin 5 is seen through. FIG. 4 is a plan view corresponding to FIG.

  The RF power module 1 of the present embodiment shown in FIGS. 4 and 5 includes a wiring board (multilayer board, multilayer wiring board, module board) 3 and a semiconductor chip (semiconductor) mounted (mounted) on the wiring board 3. Element, active element) 2, a passive component (passive element, chip component) 4 mounted (mounted) on the wiring substrate 3, and a sealing resin covering the upper surface of the wiring substrate 3 including the semiconductor chip 2 and the passive component 4 (Sealing resin part) 5. The semiconductor chip 2 and the passive component 4 are electrically connected to the conductor layer (transmission line) of the wiring board 3. The RF power module 1 can also be mounted on, for example, an external circuit board (not shown) or a mother board.

The wiring substrate 3 is, for example, a multilayer substrate (multilayer wiring substrate) in which a plurality of insulating layers (dielectric layers) 11 and a plurality of conductor layers or wiring layers (not shown) are stacked and integrated. In FIG. 5, the wiring substrate 3 is formed by stacking four insulating layers 11. However, the number of the insulating layers 11 to be stacked is not limited to this and can be variously changed. As a material for forming the insulating layer 11 of the wiring board 3, for example, a ceramic material such as alumina (aluminum oxide, Al ₂ O ₃ ) can be used. In this case, the wiring board 3 is a ceramic multilayer board. The material of the insulating layer 11 of the wiring board 3 is not limited to a ceramic material and can be variously changed. For example, a glass epoxy resin may be used.

  Between the upper surface (front surface, main surface, first main surface) 3a and lower surface (back surface, main surface) 3b of the wiring substrate 3 and between the insulator layers 11, a conductor layer (wiring layer, wiring for wiring formation) is formed. Pattern, conductor pattern). By the uppermost conductor layer of the wiring board 3, a board-side terminal (terminal, electrode, transmission line, wiring pattern) 12 a made of a conductor is formed on the upper surface 3 a of the wiring board 3, and the lowermost conductor layer of the wiring board 3. Thus, an external connection terminal (terminal, electrode, module electrode) 12b made of a conductor is formed on the lower surface 3b of the wiring board 3. The external connection terminal 12b corresponds to, for example, the input terminals 105a and 105b, the output terminals 107a and 107b, the bias control signal input terminals 110a and 110b, and the output detection signal output terminals 111a and 111b in FIG. A conductor layer (wiring layer, wiring pattern, conductor pattern) is also formed inside the wiring board 3, that is, between the insulator layers 11, but is not shown in FIG. 5 for simplification. Among the wiring patterns formed by the conductor layer of the wiring board 3, the wiring pattern for supplying the reference potential (for example, the reference potential supplying terminal 12 c on the lower surface 3 b of the wiring board 3) is used for forming the wiring of the insulator layer 11. A solid pattern that covers most of the surface area can be formed, and a wiring pattern for a transmission line can be formed as a strip pattern.

  Each conductor layer (wiring layer) constituting the wiring board 3 is electrically connected through a conductor or a conductor film in a via hole (through hole) 13 formed in the insulator layer 11 as necessary. Accordingly, the board-side terminal 12a on the upper surface 3a of the wiring board 3 is connected to the upper surface 3a of the wiring board 3 and / or an internal wiring layer (wiring layer between the insulator layers 11), a conductor film in the via hole 13 or the like as necessary. Is electrically connected to the external connection terminal 12b on the lower surface 3b of the wiring board 3. Of the via holes 13, the via holes 13 a provided below the semiconductor chip 2 can also function as thermal vias for conducting heat generated in the semiconductor chip 2 to the lower surface 3 b side of the wiring substrate 3.

  The semiconductor chip 2 is a semiconductor chip 2 on which a semiconductor integrated circuit corresponding to a circuit configuration surrounded by a dotted line indicating the semiconductor chip 2 in the circuit block diagram of FIG. 1 is formed. In the present embodiment, detection circuits 109A and 109B of the SBD detection system as shown in FIG. 2 are formed as part of the semiconductor integrated circuit in the semiconductor chip 2 (or the surface layer portion of the semiconductor chip 2). . Therefore, in the semiconductor chip 2 (or the surface layer portion), the LDMOSFET elements constituting the power amplification circuits 102A and 102B (the amplification stages 102A1 to 102A3 and 102B1 to 102B3) and the output power of the power amplification circuits 102A and 102B are detected. Thus, a semiconductor integrated circuit including Schottky barrier diode elements, capacitance (capacitor) elements, and resistance elements that form detection circuits 109A and 109B is formed. That is, the LDMOSFET elements for the power amplifier circuits 102A and 102B and the Schottky barrier diode elements, the capacitor elements, and the resistor elements for the detection circuits 109A and 109B are formed in the same semiconductor chip 2. For example, the semiconductor chip 2 is formed by forming a semiconductor integrated circuit on a semiconductor substrate (semiconductor wafer) made of, for example, single crystal silicon, and then grinding the back surface of the semiconductor substrate as necessary, and then dicing or the like. The chip 2 is separated.

  In the semiconductor chip 2 mounting region of the wiring board 3, a planar rectangular recess (recess) 14 called a cavity is provided, and the semiconductor chip 2 is placed on, for example, a solder layer 14 a on the bottom surface of the recess 14 of the wiring board 3. Die bonding is performed face up with a bonding material (adhesive) such as 15. For die bonding of the semiconductor chip 2, silver paste or the like can be used instead of the solder 15. An electrode (bonding pad) 2 a formed on the surface (upper surface) of the semiconductor chip 2 is electrically connected to a substrate-side terminal 12 a on the upper surface 3 a of the wiring substrate 3 via a bonding wire 8. Further, a back surface electrode 2 b (corresponding to a back surface electrode 89 described later) is formed on the back surface of the semiconductor chip 2, and the back surface electrode 2 b of the semiconductor chip 2 is formed on the conductor layer 14 a on the bottom surface of the recess 14 of the wiring substrate 3. They are connected (bonded) by a bonding material such as solder 15, and are further electrically connected to a reference potential supply terminal 12 c on the lower surface 3 b of the wiring substrate 3 through a conductor film or the like in the via hole 13.

  The passive component 4 includes a passive element such as a resistance element (for example, a chip resistor), a capacitance element (for example, a chip capacitor), or an inductor element (for example, a chip inductor), and includes, for example, a chip component. The passive component 4 is mounted on a board-side terminal 12 a on the upper surface 3 a of the wiring board 3 by a bonding material (adhesive) having good conductivity such as solder 17. The board-side terminal 12a on the upper surface 3a of the wiring board 3 to which the semiconductor chip 2 or the passive component 4 is electrically connected is connected to the wiring board 3 via a wiring layer inside the wiring board 2, a conductor film in the via hole 13, or the like. Is electrically connected to the external connection terminal 12b on the lower surface 3b of the. In the present embodiment, since the Schottky barrier diode elements for the detection circuits 109A and 109B are formed in the semiconductor chip 2, Schottky barrier diode elements other than the Schottky barrier diode formed in the semiconductor chip 2 are It is not mounted on the upper surface 3 a of the wiring board 3.

  The sealing resin 5 is formed on the wiring substrate 3 so as to cover the semiconductor chip 2, the passive component 4 and the bonding wire 8. The sealing resin 5 is made of, for example, a resin material such as an epoxy resin, and can contain a filler.

  In the present embodiment, as described above, the detection circuits 109A and 109B of the SBD detection method using the Schottky barrier diode are also formed in the semiconductor chip 2 (or the surface layer portion) together with the power amplifier circuits 102A and 102B. That is, a part of a semiconductor integrated circuit in which the LDMOSFET elements constituting the power amplifier circuits 102A and 102B and the Schottky barrier diode elements, capacitor elements and resistor elements constituting the detection circuits 109A and 109B are formed on the semiconductor chip 2 It is formed as. For this reason, it is not necessary to mount the components for the detection circuits 109A and 109B of the SBD detection method on the wiring substrate 3 outside the semiconductor chip 2. Therefore, the planar size of the RF power module 1 can be reduced, and the RF power module 1 can be downsized. For example, as compared with the RF power module 201 of the comparative example of FIG. 3, the planar dimensions of the RF power module 1 of the present embodiment of FIGS. 4 and 5 are equivalent to the wiring board region for the detection circuit 209B. ) Can be small. Since the power amplifier circuits 102A and 102B and the SBD detection system detection circuits 109A and 109B are integrated on the semiconductor chip 2, the SBD detection system detection circuits 109A and 109B are arranged in the immediate vicinity of the LDMOSFET which is an amplification element. Thus, the detection circuits 109A and 109B are less susceptible to the parasitic resistance and parasitic inductance of the bonding wire 8 and the wiring of the wiring board 3, and the loss is small and the structure is less susceptible to the disturbance.

  Next, the structure of the semiconductor device of the present embodiment (corresponding to the semiconductor chip 2) will be described with reference to the drawings. FIG. 6 is a cross-sectional view of the main part of the semiconductor device (corresponding to the semiconductor chip 2) of the present embodiment.

  The semiconductor device of the present embodiment shown in FIG. 6 corresponds to the semiconductor chip 2 on which the power amplifier circuits 102A and 102B and the detection circuits 109A and 109B are formed, and the semiconductor device of the present embodiment is formed. The semiconductor substrate 21 includes, for example, an LDMOSFET formation region 21A where an LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) is formed, an SBD formation region 21B where a Schottky barrier diode element is formed, and a capacitance ( The capacitor has a capacitor formation region 21C in which elements are formed and a resistance element formation region 21D in which resistance elements are formed. The LDMOSFET formed in the LDMOSFET formation region 21A corresponds to the LDMOSFET constituting the power amplification circuits 102A and 102B (the respective amplification stages 102A1 to 102A3 and 102B1 to 102B3), and is a Schottky barrier diode formed in the SBD formation region 21B. The element corresponds to the Schottky barrier diode element that constitutes the detection circuits 109A and 109B, and the capacitive element formed in the capacitor forming region 21C corresponds to the capacitive element that constitutes the detection circuits 109A and 109B. The resistance elements formed in the region 21D correspond to the resistance elements constituting the detection circuits 109A and 109B.

As shown in FIG. 6, a semiconductor substrate (hereinafter referred to as a low resistance substrate) made of, for example, a p ⁺ type silicon (Si) single crystal and having a resistivity (specific resistance) of about 1 to 10 mΩ · cm, for example. An epitaxial layer 22 made of p-type single crystal silicon having a resistivity (specific resistance) of about 20 Ωcm and a film thickness of about 2 μm is formed on the main surface of the substrate 21. The impurity concentration of the epitaxial layer 22 is lower than the impurity concentration of the substrate 21, and the resistivity of the epitaxial layer 22 is higher than the resistivity of the substrate 21. An element isolation region 25 made of an insulator is formed on the main surface of the epitaxial layer 22 to electrically isolate each element.

A p-type well 26 is formed on a part of the main surface of the epitaxial layer 22 in the LDMOSFET formation region 21A. The p-type well 26 has a function as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET. On the surface of the p-type well 26, a gate electrode 32 of the LDMOSFET is formed via a gate insulating film 28 made of silicon oxide or the like. The gate electrode 32 is formed of a laminated film of, for example, an n-type polycrystalline silicon film 29 and a metal silicide film 30 such as a tungsten silicide (WSi _x ) film. The p-type well 26 below the gate electrode 32 is a region where the channel of the LDMOSFET is formed. Sidewall spacers 38 made of silicon oxide or the like are formed on the side walls of the gate electrode 32.

In the LDMOSFET formation region 21A, the source and drain of the LDMOSFET are formed in regions separated from each other across the channel formation region inside the epitaxial layer 22. Drain, n contact with the channel forming region ^- -type offset drain region (first low-concentration region) 35, the n ^- -type offset drain region 35 in contact with, n-type offset drain region formed apart from the channel forming region (Second low concentration region) 39 and an n ⁺ type drain region (high concentration offset region) 42 formed in contact with the n type offset drain region 39 and further away from the channel formation region. Of these n ⁻ -type offset drain region 35, n-type offset drain region 39, and n ⁺ -type drain region region 42, the n ⁻ -type offset drain region 35 closest to the gate electrode 32 has the lowest impurity concentration. The n ⁺ -type drain region 42 that is farthest away has the highest impurity concentration. The n ⁻ type offset drain region 35 is formed in self alignment with the gate electrode 32, and the n type offset drain region 39 is formed in self alignment with the sidewall spacer 38 on the side wall of the gate electrode 32.

As described above, the LDMOSFET formed in the LDMOSFET formation region 21A has an offset drain region interposed between the gate electrode 32 and the n ⁺ -type drain region 42 having a double offset structure, and the n ⁻ -type closest to the gate electrode 32. The impurity concentration of the offset drain region 35 is relatively low, and the impurity concentration of the n-type offset drain region 39 spaced from the gate electrode 32 is relatively high. As a result of this structure, a depletion layer spreads between the gate electrode 32 and the drain, so that the feedback capacitance (Cgd) formed between the gate electrode 32 and the n ⁻ -type offset drain region 35 in the vicinity thereof is small. Become. Further, since the impurity concentration of the n-type offset drain region 39 is high, the on-resistance (Ron) of the LDMOS is also reduced. Since the n-type offset drain region 39 is formed at a position separated from the gate electrode 32, the influence on the feedback capacitance (Cgd) is small. For this reason, both the on-resistance (Ron) and the feedback capacitance (Cgd) can be reduced, so that the power added efficiency of the power amplifier circuit can be improved.

On the other hand, the source of the LDMOSFET formed in the LDMOSFET formation region 21A is in contact with the n ⁻ -type source region (low concentration region) 36 in contact with the channel formation region and the n ⁻ -type source region 36 and is separated from the channel formation region. The n ⁺ type source region (high concentration region) 43 is formed. The n ⁻ type source region 36 that is in contact with the channel formation region has a lower impurity concentration and is shallower than the n ⁺ type source region 43 that is separated from the channel formation region. A p-type halo region 37 is formed below the n ⁻ -type source region 36 to suppress the spread of impurities from the source to the channel formation region and further suppress the short channel effect. The n ⁻ type source region 36 is formed in self alignment with the gate electrode 32, and the n ⁺ type source region 43 is formed in self alignment with the sidewall spacer 38 on the side wall of the gate electrode 32.

In LDMOSFET formation region 21A, the end portion of the n ⁺ -type source region 43 ^- in the (n type end portions of the source region 36 and the contact side opposite), p-type punched layer so as to be adjacent to the n ⁺ -type source region 43 24 is formed. A p ⁺ type semiconductor region 46 for reducing the resistance of the surface of the p-type punching layer 24 is formed near the surface of the p-type punching layer 24. The p-type punching layer 24 is a conductive layer for connecting the source of the LDMOSFET and the substrate 21, and is formed of a p-type polycrystalline silicon film embedded in the groove 23 formed in the epitaxial layer 22. The groove 23 penetrates the epitaxial layer 22, and the bottom of the p-type punching layer 24 reaches the substrate 21. Further, the p-type punch layer 24 may be formed by ion implantation of a high-concentration and high-energy p-type impurity instead of the p-type polycrystalline silicon film embedded in the trench 23.

An n-type well 27 is formed in the epitaxial layer 22 of the SBD formation region 21B. In the n-type well 27, a plurality of n ⁺ -type semiconductor regions (n ⁺ -type impurity diffusion layers, n ⁺ -type cathode regions) 44 having an impurity concentration higher than that of the n-type well 27 are formed. A plurality of Schottky electrodes (metal electrode, anode region, anode electrode) 52 made of a metal material such as tungsten (W) is formed on the n-type well 27 between the plurality of n ⁺ -type semiconductor regions 44. That is, the Schottky electrode 52 is formed on the n-type well 27 in the adjacent n ⁺ -type semiconductor region. A Schottky junction is formed between each Schottky electrode 52 and the n-type well 27. That is, the Schottky electrode 52 becomes an anode region, and the n-type well 27 becomes a cathode region. The impurity concentration of the n-type well 27 is adjusted to such an impurity concentration that a Schottky junction can be formed with the Schottky electrode 52. A region where the Schottky electrode 52 and the n-type well 27 are in contact (Schottky junction or Schottky junction surface) is surrounded by a p ⁺ -type guard ring layer (p ⁺ -type semiconductor region) 47 for preventing leakage, The n-type well 27 inside the p ⁺ -type guard ring layer 47 and the lower surface of the Schottky electrode 52 come into contact with each other, and a Schottky junction is formed therebetween. The end region on the lower surface of the Schottky electrode 52 is in contact with the p ⁺ -type guard ring layer 47 so as to overlap.

  Over the element isolation region 25 of the resistance element formation region 21D, a silicon film into which an impurity has been introduced, for example, an n-type polycrystalline silicon film (a polycrystalline silicon film doped with (introduced with) an n-type impurity such as phosphorus (P)) ) Is formed.

On the epitaxial layer 22, an insulating film (interlayer insulating film) composed of a relatively thin silicon nitride film and a relatively thick silicon oxide film thereon so as to cover the gate electrode 32, the Schottky electrode 52, and the resistance element 33. ) 61 is formed. A contact hole (opening) 62 is formed in the insulating film 61, and a plug (conductor portion) 63 made of a conductive film mainly composed of a tungsten (W) film is formed in the contact hole 62. The plug 63 includes an n ⁺ -type drain region 42, an n ⁺ -type source region 43 in the LDMOSFET formation region 21A, a p-type punching layer 24 (p ⁺ -type semiconductor region 46), and a plurality of n ⁺ -type semiconductor regions 44 in the SBD formation region 21B. The plurality of Schottky electrodes 52 and the resistive element 33 in the resistive element forming region 21D are formed on upper ends of the resistive elements 33 and are electrically connected thereto.

  An insulating film 64 made of a silicon oxide film or the like is formed on the insulating film 61 in which the plug 63 is embedded. A wiring groove (opening, wiring opening) 65 is formed in the insulating film 64, and a wiring (first layer wiring) 66 made of a conductive film mainly composed of a tungsten (W) film or the like is formed in the wiring groove 65. Is formed. The wiring 66 is electrically connected to the plug 63.

The source electrode 71 of the wiring 66 is electrically connected to the source (n ⁺ type source region 43) of the LDMOSFET via the plug 63 and is also connected to the p type punching layer 24 (p ⁺ type semiconductor) via the plug 63. It is electrically connected to the region 46), and is further electrically connected to the substrate 21 (and a back electrode 89 described later) via the p-type punching layer 24. Therefore, the source (n ⁺ type source region 43) of the LDMOSFET is electrically connected to the p type punching layer 24 (p ⁺ type semiconductor region 46) via the plug 63, the source electrode 71 and the plug 63, and further p It is electrically connected to the substrate 21 (and a back electrode 89 described later) through the die punching layer 24. Further, the drain electrode 72 of the wiring 66 is electrically connected to the drain (n ⁺ type drain region 42) of the LDMOSFET through the plug 63. Further, the cathode electrode 73 in the wiring 66 is electrically connected to the plurality of n ⁺ type semiconductor regions 44 in the SBD formation region 21 ^</ b> B through the plug 63. The anode electrode 74 in the wiring 66 is electrically connected to the plurality of Schottky electrodes 52 in the SBD formation region 21 </ b> B through the plug 63. In addition, the lower electrode 75 formed in the capacitor formation region 21 </ b> C of the wiring 66 serves as a lower electrode of a MIM (Metal Insulator Metal) type capacitive element (MIM capacitor) 87.

The plurality of Schottky electrodes 52 are electrically connected to each other via the plug 63 and the anode electrode 74, and the plurality of n ⁺ type semiconductor regions 44 are electrically connected to each other by the plug 63 and the cathode electrode 73, thereby A plurality of Schottky junctions formed between the Schottky electrode 52 and the n-type well 27 are connected in parallel, and a Schottky diode element is formed in the SBD formation region 21B. The Schottky barrier diode element can obtain diode characteristics (rectification characteristics) by the difference in work function between the n-type well 27 made of Si and the Schottky electrode 52 which is a metal electrode. In this embodiment, a plurality of Schottky junctions formed by a plurality of Schottky electrodes 52 are connected in parallel to form a Schottky diode element, and a plug 63 is connected to the n ⁺ type semiconductor region 44 between adjacent Schottky junctions. By electrically connecting the cathode electrode 73 via the Schottky junction, the total area of the Schottky junction can be increased without increasing the parasitic resistance.

  Also, the Schottky diode element formed in the SBD formation region 21B is not directly connected to the LDMOSFET element in the LDMOSFET formation region 21A, but is the main substrate on the side where the LDMOSFET element or the Schottky diode element is formed. Is electrically connected to the LDMOSFET element in the LDMOSFET formation region 21A via other passive elements formed on the surface) (passive elements other than Schottky diodes, such as the capacitive element 87 and the resistive element 33). Therefore, the anode electrode 74 or the cathode electrode 73 of the Schottky diode element is another passive element (passive element other than the Schottky diode) formed on the substrate 21 (the main surface on the side where the LDMOSFET element or the Schottky diode element is formed) For example, it is electrically connected to the capacitor element 87 and the resistor element 33).

  An insulating film 81 made of a silicon oxide film or the like is formed on the insulating film 64 in which the wiring 66 is embedded. An opening 82 is formed in the insulating film 81 in the capacitor forming region 21 </ b> C, and an insulating film 83 that functions as a capacitor insulating film of the MIM type capacitive element 87 is formed on the lower electrode 75 exposed from the opening 82. ing. The insulating film 64 also has an opening 84 that exposes the wiring 66 at the bottom.

  A wiring 85 as a second layer wiring formed on the insulating film 81 is connected to the wiring 66 through the opening 84. The wiring 85 is made of a conductive film mainly composed of, for example, an aluminum (Al) alloy film. In the capacitor forming region 21 </ b> C, an MIM type capacitive element 87 is formed by the upper electrode 86 formed on the lower electrode 75 via the insulating film 83.

  A surface protective film 88 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the insulating film 81 so as to cover the wiring 85. Further, on the back surface of the substrate 21 (the main surface opposite to the side on which the epitaxial layer 22 is formed), for example, a laminated film of a nickel (Ni) film, a titanium (Ti) film, a Ni film, and a gold (Au) film, etc. A back electrode (back source electrode) 89 made of is formed. The back electrode 89 is electrically connected to the source region of the LDMOSFET through the p-type punching layer 24, the plug 63 and the source electrode 71. The back electrode 89 corresponds to the back electrode 2 b of the semiconductor chip 2.

  Next, a manufacturing process of the semiconductor device of the present embodiment (corresponding to the semiconductor chip 2) will be described with reference to the drawings. 7 to 14 are main part cross-sectional views during the manufacturing process of the semiconductor device (corresponding to the semiconductor chip 2) of the present embodiment, and the cross section corresponding to FIG. 6 is shown.

  First, as shown in FIG. 7, a substrate 21 made of p-type single crystal silicon is prepared, and an epitaxial layer 22 made of p-type single crystal silicon is formed on the main surface of the substrate 21 by using a known epitaxial growth method. To do.

  Next, in the LDMOSFET formation region 21A, a part of the epitaxial layer 22 (punched layer formation region) is etched using a photolithography technique and a dry etching technique to form a groove 23 reaching the substrate 21. Then, a p-type polycrystalline silicon film is deposited on the substrate 21 including the inside of the trench 23 by using a CVD (Chemical Vapor Deposition) method or the like so as to fill the inside of the trench 23, and then the p-type polycrystalline outside the trench 23. By removing the silicon film by an etch back method or the like, a p-type punching layer 24 made of a p-type polycrystalline silicon film is formed in the groove 23. The p-type punching layer 24 penetrates the epitaxial layer 22, and the bottom of the p-type punching layer 24 reaches the substrate 21. Thus, by embedding the p-type polycrystalline silicon film doped with impurities in the groove 23, the p-type punching layer 24 having a low parasitic resistance can be formed. It is also possible to form a punched layer having a smaller parasitic resistance by embedding a metal film in the groove 23 instead of the polycrystalline silicon film. In addition, when a punching layer having a low parasitic resistance is unnecessary, the p-type punching layer 24 may be formed by ion implantation of a high-concentration and high-energy p-type impurity.

  Next, an element isolation region 25 made of an insulator is formed on the main surface of the epitaxial layer 22 by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method.

  Next, as shown in FIG. 8, by using a photoresist pattern (not shown) as a mask, a p-type impurity such as boron (B) is ion-implanted into a part of the epitaxial layer 22, thereby punch-through stopper. A p-type well 26 is formed. The p-type well 26 is formed in a part of the LDMOSFET formation region 21A, and is mainly formed in the source formation region and the channel formation region of the LDMOSFET.

  Next, an n-type well 27 is formed by ion-implanting n-type impurities such as phosphorus (P) or arsenic (As) into the epitaxial layer 22 in the SBD formation region 21B using a photoresist pattern (not shown) as a mask. Form.

  Next, after cleaning the surface of the epitaxial layer 22 with hydrofluoric acid or the like, the substrate 21 is subjected to a heat treatment (thermal oxidation treatment) at about 800 ° C., for example, so that silicon oxide having a film thickness of about 11 nm is formed on the surface of the epitaxial layer 22. An insulating film 28a for forming a gate insulating film made of a film or the like is formed. As the insulating film 28a, a silicon oxide film containing nitrogen, that is, a so-called oxynitride film may be used instead of the thermal oxide film. In this case, hot electron traps at the interface of the insulating film 28a can be reduced. Alternatively, a silicon oxide film may be deposited on the thermal oxide film by a CVD method, and the insulating film 28a may be constituted by these two oxide films.

Next, the gate electrode 32 is formed on the insulating film 28a in the LDMOSFET formation region 21A. In order to form the gate electrode 32, for example, an n-type impurity such as phosphorus (P) is doped on the main surface of the epitaxial layer 22 (that is, on the insulating film 28 a) by CVD or the like ( Introduced polycrystalline silicon film) 29 is deposited, and then a metal silicide film 30 such as a tungsten silicide (WSi _x ) film is deposited on the n-type polycrystalline silicon film 29 by CVD or the like. After an insulating film (cap insulating film) 31 made of a silicon oxide film or the like is deposited thereon by CVD or the like, the insulating film 31, the metal silicide film 30, and the n-type polycrystalline silicon film are used by using a photolithography technique and a dry etching technique. 29 is patterned. As a result, a gate electrode 32 comprising the patterned n-type polycrystalline silicon film 29 and the metal silicide film 30 thereon is formed on the surface of the p-type well 26 in the LDMOSFET formation region 21A via the insulating film 28a. The insulating film 28a under the gate electrode 32 becomes the gate insulating film 28 of the LDMOSFET.

  Next, a silicon film doped with impurities, for example, an n-type polycrystalline silicon film (polycrystalline doped with n-type impurities such as phosphorus (P)) is formed on the element isolation region 25 of the resistance element forming region 21D. A resistance element 33 made of a silicon film 33a is formed. For example, an n-type polycrystalline silicon film 33a is deposited on the main surface of the epitaxial layer 22 by a CVD method or the like, and then an insulating film (cap insulation) made of a silicon oxide film or the like is formed on the n-type polycrystalline silicon film 33a by a CVD method or the like. After the film 34) is deposited, the insulating film 34 and the n-type polycrystalline silicon film 33a are patterned using a photolithography technique and a dry etching technique. Thereby, the resistance element 33 made of the patterned n-type polycrystalline silicon film 33a is formed in the resistance element formation region 21D. Resistance element 33 can also be formed of a p-type polycrystalline silicon film. The impurity concentration of the silicon film constituting the resistance element 33 can be selected in consideration of the resistivity required for the resistance element 33 and the like. In addition, after forming the resistance element 33, the insulating film 28a and the gate electrode 32 can be formed.

Next, as shown in FIG. 9, n-type impurities such as phosphorus (P) are ion-implanted into a part of the epitaxial layer 22 in the LDMOSFET formation region 21A using a photoresist pattern (not shown) as a mask. Thus, the n ⁻ type offset drain region 35 is formed. The n ⁻ type offset drain region 35 terminates at the lower portion of the side wall of the gate electrode 32 so that the end thereof is in contact with the channel formation region. By reducing the impurity concentration of the n ⁻ -type offset drain region 35, a depletion layer spreads between the gate electrode 32 and the drain, so that a feedback capacitance (between the drain and gate electrode) formed between the two is formed. Parasitic capacitance, Cgd) is reduced.

Next, n ⁻ -type source region 36 is formed by ion-implanting n-type impurities such as arsenic (As) into the surface of p-type well 26 of LDMOSFET formation region 21A using a photoresist pattern (not shown) as a mask. Form. The n ⁻ -type source region 36 terminates at the lower portion of the side wall of the gate electrode 32 so that the end thereof is in contact with the channel formation region. By forming the n ⁻ -type source region 36 relatively shallow, the spread of impurities from the source to the channel formation region can be suppressed, so that a decrease in threshold voltage can be suppressed.

Next, following the ion implantation for forming the n ⁻ -type source region 36, a p-type impurity such as boron (B) is ion-implanted into the surface of the p-type well 26 in the LDMOSFET formation region 21 A, thereby causing n ^A p-type halo region 37 is formed below the -type source region 36. At this time, an oblique ion implantation method in which impurities are ion-implanted from an oblique direction with respect to the main surface of the substrate 21 is used. The p-type halo region 37 is not necessarily formed. However, when the p-type halo region 37 is formed, the spread of impurities from the source to the channel formation region is further suppressed, and the short channel effect is further suppressed. The voltage drop can be further suppressed.

  Next, a side wall spacer (side wall insulating film, side wall spacer) 38 made of silicon oxide (insulating film) or the like is formed on the side wall of the gate electrode 32. The sidewall spacer 38 can be formed, for example, by depositing a silicon oxide film (insulating film) on the substrate 21 by CVD or the like and then anisotropically etching the silicon oxide film (insulating film). In the step of forming the side wall spacer 38 on the side wall of the gate electrode 32, the side wall spacer (side wall insulating film, side wall spacer) 38a similar to the side wall spacer 38 is also formed on the side wall of the resistance element 33 in the resistance element forming region 21D. Is formed.

Next, an n-type impurity such as phosphorus (P) is ion-implanted into a part of the n ⁻ -type offset drain region 35 of the LDMOSFET formation region 21A. As a result, an n-type offset drain region 39 is formed in a part of the n ⁻ -type offset drain region 35 in a self-aligned manner with respect to the sidewall spacer 38 formed on the side wall on the drain side of the gate electrode 32. By making the ion implantation acceleration energy the same in the ion implantation step for forming the n ⁻ type offset drain region 35 and the ion implantation step for forming the n type offset drain region 39, the n type offset drain region 39 is formed. Is substantially the same as the junction depth of the n ⁻ -type offset drain region 35. Further, since the impurity implanted into the n-type offset drain region 39 is an impurity having the same conductivity type (here, n-type) as the impurity implanted into the n ⁻ -type offset drain region 35, the impurity concentration of the n-type offset drain region 39 is Becomes higher than the impurity concentration of the n ⁻ -type offset drain region 35. The n ⁻ -type offset drain region 35 is formed in a self-aligned manner with respect to the gate electrode 32, whereas the n-type offset drain region 39 is self-aligned with respect to the sidewall spacer 38 on the side wall of the gate electrode 32. Since the n-type offset drain region 39 is formed in a consistent manner, the n-type offset drain region 39 is formed away from the gate electrode 32 by an amount corresponding to the film thickness of the sidewall spacer 38 along the gate length direction.

Next, as shown in FIG. 10, a part of the n-type offset drain region 39 in the LDMOSFET formation region 21A, a p-type well 26 in the source formation region, and a part of the n-type well 27 in the SBD formation region 21B. An n-type impurity such as arsenic (As) is formed in a part of each of the n-type offset drain region 39, the p-type well 26 and the n-type well 27 using a photoresist pattern (not shown) having an opening in the upper part as a mask. Ion implantation. As a result, a part of the n-type offset drain region 39 in the LDMOSFET formation region 21A has an impurity concentration higher than that of the n-type offset drain region 39 and further separated from the channel formation region than the n-type offset drain region 39. ⁺ -type drain region 42 are formed, also, the p-type well 26 of the LDMOSFET formation region 21A, n ^- impurity concentration higher than type source region 36 and n ^- position of the bottom portion than -type source region 36 (junction A deep n ⁺ -type source region 43 is formed, and a plurality of n ⁺ -type semiconductor regions (n ⁺ -type) having a higher impurity concentration than the n-type well 27 are formed in the n-type well 27 of the SBD formation region 21B. An impurity diffusion layer, n ⁺ -type cathode region) 44 is formed. The n ⁺ -type semiconductor region 44 is formed for taking out (connecting) the cathode electrode of the Schottky barrier diode therefrom. The n ⁺ type source region 43 is formed in a self-aligned manner with respect to the side wall spacer 38 on the side wall of the gate electrode 32 and is formed in contact with the n ⁻ type source region 36. Therefore, the n ⁺ -type source region 43 is formed away from the channel formation region by an amount corresponding to the film thickness of the sidewall spacer 38 along the gate length direction.

Through the steps so far, as shown in FIG. 10, the drain (drain region) composed of the n ⁻ type offset drain region 35, the n type offset drain region 39 and the n ⁺ type drain region 42, the n ⁻ type source region 36. MISFETs (Metal Insulator Semiconductor Field Effect Transistors) such as LDMOSFETs having a source (source region) composed of n ⁺ type source region 43 and gate electrode 32 are formed in LDMOSFET formation region 21A (the main surface of epitaxial layer 2). It is formed. Note that the MOSFET in this embodiment is not only a MISFET using an oxide film (silicon oxide film) as a gate insulating film but also a MISFET using an insulating film other than an oxide film (silicon oxide film) as a gate insulating film. Shall also be included.

Next, as shown in FIG. 11, a photoresist pattern (not shown) having openings over the p-type punching layer 24 in the LDMOSFET formation region 21A and a part of the n-type well 27 in the SBD formation region 21B is formed. As a mask, p-type impurities such as boron fluoride (BF ₂ ) are ion-implanted into the surface of the p-type punching layer 24 and a part of the n-type well 27 in the SBD formation region 21B. Thereby, ap ⁺ type semiconductor region 46 is formed in the upper region of the p type punching layer 24, and ap ⁺ type guard ring layer (p ⁺ type semiconductor region) 47 is formed in the n type well 27 of the SBD formation region 21B. By forming the p ⁺ type semiconductor region 46 in the upper region of the p-type punching layer 24, the resistance of the surface of the p-type punching layer 24 can be reduced. The p ⁺ -type guard ring layer 47 formed in the n-type well 27 in the SBD formation region 21B is formed so as to surround the region where the Schottky junction of the Schottky barrier diode is to be formed, and serves as a guard ring for the Schottky barrier diode. It can function and have a leak prevention function.

Next, as shown in FIG. 12, the insulating film (for example, the insulating film 28a) on the region where the Schottky junction is to be formed in the n-type well 27 in the SBD formation region 21B is removed by etching or the like and the surface (Schottky junction formation) is removed. After exposing the surface of the n-type well 27 in a predetermined region, a metal film made of, for example, tungsten (W) is formed on the epitaxial layer 22, and this metal film is patterned using a photolithography technique and a dry etching technique. By performing (dry etching), a plurality of Schottky electrodes (metal electrodes, anode electrodes) 52 made of a patterned metal film are formed in the SBD formation region 21B. When the insulating film (for example, the insulating film 28a) on the region where the Schottky junction is to be formed in the n-type well 27 in the SBD formation region 21B is removed by etching, an etching mask layer having an opening above the region where the Schottky junction is to be formed (For example, a photoresist pattern (not shown) is used to perform etching so that the insulating film (for example, the insulating film 28a) is left in a region other than the region where the Schottky junction is to be formed, and then the etching mask layer is formed. It is more preferable to form a metal film for forming the Schottky electrode 52 after the removal. As a metal material constituting the Schottky electrode 52, for example, tungsten (W) or titanium (Ti) can be used. Since the metal film for forming the Schottky electrode 52 is formed after exposing the surface of the n-type well 27 in the Schottky junction formation region as described above, the n-type well 27 and the metal material in the Schottky junction formation region are formed. The Schottky electrode 52 is in contact. As a result, a Schottky junction (Schottky junction) is formed between the Schottky electrode 52 and the n-type well 27 in the Schottky junction formation scheduled region, and a Schottky diode is formed in the SBD formation region 21B. The region (Schottky junction or Schottky junction surface) and the Schottky electrode 52 and the n-type well 27 are in contact is surrounded by a p ⁺ -type guard ring layer 47, the inner p ⁺ -type guard ring layer 47 n The mold well 27 and the Schottky electrode 52 are in contact with each other, and a Schottky junction is formed therebetween.

  Next, as shown in FIG. 13, an insulating film (interlayer insulating film) 61 is formed on the substrate 21 by using, for example, a CVD method. After the formation of the insulating film 61, CMP (Chemical Mechanical Polishing) treatment is performed as necessary to planarize the surface of the insulating film 61. The insulating film 61 is composed of, for example, a relatively thin silicon nitride film and a relatively thick silicon oxide film thereon, and the lower silicon nitride film functions as an etching stopper film when a contact hole 62 described later is formed. be able to. A single film such as a silicon oxide film can also be used as the insulating film 61.

Next, the insulating film 61 is dry-etched using a photoresist pattern (not shown) as an etching mask, so that the LDMOSFET drain (n ⁺ -type drain region 42) and source (n ⁺ -type source region) in the LDMOSFET formation region 21A are obtained. 43) and the p-type punching layer 24 (p ⁺ -type semiconductor region 46), the plurality of n ⁺ -type semiconductor regions 44 and the plurality of Schottky electrodes 52 in the SBD formation region 21B, and both ends of the resistance element 33 in the resistance element formation region 21D. A contact hole (opening) 62 is formed in each upper part.

Next, a plug (conductor portion, contact layer) 63 mainly composed of a tungsten (W) film is embedded in the contact hole 62. The plug 63 is made of a conductor. For example, after forming a barrier film (for example, a titanium nitride film) on the insulating film 61 including the inside (on the bottom and side walls) of the contact hole 62, the contact hole 62 is filled on the barrier film with a tungsten film by a CVD method or the like. The plug 63 can be formed by removing the unnecessary tungsten film and barrier film on the insulating film 61 by the CMP method or the etch back method. The plug 63 embedded in the contact hole 62 includes an n ⁺ type drain region 42, an n ⁺ type source region 43, a p type punching layer 24 (p ⁺ type semiconductor region 46) in the LDMOSFET formation region 21A at the bottom of the contact hole 62, The n ⁺ type semiconductor region 44 in the SBD formation region 21B, the Schottky electrode 52, or the resistance element 33 in the resistance element formation region 21D is electrically connected.

  Next, an insulating film 64 made of, for example, a silicon oxide film is formed on the insulating film 61 in which the plug 63 is embedded by a CVD method or the like. Then, the insulating film 64 is dry-etched using a photoresist pattern (not shown) as an etching mask, thereby forming a wiring groove (opening, wiring opening) 65 in the insulating film 64. At this time, the upper surface of the plug 63 is exposed at the bottom of the wiring groove 65.

  Next, a wiring (first layer wiring) 66 is formed in the wiring groove 65. For example, a barrier film (for example, a titanium nitride film) is formed on the insulating film 64 including the bottom and side walls of the wiring trench 65 by a sputtering method or the like, and a tungsten film is filled in the barrier film by a CVD method or the like. Then, unnecessary tungsten film and barrier film on the insulating film 64 are removed by CMP method or etch back method, etc., and the barrier film and tungsten film are left in the wiring trench 65 to thereby form wiring (first layer wiring). 66 is formed in the wiring groove 65. By the wiring 66, a source electrode 71, a drain electrode 72, a cathode electrode 73, an anode electrode 74, and a lower electrode 75 are formed.

  The wiring (first layer wiring) 66 may be formed by patterning using a photolithography method and a dry etching method after sputtering of a metal such as W. However, in this case, the insulating film 64 made of a silicon oxide film or the like is not formed, and an insulating film 81 to be described later also functions as the insulating film 64.

Of the formed wiring 66, the source electrode 71 is electrically connected to the source (n ⁺ -type source region 43) of the LDMOSFET through the plug 63, and the p-type punching layer 24 (p ^It is electrically connected to the ⁺ type semiconductor region 46) and further electrically connected to the substrate 21 (and the back electrode 89 to be formed later) through the p type punching layer 24. Therefore, the source (n ⁺ type source region 43) of the LDMOSFET is electrically connected to the p type punching layer 24 (p ⁺ type semiconductor region 46) via the plug 63, the source electrode 71 and the plug 63, and further p It is electrically connected to the substrate 21 (and the back electrode 89 to be formed later) through the die punching layer 24. Of the formed wiring 66, the drain electrode 72 is electrically connected to the drain (n ⁺ type drain region 42) of the LDMOSFET through the plug 63. Of the formed wiring 66, the cathode electrode 73 is electrically connected to the plurality of n ⁺ type semiconductor regions 44 through the plug 63. Of the formed wiring 66, the anode electrode 74 is electrically connected to the plurality of Schottky electrodes 52 through the plug 63. Of the wiring 66, the lower electrode 75 formed in the capacitor formation region 21C serves as a lower electrode of a capacitor (capacitance element).

  Next, as shown in FIG. 14, an insulating film 81 made of, for example, a silicon oxide film is formed on the insulating film 64 in which the wiring 66 is embedded by a CVD method or the like. Then, an opening 82 is formed in the insulating film 81 in the capacitor forming region 21C by dry etching the insulating film 81 using a photoresist pattern (not shown) as an etching mask. The lower electrode 75 is exposed at the bottom of the opening 82.

  Next, an insulating film 83 (for example, a silicon nitride film or a silicon carbide film) is formed as a capacitor insulating film on the insulating film 81 including the bottom and side walls of the opening 82, and a photolithography method and dry etching are performed. The insulating film 83 is patterned using a method. The patterned insulating film 83 remains on the lower electrode 75 at the bottom of the opening 82 and becomes a capacitor insulating film of the capacitor. Then, an opening (through hole) 84 is formed by dry etching the insulating film 81 using a photoresist pattern (not shown) as an etching mask. The wiring 66 is exposed at the bottom of the opening 84.

  Next, a conductor film mainly composed of, for example, an aluminum (Al) alloy film is formed on the insulating film 81 so as to fill the openings 82 and 84, and the conductive film is formed using a photolithography method and a dry etching method. By patterning the body film, a wiring (second layer wiring) 85 is formed from the patterned conductor film. The wiring 85 is electrically connected to the wiring 66 at the bottom of the opening 84. In the capacitor formation region 21 </ b> C, the capacitor upper electrode 86 is formed by the wiring 85 formed on the lower electrode 75 via the insulating film 83. Therefore, an MIM (Metal Insulator Metal) type capacitive element (MIM capacitor) 87 is formed in the capacitor formation region 21C by the lower electrode 75, the insulating film 83 as a capacitive insulating film, and the upper electrode 86. Then, a surface protective film 88 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the insulating film 81 so as to cover the wiring 85.

  Thereafter, a part of the surface protective film 88 is selectively removed to expose a part of the wiring 85 (a pad portion (not shown)), and then the back surface of the substrate 21 (opposite to the main surface on which the epitaxial layer 22 is formed). Side main surface) is polished if necessary, and then a back electrode (back source electrode) 89 is formed on the entire back surface of the substrate 21. Through the steps so far, the circuit in the semiconductor chip 2 (the circuit including the power amplifier circuits 102A and 102B and the detection circuits 109A and 109B) is substantially completed. The back electrode 89 can be formed by sequentially depositing, for example, a nickel (Ni) film, a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film by a sputtering method. The back electrode 89 is electrically connected to the source of the LDMOSFET through the p-type punching layer 24, the plug 63 and the source electrode 71.

  Then, after the substrate 21 is separated into semiconductor chips (semiconductor chip 2), as shown in FIGS. 4 and 5, the substrate 21 is soldered to the wiring substrate 3 via the back electrode 89 (that is, the back electrode 2b). Attached.

  In the present embodiment, as described above, the LDMOSFET for the power amplifier circuits 102A and 102B and the Schottky barrier diode element for the detection circuits 109A and 109B are formed in the same semiconductor chip 2, and FIG. As shown in FIG. 14, the LDMOS for the power amplifier circuits 102A and 102B is formed in the LDMOSFET formation region 21A of the substrate 21 constituting the semiconductor chip 2, and the Schottky barrier diode element for the detection circuits 109A and 109B is formed on the substrate 21. It is formed in the SBD formation region 21B.

  A general Schottky barrier diode element uses an n-type semiconductor substrate, and has a structure in which an anode electrode is drawn from a Schottky junction on the surface of the semiconductor substrate and a cathode electrode is drawn from the back surface of the semiconductor substrate. However, as in this embodiment, in the semiconductor device (semiconductor chip) used in the RF power module, the backside source electrode of the LDMOSFET that constitutes the power amplifier circuit is formed on the backside of the semiconductor substrate. Like the barrier diode element, the cathode electrode cannot be drawn from the back surface of the semiconductor substrate. For this reason, the cathode electrode of the Schottky barrier diode needs to be drawn from the surface side of the semiconductor substrate, like the anode electrode.

  In order to improve the detection sensitivity (detection sensitivity) of the detection circuits 109A and 109B, the value of the current flowing through the Schottky barrier diode element by increasing the junction area of the Schottky barrier diode element for the detection circuits 109A and 109B. Need to be increased. The detection sensitivity (detection sensitivity) of the detection circuits 109A and 109B can be improved by increasing the junction area of the Schottky barrier diode element and increasing the current value flowing through the Schottky barrier diode element, and the performance of the RF power module 1 Can be improved.

  15 is a cross-sectional view of a principal part showing the structure of a Schottky barrier diode element of a comparative example examined by the inventors, FIG. 16 is a plan view of the principal part, and a cross section taken along line BB in FIG. Almost corresponds to. FIG. 15 shows a cross section of a region corresponding to the SBD formation region 21B. FIG. 16 is a plan view, but hatched for easy understanding. Further, in the cross-sectional view of FIG. 15, the structure above the insulating film 64 is omitted for the sake of simplicity.

In the Schottky barrier diode element of the comparative example shown in FIGS. 15 and 16, one large-area Schottky electrode 252 (corresponding to the Schottky electrode 52 of the present embodiment) is formed on the surface of the n-type well 27. A Schottky junction (Schottky junction plane) 253 is formed between the Schottky electrode 252 and the n-type well 27. A large-area anode electrode 274 (corresponding to the anode electrode 74 of the present embodiment) is formed above the Schottky electrode 252, and the Schottky electrode 252 and the anode electrode 274 are embedded in the plurality of contact holes 62. The plurality of plugs 63 are electrically connected. A contact region (Schottky junction 253) between the Schottky electrode 252 and the n-type well 27 is surrounded by an annular p ⁺ -type guard ring layer 247 (corresponding to the p ⁺ -type guard ring layer 47 of the present embodiment), An n ⁺ type semiconductor region 244 (corresponding to the n ⁺ type semiconductor region 44 of the present embodiment) is formed on the outer periphery of the p ⁺ type guard ring layer 247. The n ⁺ type semiconductor region 244 is a cathode electrode 273 having a shape surrounding the anode electrode 274 in the same layer as the anode electrode 274 through a plug 63 embedded in a contact hole 62 formed on the n ⁺ type semiconductor region 244. Electrically corresponding to the cathode electrode 273 of this embodiment). The anode electrode 74 in the same layer as the cathode electrode 273 surrounded by the cathode electrode 273 can be drawn out (taken out) by the upper lead electrode 285 (corresponding to the second layer wiring).

  In the Schottky barrier diode element having the structure of the comparative example as shown in FIGS. 15 and 16, the cathode electrode 273 and the anode electrode 274 are drawn from the surface side of the substrate 21, and the current path 250 flowing through the n-type well 27 is , Near the Schottky junction (Schottky junction surface) 253 between the Schottky electrode 252 and the n-type well 27 (that is, near the surface of the n-type well 27), and substantially parallel to the Schottky junction surface (to the main surface of the substrate 21) Parallel). Therefore, it is easily affected by the parasitic resistance of the n-type well 27. When the junction area of the Schottky junction 253 between the Schottky electrode 252 and the n-type well 27 is small, the influence of the parasitic resistance of the n-type well 27 is small, so the current value is almost proportional to the junction area. As the area (planar dimension) increases and the junction area of the Schottky junction increases, the distance that the current passes through the n-type well 27 becomes longer (that is, the current path 250 becomes longer), and the parasitic resistance increases. Therefore, when the junction area of the Schottky junction increases, the value of the current flowing through the Schottky barrier diode element is not proportional to the junction area of the Schottky junction, and the Schottky electrode 252 is further enlarged to obtain the desired current value. The junction area of the junction must be increased. For this reason, the area utilization efficiency of the Schottky barrier diode is deteriorated, and the size of the semiconductor device (semiconductor chip) is increased. Further, since the current increase rate of the Schottky barrier diode element when the junction area of the Schottky junction is increased is suppressed, there is a possibility that the detection sensitivity of the detection circuits 109A and 109B is not sufficiently improved.

The Schottky barrier diode element (Schottky barrier diode element formed in the SBD formation region 21B) formed in the semiconductor device (corresponding to the semiconductor chip 2) of the present embodiment will be described in more detail. FIG. 17 is a fragmentary cross-sectional view showing the structure of the Schottky barrier diode element in the semiconductor device of the present embodiment, and FIGS. 18 to 20 are fragmentary plan views thereof. In the cross-sectional view of FIG. 17, a cross section of the region corresponding to the SBD formation region 21 </ b> B is shown, but the illustration of the structure of the insulating film 81 and the upper layer is omitted for simplification. A cross section taken along line CC in FIG. 18 substantially corresponds to FIG. 18 to 20 are plan views of the same region. FIG. 18 shows a planar layout of the Schottky electrode 52, the contact holes 62a and 62b, the cathode electrode 73, and the anode electrode 74, and other components are described. In FIG. 19, the planar layout of the Schottky junction 53, the p ⁺ -type guard ring layer 47, and the n ⁺ -type semiconductor region 44 is shown, and other components are not shown. 20, the planar layout of the n ⁺ type semiconductor region 44, the Schottky electrode 52, the Schottky junction 53, and the contact holes 62a and 62b is shown, and the other components are not shown. FIG. 18 is a plan view, but hatched for easy understanding.

In this embodiment, as can be seen from FIGS. 17 to 20, a plurality of Schottky electrodes 52 are formed on the surface of the n-type well 27 in the SBD formation region 21 </ b> B. A Schottky junction (Schottky junction 53) is formed. Each Schottky electrode 52 has, for example, an elongated rectangular planar shape (layout pattern), and a plurality of Schottky electrodes 52 are arranged in parallel (in parallel) with each other. In addition, a Schottky junction (Schottky junction surface) 53 that is a contact region between each Schottky electrode 52 and the n-type well 27 also has, for example, an elongated rectangular planar shape (layout pattern), and a plurality of Schottky junctions 53. Are arranged in parallel to each other (in parallel). As described above, the plurality of Schottky junctions 53 are formed to be separated from each other by the contact regions of the plurality of Schottky electrodes 52 and the n-type well 27, and the n ⁺ -type semiconductor region is interposed between the adjacent Schottky junctions 53. 44 is formed. An n ⁺ type semiconductor region 44 is also provided outside the Schottky junctions 53 at both ends of the plurality of Schottky junctions 53 arranged in parallel. Therefore, the n ⁺ type semiconductor regions 44 exist on both sides of each Schottky junction 53. In other words, a Schottky junction 53 is formed between adjacent n ⁺ type semiconductor regions 44. Each n ⁺ type semiconductor region 44 also has, for example, a rectangular planar shape (layout pattern). Further, a plurality of Schottky junction 53 is surrounded by a p ⁺ -type guard ring layer 47, respectively, near the edge region of the lower surface of the Schottky electrode 52 is in contact overlaps the p ⁺ -type guard ring layer 47 Yes.

  A contact hole 62a (a contact hole 62a of the contact hole 62) is formed on each Schottky electrode 52, and a plug 63a (a plug 63a of the plug 63) is embedded in the contact hole 62a. The planar shape (layout pattern) of the contact hole 62a and the plug 63a embedded therein has, for example, an elongated rectangular planar shape (layout pattern) in accordance with the planar shape of the Schottky electrode 52. A comb-shaped (finger structure) anode electrode 74 is formed above the plurality of Schottky electrodes 52. Each Schottky electrode 52 is electrically connected to a comb-shaped anode electrode 74 through a plug 63a embedded in the contact hole 62a on the upper side. That is, the plurality of Schottky electrodes 52 and the comb-shaped anode electrode 74 are electrically connected by the plurality of plugs 63 a formed on the plurality of Schottky electrodes 52.

A contact hole 62b (a contact hole 62b of the contact hole 62) is formed on each n ⁺ type semiconductor region 44, and a plug 63b (a plug 63b of the plug 63) is embedded in the contact hole 62b. Yes. The planar shape (layout pattern) of the contact hole 62 b and the plug 63 b embedded therein has, for example, an elongated rectangular planar shape (layout pattern) in accordance with the planar shape of the n ⁺ type semiconductor region 44. A comb-shaped (finger structure) cathode electrode 73 is formed between the plurality of Schottky junctions 53 and above each of the plurality of n ⁺ -type semiconductor regions 44 provided on both sides. Each n ⁺ -type semiconductor region 44 is electrically connected to the comb-shaped cathode electrode 73 through a plug 63b embedded in the contact hole 62b in the upper part. That is, the plurality of n ⁺ type semiconductor regions 44 and the comb-shaped cathode electrode 73 are electrically connected by the plurality of plugs 63 b formed on the plurality of n ⁺ type semiconductor regions 44.

The cathode electrode 73 of the comb includes an electrode portion 73a to be connected to the n ⁺ -type semiconductor region 44 via the plug 63b and extend (position) on the respective n ⁺ -type semiconductor region 44, a plurality of electrode portions 73a It has the connection part 73b which connects one edge part, and the connection part 73b and the some electrode part 73a are substantially orthogonally crossed. The plurality of electrode portions 73a of the cathode electrode 73 are connected to the plurality of n ⁺ type semiconductor regions 44 through the plurality of plugs 63b. The plurality of electrode portions 73a of the cathode electrode 73 have a rectangular planar shape (layout pattern), for example, and are arranged in parallel (in parallel) with each other. One end of the plurality of electrode portions 73a is connected to the connecting portion 73b, and the plurality of electrode portions 73a are connected by the connecting portion 73b. Accordingly, the plurality of n ⁺ -type semiconductor regions 44 formed between and on both sides of the plurality of Schottky junctions 53 are electrically connected to each other by the conductor portion (plug 63b) and the cathode electrode 74 filling the contact hole 62b on the upper side. Connected.

  The comb-shaped anode electrode 74 extends (positions) on each Schottky electrode 52 and connects the electrode portion 74a connected to the Schottky electrode 52 via the plug 63a and one end portion of the plurality of electrode portions 74a. The connecting portion 74b and the plurality of electrode portions 74a are substantially orthogonal to each other. The plurality of electrode portions 74a of the anode electrode 74 are connected to the plurality of Schottky electrodes 52 through the plurality of plugs 63a. The plurality of electrode portions 74a of the anode electrode 74 have a rectangular planar shape (layout pattern), for example, and are arranged in parallel (in parallel) with each other. One end of the plurality of electrode portions 74a is connected to the connecting portion 74b, and the plurality of electrode portions 74a are connected by the connecting portion 74b. Accordingly, the plurality of Schottky electrodes 52 are electrically connected to each other by the conductor portion (plug 63a) filling the contact hole 62a above the anode and the anode electrode 74. Accordingly, the plurality of Schottky junctions (Schottky junctions 53) formed by forming the plurality of Schottky barriers 52 on the n-type well 27 are connected in parallel.

  The comb-shaped cathode electrode 73 and the anode electrode 74 are formed in the same layer (that is, formed by the wiring 66 in the same layer), but the cathode electrode 73 and the anode electrode 74 are not in contact with each other. The plurality of electrode portions 73a of the cathode electrode 73 and the plurality of electrode portions 74b of the anode electrode 74 are alternately arranged. That is, the electrode part 74a is arrange | positioned between the adjacent electrode parts 73a. Further, the connecting portion 73a of the cathode electrode 73 and the end portions of the plurality of electrode portions 73a are connected, and the connecting portion 74b of the anode electrode 74 and the end portions of the plurality of electrode portions 74a are connected. The end portions are located on the opposite sides of the cathode electrode 73 and the anode electrode 74. With such a structure, the comb-shaped cathode electrode 73 and the anode electrode 74 formed in the same layer can be prevented from contacting each other. Further, since the cathode electrode 73 and the anode electrode 74 do not intersect with each other, it is possible to prevent parasitic capacitance from being generated between the cathode electrode 73 and the anode electrode 74.

As described above, in the present embodiment, the structure as shown in FIGS. 17 to 20 is adopted, and the layout (planar layout, layout pattern, planar shape) of the Schottky junction 53 is formed into an elongated rectangular shape, and the upper part thereof is formed. The plug 63a and the anode electrode 74 connected to the plug 63a are drawn out. Then, an n ⁺ type semiconductor region 44 is provided on both sides of each Schottky junction 53, and the cathode electrode 73 is drawn from the contact hole 62b and the plug 63b having an elongated rectangular layout. Such a layout pattern is repeated to obtain a comb-shaped planar layout as a whole. That is, the anode and the cathode are alternately arranged on one n-type well 27.

In general, the impurity concentration of the n-type well in the vicinity of the Schottky junction of the Schottky barrier diode is about 10 ¹⁵ to 10 ¹⁷ / cm ³ , and the sheet resistance value is considerably higher than that of the source / drain of the MOSFET. When the anode electrode is drawn from the Schottky junction on the surface of the semiconductor substrate and the cathode electrode is drawn from the back side of the semiconductor substrate, the current path is perpendicular to the Schottky junction plane (perpendicular to the main surface of the semiconductor substrate). Therefore, by adjusting the impurity concentration of the n-type well near the anode electrode (shallow region) to such a low level that a Schottky junction can be formed, and increasing the impurity concentration from the deep region of the semiconductor substrate to the back surface of the semiconductor substrate, Parasitic resistance can be suppressed.

  However, in the present embodiment, the Schottky barrier diode elements that constitute the detection circuits 109A and 109B are formed in the same semiconductor device (semiconductor chip 2) together with the LDMOSFET elements that constitute the power amplifier circuits 102A and 102B. Therefore, a back surface electrode (back surface source electrode) 89 serving as a ground (GND) electrode is formed on the entire back surface of the substrate 21 constituting the semiconductor device (semiconductor chip 2). For this reason, the cathode electrode cannot be drawn out from the back surface of the substrate 21 like a general Schottky barrier diode element. For this reason, the cathode electrode of the Schottky barrier diode, like the anode electrode, needs to be drawn out from the surface side of the substrate (semiconductor substrate). In this case, the current path of the Schottky barrier diode is a region close to the Schottky junction surface, and the current path is parallel to the Schottky junction surface (parallel to the main surface of the semiconductor substrate). The parasitic resistance is not reduced even if the impurity concentration on the back surface of the semiconductor substrate is increased. Therefore, in order to reduce the parasitic resistance of the Schottky barrier diode, it is important to shorten the current path.

In this embodiment, a structure as shown in FIGS. 17 to 20 is adopted. That is, by providing a plurality of Schottky electrodes 52 spaced apart from each other on the n-type well 27, a plurality of Schottky junctions 53 (separated from each other) are formed in one n-type well 27, and adjacent to both sides of the Schottky junction 53 (that is, An n ⁺ -type semiconductor region 44 is provided between adjacent Schottky junctions 53 and the cathode electrode 73 is drawn therefrom. A plurality of Schottky junctions 53 are formed in the n-type well 27, and the cathode electrode 73 is drawn from both sides of each Schottky junction 53 (that is, from between adjacent Schottky junctions 53). The current path (current path of the n-type well 27) to the lead-out part or the connection part (n ⁺ type semiconductor region 44) of the electrode 73 can be shortened. For this reason, the parasitic resistance of the Schottky barrier diode can be reduced, the value of the current flowing through the Schottky barrier diode element (that is, the forward current of the Schottky barrier diode element) can be increased, and the loss during high-frequency operation is also reduced. Can be reduced.

  Further, in the present embodiment, by increasing the number of Schottky electrodes 52 (that is, by increasing the number of Schottky junctions 53), the Schottky junction is not lengthened (that is, without increasing the parasitic resistance). The total junction area of the portion 53 (total junction area of a plurality of Schottky junctions 53 connected in parallel) can be increased, and the current (forward current) of the Schottky barrier diode element can be increased efficiently. Can do. Therefore, it is possible to improve the detection sensitivity (detection sensitivity) of the detection circuits 109A and 109B of the SBD detection method using a Schottky barrier diode. For example, since the forward current of a Schottky barrier diode can be increased significantly, loss during rectification is reduced, conversion efficiency from RF (high frequency) to DC (direct current) is increased, and detection sensitivity is improved. Can do. Therefore, the performance of the RF power module 1 can be improved. Compared with the structure of the comparative example shown in FIGS. 15 and 16, the structure of the present embodiment shown in FIGS. 17 to 20 has a Schottky barrier when the total junction area of the Schottky junction is the same. Although the planar dimension (area) of the diode element slightly increases, the effect of increasing the current (forward current) of the Schottky barrier diode by reducing the parasitic resistance is larger. For this reason, the planar dimension (area) of the Schottky barrier diode element necessary for obtaining a desired current value (forward current) can be minimized. Therefore, the area utilization efficiency of the Schottky barrier diode can be improved, and the semiconductor device (semiconductor chip) and the RF power module on which it is mounted can be miniaturized.

  In the present embodiment, the cathode electrode 73 and the anode electrode 74 are formed by the wiring 66 in the same layer, and the cathode electrode 73 and the anode electrode 74 are arranged in a planar layout so as not to intersect. There is no parasitic capacitance (inter-wiring capacitance) between the anode electrode 74 and the anode electrode 74. Thereby, the parasitic capacitance between wirings can be suppressed and the performance of the semiconductor device can be further improved.

  In this embodiment, the Schottky barrier diode element and the LDMOSFET element are formed (integrated) on one substrate 21, but the Schottky barrier diode element formed on the substrate 21 is formed on the substrate 21. The structure is not directly connected to the LDMOSFET element, but is electrically connected to the LDMOSFET element via other passive elements (for example, the capacitive element 87 and the resistance element 33) formed on the substrate 21 by the circuit configuration. Yes. In addition, since the Schottky barrier diode elements used in the detection circuits 109A and 109B of the SBD detection system have different operation purposes and cannot have a common potential, the wiring for each Schottky barrier diode element has a common potential. It is necessary to form the upper portion (surface side) metal wiring of the substrate 21 instead of the back surface electrode of the substrate 21. Therefore, in the present embodiment, the Schottky barrier diode element has both the anode electrode and the cathode electrode of the substrate 21 to be connected to other passive elements (such as a capacitor element and a resistance element) and an active element (such as an LDMOS). It is formed by metal wiring on the top (front side). That is, in the present embodiment, the cathode electrode 73 is drawn from the surface side of the substrate 21 like the anode electrode 74, and both the anode electrode 74 and the cathode electrode 73 are formed by metal wiring on the upper side (surface side) of the substrate 21. ing. As a result, the power amplifier circuits 102A and 102B having LDMOSFET elements and the SBD detection type detection circuits 109A and 109B having Schottky barrier diode elements are formed (integrated) on the same substrate 21 (that is, in the same semiconductor chip 2). Therefore, the RF power module 1 can be downsized.

  FIG. 21 is a graph showing voltage-current characteristics of a Schottky barrier diode. The horizontal axis of the graph of FIG. 21 corresponds to the potential difference between the anode electrode and the cathode electrode, and the vertical axis of the graph of FIG. 21 represents the current density of the forward current (the forward current of the Schottky barrier diode is the total area of the Schottky junction). Corresponding to the value divided by. Note that the horizontal axis and the vertical axis of the graph of FIG. 21 are shown in arbitrary units.

  Further, in the graph of FIG. 21, the “comparative example (50 μm × 100 μm)” corresponding to the structure of FIGS. 15 and 16 and “the present embodiment corresponding to the structure of the present embodiment of FIGS. The “first case (5 μm × 100 μm: 10 parallel)” and the “second case of the present embodiment (10 μm × 100 μm: 5 parallel)” are shown. In the three cases shown in the graph of FIG. 21, the total area of the Schottky junction is the same, and the “comparative example (50 μm × 100 μm)” is a 50 μm × 100 μm Schottky junction 253 by one Schottky electrode 252. In the first case of the present embodiment (5 μm × 100 μm: 10 in parallel), 10 Schottky electrodes 52 form 10 Schottky junctions 53 having 10 μm × 100 μm. Corresponding to the case where the electrodes are formed in parallel, in the “second case of the present embodiment (10 μm × 100 μm: 5 in parallel)”, five 10 μm × 100 μm Schottky junctions 53 are formed by five Schottky electrodes 52. This corresponds to the case where they are formed in parallel.

  As can be seen from the graph of FIG. 21, the structure of the present embodiment shown in FIGS. 17 to 20 is compared with the structure of FIGS. 15 and 16 (corresponding to the “comparative example” of the graph of FIG. 21). In the graph of FIG. 21, “the first case of the present embodiment” and “the second case of the present embodiment”) can shorten the current path of the n-type well 27. The parasitic resistance of the Schottky barrier diode can be reduced, and the forward current of the Schottky barrier diode element can be increased.

  FIG. 22 is a graph showing the correlation between the total area of the Schottky junction of the Schottky barrier diode and the current value. The horizontal axis of the graph of FIG. 22 corresponds to the total area of the Schottky barrier diode of the Schottky barrier diode, and the vertical axis of the graph of FIG. 22 represents the current value (forward current) flowing through the Schottky barrier diode when a predetermined voltage is applied. ). Note that the horizontal axis and the vertical axis of the graph of FIG. 22 are shown in arbitrary units. In the graph of FIG. 22, “comparative example” corresponding to the structure of FIGS. 15 and 16 and “this embodiment” corresponding to the structure of the present embodiment of FIGS. 17 to 20 are shown. Yes. In the case of “comparative example” in the graph of FIG. 22, the total area of the Schottky junction is increased by increasing the area of one Schottky electrode 252, and in the case of “this embodiment” in the graph of FIG. 22, By increasing the number of Schottky electrodes 52 (Schottky junctions 53) connected in parallel, the total area of the Schottky junctions is increased.

  As can be seen from the graph of FIG. 22, in the structure of FIGS. 15 and 16 (corresponding to “Comparative Example” of the graph of FIG. 22), the current passes through the n-type well 27 as the junction area of the Schottky junction increases. Since the distance to be increased (that is, the current path becomes longer) and the parasitic resistance increases, if the junction area of the Schottky junction increases, the current value (forward current) of the Schottky barrier diode element is proportional to the junction area of the Schottky junction. No longer. For this reason, in order to obtain a desired current value (forward current), the junction area of the Schottky junction must be increased.

  On the other hand, in the structure of this embodiment shown in FIGS. 17 to 20 (corresponding to “this embodiment” in the graph of FIG. 22), a plurality of Schottky electrodes 52 are formed on one n-type well 27. (That is, a plurality of Schottky junctions 53 are formed), and the cathode electrode 73 is drawn out from both sides of each Schottky junction 53, so that the distance (current path) through which the current passes through the n-type well 27 can be shortened. it can. Further, the total area of the Schottky junction can be increased without increasing the current path by increasing the number of Schottky electrodes 52 and increasing the number of Schottky junctions 53 instead of increasing the area of each Schottky electrode 52. it can. For this reason, in this embodiment, even if the total area of the Schottky junction is increased, the parasitic resistance does not increase. Therefore, as shown in the graph of FIG. 22, the current value (forward current) of the Schottky barrier diode element is the Schottky barrier. This is proportional to the bonding area of the bonding. Accordingly, the planar dimension (area) of the Schottky barrier diode element necessary to obtain a desired current value (forward current) can be minimized. As a result, it is possible to reduce both the size of the semiconductor device and improve the detection sensitivity (detection sensitivity) of the detection circuits 109A and 109B of the SBD detection method using a Schottky barrier diode. Further, since the current (forward current) of the Schottky barrier diode can be made proportional to the junction area of the Schottky junction, the design of the semiconductor integrated circuit formed on the semiconductor substrate is facilitated.

(Embodiment 2)
FIG. 23 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention, and FIGS. 24 and 25 are plan views thereof. 23 shows a cross section of a region corresponding to the SBD formation region 21B, and substantially corresponds to FIG. 17 of the first embodiment. 24 corresponds to FIG. 23. FIG. 24 and FIG. 25 are plan views of the same region. In FIG. 24, the Schottky electrode 52, contact holes 62a and 62b, The planar layout of the cathode electrode 73 and the anode electrode 74 is shown and the other components are not shown. In FIG. 25, the planar layout of the Schottky electrode 52, the Schottky junction 53, the contact hole 62b, and the cathode electrode 73 is shown. The other components are not shown. FIG. 24 is a plan view, but hatched for easy understanding.

  As in the first embodiment, the cathode electrode 73 and the anode electrode 74 have a comb shape. However, in this embodiment, as shown in FIGS. The plurality of electrode portions 73 a and the plurality of electrode portions 74 a of the comb-shaped anode electrode 74 are orthogonal to each other, and the anode electrode 74 is more than the cathode electrode 73 so that the cathode electrode 73 and the anode electrode 74 are not in contact with each other. Is also formed by one upper layer wiring (wiring 85). That is, the cathode electrode 73 and the anode electrode 74 are not formed in the same layer, the cathode electrode 73 is formed by the first layer wiring, and the anode electrode 74 is formed by the second layer wiring.

The plurality of electrode portions 73a of the cathode electrode 73 are connected to the plurality of n ⁺ -type semiconductor regions 44 via the plurality of conductor portions (plugs 63b) filling the plurality of contact holes 62b, and the plurality of electrode portions 74a of the anode electrode 74 are connected. Are connected to the plurality of Schottky electrodes 52 via a plurality of conductor portions (plugs 63a) filling the plurality of contact holes 62a, but the anode electrode 74 is formed by a wiring one layer higher than the cathode electrode 73. Therefore, the contact hole 62a for connecting the anode electrode 74 and the Schottky electrode 52 is formed so as to penetrate a plurality of interlayer insulating films (that is, the insulating films 61, 64, 81). Further, the extending direction of the electrode portion 74a of the anode electrode 74 and the extending direction of the Schottky electrode 52 are orthogonal to each other, and each electrode portion 74a of the anode electrode 74 is in a region intersecting with the Schottky electrode 52 in a plane. The contact hole 62a is connected to the Schottky electrode 52 through a conductor portion (plug 63a). Therefore, in the first embodiment, each electrode portion 74a of the anode electrode 74 is connected to one Schottky electrode 52 via a conductor portion (plug 63a) filling one contact hole 62a. Then, each electrode portion 74a of the anode electrode 74 is connected to the plurality of Schottky electrodes 52 via a plurality of conductor portions (plugs 63a) filling the plurality of contact holes 62a. Since other configurations are substantially the same as those of the first embodiment, description thereof is omitted here. For example, the planar layout of the n ⁺ type semiconductor region 44, the p ⁺ type guard ring layer 47, the Schottky electrode 52, the Schottky junction 53, the contact hole 62b, the plug 63b, and the cathode electrode 73 is substantially the same as in the first embodiment. can do.

  Also in the present embodiment, substantially the same effect as in the first embodiment can be obtained. For example, the total junction area of the Schottky junction can be increased without increasing the parasitic resistance, and the forward current of the Schottky barrier diode element can be increased efficiently. For this reason, the detection sensitivity (detection sensitivity) of the detection circuits 109A and 109B of the SBD detection method using the Schottky barrier diode can be improved, and the performance of the RF power module 1 can be improved. Further, the area utilization efficiency of the Schottky barrier diode can be improved, and the semiconductor device can be miniaturized.

(Embodiment 3)
FIG. 26 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention, and FIGS. 27 and 28 are fragmentary plan views thereof. 26 shows a cross section of a region corresponding to the SBD formation region 21B, and substantially corresponds to FIG. 17 of the first embodiment. Further, the cross section taken along line EE in FIG. 27 substantially corresponds to FIG. 27 and FIG. 28 are plan views of the same region. FIG. 27 shows the planar layout of the Schottky electrode 52, the contact holes 62a and 62b, the cathode electrode 73, and the anode electrode 74, and other components. In FIG. 28, the planar layout of the Schottky junction 53, the Schottky electrode 52, the contact hole 62b, and the cathode electrode 73 is shown, and the other components are not shown. FIG. 27 is a plan view, but hatched for easy understanding.

The cathode electrode 73 of this embodiment includes an electrode portion 73a to be connected to the n ⁺ -type semiconductor region 44 via the plug 63b and extend (position) on the respective n ⁺ -type semiconductor region 44, a plurality of electrode portions It has the connection part 73b which connects one edge part of 73a, and the connection part 73c which connects area | regions other than the edge part of several electrode part 73a further. The connecting portions 73b and 73c are substantially orthogonal to the plurality of electrode portions 73a. The plurality of electrode portions 73a of the cathode electrode 77 electrically connected to the plurality of n ⁺ -type semiconductor regions 44 through the conductor portions (plugs 63b) filling the contact holes 62b are not only connected by the connecting portions 73b but also by the connecting portions 73c. Are connected, the current path of the cathode electrode 73 can be shortened, and current loss and delay can be further suppressed.

Further, the Schottky electrode 52 is divided into a plurality of portions between the adjacent n ⁺ type semiconductor regions 44. That is, the plurality of Schottky electrodes 52 are arranged side by side in the vertical and horizontal directions. On the region between the plurality of Schottky electrodes 52, the electrode portion 73a extends in the vertical direction of FIG. 28, and on the region between the plurality of Schottky electrodes 52, the electrode portion 73c extends in the horizontal direction of FIG. The layout is such that the Schottky electrode 52 does not overlap the cathode electrode 73 in plan view. Thereby, the parasitic capacitance between the Schottky electrode 52 and the cathode electrode 73 can be reduced. A p ⁺ -type guard ring layer 47 is formed so as to surround the Schottky junction 53 formed between each Schottky electrode 52 and the n-type well.

  Further, the anode electrode 74 of the present embodiment has a comb shape similar to that of the first embodiment. The plurality of electrode portions 74a of the comb-shaped anode electrode 74 and the connecting portion 73c of the cathode electrode 73 are orthogonal to each other, and the anode electrode 74 is a cathode electrode so that the cathode electrode 73 and the anode electrode 74 are not in contact with each other. It is formed by a wiring (wiring 85) one layer higher than 73. That is, the cathode electrode 73 and the anode electrode 74 are not formed in the same layer, the cathode electrode 73 is formed by the first layer wiring, and the anode electrode 74 is formed by the second layer wiring.

The plurality of electrode portions 73a of the cathode electrode 73 are connected to the plurality of n ⁺ -type semiconductor regions 44 via the plurality of conductor portions (plugs 63b) filling the plurality of contact holes 62b, and the plurality of electrode portions 74a of the anode electrode 74 are connected. Are connected to the plurality of Schottky electrodes 52 via a plurality of conductor portions (plugs 63a) filling the plurality of contact holes 62a, but the anode electrode 74 is formed by a wiring one layer higher than the cathode electrode 73. Therefore, the contact hole 62a for connecting the anode electrode 74 and the Schottky electrode 52 is formed so as to penetrate a plurality of interlayer insulating films (that is, the insulating films 61, 64, 81). Since other configurations are substantially the same as those of the first embodiment, description thereof is omitted here. For example, the planar layout of the n ⁺ -type semiconductor region 44, the contact hole 62b, the plug 63b, and the anode electrode 74 can be made substantially the same as in the first embodiment.

  Also in the present embodiment, substantially the same effect as in the first embodiment can be obtained. For example, the total junction area of the Schottky junction can be increased without increasing the parasitic resistance, and the forward current of the Schottky barrier diode element can be increased efficiently. Therefore, the detection sensitivity (detection sensitivity) of the detection circuits 109A and 109B of the SBD detection system using the Schottky barrier diode can be improved, and the performance of the RF power module 1 can be improved. Further, the area utilization efficiency of the Schottky barrier diode can be improved, and the semiconductor device can be miniaturized.

(Embodiment 4)
FIGS. 29 to 32 are cross-sectional views of the main part during the manufacturing process of the semiconductor device according to another embodiment of the present invention, showing the same region as in FIGS. 6 to 14 in the first embodiment. ing. Since the manufacturing process up to FIG. 7 is the same as that of the first embodiment, the description thereof is omitted here, and the manufacturing process following FIG. 7 will be described.

  After the structure of FIG. 7 is obtained in the same manner as in the first embodiment, an insulating film 28a for forming a gate insulating film is formed in the same manner as in the first embodiment, as shown in FIG. Then, a gate electrode 32 is formed on the insulating film 28a in the LDMOSFET formation region 21A. In this embodiment, the gate electrode 32 is doped with an n-type polycrystalline silicon film (phosphorus (P) or other n-type impurity). (Introduced polycrystalline silicon film) 29. For example, an n-type polycrystalline silicon film 29 is deposited on the main surface of the epitaxial layer 22 (that is, on the insulating film 28a) by CVD or the like, and then (without forming the metal silicide film 30), an n-type polycrystalline silicon film is formed. After depositing an insulating film (cap insulating film) 31 made of a silicon oxide film or the like by CVD or the like on 29, the insulating film 31 and the n-type polycrystalline silicon film 29 are patterned using a photolithography technique and a dry etching technique. . Thus, a gate electrode 32 made of the patterned n-type polycrystalline silicon film 29 is formed on the surface of the p-type well 26 in the LDMOSFET formation region 21A via the insulating film 28a. The insulating film 28a under the gate electrode 32 becomes the gate insulating film 28 of the LDMOSFET. Further, the insulating film 31 and the n-type polycrystalline silicon film 29 are left in the patterning step so that the insulating film 31 and a part of the n-type polycrystalline silicon film 29 are left on the element isolation region 25 in the resistance element forming region 21D. Then, the resistance element 33 made of the n-type polycrystalline silicon film 29 remaining (patterned) remaining in the resistance element formation region 21D is formed. Therefore, in the present embodiment, the gate electrode 32 and the resistance element 33 are formed by the n-type polycrystalline silicon film 29 in the same layer.

Thereafter, in the same manner as in the first embodiment (the same steps as in FIGS. 9 to 11 are performed), the n ⁻ type offset drain region 35, the n ⁻ type source region 36, the p type halo region 37, and the sidewall spacer. 38, 38a, n-type offset drain region 39, n ⁺ -type drain region 42, n ⁺ -type source region 43, p ⁺ -type semiconductor region 46 and p ⁺ -type guard ring layer (p ⁺ -type semiconductor region) 47 are formed.

Next, in the present embodiment, as shown in FIG. 30, the upper part of the SBD formation region 21B in the Schottky junction formation region, the n-type offset drain region 39, the n ⁺ -type drain region 42, the side of the LDMOSFET formation region 21A Openings are formed in the upper portion of the wall spacer 38, the gate electrode 32, the n ⁺ type source region 43 and the p ⁺ type semiconductor region 46 (p type punching layer 24) and the upper ends of both ends of the resistance element 33 in the resistance element forming region 21D. The main surface of the epitaxial layer 22 is etched using an etching mask layer (for example, a photoresist pattern, not shown) having an insulating film (for example, the insulating film 28a or the insulating film 31) on the main surface of the epitaxial layer 22. Selectively removing the Schottky junction formation region of the n-type well 27 in the SBD formation region 21B, and the resistance element formation region And both end portions of the resistor element 33 of 21D, n-type offset drain region 39 of the LDMOSFET formation region 21A, n ⁺ -type drain region 42, gate electrode 32, n ⁺ -type source region 43 and p ⁺ -type semiconductor region 46 (p-type punching The surface with layer 24) is exposed. At this time, at least a part of the sidewall spacer 38 is left.

Then, a metal film such as a cobalt (Co) film is deposited on the substrate 21 (epitaxial layer 22) and subjected to heat treatment, thereby forming a Schottky junction formation region and a resistance element formation region of the n-type well 27 in the SBD formation region 21B. Both end portions of the resistance element 33 of 21D, the n-type offset drain region 39, the n ⁺ -type drain region 42, the gate electrode 32, the n ⁺ -type source region 43 and the p ⁺ -type semiconductor region 46 (p-type punching layer) of the LDMOSFET formation region 21A 24) the silicon (Si) element and the metal element (for example, Co) in the metal film are reacted. Thus, as shown in FIG. 31, the Schottky junction formation planned region of the n-type well 27 in the SBD formation region 21B, both end portions of the resistance element 33 in the resistance element formation region 21D, and the n-type offset drain region in the LDMOSFET formation region 21A 39, a metal silicide film 91 (for example, a cobalt silicide film) on the surface (upper part) of the n ⁺ type drain region 42, the gate electrode 32, the n ⁺ type source region 43, and the p ⁺ type semiconductor region 46 (p type punching layer 24). Can be selectively formed. Thereafter, unreacted metal film (for example, cobalt film) is removed. FIG. 31 shows a state in which the metal silicide film 91 is formed and the unreacted metal film is removed. The surface (upper part) and resistance of the n-type offset drain region 39, n ⁺ -type drain region 42, gate electrode 32, n ⁺ -type source region 43 and p ⁺ -type semiconductor region 46 (p-type punching layer 24) in the LDMOSFET formation region 21A By forming the metal silicide film 91 on the surface (upper part) of both ends of the resistance element 33 in the element formation region 21D, the diffusion resistance and contact resistance of these regions can be reduced. In addition, a Schottky electrode (metal electrode, anode region, anode electrode) 52 of the Schottky diode element is formed by the metal silicide film 91 formed on the surface (upper part) of the Schottky junction formation region of the n-type well 27 of the SBD formation region 21B. It is formed. Also in the present embodiment, a plurality of Schottky electrodes 52 are formed on the n-type well 27 as in the first embodiment. The Schottky electrode 52 made of the metal silicide film 91 is in contact with the n-type well 27 in the region where the Schottky junction is to be formed, and a Schottky junction is formed between the Schottky electrode 52 and the n-type well 27. The end region of the Schottky electrode 52 made of the metal silicide film 91 preferably overlaps with the p ⁺ -type guard ring layer 47 serving as a guard ring. As described above, in the present embodiment, the Schottky electrode 52 of the Schottky diode element formed in the SBD formation region 21B is made of the metal silicide film 91 such as a cobalt silicide film, for example, and a salicide (Salicide: Self Aligned Silicide) process. Can be used.

In the present embodiment, using the salicide process as described above, the n-type offset drain region 39, the n ⁺ -type drain region 42, the gate electrode 32, the n ⁺ -type source region 43 and the p ⁺ -type semiconductor in the LDMOSFET formation region 21A. A metal silicide film 91 is formed on the surface (upper part) of the region 46 (p-type punching layer 24), and from the metal silicide film 91 on the surface (upper part) of the region where the Schottky junction is to be formed in the n-type well 27 in the SBD formation region 21B. A Schottky electrode 52 is formed. Accordingly, the metal silicide film on the n-type offset drain region 39, the n ⁺ -type drain region 42, the gate electrode 32, the n ⁺ -type source region 43 and the p ⁺ -type semiconductor region 46 (p-type punching layer 24) in the LDMOSFET formation region 21A. 91 and the Schottky electrode 52 in the SBD formation region 21B are made of the same kind of metal silicide (for example, cobalt silicide). Therefore, the Schottky electrode 52 in the SBD formation region 21B can be formed in the same process as the process of forming the metal silicide film 91 on the source, drain and gate electrode 32 of the LDMOSFET. For this reason, the number of manufacturing steps can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

  Subsequent manufacturing steps are substantially the same as those in the first embodiment. That is, as shown in FIG. 32, as in the first embodiment, an insulating film 61 is formed on the substrate 21, a contact hole 62 is formed in the insulating film 61, and a plug 63 is formed in the contact hole 62. Form. Then, an insulating film 64 is formed on the insulating film 61 in which the plug 63 is embedded, a wiring groove 65 is formed in the insulating film 64, and a wiring (first layer wiring) 66 is formed in the wiring groove 65. By the wiring 66, a source electrode 71, a drain electrode 72, a cathode electrode 73, an anode electrode 74, and a lower electrode 75 are formed. The anode electrode 74 is electrically connected to the plurality of Schottky electrodes 52 made of the metal silicide film 91 through the plurality of plugs 63.

  Then, similarly to the first embodiment, an insulating film 81 is formed on the insulating film 64 in which the wiring 66 is embedded, an opening 82 is formed in the insulating film 81, and an insulating film 83 as a capacitor insulating film is formed. Then, an opening 84 is formed in the insulating film 81, and wiring 85 is formed on the insulating film 81 so as to fill the openings 82 and 84. An upper electrode 86 of the capacitor is formed by the wiring 85 formed on the lower electrode 75 via the insulating film 83. Thereafter, a surface protective film 88 is formed, and a back electrode 89 is formed on the back surface of the substrate 21.

  As described above, in the semiconductor device of this embodiment, the Schottky electrode 52 of the Schottky barrier diode element is formed by the metal silicide film 91 in the same layer as the metal silicide film 91 on the source, drain, and gate electrode 32 of the LDMOSFET. Has substantially the same configuration as the semiconductor device of the first embodiment. Also in the present embodiment, substantially the same effect as in the first embodiment can be obtained. Further, in the present embodiment, the Schottky electrode 52 made of the metal film 91 is formed in the SBD formation region 21B in the same process as the process (salicide process) of forming the metal silicide film 91 on the source, drain and gate electrodes 32 of the LDMOSFET. Can be formed. For this reason, the number of manufacturing steps can be reduced, and the manufacturing cost of the semiconductor device can be further reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for application to a semiconductor device used in a high-frequency power amplifier for a mobile phone.

1 is a circuit block diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a Schottky barrier diode detection type detection circuit. It is a top view which shows the structure of the RF power module of a comparative example. It is a top view which shows the structure of RF power module which is one embodiment of this invention. It is sectional drawing of the RF power module of FIG. It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; It is principal part sectional drawing which shows the structure of the Schottky barrier diode element in the semiconductor device of a comparative example. FIG. 16 is a plan view of a principal part of a Schottky barrier diode element in the semiconductor device of FIG. 15. It is principal part sectional drawing which shows the structure of the Schottky barrier diode element in the semiconductor device which is one embodiment of this invention. FIG. 18 is a plan view of a principal part of a Schottky barrier diode element in the semiconductor device of FIG. 17. FIG. 18 is a plan view of a principal part of a Schottky barrier diode element in the semiconductor device of FIG. 17. FIG. 18 is a plan view of a principal part of a Schottky barrier diode element in the semiconductor device of FIG. 17. It is a graph which shows the voltage-current characteristic of a Schottky barrier diode. It is a graph which shows the correlation with the total area of a Schottky junction of a Schottky barrier diode, and an electric current value. It is principal part sectional drawing of the semiconductor device which is other embodiment of this invention. FIG. 24 is a main part plan view of the semiconductor device in FIG. 23; FIG. 24 is a main part plan view of the semiconductor device in FIG. 23; It is principal part sectional drawing of the semiconductor device which is other embodiment of this invention. FIG. 27 is a main part plan view of the semiconductor device in FIG. 26; FIG. 27 is a main part plan view of the semiconductor device in FIG. 26; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; It is a circuit diagram which shows the detection circuit of MOSFET detection system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 RF power module 2 Semiconductor chip 2a electrode 2b Back surface electrode 3 Wiring board 3a Upper surface 3b Lower surface 4 Passive component 5 Sealing resin 8 Bonding wire 11 Insulating layer 12a Substrate side terminal 12b External connection terminal 12c Reference potential supply terminal 13 Via hole 13a Via hole 14 Depression 14a Conductor layer 15 Solder 17 Solder 21 Substrate 21A LDMOSFET formation region 21B
21C Capacitor formation region 21D Resistance element formation region 22 Epitaxial layer 23 Groove 24 P-type punching layer 25 Element isolation region 26 P-type well 27 N-type well 28 Gate insulating film 28a Insulating film 29 n-type polycrystalline silicon film 30 Metal silicide film 31 Insulating film 32 Gate electrode 33 Resistance element 33a n-type polycrystalline silicon film 34 insulating film 35 n ⁻ type offset drain region 36 n ⁻ type source region 37 p type halo region 38 side wall spacer 38a side wall spacer 39 n type offset drain region 42 n ⁺ -type drain region 43 n ⁺ -type source region 44 n ⁺ -type semiconductor region 46 p ⁺ -type semiconductor region 47 p ⁺ -type guard ring layer 52 Schottky electrode 53 Schottky junction 61 insulating film 62 contact holes 62a contact hole 62b contact hole 3 Plug 63a Plug 63b Plug 64 Insulating film 65 Wiring groove 66 Wiring 71 Source electrode 72 Drain electrode 73 Cathode electrode 73a Electrode part 73b Connecting part 74 Anode electrode 74a Electrode part 74b Connecting part 75 Lower electrode 81 Insulating film 82 Opening part 83 Insulating film 84 Opening 85 Wiring 86 Upper electrode 87 Capacitor element 88 Surface protection film 89 Back surface electrode 91 Metal silicide films 102A, 102B Power amplification circuits 102A1, 102A2, 102A3 Amplification stages 102B1, 102B2, 102B3 Amplification stages 103A, 103B Bias circuits 104A, 104B Power supply circuit 105a, 105b Input terminal 106A, 106B Matching circuit 107a, 107b Output terminal 108A, 108B Matching circuit 109A, 109B Detection circuit 110a, 110b Bias control signal input terminal 11 DESCRIPTION OF SYMBOLS 1a, 111b Output terminal 121 Schottky barrier diode element 122 Capacitance element 123 Resistance element 201 RF power module 202 Semiconductor chip 203 Wiring board 204 Passive component 204a Chip SBD
205 Sealing resin 208 Bonding wire 209A Detection circuit 209B Detection circuit 212 Substrate side terminal 244 n ⁺ type semiconductor region 247 p ⁺ type guard ring layer 250 Current path 252 Schottky electrode 253 Schottky junction 273 Cathode electrode 274 Anode electrode 285 Lead electrode

Claims (19)

A semiconductor substrate;
A MISFET formed on the first main surface of the semiconductor substrate;
A Schottky diode formed on the first main surface of the semiconductor substrate;
A passive element other than the Schottky diode formed on the first main surface of the semiconductor substrate;
A back electrode formed on a second main surface opposite to the first main surface of the semiconductor substrate and electrically connected to a source region of the MISFET;
A semiconductor device, wherein an anode electrode or a cathode electrode of the Schottky diode is electrically connected to the passive element. The semiconductor device according to claim 1,
A semiconductor device, wherein an anode electrode and a cathode electrode of the Schottky diode are formed on the first main surface side of the semiconductor substrate. The semiconductor device according to claim 2,
The Schottky diode is
A first semiconductor region of a first conductivity type formed on the first main surface of the semiconductor substrate;
A plurality of Schottky electrodes formed on the first semiconductor region, each forming a Schottky junction with the first semiconductor region;
The semiconductor device further includes an interlayer insulating film formed on the Schottky electrode,
Having an anode electrode and a cathode electrode of the Schottky diode formed on the interlayer insulating film;
The plurality of Schottky electrodes are electrically connected to each other via the anode electrode,
The semiconductor device, wherein the cathode electrode is electrically connected between a plurality of Schottky junctions formed by the plurality of Schottky electrodes and the first semiconductor region. The semiconductor device according to claim 3.
A first conductivity type second semiconductor region having an impurity concentration higher than that of the first semiconductor region between the plurality of Schottky junctions formed by the plurality of Schottky electrodes and the first semiconductor region;
The semiconductor device, wherein the cathode electrode is electrically connected to the second semiconductor region. The semiconductor device according to claim 3.
The semiconductor device, wherein the anode electrode and the cathode electrode have a comb shape. The semiconductor device according to claim 3.
The semiconductor device, wherein the anode electrode and the cathode electrode are formed of the same layer of wiring and do not cross each other. The semiconductor device according to claim 3.
A first metal silicide film formed on the source region and the drain region of the MISFET;
The plurality of Schottky electrodes are made of the same type of metal silicide as the first metal silicide film. The semiconductor device according to claim 1,
The semiconductor device, wherein the MISFET is an LDMOSFET. The semiconductor device according to claim 1,
The semiconductor device is mounted on a mobile phone,
The semiconductor device, wherein the Schottky diode is used in an output detection circuit of an amplifier circuit formed by the MISFET. The semiconductor device according to claim 1,
A groove formed from the first main surface of the semiconductor substrate;
A punched layer formed in the groove;
Further comprising
The semiconductor device according to claim 1, wherein the source region of the MISFET is electrically connected to the back electrode through the punching layer. The semiconductor device according to claim 1,
A first semiconductor region of a first conductivity type formed on the first main surface of the semiconductor substrate;
A plurality of second semiconductor regions of a first conductivity type having an impurity concentration higher than that of the first semiconductor region formed in the first semiconductor region;
A plurality of Schottky electrodes formed on a first semiconductor region between the plurality of second semiconductor regions, each forming a Schottky junction with the first semiconductor region;
Further comprising
The plurality of Schottky electrodes are electrically connected to each other via an anode electrode of the Schottky diode;
The plurality of second semiconductor regions are electrically connected to each other via a cathode electrode of the Schottky diode. The semiconductor device according to claim 11.
An interlayer insulating film formed on the first main surface of the semiconductor substrate so as to cover the MISFET and the plurality of Schottky electrodes;
A plurality of first openings formed in the interlayer insulating film and exposing the plurality of Schottky electrodes at the bottom;
A plurality of first conductor portions filling the plurality of first openings;
A plurality of second openings formed in the interlayer insulating film and exposing the plurality of second semiconductor regions at the bottom;
A plurality of second conductor portions filling the plurality of second openings;
Further comprising
The anode electrode and the cathode electrode are formed on the interlayer insulating film,
The plurality of Schottky electrodes are electrically connected to each other via the plurality of first conductor portions and the anode electrode,
The plurality of second semiconductor regions are electrically connected to each other via the plurality of second conductor portions and the cathode electrode. A wiring board;
A semiconductor chip mounted on the first main surface of the wiring board and having a back electrode on its back surface;
Have
In the semiconductor chip, a MISFET and a Schottky diode are formed,
The semiconductor device according to claim 1, wherein the back electrode of the semiconductor chip is electrically connected to a source region of the MISFET. The semiconductor device according to claim 13.
The semiconductor device, wherein the MISFET is an LDMOSFET. The semiconductor device according to claim 13.
A semiconductor device, wherein no Schottky diode element other than the Schottky diode formed on the semiconductor chip is mounted on the first main surface of the wiring board. The semiconductor device according to claim 13.
In the semiconductor chip, a power amplifier circuit and a detection circuit for detecting the output of the power amplifier circuit are formed,
The semiconductor device according to claim 1, wherein the MISFET is used in the power amplifier circuit, and the Schottky diode is used in the detection circuit. The semiconductor device according to claim 13.
The semiconductor device is a power amplifying device mounted on a mobile phone. A method for manufacturing a semiconductor device, comprising: a MISFET comprising a source region, a drain region and a gate electrode formed on a first main surface of a semiconductor substrate; and a Schottky diode formed on the first main surface of the semiconductor substrate,
(A) preparing the semiconductor substrate;
(B) forming a MISFET on the first main surface of the semiconductor substrate; forming a first conductive type first semiconductor region on the first main surface of the semiconductor substrate; and forming the first semiconductor region on the first semiconductor region. Forming a plurality of second semiconductor regions of the first conductivity type having an impurity concentration higher than that of the semiconductor region;
(C) forming a plurality of Schottky electrodes on the first semiconductor region between the plurality of second semiconductor regions, each forming a Schottky junction with the first semiconductor region;
(D) forming an interlayer insulating film on the first main surface of the semiconductor substrate so as to cover the MISFET and the plurality of Schottky electrodes;
(E) forming a plurality of first openings that expose the Schottky electrode at the bottom and a plurality of second openings that expose the second semiconductor region at the bottom, respectively, in the interlayer insulating film; When,
(F) filling the plurality of first openings and the plurality of second openings with a conductor, forming a wiring on the interlayer insulating film, and electrically connecting the plurality of Schottky electrodes to each other; Electrically connecting the second semiconductor regions to each other;
(G) forming a back electrode electrically connected to the source region of the MISFET on a second main surface opposite to the first main surface of the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 18.
The plurality of Schottky electrodes are made of metal silicide,
In the step (c), a metal silicide film of the same type as the metal silicide constituting the plurality of Schottky electrodes is also formed on the surfaces of the source region and the drain region of the MISFET. Method.

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