JP2006010897A - Display apparatus and driving method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus and a driving method for the same capable of increasing image quality and long term reliability of an electrooptical element by incorporating a function which reduces influence of switching noise of a switching element into a pixel. <P>SOLUTION: In an active matrix type display apparatus in which pixels 20 including a liquid crystal cell 22 are arranged in a matrix form, a write-in voltage compensation transistor 24 is connected and provided between a holding capacitance 23 and a fixed potential Vk. After writing of input data Vdata on the pixels is started by turning on a data write-in transistor 21 during an ON state of the write-in voltage compensation transistor 24 , the write-in voltage compensation transistor 24 is turned off and subsequently, the data write-in transistor 21 is turned off and thereafter, the write-in voltage compensation transistor 24 is turned on. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device and a driving method of the display device, and more particularly to a display device in which pixels having switching elements and capacitive elements in addition to electro-optical elements are two-dimensionally arranged in a matrix and a driving method of the display device.

  A pixel including an electro-optic element at each intersection between a data line group wired in parallel and a gate line group electrically insulated from the data line group and wired in parallel perpendicular to the data line group Are arranged in a matrix, for example, a liquid crystal display device using a liquid crystal cell as an electro-optical element, each pixel is composed of a switching element and a capacitor element for writing data.

  FIG. 5 shows a circuit configuration of a general pixel when a MOS transistor is used as a switching element. In this pixel 100, switching noise mixed through the parasitic capacitances Ca and Cb of the transistor 101 when the data write transistor Q 101 is turned on / off, or a channel-gate capacitance due to the data write transistor 101 being turned on / off. Under the influence of switching noise generated by the effect of charge / discharge of charge on Cc, the potential Vwrite due to the charge accumulated in the storage capacitor 103 is the input write voltage (or expected write voltage) Vdata. It will be different. In addition, since the load capacitance of the gate line 104 varies depending on the distance from the driving circuit to each pixel 100, the slope of the gate voltage of the data write transistor 101 varies.

  Due to these effects, there is a problem that a difference occurs between an image (or video) that is actually displayed and an image (or video) that is actually output, and display quality deteriorates. Further, when the counter electrode potential (counter substrate potential) Vcom of the liquid crystal cell 102 is set to a fixed potential, the voltage difference due to the effect of switching noise becomes asymmetric with respect to the counter electrode potential Vcom. As a result, the display quality deteriorates. For this reason, conventionally, measures such as adjusting the counter electrode potential (fixed potential) Vcom are taken to reduce the influence of switching noise of the data write transistor Q101 (see, for example, Patent Document 1).

JP-A-5-204337

  However, in the conventional technique for adjusting the counter electrode potential Vcom, since the adjustment must be performed manually, there is a problem that it is difficult to reliably reduce the influence of the switching noise of the data write transistor Q101.

  Accordingly, the present invention provides a display device and a display device driving method capable of improving image quality and improving long-term reliability of an electro-optic element by providing a pixel with a function of reducing the influence of switching noise of the switching element. The purpose is to provide.

  In order to achieve the above object, in the present invention, an electro-optical element, a first switching element in which one main electrode is connected to a data line and the other main electrode is connected to one end of the electro-optical element, A capacitive element having one end connected to a connection node between the first switching element and the electro-optic element, one main electrode connected to the other end of the capacitive element, and the other main electrode connected to a fixed potential. In a display device in which pixels including two switching elements are arranged in a matrix, the first switching element is turned on while the second switching element is on, and writing of input data to the pixel is started. Then, the second switching element is turned off, and then the first switching element is turned off, and then the second switching element is turned on. That.

  In the above configuration, the first switching element is turned on to start writing input data to the pixel. At this time, the second switching element is in an OFF state. After the input data is written, the second switching element is turned off. As a result, the connection node B between the other end of the capacitive element and one main electrode of the second switching element is in a floating state. Thereafter, the first switching element is turned off. At this time, if it is assumed that the write voltage to the capacitor element is reduced by ΔV from the input potential due to the influence of the switching noise of the first switching element, the connection node B is in a floating state, and thus the law of charge conservation. Accordingly, the potential of the connection node B also decreases by ΔV following the write voltage. Thereafter, the second switching element is turned on, and the writing potential at the connection node A between the first switching element and the electro-optic element is raised by ΔV to become the input potential.

  As a result, the potential change of the connection node A due to the influence of the switching noise of the first switching element is canceled by the on-off-on-on operation of the second switching element, and thus occurs when data is written to the capacitor element. The influence of the switching noise of the first switching element can be reduced, and the difference in the influence of the switching noise due to the difference in the slope of the voltage applied to the gate line caused by the distance between the driving means and the pixel can be reduced in the same manner. As a result, the write voltage to the actual capacitive element can be made closer to the input potential or the expected potential, so the absolute value of the difference between the average value of the write voltage and the counter electrode potential in the same display area And the relative difference in write voltage in the same display area can be reduced.

  According to the present invention, it is possible to reduce the absolute value of the difference between the average value of the writing voltage in the same display area and the counter electrode potential and the relative difference of the writing voltage in the same display area. The long-term reliability of the element can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of a display device to which the present invention is applied. Here, a dot sequential drive type active matrix liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel will be described as an example. However, the present invention is not limited to application to a dot sequential driving method in which image data is written in units of pixels, but can also be applied to a line sequential driving method in which image data is written in units of rows.

  As is clear from FIG. 1, the active matrix liquid crystal display device according to this application example has a pixel array unit 11, a vertical drive circuit 12, and a horizontal drive circuit 13. In the pixel array unit 11, pixels 20 including liquid crystal cells that are electro-optical elements are two-dimensionally arranged in a matrix on a first semiconductor substrate or an insulating substrate (not shown). In this arrangement, gate line groups 14-1 to 14-m are wired for each row, and data line groups 15-1 to 15-n are wired for each column. In other words, the data line groups 15-1 to 15-n are wired in parallel, and the gate line groups 14-1 to 14-m are electrically connected to the data line groups 15-1 to 15-n. Insulated and orthogonally wired in parallel, the pixels 20 are arranged in a matrix at each intersection of the gate line groups 14-1 to 14-m and the data line groups 15-1 to 15-n. Yes.

  A vertical drive circuit (gate line drive circuit) 12 for driving the gate line groups 14-1 to 14-m around the pixel array unit 11 together with the pixel array unit 11 on the first semiconductor substrate or the insulating substrate. And a horizontal drive circuit (data line drive circuit) 13 for driving the data line groups 15-1 to 15-n are arranged. A second semiconductor substrate or insulating substrate (opposite substrate) is disposed opposite to the first semiconductor substrate or insulating substrate with a predetermined gap, and a liquid crystal material (liquid crystal layer) is sealed between the two substrates. Thus, a liquid crystal panel is formed.

  The vertical drive circuit 12 is disposed, for example, on the left side of the pixel array unit 11. Here, the configuration in which the vertical drive circuit 12 is disposed on the left side of the pixel array unit 11 is described as an example, but the vertical drive circuit 12 is disposed on the right side of the pixel array unit 11 or on both the left and right sides of the pixel array unit 11. It is also possible to adopt a configuration in which The vertical drive circuit 12 includes a shift register, a buffer circuit, and the like, and is synchronized with a vertical clock pulse VCK (generally, vertical clock pulses VCK and VCKX having phases opposite to each other) when a vertical start pulse VST is given. Thus, the vertical scanning pulses φV1 to φVm are sequentially output and given to the gate line groups 14-1 to 14-m of the pixel array unit 11, so that the pixels 20 are sequentially selected in units of rows.

  The horizontal drive circuit 13 is configured to include, for example, a horizontal scanning circuit 131 and horizontal sampling switches 132-1 to 132-n. The horizontal scanning circuit 131 includes a shift register and starts a shift operation in response to a horizontal start pulse HST. The horizontal start pulse HST is converted into a horizontal clock pulse HCK (generally, horizontal clock pulses HCK having opposite phases to each other). , HCKX) and sequentially shifting the transfer pulses of each transfer stage as horizontal sampling pulses φH1 to φHn.

  One end of each of the horizontal sampling switches 132-1 to 132-n is commonly connected to the signal input line 16, and each other end is connected to each one end of the data line group 15-1 to 15-n of the pixel array unit 11. Has been. These horizontal sampling switches 132-1 to 132-n are turned on in response to horizontal sampling pulses φH1 to φHn sequentially output from the horizontal scanning circuit 131, whereby analog signals input via the signal input line 16 are input. The video signal Vsig is sequentially sampled and supplied to each of the data line groups 15-1 to 15-n.

  The analog video signal Vsig input through the signal input line 16 is a signal whose polarity is inverted, for example, every 1H (H is a horizontal scanning period) with reference to the counter electrode potential Vcom. As described above, the driving method for inverting the polarity of the analog video signal Vsig every 1H is called a 1H inversion (line inversion) driving method. In addition to the 1H inversion driving method, a driving method for inverting the polarity of the analog video signal Vsig for each screen (field / frame) may be employed.

  In the active matrix liquid crystal display device having the above configuration, the present invention is characterized by the circuit configuration of a pixel (pixel circuit) 20 including a liquid crystal cell. Hereinafter, a specific circuit configuration and circuit operation of the pixel 20 will be described.

  FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel (pixel circuit) 20. Here, a case where a MOS transistor is used as the switching element is shown as an example. In FIG. 2, the pixel 20 has a configuration including a write voltage compensation transistor 24, which is a second switching element, in addition to a data write transistor 21, a liquid crystal cell 22, and a storage capacitor 23, which are first switching elements. .

  The data write transistor 21 has a gate electrode connected to the gate line 14 (14-1 to 14-m) and one main electrode connected to the data line 15 (15-1 to 15-n). A gate voltage Vg1 (corresponding to the vertical scanning pulses φV1 to φVm in FIG. 1) is applied to the gate electrode of the data write transistor 21 through the gate line 14 in units of rows.

  The other main electrode of the data writing transistor 21 is connected to the pixel electrode of the liquid crystal cell 22 and one end of the storage capacitor 23. Hereinafter, this connection node is referred to as a node A. A fixed potential (hereinafter referred to as “counter electrode potential”) Vcom is applied to the counter electrode of the liquid crystal cell 22. One main electrode of the write voltage compensation transistor 24 is connected to the other end of the storage capacitor 23. Hereinafter, this connection node is referred to as a node B.

  A gate voltage Vg2 is applied to the gate electrode of the write voltage compensation transistor 24 in units of rows, and a fixed potential Vk, for example, a ground potential (0 [V]) is applied to the other main electrode in common to each pixel. A timing relationship between the gate voltage Vg1 applied to the gate electrode of the data write transistor 21 and the gate voltage Vg2 applied to the gate electrode of the write voltage compensation transistor 24 is shown in FIG.

  Next, the circuit operation of the pixel 20 having the above configuration will be described.

  The data write transistor 21 is turned on in response to the gate voltage Vg 1, whereby charges corresponding to the data Vdata are accumulated in the storage capacitor 23. However, when the data write transistor 21 is turned off, as described above, the influence of the charge / discharge of charges on each parasitic capacitance of the data write transistor 21 or the channel-gate capacitance associated with the on / off of the transistor 21. As a result, switching noise is generated, and a difference occurs between the potential Vdata applied to the data write transistor 21 and the potential Vwrite actually written to the storage capacitor 23. The effect of the write voltage compensation transistor 24 is to reduce the influence of the switching noise.

  The operation of the write voltage compensation transistor 24 will be described with reference to FIG. 3 showing the timing relationship between the gate voltage Vg1 of the data write transistor 21 and the gate voltage Vg2 of the write voltage compensation transistor 24.

  First, when the gate voltage Vg1 transits from L level (low level) to H level (high level) at time t1, the data write transistor 21 is turned on in response to this, and writing of data Vdata is started. At this time, the write voltage compensation transistor 24 is in an on state. When the writing of the data Vdata is finished, the gate voltage Vg2 changes from the H level to the L level at time t2, and in response to this, the write voltage compensation transistor 24 is turned off. As a result, a connection node between the other end of the storage capacitor 23 and one main electrode of the write voltage compensation transistor 24, that is, the node B is in a floating state (high impedance state).

  Next, when the gate voltage Vg1 transitions from the H level to the L level at time t3, the data write transistor 21 is turned off in response thereto. At this time, it is assumed that the write voltage Vwrite to the storage capacitor 23 decreases by ΔV from the input potential Vdata due to the influence of switching noise of the data write transistor 21. Then, since the node B is in a floating state, the potential of the node B also decreases by ΔV following the write voltage Vwrite according to the law of charge conservation.

  Thereafter, when the gate voltage Vg2 transitions from the L level to the H level at time t4, the write voltage compensation transistor 24 is turned on in response to this, and the write potential of the node A is raised by ΔV to become the potential Vdata. As a result, the potential change of the node A due to the influence of the switching noise of the data write transistor 21 is canceled by the operation of the write voltage compensation transistor 24 from on to off to on.

  However, in actuality, the total parasitic capacitance of the data write transistor 21 and the write voltage compensation transistor 24, the wiring capacitance, the capacitance with the counter electrode across the liquid crystal, that is, the capacitance CL of the liquid crystal cell 22, or each load resistance and write voltage compensation The influence of the switching noise of the transistor 24 must be taken into consideration.

  Therefore, since it is complicated to calculate all of these, the influence of the switching noise of the write voltage compensation transistor 24 is canceled by the off operation and the on operation. Further, paying attention to the movement of charge, the capacitance of the storage capacitor 23 is C0, the parasitic capacitance between the gate electrode of the data write transistor 21 and the node A is C1, and the gate electrode of the write voltage compensation transistor 24 is between the node B and the node B. FIG. 4 shows an equivalent circuit when the parasitic capacitance of C2 is C2.

  Then, the potential of the fixed potential Vk is set to 0 V, and the potential change due to the parasitic capacitances C1 and C2 of the transistors 21 and 24 is calculated (other parasitic capacitances and parasitic resistances are ignored). In the following calculation, it is assumed that a sufficient time has elapsed since the data write transistor 21 and the write voltage compensation transistor 24 are turned on or off.

とする。 First, when both the data write transistor 21 and the write voltage compensation transistor 24 are on (period t1 to t2), the total charge amount Call written with reference to the node B is calculated.

And

が成り立つ。 Next, when both the transistors 21 and 22 are turned off (period t3 to t4) and the potential of the node A is decreased by ΔV due to the influence of switching noise of the data write transistor 21, the potential Vb of the node B is set as a reference. When the total charge amount Call is obtained,

Holds.

となる。さらに、書込み電圧補償トランジスタ２４がオンすると、ノードＡの電位ＶａはノードＡを基準に解くと、 From the equation (1) = (2), if the potential of the node A is decreased by ΔV,

It becomes. Further, when the write voltage compensation transistor 24 is turned on, the potential Va of the node A is solved based on the node A.

となり、（４）式より、

From equation (4),

で表せる。

It can be expressed as

  Usually, C1 and C2 are parasitic capacitances of the transistors, and are sufficiently small values with respect to the capacitance C0 of the storage capacitor 23. Therefore, C1 / (C0 + C1) ≈0, C2 / (C0 + C2) ≈0, C0 / (C0 + C1) ≈1, and Equation (5) becomes Va≈Vdata. That is, the expected write voltage Vdata and the actually written voltage Va are substantially equal. Therefore, if the parasitic capacitances C1 and C2 are so small as to be negligible with respect to the capacitance C0 of the storage capacitor 23, the influence of the switching noise of the data write transistor 21 is almost eliminated. If such a pixel 20 is used, the influence of switching noise can be reduced.

  Further, it is applied to the gate electrode of the data write transistor 21 of each pixel 20 due to the difference in parasitic capacitance and parasitic resistance of the gate line 14 (14-1 to 14-m) generated by the distance between the vertical drive circuit 12 and the pixel 20. It can be seen that even if the slope of the voltage is different, the difference in the influence of the switching noise due to the difference in the slope can be reduced in the same manner.

  As described above, in the active matrix display device in which the pixels 20 including the electro-optic element (in this embodiment, the liquid crystal cell 22) are arranged in a matrix, the write voltage is applied between the storage capacitor 23 and the fixed potential Vk. The compensation transistor 24 is connected, and the data write transistor 21 is turned on in the ON state of the write voltage compensation transistor 24 to start writing the input data Vdata to the pixel 20, and then the write voltage compensation transistor 24 is turned off. By adopting a configuration in which the write voltage compensation transistor 24 is turned on after the data write transistor 21 is turned off, the following effects can be obtained.

  That is, the write voltage compensation transistor 24 is turned on to turn on the data write transistor 21 to start writing the input data Vdata to the pixel 20, and after the write of the input data Vdata is finished, the write voltage compensation transistor 24 is turned off. By doing so, the node B enters a floating state. Thereafter, when the data write transistor 21 is turned off, the write voltage Vwrite to the storage capacitor 23 decreases by ΔV from the input potential Vdata due to the influence of switching noise of the data write transistor 21, but the node B is in a floating state. Since the potential at the node B also decreases by ΔV following the write voltage Vwrite, the write voltage Vwrite at the node A is raised by ΔV by turning on the write voltage compensation transistor 24 to become the input potential Vdata. .

  As a result, the potential change at the node A due to the influence of the switching noise of the data write transistor 21 is canceled by the operation of the write voltage compensation transistor 24 from ON → OFF → ON, so that the data generated at the time of writing data to the storage capacitor 23 The influence of the switching noise of the write transistor 21 can be reduced, and the influence of the switching noise caused by the difference in the slope of the voltage applied to the gate lines 14-1 to 14-m caused by the distance between the vertical drive circuit 12 and the pixel 20 can be reduced. The difference can be reduced in the same way.

  As a result, the write voltage Vwrite to the actual storage capacitor 23 can be made closer to the input potential Vdata (or the expected potential), so that the average value of the write voltage and the counter electrode potential Vcom in the same display region. The absolute value of the difference between the two and the relative difference between the write voltages in the same display area can be reduced, and therefore the image quality and the long-term reliability of the electro-optic element (liquid crystal cell 22) can be improved. Further, if a small-sized low breakdown voltage transistor or the like is used as the second switching element (in this example, the write voltage compensation transistor 24), a highly practical circuit configuration in consideration of the layout area can be realized.

  In the above embodiment, the case where the present invention is applied to an active matrix liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel has been described as an example, but the present invention is not limited to this application example. In addition to the electro-optic element, the present invention can be applied to all active matrix display devices in which pixels including a capacitor element that holds a potential written by a switching element are arranged in a matrix.

1 is a block diagram illustrating a configuration example of an active matrix liquid crystal display device to which the present invention is applied. It is a circuit diagram which shows an example of a circuit structure of a pixel (pixel circuit). 4 is a timing chart showing a timing relationship between a gate voltage Vg1 of a data write transistor and a gate voltage Vg2 of a write voltage compensation transistor. It is an equivalent circuit diagram of a pixel circuit. It is a figure where it uses for description of the subject of a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel array part, 12 ... Vertical drive circuit, 13 ... Horizontal drive circuit, 14-1 to 14-m ... Gate line group, 5-1 to 15-n ... Data line group, 20 ... Pixel (pixel circuit), 21: Data writing transistor (first switching element), 22: Liquid crystal cell, 23 ... Capacitor element, 24 ... Writing voltage compensation transistor (second switching element)

Claims (2)

An electro-optic element;
A first switching element having one main electrode connected to the data line and the other main electrode connected to one end of the electro-optic element;
A capacitive element having one end connected to a connection node between the first switching element and the electro-optic element;
A pixel array unit in which pixels including a second switching element in which one main electrode is connected to the other end of the capacitive element and the other main electrode is connected to a fixed potential;
The first switching element is turned on while the second switching element is turned on to start writing the input data to the pixel, and then the second switching element is turned off, and then the first switching element is turned on. And a driving means for turning on the second switching element after being turned off. An electro-optic element;
A first switching element having one main electrode connected to the data line and the other main electrode connected to one end of the electro-optic element;
A capacitive element having one end connected to a connection node between the first switching element and the electro-optic element;
A display device driving method in which pixels including one main electrode on the other end of the capacitive element and a second switching element on the other main electrode connected to a fixed potential are arranged in a matrix. ,
Turning on the first switching element in the on state of the second switching element to start writing input data to the pixel, and then turning off the second switching element;
Next, after the first switching element is turned off, the second switching element is turned on. The method for driving a display device,

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