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JP2006005190A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2006005190A
JP2006005190A JP2004180455A JP2004180455A JP2006005190A JP 2006005190 A JP2006005190 A JP 2006005190A JP 2004180455 A JP2004180455 A JP 2004180455A JP 2004180455 A JP2004180455 A JP 2004180455A JP 2006005190 A JP2006005190 A JP 2006005190A
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Prior art keywords
insulating film
semiconductor device
film
wiring
copper
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JP2004180455A
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Japanese (ja)
Inventor
Hiromi Shimazu
ひろみ 島津
Tomio Iwasaki
富生 岩▲崎▼
Hiroyuki Ota
裕之 太田
Kensuke Ishikawa
憲輔 石川
Osamu Inoue
修 井上
Takafumi Oshima
隆文 大島
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2004180455A priority Critical patent/JP2006005190A/en
Priority to TW094113466A priority patent/TWI260067B/en
Priority to CNB2005100780184A priority patent/CN100397637C/en
Priority to US11/155,272 priority patent/US7459786B2/en
Publication of JP2006005190A publication Critical patent/JP2006005190A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an occurrence of a void caused by a stress migration in a wiring structure with a copper as a main construction material. <P>SOLUTION: A multilayer wiring structure formed on an insulating film on a semiconductor substrate comprises a first insulating film having a high barrier performance and a compression stress, a second insulating film having a tensile stress, and at least a third insulating film having a dielectric constant lower than those of the first and second insulating films laminated from the below so as to contact on the upper surface of the first wiring with the main construction material as copper. The wiring structure has via holes so that they pass through the first insulating film, the second insulating film, and the third insulating film and contact the first wiring. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置に関し、特に、埋込配線の主配線材料として銅を主成分とする導体膜を用いる半導体装置に関するものである。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a conductor film containing copper as a main component as a main wiring material for embedded wiring.

近年、ＬＳＩの高集積化、高速化を目的としたトランジスタの微細化に伴って、配線の信号遅延が顕在化してきており、これに伴い、配線抵抗の低減と配線間容量の低減とが望まれている。そこで、配線抵抗の低減のため、配線材料として従来のアルミニウム合金よりも低抵抗で、マイグレーション耐性に優れた銅（Ｃｕ）を用いた銅配線技術が開発されつつある。また、配線間容量を低減するために、層間絶縁膜材料としては低誘電率絶縁膜の適用が検討されている。   In recent years, with the miniaturization of transistors for the purpose of higher integration and higher speed of LSI, signal delay of wiring has become apparent, and accordingly, reduction of wiring resistance and reduction of capacitance between wiring are desired. It is rare. Therefore, in order to reduce the wiring resistance, a copper wiring technique using copper (Cu), which is lower in resistance than conventional aluminum alloys and excellent in migration resistance, is being developed as a wiring material. Further, in order to reduce the capacitance between wirings, application of a low dielectric constant insulating film as an interlayer insulating film material has been studied.

これらの銅配線構造は埋込配線技術によって形成される。埋込配線技術は、例えば次の通りである。まず、絶縁膜に配線溝や孔等のような配線開口部を形成した後、その配線開口部内を含む絶縁膜上に導電性バリア膜および銅を主成分とする導体膜を下方から順に堆積する。続いて、化学機械研磨法等によって余分な導体膜および導電性バリア膜を研磨することにより、配線開口部内に埋込配線を形成する。その後、洗浄処理を施した後、その絶縁膜および埋込配線の上面上に、例えば窒化シリコン膜等からなる拡散防止絶縁膜を形成する。その後、拡散防止絶縁膜上面上に低誘電率膜を堆積する。   These copper wiring structures are formed by embedded wiring technology. The embedded wiring technology is, for example, as follows. First, after forming a wiring opening such as a wiring groove or a hole in the insulating film, a conductive barrier film and a conductor film mainly composed of copper are sequentially deposited from below on the insulating film including the inside of the wiring opening. . Subsequently, the buried conductor is formed in the wiring opening by polishing the excess conductor film and the conductive barrier film by a chemical mechanical polishing method or the like. Thereafter, after performing a cleaning process, a diffusion preventing insulating film made of, for example, a silicon nitride film is formed on the insulating film and the upper surface of the embedded wiring. Thereafter, a low dielectric constant film is deposited on the upper surface of the diffusion preventing insulating film.

しかしＣｕ配線構造の開発過程において予想外にストレスマイグレーションに弱いことが明らかとなり、銅配線内やビア内部にストレスマイグレーションによるボイドが形成されることが懸念され、以下の技術が開示されている。   However, in the course of developing the Cu wiring structure, it has been revealed that it is unexpectedly vulnerable to stress migration, and there are concerns about the formation of voids due to stress migration in copper wiring and vias, and the following techniques are disclosed.

例えば、特開２００３−３０３８８０号公報には、上層配線とビアとの接続部分の応力を緩和するために、層間絶縁膜を積層構造とする技術が開示されている（ビア内部のストレスマイグレーションを防止する技術）。
さらに、例えば、特開２００３−２５７９７９号公報には、配線用の銅中に不純物原子を添加する技術が開示されている（銅配線のストレスマイグレーションを防止する技術）。 For example, Japanese Patent Laid-Open No. 2003-303880 discloses a technique in which an interlayer insulating film has a stacked structure in order to relieve stress at a connection portion between an upper wiring and a via (prevents stress migration inside the via). Technology).
Further, for example, Japanese Patent Application Laid-Open No. 2003-257879 discloses a technique of adding impurity atoms into copper for wiring (technology for preventing stress migration of copper wiring).

特開２００３−３０３８８０号公報JP 2003-303880 A 特開２００３−２５７９７９号公報JP 2003-257799 A

しかし、上記の銅配線構造を有する半導体装置においては、配線間を接続するビアホールの下部の配線において、ストレスマイグレーション不良が発生する問題がある。この問題は、ビアホール径が小さい場合に特に顕著である。これにより、ビアホール下部付近の配線部においてボイドが発生し、配線抵抗が増大したり断線不良が生じることが懸念されている。   However, in the semiconductor device having the above-described copper wiring structure, there is a problem that stress migration failure occurs in the wiring under the via hole connecting the wiring. This problem is particularly noticeable when the via hole diameter is small. As a result, voids are generated in the wiring portion near the lower portion of the via hole, and there is a concern that the wiring resistance increases or disconnection failure occurs.

そこで、本発明の目的は、銅を主構成材料とする配線構造において、ストレスマイグレーションによるボイドの発生を抑制し、信頼性の高い半導体装置を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor device that suppresses the generation of voids due to stress migration in a wiring structure that uses copper as a main constituent material.

本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。   The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

上記の目的は、半導体基板上の絶縁膜上に形成される多層配線構造において、主構成材料が銅からなる第１の配線の上面に接するように、下から順にバリア性が高く、かつ圧縮応力を有する第１の絶縁膜、引張応力を有する第２の絶縁膜、前記第１の絶縁膜と前記第２の絶縁膜よりも誘電率の低い第３の絶縁膜が少なくとも積層されており、前記第１の絶縁膜、前記第２の絶縁膜、および前記第３の絶縁膜を貫通し前記第１の配線に接するようにビアが設けられ、ビアを介して第２の配線が接続されている配線構造とすることにより達成される。   In the multilayer wiring structure formed on the insulating film on the semiconductor substrate, the above-mentioned object has a high barrier property in order from the bottom and compressive stress so that the main constituent material is in contact with the upper surface of the first wiring made of copper. At least a first insulating film having a tensile stress, a second insulating film having a tensile stress, and a third insulating film having a dielectric constant lower than that of the second insulating film. Vias are provided through the first insulating film, the second insulating film, and the third insulating film so as to be in contact with the first wiring, and the second wiring is connected through the vias. This is achieved by using a wiring structure.

上記において、好ましくは、前記第１の絶縁膜の膜厚が、前記第２の絶縁膜の膜厚よりも小さいことを特徴とする。
上記において、好ましくは、前記第１の絶縁膜のヤング率が前記第２の絶縁膜のヤング率よりも大きく、なおかつ前記第１の絶縁膜の膜厚が、前記第２の絶縁膜の膜厚よりも小さいことを特徴とする。
上記において、好ましくは、前記第２の絶縁膜がバリア性の高い絶縁膜であることを特徴とする。
上記において、好ましくは、前記第１の絶縁膜が少なくとも窒素原子を含む絶縁膜からなることを特徴とする。
上記において、好ましくは、前記第３の絶縁膜が引張応力を有する低誘電率絶縁膜であることを特徴とする。 In the above, preferably, the film thickness of the first insulating film is smaller than the film thickness of the second insulating film.
In the above, preferably, the Young's modulus of the first insulating film is larger than the Young's modulus of the second insulating film, and the film thickness of the first insulating film is equal to the film thickness of the second insulating film. It is characterized by being smaller than.
In the above, preferably, the second insulating film is an insulating film having a high barrier property.
In the above, preferably, the first insulating film is made of an insulating film containing at least nitrogen atoms.
In the above, preferably, the third insulating film is a low dielectric constant insulating film having a tensile stress.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
本発明によれば、銅を主構成材料とした金属膜からなる配線において、ビアホール底部付近の応力勾配を低減することができ、これによりストレスマイグレーションによるボイドの発生を抑制できるため、信頼性の高い半導体装置が提供される。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, in a wiring made of a metal film containing copper as a main constituent material, it is possible to reduce the stress gradient near the bottom of the via hole, thereby suppressing the generation of voids due to stress migration, and thus high reliability. A semiconductor device is provided.

以下、本発明の実施の形態について図を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（実施形態１）
まず、本発明における第１の実施形態を図１により説明する。本実施形態による半導体装置の主要部の断面構造を図１に示す。 (Embodiment 1)
First, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a cross-sectional structure of the main part of the semiconductor device according to the present embodiment.

図１に示す本実施形態１の半導体装置においては、半導体基板として例えば単結晶シリコンからなるシリコン基板１の主面（素子形成面，回路形成面）にトランジスタが形成されており、前記トランジスタは、例えばゲート絶縁膜３、ゲート電極４および拡散層（図示せず）等で構成されている。それぞれのトランジスタは、酸化シリコンや窒化シリコンなどからなる素子分離膜２によって素子分離されている。また、前記ゲート電極４および、拡散層上面にはシリサイド７が形成されている。   In the semiconductor device according to the first embodiment shown in FIG. 1, a transistor is formed on a main surface (element formation surface, circuit formation surface) of a silicon substrate 1 made of, for example, single crystal silicon as a semiconductor substrate. For example, the gate insulating film 3, the gate electrode 4, a diffusion layer (not shown), and the like are included. Each transistor is isolated by an element isolation film 2 made of silicon oxide or silicon nitride. Silicide 7 is formed on the gate electrode 4 and the upper surface of the diffusion layer.

前記ゲート絶縁膜３は、例えば酸化シリコン、窒化シリコン、酸化チタン、酸化ジルコニウム、酸化ハフニウム、五酸化タンタル等の誘電体膜あるいはこれらの積層構造からなり、例えば化学気相蒸着法、スパッタリング法などを用いて形成される。また、前記ゲート電極４は、例えば多結晶シリコン膜や金属膜、シリコンゲルマニウム膜あるいは金属シリサイド膜あるいはこれらの積層構造からなり、例えば、化学気相蒸着法、スパッタリング法などを用いて形成される。
前記ゲート絶縁膜３、ゲート電極４、シリサイド７の側壁には酸化シリコンや窒化シリコン等からなるサイドウォール６が形成されている。 The gate insulating film 3 is made of, for example, a dielectric film such as silicon oxide, silicon nitride, titanium oxide, zirconium oxide, hafnium oxide, tantalum pentoxide, or a laminated structure thereof. For example, chemical vapor deposition or sputtering is used. Formed using. The gate electrode 4 is made of, for example, a polycrystalline silicon film, a metal film, a silicon germanium film, a metal silicide film, or a laminated structure thereof, and is formed using, for example, a chemical vapor deposition method or a sputtering method.
Side walls 6 made of silicon oxide, silicon nitride, or the like are formed on the side walls of the gate insulating film 3, the gate electrode 4, and the silicide 7.

前記トランジスタを含むシリコン基板１の主面の上部全面は、絶縁膜８で覆われている。ここで、絶縁膜８は、例えば低誘電絶縁膜（ＳｉＯＣ、ＳｉＯＦもしくはＳｉＯＣやＳｉＯ2のポーラス材料等）やＢＰＳＧ（Ｂoron−doped Ｐhospho Ｓilicate Ｇlass）膜やＳＯＧ（Ｓpin Ｏn Ｇlass）膜、あるいはテトラエトキシシランを原料としたＣＶＤ法により形成した酸化シリコン膜（以下ＴＥＯＳ（Tetra-Ｅthoxy-Ｓilicate）膜という）、あるいは化学気相蒸着法やスパッタ法で形成したシリコン酸化膜や窒化膜等からなる。あるいは、これらの積層構造からなる。絶縁膜であれば、これに限定されるものではない。 The entire upper surface of the main surface of the silicon substrate 1 including the transistor is covered with an insulating film 8. Here, the insulating film 8 is, for example, a low dielectric insulating film (such as a porous material of SiOC, SiOF or SiOC or SiO 2 ), a BPSG (Boron-doped Phospho Silicate Glass) film, an SOG (Spin On Glass) film, or tetraethoxy. It consists of a silicon oxide film (hereinafter referred to as TEOS (Tetra-Ethoxy-Silicate) film) formed by a CVD method using silane as a raw material, or a silicon oxide film or a nitride film formed by chemical vapor deposition or sputtering. Or it consists of these laminated structures. The insulating film is not limited to this as long as it is an insulating film.

さらに、前記絶縁膜８の上面には、第１の線間絶縁膜９が形成されている。前記第１の線間絶縁膜９は、前記絶縁膜８と同様、低誘電絶縁膜（ＳｉＯＣ、ＳｉＯＦもしくはＳｉＯＣやＳｉＯ2のポーラス材料等）やＢＰＳＧ膜やＳＯＧ膜、ＴＥＯＳ膜、あるいは化学気相蒸着法やスパッタ法で形成したシリコン酸化膜や窒化膜等からなる。あるいは、これらの積層構造からなる。絶縁膜であれば、これに限定されるものではない。 Further, a first inter-line insulating film 9 is formed on the upper surface of the insulating film 8. As with the insulating film 8, the first inter-line insulating film 9 is a low dielectric insulating film (such as a porous material of SiOC, SiOF or SiOC or SiO 2 ), a BPSG film, an SOG film, a TEOS film, or a chemical vapor phase. It consists of a silicon oxide film or a nitride film formed by a vapor deposition method or a sputtering method. Or it consists of these laminated structures. The insulating film is not limited to this as long as it is an insulating film.

例えば、第１の線間絶縁膜９を、下層から順にＴＥＯＳ膜、低誘電絶縁膜、ＴＥＯＳ膜の積層構造とすることによって、これらの低誘電率絶縁膜の機械的強度を確保することができる。しかし、もちろんＴＥＯＳ膜の代わりに、前述のＣＶＤ法を用いて形成した低誘電絶縁膜を用いてもよい。   For example, when the first inter-line insulating film 9 has a laminated structure of a TEOS film, a low dielectric insulating film, and a TEOS film in order from the lower layer, the mechanical strength of these low dielectric constant insulating films can be ensured. . However, of course, instead of the TEOS film, a low dielectric insulating film formed by using the above-described CVD method may be used.

前記第１の線間絶縁膜９には、配線を形成するための配線溝１０が形成されている。前記配線溝１０内には、例えば下から順にスパッタ法により形成された窒化タンタル膜（ＴａＮ）およびタンタル膜（Ｔａ）を含むバリア膜１１が設けられている。このバリア膜１１の形成方法としては、ＣＶＤ法を用いてもよいし、また、スパッタ法の一種であるイオン化スパッタ法を用いてもよい。このイオン化スパッタ法は、バリア膜を構成する金属をイオン化し、さらに、基板にバイアスを印加することによって、金属イオンに指向性を持たせるものであり、微細な溝の内部においても被覆性良く膜を堆積させることができる。   A wiring trench 10 for forming a wiring is formed in the first inter-line insulating film 9. In the wiring trench 10, for example, a barrier film 11 including a tantalum nitride film (TaN) and a tantalum film (Ta) formed by sputtering is sequentially provided from the bottom. As a method for forming the barrier film 11, a CVD method may be used, or an ionization sputtering method which is a kind of sputtering method may be used. In this ionization sputtering method, the metal constituting the barrier film is ionized and a bias is applied to the substrate to impart directionality to the metal ions. Can be deposited.

バリア膜１１としては、前述のＴａＮおよびＴａとの積層膜に限定されるものではなく、例えば、Ｔａ、ＴａＮ、ＴａＳｉＮ、Ｗ、窒化タングステン（ＷＮ）、ＷＳｉＮ、Ｔｉ、ＴｉＮもしくはＴｉＳｉＮからなる単層膜や、これらの積層膜を用いても良い。また、バリア膜１１として、Ｒｕ、Ｔｉを添加したＲｕからなる単層膜や、ＲｕとＴｉＮの積層膜、ＲｕとＴａＮの積層膜を用いてもよい。バリア膜１１としてＲｕを用いた場合には、ＲｕとＣｕとの密着性を向上させ、マイグレーションを防止する効果もさらに得られる。   The barrier film 11 is not limited to the above-mentioned laminated film of TaN and Ta, and for example, a single layer made of Ta, TaN, TaSiN, W, tungsten nitride (WN), WSiN, Ti, TiN or TiSiN A film or a laminated film thereof may be used. As the barrier film 11, a single layer film made of Ru to which Ru or Ti is added, a laminated film of Ru and TiN, or a laminated film of Ru and TaN may be used. When Ru is used as the barrier film 11, the effect of improving the adhesion between Ru and Cu and preventing migration is further obtained.

次いで、前記配線溝１０内のバリア膜１１上には、第１の銅配線１２が形成されている。前記第１の銅配線１２は、例えば、電界メッキ用のシード膜とめっき膜の積層からなる。シード膜は例えばイオン化スパッタ法などのスパッタ法を用いて形成する。   Next, a first copper wiring 12 is formed on the barrier film 11 in the wiring trench 10. The first copper wiring 12 is composed of, for example, a laminate of a seed film for electroplating and a plating film. The seed film is formed using a sputtering method such as an ionization sputtering method.

シリコン基板１の主面に形成された拡散層と、シリコン基板１の主面上に形成された第１の銅配線１２とは、前記絶縁膜８に設けられたコンタクトプラグ５を介して、電気的に接続されている。   The diffusion layer formed on the main surface of the silicon substrate 1 and the first copper wiring 12 formed on the main surface of the silicon substrate 1 are electrically connected via contact plugs 5 provided on the insulating film 8. Connected.

次に、前記第１の線間絶縁膜９、および第１の銅配線１２の上面には、拡散防止絶縁膜１３が形成されている。拡散防止絶縁膜１３は、銅原子が層間絶縁膜中に拡散するのを防止するためのバリア膜として形成されている。ここで、前記拡散防止絶縁膜１３は、銅の拡散に対するバリア性が酸化シリコンより高く、かつ圧縮応力を有する絶縁膜である。   Next, a diffusion prevention insulating film 13 is formed on the top surfaces of the first inter-line insulating film 9 and the first copper wiring 12. The diffusion preventing insulating film 13 is formed as a barrier film for preventing copper atoms from diffusing into the interlayer insulating film. Here, the diffusion preventing insulating film 13 is an insulating film having a barrier property against copper diffusion higher than that of silicon oxide and having compressive stress.

ここで、前記配線拡散防止絶縁膜１３として、例えばＳｉＮ膜（窒化シリコン膜）、ＳｉＯＮ（酸窒化シリコン膜）、ＳｉＣ膜（炭化シリコン膜）もしくはＳｉＣＮ膜（炭窒化シリコン膜）等を用いてもよい。   Here, for example, a SiN film (silicon nitride film), a SiON (silicon oxynitride film), a SiC film (silicon carbide film), a SiCN film (silicon carbonitride film) or the like may be used as the wiring diffusion preventing insulating film 13. Good.

さらに、前記拡散防止絶縁膜１３の上面には、第１の層間絶縁膜１４が形成されている。ここで、前記第１の層間絶縁膜１４は、引張応力を有する膜である。
さらに、前記第１の層間絶縁膜１４の上面には、第２の層間絶縁膜１５が形成されている。 Further, a first interlayer insulating film 14 is formed on the upper surface of the diffusion preventing insulating film 13. Here, the first interlayer insulating film 14 is a film having a tensile stress.
Further, a second interlayer insulating film 15 is formed on the upper surface of the first interlayer insulating film 14.

ここで、前記第２の層間絶縁膜１５は、例えば低誘電率絶縁膜である。低誘電率絶縁膜は、例えば、ＳｉＯＣを主成分とする膜、あるいはＳｉＯＦを主成分とする膜、ＳｉＣを主成分とする膜や、芳香族炭化水素構造の有機ポリマー膜（ＣとＨを含有する膜）や、上記各種膜やＳｉＯ2（酸化シリコン膜）等の膜中に空孔を導入（ポーラス化）することにより誘電率を下げることができる。これらの膜は、ＣＶＤ法を用いて形成することができる。さらに低誘電率絶縁膜は、例えば芳香族ポリマー材料を塗布し、熱処理を施すことにより形成することができる。また、低誘電絶縁膜として、有機系のシリカガラスを用いてもよい。この場合も、材料を塗布した後熱処理を施す。この有機系のシリカガラスの組成は、主にＳｉＯＣＨである。また、他の有機ポリマー材料や、上記の各種材料に空孔を導入した材料を用いることもできる。 Here, the second interlayer insulating film 15 is, for example, a low dielectric constant insulating film. The low dielectric constant insulating film is, for example, a film containing SiOC as a main component, a film containing SiOF as a main component, a film containing SiC as a main component, or an organic polymer film having an aromatic hydrocarbon structure (containing C and H). The dielectric constant can be lowered by introducing pores into the film such as the above-described various films and SiO 2 (silicon oxide film). These films can be formed using a CVD method. Further, the low dielectric constant insulating film can be formed, for example, by applying an aromatic polymer material and performing a heat treatment. An organic silica glass may be used as the low dielectric insulating film. Also in this case, heat treatment is performed after the material is applied. The composition of this organic silica glass is mainly SiOCH. In addition, other organic polymer materials and materials obtained by introducing pores into the various materials described above can also be used.

このような低誘電絶縁膜の誘電率は、酸化シリコン膜（例えば、ＴＥＯＳ膜）より低く（誘電率が３．７以下であり）、その結果、配線間の寄生容量が低減されるため半導体装置の動作の高速化を図ることができる。   The dielectric constant of such a low dielectric insulating film is lower than that of a silicon oxide film (for example, TEOS film) (dielectric constant is 3.7 or less), and as a result, the parasitic capacitance between wirings is reduced, so that the semiconductor device The speed of the operation can be increased.

次に、前記第２の層間絶縁膜１５の上面には、第２の線間絶縁膜１６が形成されている。
ここで、前記第２の線間絶縁膜１６は、前記第１の線間絶縁膜９と同様に、例えば低誘電絶縁膜（ＳｉＯＣ、ＳｉＯＦもしくはＳｉＯＣやＳｉＯ2のポーラス材料等）やＢＰＳＧ膜やＳＯＧ膜、ＴＥＯＳ膜、あるいは化学気相蒸着法やスパッタ法で形成したシリコン酸化膜や窒化膜等からなる。あるいは、これらの積層構造からなる。絶縁膜であれば、これに限定されるものではない。 Next, a second interline insulating film 16 is formed on the upper surface of the second interlayer insulating film 15.
Here, like the first inter-line insulating film 9, the second inter-line insulating film 16 is, for example, a low dielectric insulating film (such as a porous material of SiOC, SiOF or SiOC or SiO 2 ), a BPSG film, It consists of a SOG film, a TEOS film, a silicon oxide film or a nitride film formed by chemical vapor deposition or sputtering. Or it consists of these laminated structures. The insulating film is not limited to this as long as it is an insulating film.

前記第２の線間絶縁膜１６、前記第２の層間絶縁膜１５、前記第１の層間絶縁膜１４、および前記拡散防止絶縁膜１３、を貫通するように、ビアホール（接続孔）１７ｂおよび配線溝１７ａが形成されている。ビアホール１７ｂは、第１の銅配線１２と配線溝１７ａとの間に配置されており、第２の層間絶縁膜１５、第１の層間絶縁膜１４及び拡散防止絶縁膜１３を貫通し、かつ配線溝１７ａ及び第１の銅配線１２に連なっている。   Via holes (connection holes) 17b and wirings so as to penetrate the second inter-line insulating film 16, the second interlayer insulating film 15, the first interlayer insulating film 14, and the diffusion preventing insulating film 13. A groove 17a is formed. The via hole 17b is disposed between the first copper wiring 12 and the wiring groove 17a, penetrates through the second interlayer insulating film 15, the first interlayer insulating film 14, and the diffusion preventing insulating film 13, and is connected to the wiring. It continues to the groove 17 a and the first copper wiring 12.

前記ビアホール１７ｂおよび配線溝１７ａ内には、例えば下から順にスパッタ法により形成された窒化タンタル膜（ＴａＮ）およびタンタル膜（Ｔａ）を含むバリア膜１８が設けられている。このバリア膜１８の形成方法としては、ＣＶＤ法を用いてもよいし、また、スパッタ法の一種であるイオン化スパッタ法を用いてもよい。このイオン化スパッタ法は、バリア膜を構成する金属をイオン化し、さらに、基板にバイアスを印加することによって、金属イオンに指向性を持たせるものであり、微細な溝の内部においても被覆性良く膜を堆積させることができる。   In the via hole 17b and the wiring groove 17a, for example, a barrier film 18 including a tantalum nitride film (TaN) and a tantalum film (Ta) formed by sputtering is sequentially provided from the bottom. As a method for forming the barrier film 18, a CVD method may be used, or an ionization sputtering method which is a kind of sputtering method may be used. In this ionization sputtering method, the metal constituting the barrier film is ionized and a bias is applied to the substrate to impart directionality to the metal ions. Can be deposited.

前記バリア膜１８としては、前述のＴａＮおよびＴａとの積層膜に限定されるものではなく、例えば、Ｔａ、ＴａＮ、ＴａＳｉＮ、Ｗ、窒化タングステン（ＷＮ）、ＷＳｉＮ、Ｔｉ、ＴｉＮもしくはＴｉＳｉＮからなる単層膜や、これらの積層膜を用いても良い。また、バリア膜１８として、Ｒｕ、Ｔｉを添加したＲｕからなる単層膜や、ＲｕとＴｉＮの積層膜、ＲｕとＴａＮの積層膜を用いてもよい。バリア膜１８としてＲｕを用いた場合には、ＲｕとＣｕとの密着性を向上させ、マイグレーションを防止する効果もさらに得られる。   The barrier film 18 is not limited to the above-mentioned laminated film of TaN and Ta. For example, the barrier film 18 is made of Ta, TaN, TaSiN, W, tungsten nitride (WN), WSiN, Ti, TiN, or TiSiN. A layer film or a laminated film thereof may be used. As the barrier film 18, a single layer film made of Ru to which Ru or Ti is added, a laminated film of Ru and TiN, or a laminated film of Ru and TaN may be used. When Ru is used as the barrier film 18, the effect of improving the adhesion between Ru and Cu and preventing migration is further obtained.

次いで、前記ビアホール１７ｂおよび配線溝１７ａ内の前記バリア膜１８上には、主構成材料が銅膜からなるビア１９、および第２の銅配線２０が形成されている。前記ビア１９、および第２の銅配線２０は、例えば、電界メッキ用のシード膜とめっき膜の積層からなる。シード膜は例えばイオン化スパッタ法などのスパッタ法を用いて形成する。
ここで、ビア１９とは、銅配線２０の一部からなり、銅配線２０と下層の銅配線１２とを電気的に接続するための部分である。 Next, a via 19 and a second copper wiring 20 whose main constituent material is a copper film are formed on the barrier film 18 in the via hole 17b and the wiring groove 17a. The via 19 and the second copper wiring 20 are made of, for example, a laminate of an electroplating seed film and a plating film. The seed film is formed using a sputtering method such as an ionization sputtering method.
Here, the via 19 is a portion for forming a part of the copper wiring 20 and electrically connecting the copper wiring 20 and the lower-layer copper wiring 12.

次いで、前記第２の線間絶縁膜１６、および第２の銅配線２０の上面には、絶縁膜２１、絶縁膜２２などが形成されている。
その後、所望の工程により、半導体装置が完成される。 Next, an insulating film 21, an insulating film 22, and the like are formed on the upper surfaces of the second interline insulating film 16 and the second copper wiring 20.
Thereafter, the semiconductor device is completed by a desired process.

本実施形態においては、２層配線構造の場合について説明したが、前記拡散防止絶縁膜１３の層から前記第２の線間絶縁膜１６までの層を形成する前述の工程を、必要な配線層分繰り返すことで多層配線構造を得ることができる。
本発明による配線構造は多層配線構造内において、少なくとも一層に使用されていればよく必ずしも全層に用いる必要はない。 In the present embodiment, the case of the two-layer wiring structure has been described. However, the above-described process of forming a layer from the layer of the diffusion preventing insulating film 13 to the second inter-line insulating film 16 requires the necessary wiring layer. By repeating the process, a multilayer wiring structure can be obtained.
The wiring structure according to the present invention may be used in at least one layer in the multilayer wiring structure, and is not necessarily used in all layers.

ビア下部の配線におけるストレスマイグレーションはビア径が小さくなるほど加速されるため、多層配線構造において、最小ビア径が相対的に小さい、下層部分のビアが形成される層間絶縁膜部分にのみ、本発明による配線構造を適用することにより、工程数の増加を防ぐことができ、かつストレスマイグレーションによる抵抗上昇を防止することが可能である。   Since stress migration in the wiring under the via is accelerated as the via diameter becomes smaller, in the multilayer wiring structure, the present invention is applied only to the interlayer insulating film portion where the minimum via diameter is relatively small and the lower via is formed. By applying the wiring structure, it is possible to prevent an increase in the number of processes and to prevent an increase in resistance due to stress migration.

つぎに、上記構成の本実施形態１による半導体装置の作用効果を以下に説明する。従来の主構成材料が銅膜である配線においては、ビア下部においてストレスマイグレーションによってボイドが発生し、抵抗が増大することが懸念されていた。本願発明者らは、実験と解析により、ビア下部配線におけるボイドによる抵抗増大は、ビア下部銅膜応力勾配の増大によって加速されていることを明らかにした。   Next, operational effects of the semiconductor device according to the first embodiment having the above-described configuration will be described below. In a conventional wiring whose main constituent material is a copper film, there has been a concern that voids are generated due to stress migration in the lower portion of the via and resistance increases. The inventors of the present application have made it clear from experiments and analysis that the increase in resistance due to voids in the via lower wiring is accelerated by an increase in the stress gradient of the via lower copper film.

本願発明者らは、本発明者らは、主構成材料が銅からなる第１の配線の上面に第２の配線を接続するためのビアホールが形成された部分における絶縁膜構造の応力を抑制することにより、ビア下銅膜応力勾配を低減でき、ビア下配線ボイドによる抵抗増大を防止できることを見出した。   The inventors of the present application suppress the stress of the insulating film structure in the portion where the via hole for connecting the second wiring is formed on the upper surface of the first wiring whose main constituent material is copper. As a result, it has been found that the stress gradient of the copper film under the via can be reduced, and the increase in resistance due to the wiring void under the via can be prevented.

すなわち、前記拡散防止絶縁膜１３が圧縮応力を有する場合には、前記第１の銅配線１２はビアホール１７ｂの側壁から圧縮の力を受け、ビア下付近の応力勾配が生じる。そこで、前記拡散防止絶縁膜１３とは逆符号の引張応力を有する第１の層間絶縁膜を設けることにより、銅配線に作用する圧縮応力を低減でき、ビア下部に発生する応力勾配を低減することができる。これにより、ビア下部においてストレスマイグレーションによるボイドの成長が抑制され、抵抗上昇が防止される。したがって、信頼性の高い半導体装置が得られる。   That is, when the diffusion preventing insulating film 13 has a compressive stress, the first copper wiring 12 receives a compressive force from the side wall of the via hole 17b, and a stress gradient near the via is generated. Therefore, by providing a first interlayer insulating film having a tensile stress opposite in sign to that of the diffusion preventing insulating film 13, the compressive stress acting on the copper wiring can be reduced, and the stress gradient generated in the lower portion of the via can be reduced. Can do. This suppresses the growth of voids due to stress migration in the lower portion of the via, thereby preventing an increase in resistance. Therefore, a highly reliable semiconductor device can be obtained.

この場合、前記拡散防止絶縁膜１３の膜厚が、前記第１の層間絶縁膜１４の膜厚よりも小さい方が好ましい。これは、銅配線の上面から離れるに従い、銅配線に及ぼす影響が小さくなるため、銅配線上に直接設けられる、拡散防止絶縁膜１３よりも、さらにその上面に形成される第１の層間絶縁膜１４の膜厚を厚くすることにより、より高い効果が得られる。   In this case, it is preferable that the film thickness of the diffusion preventing insulating film 13 is smaller than the film thickness of the first interlayer insulating film 14. Since the influence on the copper wiring is reduced as the distance from the upper surface of the copper wiring is increased, the first interlayer insulating film further formed on the upper surface of the diffusion preventing insulating film 13 provided directly on the copper wiring. By increasing the film thickness of 14, a higher effect can be obtained.

また、前記拡散防止絶縁膜１３のヤング率が、前記第１の層間絶縁膜１４のヤング率よりも大きい材料とすることが好ましい。これは、ヤング率が高い材料は原子間の結合が強く緻密な膜であるため、銅配線から銅原子が絶縁膜に拡散するのを防止する効果が高くなるためである。この場合には、前記拡散防止絶縁膜１３の膜厚が、前記第１の層間絶縁膜１４の膜厚よりも小さい方が好ましい。これは、前述した理由のほかに、ヤング率が小さいほど下の材料に作用する力が小さくなるため、拡散防止絶縁膜の圧縮応力の作用を抑制するには、前記拡散防止絶縁膜の膜厚よりも厚くした方がより高い効果が得られる。   The diffusion preventing insulating film 13 is preferably made of a material having a Young's modulus larger than that of the first interlayer insulating film 14. This is because the material having a high Young's modulus is a dense film having strong bonds between atoms, and therefore, the effect of preventing diffusion of copper atoms from the copper wiring into the insulating film is enhanced. In this case, it is preferable that the thickness of the diffusion preventing insulating film 13 is smaller than the thickness of the first interlayer insulating film 14. In addition to the reason described above, the smaller the Young's modulus, the smaller the force acting on the lower material. Therefore, in order to suppress the action of the compressive stress of the diffusion prevention insulating film, the thickness of the diffusion prevention insulation film A higher effect can be obtained by increasing the thickness.

また、前記第１の層間絶縁膜１４を銅原子の拡散に対してバリア性の高い絶縁膜とすれば、前記拡散防止絶縁膜１３の膜厚を薄くすることができる。圧縮応力を有する緻密な絶縁膜は誘電率が相対的に高くなる。したがって、圧縮応力を有する拡散防止絶縁膜上面に設ける第１の層間絶縁膜１４を、前記拡散防止絶縁膜よりも誘電率が低く、かつ引張応力を有し、かつバリア性の高い絶縁膜とすることにより、配線間容量を低減する効果も得られる。第１の層間絶縁膜１４の膜厚を、前記拡散防止絶縁膜よりも厚くすることにより、配線間容量を低減することができる。   Further, if the first interlayer insulating film 14 is an insulating film having a high barrier property against the diffusion of copper atoms, the film thickness of the diffusion preventing insulating film 13 can be reduced. A dense insulating film having a compressive stress has a relatively high dielectric constant. Therefore, the first interlayer insulating film 14 provided on the upper surface of the diffusion preventing insulating film having compressive stress is an insulating film having a dielectric constant lower than that of the diffusion preventing insulating film, a tensile stress, and a high barrier property. As a result, an effect of reducing the capacitance between the wirings can also be obtained. By making the film thickness of the first interlayer insulating film 14 thicker than that of the diffusion preventing insulating film, the inter-wiring capacitance can be reduced.

また、前記拡散防止絶縁膜１３が、例えばＳｉＣＮやＳｉＮなど、少なくとも窒素原子を含む絶縁膜とすることにより銅配線との密着性を向上することができ、銅配線と拡散防止絶縁膜界面でのはく離を防止する効果も得られる。   Further, the diffusion prevention insulating film 13 can be improved in adhesion with the copper wiring by being an insulating film containing at least a nitrogen atom such as SiCN or SiN, and can be improved at the interface between the copper wiring and the diffusion preventing insulating film. The effect of preventing peeling is also obtained.

また、前記第２の層間絶縁膜１５が引張応力を有する低誘電率絶縁膜とすることにより、前記第１の層間絶縁膜１４の引張応力と同じ向きの応力であるため、前記第１の層間絶縁膜１４と前記第２の層間絶縁膜１５との界面応力が低減され、この界面でのはく離を防止する効果も得られる。   In addition, since the second interlayer insulating film 15 is a low dielectric constant insulating film having a tensile stress, the stress is in the same direction as the tensile stress of the first interlayer insulating film 14. Interfacial stress between the insulating film 14 and the second interlayer insulating film 15 is reduced, and an effect of preventing separation at this interface can be obtained.

なお、前記拡散防止絶縁膜１３自体の圧縮応力を低減することによっても、第１の銅配線１２に作用する圧縮応力を低減でき、ビア下部に発生する応力勾配を低減することができる。しかし、拡散防止絶縁膜１３の応力を成膜条件などにより変化させると、膜の緻密性が損なわれ銅原子拡散のバリア性が低下することが懸念されるため、拡散防止絶縁膜はバリア性を考慮した膜質とする必要がある。したがって、応力の作用を抑制するための拡散防止絶縁膜１３の上面に設けられる第１の層間絶縁膜１４の膜応力を拡散防止絶縁膜１３とは反対符号とすることにより、バリア性を低下させることなく、銅配線内のボイドの形成を抑制することができ、信頼性の高い銅配線構造を有する半導体装置が得られる。   Note that the compressive stress acting on the first copper wiring 12 can also be reduced by reducing the compressive stress of the diffusion preventing insulating film 13 itself, and the stress gradient generated in the lower portion of the via can be reduced. However, if the stress of the diffusion preventing insulating film 13 is changed depending on the film forming conditions, etc., there is a concern that the denseness of the film is impaired and the barrier property of copper atom diffusion is lowered. Therefore, the diffusion preventing insulating film has a barrier property. It is necessary to consider the film quality. Therefore, the barrier property is lowered by setting the film stress of the first interlayer insulating film 14 provided on the upper surface of the diffusion preventing insulating film 13 for suppressing the action of stress to the opposite sign to that of the diffusion preventing insulating film 13. Therefore, formation of voids in the copper wiring can be suppressed, and a semiconductor device having a highly reliable copper wiring structure can be obtained.

（実施形態２）
次に、本発明における第２の実施形態を図２により説明する。図２は本実施形態による半導体装置の主要部の断面構造を示しており、第１の実施形態と共通の部分には同一の符号を付している。 (Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 shows a cross-sectional structure of the main part of the semiconductor device according to the present embodiment, and the same reference numerals are given to the same parts as in the first embodiment.

図２に示す本実施形態２の半導体装置においては、第１の実施形態による図１の構造の、前記第２の層間絶縁膜１５と前記第２の線間絶縁膜１６の界面に、下層から順に絶縁膜２３、絶縁膜２４が設けられた構造となっている。その他の点はほぼ同一構造であり、第１の実施形態と同様の効果が得られる。   In the semiconductor device according to the second embodiment shown in FIG. 2, from the lower layer to the interface between the second interlayer insulating film 15 and the second interline insulating film 16 in the structure of FIG. 1 according to the first embodiment. An insulating film 23 and an insulating film 24 are sequentially provided. The other points are almost the same structure, and the same effect as the first embodiment can be obtained.

なお、前記絶縁膜２３は、低誘電率膜からなる前記第２の層間絶縁膜１５のキャップ用の絶縁膜である。例えば、この絶縁膜２３は、例えば二酸化シリコン（ＳｉＯ2）に代表される酸化シリコン（ＳｉＯx）膜からなり、例えば化学機械研磨処理（ＣＭＰ；Ｃhemical Ｍechanical Ｐolishing）時における、前記第２の層間絶縁膜１５の機械的強度を確保することができ、また、表面保護および耐湿性の確保することが可能である。 The insulating film 23 is a cap insulating film made of a low dielectric constant film for the second interlayer insulating film 15. For example, the insulating film 23 is made of, for example, a silicon oxide (SiO x) film typified by silicon dioxide (SiO 2 ). For example, the second interlayer insulating film in a chemical mechanical polishing (CMP) process is used. 15 mechanical strength can be ensured, and surface protection and moisture resistance can be ensured.

絶縁膜２３の厚さは、前記第２の層間絶縁膜１５よりも相対的に薄く、例えば２５ｎｍ〜１００ｎｍ程度、好ましくは、例えば５０ｎｍ程度である。   The thickness of the insulating film 23 is relatively thinner than the second interlayer insulating film 15, and is, for example, about 25 nm to 100 nm, and preferably, for example, about 50 nm.

前記絶縁膜２３は、酸化シリコン膜に限定されるものではなく種々変更可能であり、例えば窒化シリコン（ＳｉxＮy）膜、炭化シリコン（ＳｉＣ）膜または炭窒化シリコン（ＳｉＣＮ）膜を用いても良い。   The insulating film 23 is not limited to a silicon oxide film and can be variously changed. For example, a silicon nitride (SixNy) film, a silicon carbide (SiC) film, or a silicon carbonitride (SiCN) film may be used.

絶縁膜２４は、エッチングストッパ用の絶縁膜である。第２の線間絶縁膜１６と絶縁膜２４のエッチング選択比を大きくとることで、この絶縁膜２４の表面でエッチングを一旦停止させた後、絶縁膜２４を選択的にエッチング除去する。これにより、配線溝１７ａの形成深さ精度を向上させることができ、配線溝１７ａの掘り過ぎを防止できる。   The insulating film 24 is an insulating film for an etching stopper. By increasing the etching selection ratio between the second inter-line insulating film 16 and the insulating film 24, the etching is temporarily stopped on the surface of the insulating film 24, and then the insulating film 24 is selectively etched away. Thereby, the formation depth precision of the wiring groove | channel 17a can be improved, and the excessive dug of the wiring groove | channel 17a can be prevented.

絶縁膜２３の厚さは、前記第２の層間絶縁膜１５よりも相対的に薄く、例えば２５ｎｍ〜１００ｎｍ程度、好ましくは、例えば５０ｎｍ程度である。   The thickness of the insulating film 23 is relatively thinner than the second interlayer insulating film 15, and is, for example, about 25 nm to 100 nm, and preferably, for example, about 50 nm.

（実施形態３）
次に、本発明における第３の実施形態を図３により説明する。図３は本実施形態３による半導体装置の主要部の断面構造を示しており、第１の実施形態と共通の部分には同一の符号を付している。 (Embodiment 3)
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 3 shows a cross-sectional structure of the main part of the semiconductor device according to the third embodiment, and the same reference numerals are given to the same parts as those in the first embodiment.

図３に示す本実施形態３の半導体装置においては、第１の実施形態による図１の構造の、前記第２の層間絶縁膜１５と前記第２の線間絶縁膜１６の界面に、絶縁膜２３のみが設けられた構造となっている。その他の点はほぼ同一構造であり、第１の実施形態と同様の効果が得られる。   In the semiconductor device of the third embodiment shown in FIG. 3, an insulating film is formed at the interface between the second interlayer insulating film 15 and the second interline insulating film 16 in the structure of FIG. 1 according to the first embodiment. Only 23 is provided. The other points are almost the same structure, and the same effect as the first embodiment can be obtained.

なお、前記絶縁膜２３は、低誘電率膜からなる前記第２の層間絶縁膜１５のキャップ用の絶縁膜である。例えば、この絶縁膜２３は、例えば二酸化シリコン（ＳｉＯ2）に代表される酸化シリコン（ＳｉＯx）膜からなり、例えば化学機械研磨処理（ＣＭＰ；Ｃhemical Ｍechanical Ｐolishing）時における、前記第２の層間絶縁膜１５の機械的強度を確保することができ、また、表面保護および耐湿性の確保することが可能である。 The insulating film 23 is a cap insulating film made of a low dielectric constant film for the second interlayer insulating film 15. For example, the insulating film 23 is made of, for example, a silicon oxide (SiO x) film typified by silicon dioxide (SiO 2 ). For example, the second interlayer insulating film in a chemical mechanical polishing (CMP) process is used. 15 mechanical strength can be ensured, and surface protection and moisture resistance can be ensured.

絶縁膜２３の厚さは、前記第２の層間絶縁膜１５よりも相対的に薄く、例えば２５ｎｍ〜１５０ｎｍ程度である。前記絶縁膜２３は、酸化シリコン膜に限定されるものではなく種々変更可能であり、例えば窒化シリコン（ＳｉxＮy）膜、炭化シリコン（ＳｉＣ）膜または炭窒化シリコン（ＳｉＣＮ）膜を用いても良い。   The thickness of the insulating film 23 is relatively thinner than the second interlayer insulating film 15 and is, for example, about 25 nm to 150 nm. The insulating film 23 is not limited to a silicon oxide film and can be variously changed. For example, a silicon nitride (SixNy) film, a silicon carbide (SiC) film, or a silicon carbonitride (SiCN) film may be used.

図２に示した第２の実施形態における、エッチングストッパ用の絶縁膜としての機能も兼ねている。第２の実施形態における絶縁膜２４を省略している分工程数を減らすことができる。   It also functions as an insulating film for the etching stopper in the second embodiment shown in FIG. The number of steps can be reduced by omitting the insulating film 24 in the second embodiment.

（実施形態４）
次に、本発明における第４の実施形態を図４により説明する。図４は本実施形態による半導体装置の主要部の断面構造を示しており、第１の実施形態と共通の部分には同一の符号を付している。 (Embodiment 4)
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the cross-sectional structure of the main part of the semiconductor device according to the present embodiment, and the same reference numerals are given to the common parts with the first embodiment.

図４に示す本実施形態４の半導体装置においては、第１の実施形態による図１の構造の、圧縮応力を有する拡散防止絶縁膜１３に変わって、引張応力を有する拡散防止絶縁膜２６が設けられている。なおかつ、図１の構造の、前記第１の層間絶縁膜１４に変わって、圧縮応力を有する第１の層間絶縁膜２７が設けられた構造となっている。その他の点は同一構造であり、第１の実施形態と同様の効果が得られる。   In the semiconductor device according to the fourth embodiment shown in FIG. 4, a diffusion prevention insulating film 26 having tensile stress is provided instead of the diffusion prevention insulating film 13 having compressive stress in the structure of FIG. 1 according to the first embodiment. It has been. In addition, instead of the first interlayer insulating film 14 in the structure of FIG. 1, a first interlayer insulating film 27 having a compressive stress is provided. Other points are the same structure, and the same effect as the first embodiment can be obtained.

図４に示すように、第１の銅配線１２の上面に設けられる前記拡散防止絶縁膜２６が引張応力を有する場合には、前記第１の銅配線１２はビアホール１７ｂの側壁から引張の力を受け、ビア下付近の応力勾配が生じる。   As shown in FIG. 4, when the diffusion prevention insulating film 26 provided on the upper surface of the first copper wiring 12 has a tensile stress, the first copper wiring 12 exerts a tensile force from the side wall of the via hole 17b. As a result, a stress gradient near the bottom of the via is generated.

そこで、前記拡散防止絶縁膜２６とは逆符号の圧縮応力を有する第１の層間絶縁膜２７を設けることにより、銅配線に作用する引張応力を低減でき、ビア下部に発生する応力勾配を低減することができる。これにより、ビア下部においてストレスマイグレーションによるボイドの成長が抑制され、抵抗上昇が防止される。したがって、信頼性の高い半導体装置が得られる。   Therefore, by providing the first interlayer insulating film 27 having a compressive stress opposite in sign to the diffusion preventing insulating film 26, the tensile stress acting on the copper wiring can be reduced, and the stress gradient generated in the lower portion of the via is reduced. be able to. This suppresses the growth of voids due to stress migration in the lower portion of the via, thereby preventing an increase in resistance. Therefore, a highly reliable semiconductor device can be obtained.

また、通常前記第１の銅配線１２は引張応力を有するため、その上面に引張応力を有する拡散防止絶縁膜２６を設けることにより、前記第１の銅配線１２と前記拡散防止絶縁膜２６との界面応力を低減することができ、ストレスマイグレーションを抑制する効果がさらに得られる。   Further, since the first copper wiring 12 usually has a tensile stress, the diffusion preventing insulating film 26 having a tensile stress is provided on the upper surface thereof, whereby the first copper wiring 12 and the diffusion preventing insulating film 26 are provided. The interface stress can be reduced, and the effect of suppressing stress migration can be further obtained.

また、引張応力を有する前記拡散防止絶縁膜２６の膜厚が、圧縮応力を有する前記第１の層間絶縁膜２７の膜厚よりも小さくすることにより、効果的に銅配線に生じる応力勾配を抑制できる。これは、銅配線の上面から離れるに従い、銅配線に及ぼす影響が小さくなるため、銅配線上に直接設けられる、拡散防止絶縁膜２６よりよりも、さらにその上面に形成される第１の層間絶縁膜２７の膜厚を厚くする必要があるためである。   Further, by making the film thickness of the diffusion preventing insulating film 26 having tensile stress smaller than the film thickness of the first interlayer insulating film 27 having compressive stress, the stress gradient generated in the copper wiring can be effectively suppressed. it can. This is because the influence on the copper wiring becomes smaller as the distance from the upper surface of the copper wiring becomes smaller. Therefore, the first interlayer insulation formed further on the upper surface of the diffusion prevention insulating film 26 provided directly on the copper wiring. This is because it is necessary to increase the film thickness of the film 27.

前記第１の層間絶縁膜２７を銅原子の拡散に対してバリア性の高い絶縁膜とすれば、前記拡散防止絶縁膜２６の膜厚をさらに薄くすることができる。これにより、ビア深さが同じ場合には、低誘電率絶縁膜からなる第２の層間絶縁膜１５の膜厚を厚くすることができ、配線間容量を低減することが可能である。   If the first interlayer insulating film 27 is an insulating film having a high barrier property against the diffusion of copper atoms, the thickness of the diffusion preventing insulating film 26 can be further reduced. Thereby, when the via depth is the same, the thickness of the second interlayer insulating film 15 made of the low dielectric constant insulating film can be increased, and the capacitance between the wirings can be reduced.

また、前記第１の層間絶縁膜２７を銅原子の拡散に対してバリア性の高い絶縁膜とした場合、前記拡散防止絶縁膜２６のヤング率が、前記第１の層間絶縁膜２７のヤング率よりも小さい材料とし、引張応力を有する前記拡散防止絶縁膜２６の膜厚を、圧縮応力を有する前記第１の層間絶縁膜２７の膜厚よりも大きくすることにより、配線間容量を低減することができる。   When the first interlayer insulating film 27 is an insulating film having a high barrier property against the diffusion of copper atoms, the Young's modulus of the diffusion preventing insulating film 26 is the Young's modulus of the first interlayer insulating film 27. And reducing the inter-wiring capacitance by making the film thickness of the diffusion preventing insulating film 26 having tensile stress larger than the film thickness of the first interlayer insulating film 27 having compressive stress. Can do.

また、図２に示す実施形態２や図３に示す実施形態３に示した場合と同様に、本実施形態においても、前記第２の層間絶縁膜１５と前記第２の線間絶縁膜１６の界面に、絶縁膜２３、および絶縁膜２４の積層構造、あるいは絶縁膜２３の単層が設けられた構造とした場合には、前記第２の層間絶縁膜１５の機械的強度を確保することができ、また、表面保護および耐湿性の確保することが可能である。また、エッチングストッパ用の絶縁膜としての機能の効果が得られる。   Further, as in the case of the second embodiment shown in FIG. 2 and the third embodiment shown in FIG. 3, also in this embodiment, the second interlayer insulating film 15 and the second inter-line insulating film 16 are formed. In the case where a laminated structure of the insulating film 23 and the insulating film 24 or a structure in which a single layer of the insulating film 23 is provided at the interface, the mechanical strength of the second interlayer insulating film 15 can be ensured. In addition, surface protection and moisture resistance can be ensured. Further, the function effect as an insulating film for the etching stopper can be obtained.

（実施形態５）
次に、本発明における第５の実施形態を図５により説明する。図５は本実施形態による半導体装置の主要部の断面構造を示しており、第１の実施形態と共通の部分には同一の符号を付している。 (Embodiment 5)
Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 shows the cross-sectional structure of the main part of the semiconductor device according to the present embodiment, and the same reference numerals are given to the common parts with the first embodiment.

図５に示す本実施形態の半導体装置においては、第１の実施形態による図１の構造の、前記第１の銅配線１２と前記拡散防止絶縁膜１３の界面に、窒化銅層２８が設けられた構造となっている。その他の点は同一構造であり、第１の実施形態と同様の効果が得られる。   In the semiconductor device of this embodiment shown in FIG. 5, a copper nitride layer 28 is provided at the interface between the first copper wiring 12 and the diffusion preventing insulating film 13 in the structure of FIG. 1 according to the first embodiment. It has a structure. Other points are the same structure, and the same effect as the first embodiment can be obtained.

前記第１の銅配線１２と前記拡散防止絶縁膜１３の界面に、窒化銅層２８を設けることにより、銅原子の絶縁膜中への拡散に対するバリア性を向上させることができ、さらに信頼性の高い半導体装置が得られる。   By providing the copper nitride layer 28 at the interface between the first copper wiring 12 and the diffusion preventing insulating film 13, the barrier property against the diffusion of copper atoms into the insulating film can be improved, and the reliability can be improved. A high semiconductor device can be obtained.

また、窒化銅層２８により銅原子の拡散に対するバリア性を確保することができるので、前記拡散防止絶縁膜１３の膜厚を薄くすることができ、前記拡散防止絶縁膜１３より誘電率の低い第２の層間絶縁膜の膜厚を、より厚くすることができ、配線間容量を低減することが可能である。   In addition, since the barrier property against the diffusion of copper atoms can be secured by the copper nitride layer 28, the thickness of the diffusion preventing insulating film 13 can be reduced, and the dielectric constant lower than that of the diffusion preventing insulating film 13 can be obtained. The thickness of the second interlayer insulating film can be increased, and the capacitance between wirings can be reduced.

図５における実施形態５においては、前記第１の銅配線１２と前記拡散防止絶縁膜１３の界面にのみ、窒化銅層２８が設けられた場合について示したが、図６の実施形態６に示すように、前記第１の銅配線１２とビア１９との界面にも窒化銅層２８を設けてもよい。
ただし、ビアと配線のコンタクト抵抗低減という観点では、前記第１の銅配線１２と前記拡散防止絶縁膜１３の界面にのみ、窒化銅層２８が設けられた場合の方が好ましい。 In the fifth embodiment shown in FIG. 5, the case where the copper nitride layer 28 is provided only at the interface between the first copper wiring 12 and the diffusion prevention insulating film 13 is shown. As described above, a copper nitride layer 28 may also be provided at the interface between the first copper wiring 12 and the via 19.
However, from the viewpoint of reducing contact resistance between the via and the wiring, it is preferable that the copper nitride layer 28 is provided only at the interface between the first copper wiring 12 and the diffusion preventing insulating film 13.

（実施形態７）
次に、本発明における第７の実施形態を図７により説明する。図７は本実施形態による半導体装置の主要部の断面構造を示しており、第２の実施形態と共通の部分には同一の符号を付している。 (Embodiment 7)
Next, a seventh embodiment of the present invention will be described with reference to FIG. FIG. 7 shows the cross-sectional structure of the main part of the semiconductor device according to the present embodiment, and the same reference numerals are given to the common parts with the second embodiment.

図７に示す本実施形態７の半導体装置においては、第２の実施形態による図２の構造の、前記第１の銅配線１２と前記拡散防止絶縁膜２６の界面に、窒化銅層２８が設けられた構造となっている。その他の点はほぼ同一構造であり、第２の実施形態と同様の効果が得られる。   In the semiconductor device of the seventh embodiment shown in FIG. 7, a copper nitride layer 28 is provided at the interface between the first copper wiring 12 and the diffusion prevention insulating film 26 in the structure of FIG. 2 according to the second embodiment. It has a structured. Other points are substantially the same structure, and the same effect as the second embodiment can be obtained.

前記第１の銅配線１２と前記拡散防止絶縁膜２６の界面に、窒化銅層２８を設けることにより、銅原子の絶縁膜中への拡散に対するバリア性を向上させることができ、さらに信頼性の高い半導体装置が得られる。   By providing the copper nitride layer 28 at the interface between the first copper wiring 12 and the diffusion preventing insulating film 26, it is possible to improve the barrier property against diffusion of copper atoms into the insulating film, and to improve reliability. A high semiconductor device can be obtained.

また、窒化銅層２８により銅原子の拡散に対するバリア性を確保することができるので、前記拡散防止絶縁膜２６の膜厚を薄くすることができ、前記拡散防止絶縁膜２６より誘電率の低い第２の層間絶縁膜１５の膜厚を、より厚くすることができ、配線間容量を低減することが可能である。   In addition, since the barrier property against the diffusion of copper atoms can be secured by the copper nitride layer 28, the thickness of the diffusion preventing insulating film 26 can be reduced, and the dielectric constant lower than that of the diffusion preventing insulating film 26 is obtained. The thickness of the second interlayer insulating film 15 can be increased, and the capacitance between wirings can be reduced.

図７における実施形態７においては、前記第１の銅配線１２と前記拡散防止絶縁膜２６の界面にのみ、窒化銅層２８が設けられた場合について示したが、前記第１の銅配線１２とビア１９との界面にも窒化銅層２８が設けられてもよい。
ただし、ビアと配線のコンタクト抵抗低減という観点では、前記第１の銅配線１２と前記拡散防止絶縁膜１３の界面にのみ、窒化銅層２１が設けられた場合の方が好ましい。 In the seventh embodiment in FIG. 7, the case where the copper nitride layer 28 is provided only at the interface between the first copper wiring 12 and the diffusion prevention insulating film 26 is shown. A copper nitride layer 28 may also be provided at the interface with the via 19.
However, from the viewpoint of reducing the contact resistance between the via and the wiring, it is preferable that the copper nitride layer 21 is provided only at the interface between the first copper wiring 12 and the diffusion preventing insulating film 13.

（実施形態８）
次に、本発明における第８の実施形態を図８により説明する。図８は本実施形態による半導体装置の主要部の断面構造を示しており、第２の実施形態と共通の部分には同一の符号を付している。 (Embodiment 8)
Next, an eighth embodiment of the present invention will be described with reference to FIG. FIG. 8 shows the cross-sectional structure of the main part of the semiconductor device according to the present embodiment, and the same reference numerals are given to the common parts with the second embodiment.

図８に示す本実施形態８の半導体装置においては、第２の実施形態による図２の構造の、第２の層間絶縁膜１５のすくなくとも一部に空間部２９を設けた構造となっている。その他の点は同一構造であり、第２の実施形態と同様の効果が得られる。
また、層間絶縁膜の少なくとも一部に空間部２９を設けることにより、配線間容量をさらに低減する効果も得られる。 The semiconductor device according to the eighth embodiment shown in FIG. 8 has a structure in which the space 29 is provided in at least a part of the second interlayer insulating film 15 in the structure of FIG. 2 according to the second embodiment. Other points are the same structure, and the same effect as the second embodiment can be obtained.
Further, by providing the space 29 in at least a part of the interlayer insulating film, an effect of further reducing the inter-wiring capacitance can be obtained.

（実施形態９）
次に、本発明における第９の実施形態を図９により説明する。図９は本実施形態による半導体装置の主要部の断面構造を示しており、第８の実施形態と共通の部分には同一の符号を付している。 (Embodiment 9)
Next, a ninth embodiment of the present invention will be described with reference to FIG. FIG. 9 shows the cross-sectional structure of the main part of the semiconductor device according to the present embodiment, and the same reference numerals are given to the common parts with the eighth embodiment.

図９に示す本実施形態の半導体装置においては、第８の実施形態による図８の構造の、空間部２９が第２の層間絶縁膜１５の層だけではなく、第１の層間絶縁膜１４に設けた構造となっている。その他の点は同一構造であり、第８の実施形態と同様の効果が得られる。
また、第１の層間絶縁膜１４にも空間部２９を設けることにより、配線間容量を第８の実施形態よりもさらに低減する効果が得られる。 In the semiconductor device of the present embodiment shown in FIG. 9, the space 29 of the structure of FIG. 8 according to the eighth embodiment is not limited to the layer of the second interlayer insulating film 15 but the first interlayer insulating film 14. It has a provided structure. The other points have the same structure, and the same effect as in the eighth embodiment can be obtained.
Also, by providing the space 29 in the first interlayer insulating film 14, the effect of further reducing the inter-wiring capacitance as compared with the eighth embodiment can be obtained.

このようにビアが形成されるビアホール側壁に接する領域で、第１の銅配線１２上に、圧縮応力を有する拡散防止絶縁膜１３、引張応力を有する第１の層間絶縁膜１４が積層された構造となっていれば、効果的に銅配線の応力勾配を抑制することができ、ボイドによる抵抗増大を防止することができる。   A structure in which the diffusion preventing insulating film 13 having compressive stress and the first interlayer insulating film 14 having tensile stress are laminated on the first copper wiring 12 in the region in contact with the via hole side wall where the via is formed in this way. If it becomes, it can suppress the stress gradient of a copper wiring effectively, and can prevent the resistance increase by a void.

（実施形態１０）
次に、本発明における第１０の実施形態を図１０により説明する。図１０は本実施形態１０による半導体装置の主要部の断面構造を示しており、第８の実施形態と共通の部分には同一の符号を付している。 (Embodiment 10)
Next, a tenth embodiment of the present invention will be described with reference to FIG. FIG. 10 shows a cross-sectional structure of the main part of the semiconductor device according to the tenth embodiment, and the same reference numerals are given to the common portions with the eighth embodiment.

図１０に示す本実施形態１０の半導体装置においては、第８の実施形態による図８の構造の、第２の層間絶縁膜１５が、その上面に絶縁膜２３に食い込むように形成された構造となっている。その他の点は同一構造であり、第８の実施形態と同様の効果が得られる。   In the semiconductor device according to the tenth embodiment shown in FIG. 10, the second interlayer insulating film 15 of the structure of FIG. 8 according to the eighth embodiment is formed so as to bite into the insulating film 23 on the upper surface. It has become. The other points have the same structure, and the same effect as in the eighth embodiment can be obtained.

また、第２の層間絶縁膜１５が、その上面に絶縁膜２３に食い込むように形成された構造とすることにより、前記第２の層間絶縁膜１５と絶縁膜２３との界面でのはく離を防止することができ、さらに信頼性の高い半導体装置が得られる。   Further, the second interlayer insulating film 15 is formed on the upper surface so as to bite into the insulating film 23, thereby preventing peeling at the interface between the second interlayer insulating film 15 and the insulating film 23. In addition, a highly reliable semiconductor device can be obtained.

（実施形態１１）
次に、本発明における第１１の実施形態を図１１により説明する。図１１は本実施形態１１による半導体装置の主要部の断面構造を示しており、第１０の実施形態と共通の部分には同一の符号を付している。 (Embodiment 11)
Next, an eleventh embodiment of the present invention will be described with reference to FIG. FIG. 11 shows the cross-sectional structure of the main part of the semiconductor device according to the eleventh embodiment, and the same reference numerals are given to the common parts with the tenth embodiment.

図１１に示す本実施形態１１の半導体装置においては、第１０の実施形態による図１０の構造の、絶縁膜２４がなく、絶縁膜２３が低誘電率膜１５の拡散防止絶縁膜とエッチングストッパ膜の両方の役割をするような構造となっている。その他の点は同一構造であり、第１０の実施形態と同様の効果が得られる。
また、本実施形態においては、絶縁膜２４を省略することにより、工程数を減少できるという効果も得られる。 In the semiconductor device according to the eleventh embodiment shown in FIG. 11, the diffusion prevention insulating film and the etching stopper film having the structure shown in FIG. It has a structure that plays both roles. Other points are the same structure, and the same effect as the tenth embodiment can be obtained.
In the present embodiment, the effect that the number of steps can be reduced can be obtained by omitting the insulating film 24.

（実施形態１２）
次に、本発明における第１２の実施形態を図１２により説明する。図１２は本実施形態１２による半導体装置の主要部の断面構造を示しており、第１１の実施形態と共通の部分には同一の符号を付している。 Embodiment 12
Next, a twelfth embodiment of the present invention will be described with reference to FIG. FIG. 12 shows a cross-sectional structure of the main part of the semiconductor device according to the twelfth embodiment, and the same reference numerals are given to the common portions with the eleventh embodiment.

図１２に示す本実施形態の半導体装置においては、第１１の実施形態による図１１の構造の、空間部２９が第１の層間絶縁膜１４に食い込むように形成された構造となっている。その他の点は同一構造であり、第１１の実施形態と同様の効果が得られる。   The semiconductor device of this embodiment shown in FIG. 12 has a structure in which the space 29 of the structure of FIG. 11 according to the eleventh embodiment is formed so as to bite into the first interlayer insulating film 14. The other points have the same structure, and the same effects as those of the eleventh embodiment can be obtained.

また、この場合、空間部２９が第１の層間絶縁膜１４に食い込むように形成された構造とすることにより、第１の層間絶縁膜１４と第２の層間絶縁膜１５との界面でのはく離を防止することができ、さらに信頼性の高い半導体装置が得られる。   In this case, the space 29 is formed so as to bite into the first interlayer insulating film 14, so that the separation at the interface between the first interlayer insulating film 14 and the second interlayer insulating film 15 occurs. Thus, a highly reliable semiconductor device can be obtained.

（実施形態１３）
次に、本発明における第１３の実施形態を図１３により説明する。図１３は本実施形態による半導体装置の主要部の断面構造を示しており、第８の実施形態と共通の部分には同一の符号を付している。 (Embodiment 13)
Next, a thirteenth embodiment of the present invention will be described with reference to FIG. FIG. 13 shows the cross-sectional structure of the main part of the semiconductor device according to the present embodiment, and the same reference numerals are given to the common parts with the eighth embodiment.

図１３に示す本実施形態１３の半導体装置においては、第８の実施形態による図８の構造の、空間部２９がビアホール１７ｂに隣接した構造となっている。その他の点は同一構造であり、第８の実施形態と同様の効果が得られる。
また、空間部２９がビアホール１７ｂに隣接した構造とすることにより、配線間容量をさらに低減する効果が得られる。 In the semiconductor device according to the thirteenth embodiment shown in FIG. 13, the space portion 29 of the structure of FIG. 8 according to the eighth embodiment is adjacent to the via hole 17b. The other points have the same structure, and the same effect as in the eighth embodiment can be obtained.
In addition, since the space portion 29 is adjacent to the via hole 17b, an effect of further reducing the interwiring capacitance can be obtained.

このように、ビア１９が形成されるビアホール１７ｂの側壁に接する領域で、ビア１９に隣接して空間部２９が設けられる場合、第１の銅配線１２上に設けられた、圧縮応力を有する拡散防止絶縁膜１３によって発生する銅配線の応力勾配を抑制するためには、引張応力を有する第１の層間絶縁膜１４が積層された構造とすることにより効果的に銅配線の応力勾配を抑制することができ、ボイドによる抵抗増大を防止することができる。   As described above, when the space portion 29 is provided adjacent to the via 19 in the region in contact with the side wall of the via hole 17 b where the via 19 is formed, the diffusion having compressive stress provided on the first copper wiring 12. In order to suppress the stress gradient of the copper wiring generated by the prevention insulating film 13, the stress gradient of the copper wiring is effectively suppressed by adopting a structure in which the first interlayer insulating film 14 having a tensile stress is laminated. And increase in resistance due to voids can be prevented.

（実施形態１４）
次に、本発明における第１４の実施形態を図１４により説明する。図１４は本実施形態１４による半導体装置の主要部の断面構造を示しており、第１の実施形態と共通の部分には同一の符号を付している。 (Embodiment 14)
Next, a fourteenth embodiment of the present invention will be described with reference to FIG. FIG. 14 shows a cross-sectional structure of the main part of the semiconductor device according to the fourteenth embodiment, and the same reference numerals are given to the common portions with the first embodiment.

図１４に示す本実施形態１４の半導体装置においては、第１の実施形態による図１の構造が、ビア１９と第２の銅配線２０が同じ銅膜で形成されたデュアルダマシン銅配線構造であったのに対し、シングルダマシンプロセスによって形成されたシングルダマシン銅配線構造となっている。ビア１９と第２の銅配線２０がバリア膜１８を介して接合された構造となっている。この場合にも、第１の実施形態と同様の効果が得られる。
なお、その他の実施形態においても、デュアルダマシン銅配線構造の場合についてしめしたが、シングルダマシン銅配線構造とした場合でも同様の効果が得られる。 In the semiconductor device of the fourteenth embodiment shown in FIG. 14, the structure of FIG. 1 according to the first embodiment is a dual damascene copper wiring structure in which the via 19 and the second copper wiring 20 are formed of the same copper film. In contrast, it has a single damascene copper wiring structure formed by a single damascene process. The via 19 and the second copper wiring 20 are joined through the barrier film 18. In this case, the same effect as that of the first embodiment can be obtained.
In the other embodiments, the dual damascene copper wiring structure is shown, but the same effect can be obtained even when the single damascene copper wiring structure is used.

なお、上記各実施形態に示した半導体装置は、これに限定されるものではなく、配線層数も２層に限定されるものではない。また、この半導体装置をＤＲＡＭ（Ｄynamic Ｒandom Ａccess Ｍemory）、ＳＲＡＭ（Ｓtatic Ｒandom Ａccess Ｍemory）、あるいはマイコン等に使用することが可能である。   Note that the semiconductor devices described in the above embodiments are not limited to this, and the number of wiring layers is not limited to two. Further, this semiconductor device can be used for a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a microcomputer, or the like.

以上、本発明者によってなされた発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

本発明の第１の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 1st Embodiment of this invention. 本発明の第３の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第４の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 4th Embodiment of this invention. 本発明の第５の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 5th Embodiment of this invention. 本発明の第６の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 6th Embodiment of this invention. 本発明の第７の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 7th Embodiment of this invention. 本発明の第８の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 8th Embodiment of this invention. 本発明の第９の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 9th Embodiment of this invention. 本発明の第１０の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 10th Embodiment of this invention. 本発明の第１１の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 11th Embodiment of this invention. 本発明の第１２の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by the 12th Embodiment of this invention. 本発明の第１３の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by 13th Embodiment of this invention. 本発明の第１４の実施形態による半導体装置の主要部の断面構造を示す図である。It is a figure which shows the cross-section of the principal part of the semiconductor device by 14th Embodiment of this invention.

符号の説明Explanation of symbols

１…シリコン基板、２…素子分離膜、３…ゲート絶縁膜、４…ゲート電極、５…コンタクトプラグ、６…サイドウォール、７…シリサイド膜、８…絶縁膜、９…第１の線間絶縁膜、１０…配線溝、１１…バリア膜、１２…第１の銅配線、１３…拡散防止絶縁膜、１４…第１の層間絶縁膜、１５…第２の層間絶縁膜、１６…第２の線間絶縁膜、１７ａ…配線溝、１７ｂ…ビアホール、１８…バリア膜、１９…ビア、２０…第２の銅配線、２１…絶縁膜、２２…絶縁膜、２３…絶縁膜、２４…絶縁膜、２５…絶縁膜、２６…拡散防止絶縁膜、２７…第１の層間絶縁膜、２８…窒化銅層、２９…空間部   DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation film, 3 ... Gate insulating film, 4 ... Gate electrode, 5 ... Contact plug, 6 ... Side wall, 7 ... Silicide film, 8 ... Insulating film, 9 ... 1st line insulation Membrane, 10 ... wiring trench, 11 ... barrier film, 12 ... first copper wiring, 13 ... diffusion preventing insulating film, 14 ... first interlayer insulating film, 15 ... second interlayer insulating film, 16 ... second Interline insulating film, 17a ... wiring groove, 17b ... via hole, 18 ... barrier film, 19 ... via, 20 ... second copper wiring, 21 ... insulating film, 22 ... insulating film, 23 ... insulating film, 24 ... insulating film 25 ... insulating film, 26 ... diffusion preventing insulating film, 27 ... first interlayer insulating film, 28 ... copper nitride layer, 29 ... space portion

Claims (13)

半導体基板上に絶縁膜を介在して設けられ、主構成材料が銅からなる第１の配線と、
前記第１の配線上に設けられ、前記第１の配線の銅に対してバリア性を持つ第１の絶縁膜と、
前記第１の絶縁膜上に設けられ、前記第１の絶縁膜の膜応力に対して逆符号の応力を持つ第２の絶縁膜と、
前記第２の絶縁膜上に設けられた第３の絶縁膜と、
前記第３乃至第１の絶縁膜を貫通して前記第１の配線上に設けられたビアと、
前記ビアを介して前記第１の配線に接続された第２の配線とを有することを特徴とする半導体装置。 A first wiring which is provided on a semiconductor substrate with an insulating film interposed therebetween and whose main constituent material is copper;
A first insulating film provided on the first wiring and having a barrier property against copper of the first wiring;
A second insulating film provided on the first insulating film and having a stress opposite in sign to the film stress of the first insulating film;
A third insulating film provided on the second insulating film;
A via provided on the first wiring through the third to first insulating films;
And a second wiring connected to the first wiring through the via. 請求項１に記載の半導体装置において、
前記第１の絶縁膜は、圧縮応力を有し、
前記第２の絶縁膜は、引張応力を有することを特徴とする半導体装置。 The semiconductor device according to claim 1,
The first insulating film has a compressive stress;
The semiconductor device, wherein the second insulating film has a tensile stress. 請求項１に記載の半導体装置において、
前記第１の絶縁膜は、引張応力を有し、
前記第２の絶縁膜は、圧縮応力を有することを特徴とする半導体装置。 The semiconductor device according to claim 1,
The first insulating film has a tensile stress,
The semiconductor device, wherein the second insulating film has a compressive stress. 請求項１に記載の半導体装置において、
前記第１の絶縁膜の膜厚は、前記第２の絶縁膜の膜厚よりも小さいことを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device is characterized in that the thickness of the first insulating film is smaller than the thickness of the second insulating film. 請求項１に記載の半導体装置において、
前記第１の絶縁膜は、前記第２の絶縁膜よりもヤング率が大きく、前記第２の絶縁膜よりも膜厚が小さいことを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the first insulating film has a Young's modulus greater than that of the second insulating film and is smaller than the thickness of the second insulating film. 請求項１に記載の半導体装置において、
前記第２の絶縁膜は、前記第１の配線の銅に対して酸化シリコン膜よりもバリア性が高い絶縁膜であることを特徴とする半導体装置。 The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the second insulating film is an insulating film having a higher barrier property than the silicon oxide film with respect to copper of the first wiring. 請求項１に記載の半導体装置において、
前記第３の絶縁膜は、前記第１及び第２の絶縁膜よりも誘電率が低い絶縁膜からなることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device is characterized in that the third insulating film is made of an insulating film having a lower dielectric constant than the first and second insulating films. 請求項２又は請求項３に記載の半導体装置において、
前記第1の絶縁膜は、少なくとも窒素原子を含む絶縁膜からなることを特徴とする半導体装置。 The semiconductor device according to claim 2 or claim 3,
The semiconductor device, wherein the first insulating film is made of an insulating film containing at least nitrogen atoms. 請求項２又は請求項３に記載の半導体装置において、
前記第３の絶縁膜は、引張応力を有する低誘電率絶縁膜であることを特徴とする半導体装置。 The semiconductor device according to claim 2 or claim 3,
The semiconductor device, wherein the third insulating film is a low dielectric constant insulating film having a tensile stress. 請求項１に記載の半導体装置において、
前記第１の配線と前記第１の絶縁膜との間に、少なくとも一部が窒化された銅からなる層を有することを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device comprising a layer made of copper at least partially nitrided between the first wiring and the first insulating film. 請求項１０に記載の半導体装置において、
前記少なくとも一部が窒化された銅からなる層の厚さは、前記第１の絶縁膜の膜厚よりも小さいことを特徴とする半導体装置。 The semiconductor device according to claim 10.
The semiconductor device according to claim 1, wherein a thickness of the at least partly nitrided copper layer is smaller than a thickness of the first insulating film. 請求項１に記載の半導体装置において、
前記第３の絶縁膜の少なくとも一部に空間部が設けられていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device, wherein a space is provided in at least a part of the third insulating film. 請求項１２に記載の半導体装置において、
前記空間部は、前記ビアの側壁に隣接することを特徴とする半導体装置。 The semiconductor device according to claim 12,
The semiconductor device, wherein the space portion is adjacent to a side wall of the via.
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