JP2006004562A - Input buffer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an input buffer circuit having a sufficient operation margin with respect to a threshold voltage fluctuation of a transistor constituting the circuit. <P>SOLUTION: An input buffer circuit 11 has a differential amplifier circuit 2 comprised of the Pch MOS transistor P 1 and a differential amplifier section 4, a NOR circuit 3 and a reference voltage generation section 5. The Pch MOS transistor P 1 is connected at its source to a high potential side power source Vcc and at its drain to the differential amplifier section 4. A chip enable signal CN is inputted to the gate and the transistor turns on when the potential of the chip enable signal CN is "Low". The differential amplifier section 4 outputs the signal comparing and amplifying the potential of an input signal IN and a reference potential Vref when the Pch MOS transistor P 1 turns on by the input of the input signal IN and the reference potential Vref. The chip enable signal CN and the signal outputted from the differential amplifier circuit 2 are inputted to the NORcircuit3 to performs logic operation and output an output signal OUT. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to an input buffer circuit that generates an internal signal based on an external input signal.

  Digital semiconductor integrated circuits such as memory devices and logic circuits are provided with an input buffer circuit that generates an internal signal based on an external input signal. As the input buffer circuit, a NOR circuit, a NAND circuit, or the like that converts a potential level of an external signal having a specific potential level range into a potential level range suitable for the internal operation of the digital semiconductor integrated circuit is used (for example, a patent). Reference 1).

The NOR circuit and the NAND circuit are composed of a Pch MOS transistor and an Nch MOS transistor. When the variation of the threshold voltage (Vth) of the Pch MOS transistor and the Nch MOS transistor constituting the NOR circuit and the NAND circuit increases, the circuit threshold voltage (Vin) Fluctuates and the operation margin of the input buffer circuit decreases.
JP-A-6-104725 (page 32, FIG. 32)

  The present invention provides an input buffer circuit in which an operation margin is not lowered even when a variation in threshold voltage of transistors constituting the circuit is large.

  In order to achieve the above object, a semiconductor device of one embodiment of the present invention includes a plurality of transistors that are provided between a high-potential-side power supply and a low-potential-side power supply and that are connected in cascade. A reference voltage generator for generating a reference potential obtained by dividing the high-potential side power supply potential, a Pch MOS transistor having a source connected to the high-potential side power supply and a gate to which the mode designation signal is input, and the Pch MOS A differential amplifier circuit provided between the drain of the transistor and the low-potential-side power supply, which inputs the reference potential and the input signal, and compares and amplifies the reference potential and the potential of the input signal; It is characterized by that.

  Furthermore, in order to achieve the above object, a semiconductor device according to another embodiment of the present invention includes a plurality of transistors that are provided between a high-potential side power source and a low-potential side power source, and are connected in cascade. A reference voltage generator for generating a reference potential obtained by dividing the high-potential-side power supply potential, a Pch MOS transistor having a source connected to the high-potential-side power supply and a gate specifying the mode designation signal; A differential amplifier circuit provided between a drain of a Pch MOS transistor and the low-potential side power supply, which inputs the reference potential and an input signal, compares and amplifies the reference potential and the potential of the input signal; And a logic operation circuit that inputs the mode designation signal and the signal output from the differential amplifier circuit, performs a logical operation, and outputs an output signal.

  According to the present invention, it is possible to provide an input buffer circuit in which the operation margin does not decrease even when the threshold voltage of the transistors constituting the circuit varies greatly.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, an input buffer circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 is a circuit block diagram showing an input buffer circuit, FIG. 2 is a circuit diagram showing a differential amplifier of the input buffer circuit, FIG. 3 is a NOR circuit of the input buffer circuit, and FIG. 4 is a reference voltage generator of the input buffer circuit. FIG.

  As shown in FIG. 1, the input buffer circuit 1 includes a differential amplifier circuit 2, a NOR circuit 3, and a reference voltage generator 5, and is provided inside the digital semiconductor integrated circuit.

  The differential amplifier circuit 2 includes a Pch MOS transistor P1 and a differential amplifier unit 4. The Pch MOS transistor P1 has a source connected to the high potential side power supply Vcc, a drain connected to the differential amplifier 4, and a gate to which a chip enable signal CN which is a mode designation signal is input. The potential of the chip enable signal CN ON when “Low”, and OFF when “High”.

  The differential amplifying unit 4 is provided between the drain of the Pch MOS transistor P1 and the low potential side power source Vss, and receives the input signal IN and the reference potential Vref, and the potential of the input signal IN when the Pch MOS transistor P1 is turned on. A signal obtained by comparing and amplifying the reference potential Vref is output to the NOR circuit 3. Here, the signal level of the input signal IN satisfies the 3.3V LVTTL (Low Voltage TTL) input / output interface standard, but the 5V TTL input / output interface standard, SSTL3 (Stub Series Terminated Logic for 3.3). V) The input buffer circuit 1 can cope with the signal level satisfying the input / output interface standard or the input / output interface specification of the power supply voltage of 2 V or less.

  The NOR circuit 3 receives the chip enable signal CN and the signal output from the differential amplifier circuit 2, performs a logical operation, and transmits an output signal OUT to an internal circuit of the digital semiconductor integrated circuit. Here, the internal circuit means various circuits used for memories such as SRAM (static random access memory), DRAM (dynamic random access memory), ROM (read only memory), MPU (micro processor unit), FPU (floating− Various circuits used for logic such as point processing units) or various circuits used for SoC (system on a chip).

  The reference voltage generator 5 receives the chip enable signal CN, is turned on by the potential of the chip enable signal CN, generates a reference potential Vref, and transmits the reference potential Vref to the differential amplifier 4.

  As shown in FIG. 2, the differential amplifying unit 4 includes Pch MOS transistors P2 and P3 and Nch MOS transistors N1 to N3. The source of the PchMOS transistor P2 is connected to the drain of the PchMOS transistor P1, and the gate is connected to the gate of the PchMOS transistor P3. The PchMOS transistor P3 has a source connected to the drain of the PchMOS transistor P1, and a drain connected to the gate. PchMOS transistors P2 and P3 form a current mirror circuit.

  The NchMOS transistor N1 has a drain connected to the drain of the PchMOS transistor P2, and receives an input signal IN at the gate. The NchMOS transistor N2 has a drain connected to the drain of the PchMOS transistor P3 and a reference potential Vref input to the gate. NchMOS transistors N1 and N2 form a differential pair. A differentially amplified signal of the differential amplifier circuit 2 is output from between the drain of the Pch MOS transistor P2 and the drain of the Nch MOS transistor N1.

  The Nch MOS transistor N3 has a drain connected to the sources of the NchMOS transistors N1 and N2, a source connected to the low potential side power source Vss, and a bias potential Vb input to the gate. When the bias potential Vb is “High”, the Nch MOS transistor N3 is turned on to pass a through current to the low potential side power supply Vss side, and when the bias potential Vb is “Low”, the Nch MOS transistor N3 is turned off to increase the difference. The amplifier circuit 2 stops operating.

  As shown in FIG. 3, the NOR circuit 3 includes Pch MOS transistors P4 and P5 and Nch MOS transistors N4 and N5. The source of the Pch MOS transistor P4 is connected to the high potential side power supply Vcc, and the chip enable signal CN is input to the gate. The source of the Pch MOS transistor P5 is connected to the drain of the Pch MOS transistor P4, and the signal output from the differential amplifier circuit 2 is input to the gate. The Nch MOS transistor N4 has a drain connected to the drain of the Pch MOS transistor P5, and a signal output from the differential amplifier circuit 2 is input to the gate. Pch MOS transistor P5 and Nch MOS transistor N4 operate as inverters.

  In the Nch MOS transistor N5, the drain is connected to the drain of the Pch MOS transistor P5 and the drain of the Nch MOS transistor N4, the source is connected to the low potential side power supply Vss, and the chip enable signal CN is input to the gate. Pch MOS transistor P4 and Nch MOS transistor N5 operate as inverters. An output signal OUT is output from the drain of the Nch MOS transistor N5.

  As shown in FIG. 4, the reference voltage generator 5 is composed of Pch MOS transistors P6 to P9. The source of the Pch MOS transistor P6 is connected to the high potential side power supply Vcc, and the chip enable signal CN is input to the gate. The Pch MOS transistor P7 has a source connected to the drain of the Pch MOS transistor P6 and a gate connected to the drain. The source of the Pch MOS transistor P8 is connected to the drain of the Pch MOS transistor P7, and the chip enable signal CN is input to the gate. The Pch MOS transistor P9 has a source connected to the drain of the Pch MOS transistor P8, a gate connected to the source, and a source connected to the low potential side power supply Vss. The reference potential Vref is output from between the drain of the Pch MOS transistor P7 and the source of the Pch MOS transistor P8. Here, the back gates of the Pch MOS transistors P6 to P9 are respectively connected to the sources.

  The reference potential generating unit 5 turns on the Pch MOS transistors P6 and P8 when the potential of the chip enable signal CN is “Low” and outputs the reference potential Vref, and the Pch MOS when the potential of the chip enable signal CN is “High”. The transistors P6 and P8 are turned off to stop the operation. Here, since the Pch MOS transistors P6 to P9 have the same gate length and gate width, the reference potential Vref is ½ Vcc regardless of the threshold voltage (Vth) of the Pch MOS transistors P6 to P9. Can be fixed to.

  As described above, in the input buffer circuit of this embodiment, the input signal IN and the reference potential Vref generated from the reference voltage generator 5 are input, and a signal obtained by comparing and amplifying the potential of the input signal IN and the reference potential Vref is obtained. A differential amplifier circuit 2 for outputting, and a NOR circuit for inputting the input signal IN and the signal output from the differential amplifier circuit 2 to perform a logical operation and outputting an output signal OUT are provided. The differential amplifier circuit 2 includes a current mirror circuit composed of a Pch MOS transistor capable of suppressing the influence of variations in threshold voltage of the transistor and an Nch MOS transistor forming a differential pair, and a reference potential input to the differential amplifier circuit 2 Since Vref can maintain a constant voltage regardless of the threshold voltage value of the Pch MOS transistor constituting the reference voltage generator 5, even when the threshold voltage of the Pch MOS transistor and the Nch MOS transistor constituting the circuit varies greatly. Therefore, it is possible to suppress a decrease in the operation margin of the circuit threshold voltage (Vin) as compared with a conventional input buffer circuit using a NOR circuit or a NAND circuit.

  In this embodiment, the input buffer circuit 1 has a two-stage configuration of a differential amplifier circuit 2 and a NOR circuit 3, but a waveform shaping circuit, an inverter, and the like are provided between the differential amplifier circuit 2 and the NOR circuit 3. It may be a three-stage configuration or more. Further, a NAND circuit or the like may be used instead of the NOR circuit 3. The input buffer circuit 1 may be configured by a differential amplifier circuit 2 and a reference potential generator 5.

Further, although a silicon oxide film is used as the gate insulating film of the PchMOS transistor and the NchMOS transistor constituting the input buffer circuit 1, a SiNxOy film obtained by nitriding a silicon oxide film, a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film Alternatively, a high-dielectric film (High-K gate insulating film) may be used. As the high dielectric film, an oxide of Hf (hafnium), Zr (zirconium), La (lanthanum), or a silicate thereof (for example, HfSiON) may be used.

  Next, an input buffer circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 is a circuit block diagram showing an input buffer circuit, FIG. 6 is a circuit diagram showing a first latch circuit of the input buffer circuit, and FIG. 7 is a circuit diagram showing a second latch circuit of the input buffer circuit. In this embodiment, the differential amplifier circuit and the reference voltage generator used in the first embodiment are used.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 5, the input buffer circuit 1a includes a first input circuit section 6a, a second input circuit section 6b, a second NOR circuit 3b, and a third latch circuit 8c, and a digital semiconductor integrated circuit Is provided inside.

  The first input circuit section 6a includes a first differential amplifier circuit 2a, a NAND circuit 7, a first latch circuit 8a, a Pch MOS transistor P11, an inverter 9a, and a first inverter 9b.

  The first differential amplifier circuit 2a includes a Pch MOS transistor (first Pch MOS transistor) P10 and a first differential amplifier section 4a, and has a circuit configuration similar to that of FIG. The source of the Pch MOS transistor P10 is connected to the high potential side power supply Vcc, and the signal output from the NAND circuit 7 is input to the gate. The first differential amplifier 4a is provided between the drain of the Pch MOS transistor P10 and the low-potential power supply Vss, and receives an input signal IN and a reference potential Vref generated from the reference voltage generator 5 (not shown). To do.

  The NAND circuit 7 receives the input signal IN, the signal obtained by inverting the logic level of the chip enable signal CN by the inverter 9a, and the output signal of the first input circuit unit 6a (the output signal D of the first inverter). The calculated signal is transmitted to the gate of the Pch MOS transistor P10.

  The first latch circuit 8a receives the input signal IN as a set signal, receives the output signal of the first differential amplifier circuit 2a, and resets the set signal. The signal output from the first latch circuit 8a is transmitted to the first inverter 9b. The first inverter 9b inverts the logic level of the signal output from the second latch circuit 8b.

  The Pch MOS transistor P11 has a source connected to the high potential side power supply Vcc, a drain connected to the output side of the first inverter 9b and the input side of the NAND circuit 7, and an input signal IN input to the gate. The signal is turned on when the potential of the input signal IN is “Low”, and turned off when the potential of the input signal IN is “High”.

  The second input circuit unit 6b includes a second differential amplifier circuit 2b, a first NOR circuit 3a, a second latch circuit 8b, an Nch MOS transistor N6, a second inverter 9c, and a third inverter 9d. It is configured.

  The second differential amplifier circuit 2b includes a Pch MOS transistor (second Pch MOS transistor) P12 and a second differential amplifier 4b, and has the same circuit configuration as that of FIG. The source of the Pch MOS transistor P12 is connected to the high potential side power supply Vcc, and a signal obtained by inverting the logic level of the signal output from the first NOR circuit 3a by the second inverter 9c is input to the gate. The second differential amplifier 4b is provided between the drain of the Pch MOS transistor P12 and the low-potential side power supply Vss, and receives an input signal IN and a reference potential Vref generated from the reference voltage generator 5 (not shown). To do.

  The first NOR circuit 3a receives the input signal IN, the chip enable signal CN, and the output signal of the second input circuit unit 6b (the output signal DD of the third inverter), and outputs a signal obtained by logical operation to the second NOR circuit 3a. It transmits to the inverter 9c.

  The second latch circuit 8b receives the input signal IN as a set signal, receives the output signal of the second differential amplifier circuit 2b, and resets the set signal. The signal output from the second latch circuit 8b is transmitted to the third inverter 9d. The third inverter 9d inverts the logic level of the signal output from the second latch circuit 8b.

  The Nch MOS transistor N6 has a drain connected to the output side of the third inverter 9d and the input side of the first NOR circuit 3a, a source connected to the low potential side power source Vss, and an input signal IN inputted to the gate. . The signal is turned on when the potential of the input signal IN is “High”, and turned off when the potential of the input signal IN is “Low”.

  The second NOR circuit 3b includes Pch MOS transistors P13 and P14, and Nch MOS transistors N7 and N8. The source of the Pch MOS transistor P13 is connected to the high potential side power supply Vcc, and the signal output from the first input circuit unit 6a is input to the gate. The source of the Pch MOS transistor P14 is connected to the drain of the Pch MOS transistor P13, and the chip enable signal CN is input to the gate. In the Nch MOS transistor N7, the drain is connected to the drain of the Pch MOS transistor P14, the source is connected to the low potential side power supply Vss, and the signal output from the second input circuit unit 6b is input to the gate. The Nch MOS transistor N8 has a drain connected to the drain of the Pch MOS transistor P14 and the drain of the Nch MOS transistor N7, a source connected to the low potential side power supply Vss, and a chip enable signal CN input to the gate. An output signal OUT is output from the drain of the Nch MOS transistor N8.

  The third latch circuit 8c includes inverters 9e and 9f connected in cascade. Inverter 9e has one end connected between the drain of Pch MOS transistor P14 and the drain of Nch MOS transistor N8, and the other end connected to one end of inverter 9f. The other end of the inverter 9f is connected between the drain of the Nch MOS transistor N8 and the drain of the Nch MOS transistor N7. The third latch circuit 8c serves to stabilize the level of the output signal OUT of the second NOR circuit 3b.

  As shown in FIG. 6, the first latch circuit 8a includes Pch MOS transistors P15 and P16, and Nch MOS transistors N9 to N11.

  In the Pch MOS transistor P15, the source is connected to the high potential side power supply Vcc, and the input signal IN is input to the gate. The Nch MOS transistor N9 has a drain connected to the drain of the Pch MOS transistor P15 and an input signal IN input to the gate. The Nch MOS transistor N10 has a drain connected to the source of the Nch MOS transistor N9, a source connected to the low potential side power supply Vss, and a gate connected to the drain of the Pch MOS transistor P16 and the drain of the Nch MOS transistor N11. Then, when a “High” potential is input to the gate of the Nch MOS transistor N10 and the Nch MOS transistor N10 is turned on, the Pch MOS transistor P15 and the Nch MOS transistor N9 operate as an inverter, and the signal is transmitted to the Pch MOS transistor P16 and Nch. Transmit to the gate of the MOS transistor N11.

  The source of the Pch MOS transistor P16 is connected to the high potential side power supply Vcc, and the output of the inverter composed of the Pch MOS transistor P15 and the Nch MOS transistor N9 and the signal output from the first differential amplifier circuit 2a are input to the gate. The The Nch MOS transistor N11 has a drain connected to the drain of the Pch MOS transistor P16, a source connected to the low-potential side power supply Vss, and a first difference from the output of the inverter formed of the Pch MOS transistor P15 and the Nch MOS transistor N9 at the gate. The signal output from the dynamic amplification circuit 2a is input. The Pch MOS transistor P16 and the Nch MOS transistor N11 perform an inverter operation. A signal logically operated as the first latch circuit 8a is transmitted to the first inverter 9b from between the drain of the Pch MOS transistor P16 and the drain of the Nch MOS transistor N11.

  As shown in FIG. 7, the second latch circuit 8b includes Pch MOS transistors P17 to P19 and Nch MOS transistors N12 and N13.

  In the Pch MOS transistor P17, the source is connected to the high potential side power supply Vcc, and the input signal IN is input to the gate. The Pch MOS transistor P18 has a source connected to the drain of the Pch MOS transistor P17, and a gate connected to the drain of the Pch MOS transistor P19 and the drain of the Nch MOS transistor N13. The Nch MOS transistor N12 has a drain connected to the drain of the Pch MOS transistor P18, a source connected to the low potential power source Vss, and an input signal IN input to the gate.

  Then, when a “Low” potential is input to the gate of the Pch MOS transistor P18 and the Pch MOS transistor P18 is turned on, the Pch MOS transistor P17 and the Nch MOS transistor N12 operate as inverters, and the signals are transferred to the Pch MOS transistor P19 and the Pch MOS transistor P19. Transmit to the gate of the Nch MOS transistor N13.

  The source of the Pch MOS transistor P19 is connected to the high potential side power supply Vcc, and the output of the inverter composed of the Pch MOS transistor P17 and the Nch MOS transistor N12 and the signal output from the second differential amplifier circuit 2b are input to the gate. The The Nch MOS transistor N13 has a drain connected to the drain of the Pch MOS transistor P19, a source connected to the low-potential side power supply Vss, and a second difference from the output of the inverter comprising the Pch MOS transistor P17 and the Nch MOS transistor N12 at the gate. The signal output from the dynamic amplification circuit 2b is input. The Pch MOS transistor P19 and the Nch MOS transistor N13 perform an inverter operation. A signal logically operated as the second latch circuit 8b is transmitted to the third inverter 9d from between the drain of the Pch MOS transistor P19 and the drain of the Nch MOS transistor N13.

  Next, the operation of the differential amplifier circuit will be described with reference to FIGS. FIG. 8 is a timing chart showing the operation of the first differential amplifier circuit, and FIG. 9 is a timing chart showing the operation of the second differential amplifier circuit.

  As shown in FIG. 8, the operation of the first differential amplifier circuit 2a starts with the output of the NAND circuit being the output potential of the NAND circuit 7 when the potential of the input signal IN changes from “Low” to “High”. The signal A changes from “High” to “Low”.

  Next, when the output signal A of the NAND circuit becomes “Low”, the Pch MOS transistor P10 of the first differential amplifier circuit 2a is turned on, and the first differential amplifier circuit 2a starts operating, and the input signal IN And a reference potential Vref (1/2 Vcc, “High” potential) output from the reference voltage generator 5 and a first output that is the output potential of the first differential amplifier circuit 2a. The output signal B of the differential amplifier circuit becomes “Low”.

  Subsequently, when the potential “Low” of the output signal B of the first differential amplifier circuit is input to the first latch circuit 8a, the first latch circuit 8a outputs the “Low” signal which is the previous data. And the output signal C of the first latch circuit, which is the potential of the output of the first latch circuit 8a, changes from "Low" to "High".

  Then, the first inverter 9b sets the potential “High” of the output signal C of the first latch circuit to “Low”, inverts the logic level, and sets the potential “Low” of the output signal D of the first inverter. The data is transmitted to the NAND circuit 7 and the second NOR circuit 3b.

  Next, the NAND circuit 7 receives the potential “High” of the input signal IN, the potential “High” of the signal obtained by inverting the logic level of the chip enable signal CN, and the potential “Low” of the output signal D of the first inverter. Then, the potential “High” of the output signal A of the NAND circuit which is the potential of the output of the NAND circuit 7 is output. By this signal, the Pch MOS transistor P10 is turned off and the operation of the first differential amplifier circuit 2a is stopped.

  Here, the operation period 11 of the first differential amplifier circuit is the sum of the times when the first differential amplifier circuit 2a, the first latch circuit 8a, the first inverter 9b, and the NAND circuit 7 are turned on. is there. Since the Pch MOS transistor P11 has “High” as the potential of the input signal IN input to the gate, the operation is stopped during the operation period 11 of the first differential amplifier circuit.

  As shown in FIG. 9, the operation of the second differential amplifier circuit 2b is such that when the potential of the input signal IN changes from “High” to “Low”, the logic level of the output of the first NOR circuit 3a is inverted. The output signal AA of the second inverter, which is the potential of the second inverter 9c, changes from “High” to “Low”.

  Next, when the output signal AA of the second inverter becomes “Low”, the Pch MOS transistor P12 of the second differential amplifier circuit 2b is turned on, and the second differential amplifier circuit 2b starts operating, The potential “Low” of the signal IN and the reference potential Vref (1/2 Vcc and “High” potential) output from the reference voltage generation unit 5 are input and the potential of the output of the second differential amplifier circuit 2 b. The output signal BB of the second differential amplifier circuit becomes “High”.

  Subsequently, when the potential “High” of the output signal BB of the second differential amplifier circuit is input to the second latch circuit 8 b, the second latch circuit 8 b receives the “High” signal that is the previous data. Is reset, and the output signal CC of the second latch circuit, which is the potential of the output of the second latch circuit 8b, changes from "High" to "Low".

  Then, the third inverter 9d inverts the logic level of the output signal CC of the second latch circuit “Low” to “High” and inverts the logic level to set the potential “High” of the output signal DD of the third inverter. The data is transmitted to the first NOR circuit 3a and the second NOR circuit 3b.

  Next, the first NOR circuit 3a receives the potential “Low” of the input signal IN, the potential “Low” of the chip enable signal CN, and the potential “High” of the output signal DD of the third inverter, and inputs “Low”. "" Is output.

  The second inverter 9c receives the potential “Low” of the output of the first NOR circuit 3a and applies the potential “High” of the output signal AA of the second inverter whose logic level is inverted to the Pch MOS transistor P12. Send to the gate. By this signal, the Pch MOS transistor P12 is turned off and the operation of the second differential amplifier circuit 2b is stopped.

  Here, the operation period 12 of the second differential amplifier circuit includes the second differential amplifier circuit 2b, the second latch circuit 8b, the third inverter 9d, the first NOR circuit 3a, and the second inverter. 9c is the sum of the times when each is turned on. Note that the N-channel MOS transistor N6 is stopped during the operation period 12 of the second differential amplifier circuit because “Low” which is the potential of the input signal IN is input to the gate.

  Next, the operation of the input buffer circuit will be described with reference to FIG. FIG. 10 is a timing chart showing the operation of the input buffer circuit. Here, the input signal has a duty of 50% -50%, and the potential of the chip enable signal is set to “Low” for one cycle of the input signal.

  As shown in FIG. 10, the operation of the input buffer circuit 1a is as follows. First, when the input signal IN changes from “Low” to “High”, the first differential amplification circuit 2a is turned on, and the first differential amplification is performed. The output signal B of the circuit becomes “Low”. At this time, since the second differential amplifier circuit 2b is not turned on, the initial state (here, “High”) is maintained. Next, as described with reference to FIG. 8, the first latch circuit 8a and the first inverter 9b operate, and the potential of the output signal D of the first inverter (the output of the first input circuit section 6a) D becomes “Low”. To change.

  Subsequently, the input buffer circuit 1a receives the output potential “Low” of the first input circuit section 6a and the potential “Low” of the output of the second input circuit section 6b (the output signal DD of the third inverter). Then, a logical operation is performed to output the potential changed from “Low” to “High”.

  Next, when the input signal IN changes from “High” to “Low”, the first latch circuit 8a inputs the potential “Low” of the input signal IN and the potential of the output signal C of the first latch circuit. Is changed from “High” to “Low”. The first inverter 9b inverts the potential “Low” of the output signal C of the first latch circuit, and changes the potential of the output signal D of the first inverter (output of the first input circuit portion 6a) “Low”. "" To "High".

  When the input signal IN changes from “High” to “Low”, the second input circuit portion 6b also operates simultaneously. That is, first, the second differential amplifier circuit 2b is turned on, and the output signal BB of the second differential amplifier circuit becomes “High”. Next, as described in FIG. 9, the second latch circuit 8b and the third inverter 9d operate, and the potential of the output signal DD of the third inverter (the output of the second input circuit portion 6b) DD is “High”. To change.

  Subsequently, the input buffer circuit 1a inputs the output potential “High” of the first input circuit section 6a and the output potential “High” of the second input circuit section 6b, and performs a logical operation to “High”. The potential changed from “Low” to “Low” is output.

  Next, the through current of the differential amplifier circuit will be described with reference to FIG. FIG. 11 is a diagram illustrating a through current of the differential amplifier circuit.

  As shown in FIG. 11, in the differential amplifier circuit, when the potential of the input signal IN is “High”, the period during which the first differential amplifier circuit 2a is operating (the operation period of the first differential amplifier circuit). 11) when a through current of the first differential amplifier circuit 2a is generated and the potential of the input signal IN is "Low", the period during which the second differential amplifier circuit 2b is operating (second differential). A through current of the second differential amplifier circuit 2b is generated only during the operation period 12) of the amplifier circuit. Here, the first differential amplifier circuit 2a, the NAND circuit 7, the first latch circuit 8a, the first inverter 9b, the second differential amplifier circuit 2b, the first NOR circuit 3a, and the second latch circuit The switching operation time of 8b, the second inverter 9c, and the third inverter 9d is very short with respect to one period 13 of the input signal IN. For example, when one cycle 13 of the input signal IN is 100 ns (“High” period 50 ns, “Low” period 50 ns), the switching operation time is 1 ns or less. For this reason, the operation period 11 of the first differential amplifier circuit and the operation period 12 of the second differential amplifier circuit can each be 5 ns or less, and the period during which the through current is generated is reduced to 10% or less. Can do.

  As described above, in the input buffer circuit according to the present embodiment, the first difference in which the operation margin of the circuit threshold voltage (Vin) does not decrease even when the threshold voltage of the Pch MOS transistor and the Nch MOS transistor constituting the circuit is large. A dynamic amplifier circuit 2a and a second input circuit section 6b are provided. The first differential amplifier circuit 2a operates only when the potential of the output signal A of the NAND circuit is “Low” to generate a through current, and the second differential amplifier circuit 2b outputs the output of the second inverter. Since it operates only when the potential of the signal AA is “Low” and generates a through current, in addition to the effects of the first embodiment, the through current of the differential amplifier circuit is reduced more than the first embodiment, and the input buffer circuit Current consumption can be reduced.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the second embodiment, an R / S latch circuit having an inverter configuration is used for the first latch circuit 8a and the second latch circuit 8b, but an R / S latch circuit having a NOR circuit configuration or a NAND circuit configuration is used. Also good. Further, a NOR circuit may be used instead of the NAND circuit 7. In this case, an inverter or the like is preferably provided on the input side or the output side of the NOR circuit so as to be the same as the timing chart of the output signal A of the NAND circuit shown in FIG. A NAND circuit may be used instead of the first NOR circuit 3a. In this case, an inverter or the like is preferably provided on the input side or the output side of the NAND circuit so as to be the same as the timing chart of the output signal AA of the second inverter shown in FIG. Furthermore, a NAND circuit may be used instead of the second NOR circuit 3b.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A NAND circuit that inputs an input signal, a signal obtained by inverting the logic level of a mode designation signal, and an output signal as feedback, and outputs a signal by performing a logical operation, and a source are connected to the high-potential side power supply, A first Pch MOS transistor to which a signal output from the NAND circuit is input to a gate, and a plurality of transistors connected in cascade between a drain of the first Pch MOS transistor and a low potential power source A reference voltage output from a reference voltage generator that generates a reference potential obtained by dividing the high-potential-side power supply potential by inputting a mode designation signal and the input signal, and the reference potential and the input signal A first differential amplifier that outputs a signal obtained by comparing and amplifying the potential; and the input signal is input as a set signal, and the signal output from the first differential amplifier is A first latch circuit that is input as a set signal and resets the set signal; and a first inverter that inverts the logic level of the signal output from the first latch circuit. The output signal is input as a feedback output signal to the first input circuit unit input to the NAND circuit, and the input signal, the mode designation signal, and the output signal as feedback are input and logically operated. A first NOR circuit that outputs a signal, a second inverter that inverts the logic level of the signal output from the first NOR circuit, a source connected to the high-potential-side power supply, and a gate connected to the first NOR circuit Between the drain of the second Pch MOS transistor and the low-potential-side power supply. A second differential amplifying unit provided to input the reference potential generated from the reference voltage generating unit and the input signal, and to output a signal obtained by comparing and amplifying the reference potential and the potential of the input signal; An input signal is input as a set signal, a signal output from the second differential amplifier is input as a reset signal, and a second latch circuit that resets the set signal is output from the second latch circuit A second inverter that inverts the logic level of the generated signal, and that the signal output from the third inverter is input to the first NOR circuit as an output signal as feedback. A circuit unit, the mode designation signal, a signal output from the first inverter of the first input circuit unit, and a signal output from the third inverter of the second input circuit unit. And a logical operation circuit that performs logical operation and outputs an output signal, and a third latch circuit that includes two inverters connected in cascade, one end and the other end of the inverter being connected to the logical operation circuit, An input buffer circuit comprising:

(Supplementary note 2) The input buffer circuit according to supplementary note 1, wherein the logical operation circuit is a NOR circuit or a NAND circuit.

(Supplementary note 3) The first differential amplification unit and the second differential amplification unit each include an Nch MOS transistor that forms a differential pair with a current mirror circuit including a Pch MOS transistor. Input buffer circuit.

(Supplementary Note 4) The input buffer circuit according to any one of Supplementary Notes 1 to 4, wherein the first latch circuit and the second latch circuit are configured by an inverter, a NOR circuit, or a NAND circuit.

1 is a circuit block diagram showing an input buffer circuit according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a differential amplifier section of an input buffer circuit according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a NOR circuit of an input buffer circuit according to Embodiment 1 of the present invention. FIG. 3 is a circuit diagram illustrating a reference voltage generation unit of the input buffer circuit according to the first embodiment of the invention. FIG. 6 is a circuit block diagram illustrating an input buffer circuit according to a second embodiment of the present invention. FIG. 6 is a circuit diagram showing a first latch circuit of an input buffer circuit according to Embodiment 2 of the present invention. FIG. 6 is a circuit diagram showing a second latch circuit of an input buffer circuit according to Embodiment 2 of the present invention. 9 is a timing chart illustrating an operation of the first differential amplifier circuit of the input buffer circuit according to the second embodiment of the invention. 9 is a timing chart showing the operation of the second differential amplifier circuit of the input buffer circuit according to the second embodiment of the present invention. 9 is a timing chart showing the operation of the input buffer circuit according to the second embodiment of the present invention. The figure which shows the through-current of the differential amplifier circuit which concerns on Example 2 of this invention.

Explanation of symbols

1, 1a input buffer circuit 2 differential amplifier circuit 2a first differential amplifier circuit 2b second differential amplifier circuit 3 NOR circuit 3a first NOR circuit 3b second NOR circuit 4 differential amplifier 4a first Differential amplifier 4b second differential amplifier 5 reference voltage generator 6a first input circuit 6b second input circuit 7 NAND circuit 8a first latch circuit 8b second latch circuit 8c third latch Circuits 9a, 9e, 9f Inverter 9b First inverter 9c Second inverter 9d Third inverter 11 First differential amplifier circuit operating period 12 Second differential amplifier circuit operating period 13 Input signal IN 1 Cycle A NAND circuit output signal AA second inverter output signal B first differential amplifier circuit output signal BB second differential amplifier circuit output signal C first latch circuit output signal CC second latch Path output signal CN Chip enable signal D Output signal DD of first inverter Output signal IN of third inverter IN Input signals P1-P9, P11, P13, P14 Pch MOS transistor P10 Pch MOS transistor (first Pch MOS transistor) )
P12 Pch MOS transistor (second Pch MOS transistor)
N1 to N13 Nch MOS transistor Vb Bias potential Vcc High potential side power supply Vref Reference potential Vss Low potential side power supply

Claims (5)

A reference voltage generator that is provided between a high-potential side power supply and a low-potential side power supply, has a plurality of cascade-connected transistors, and inputs a mode designation signal to generate a reference potential obtained by dividing the high-potential side power supply potential And
A Pch MOS transistor whose source is connected to the high potential side power supply and whose mode designation signal is inputted to the gate, and provided between the drain of the Pch MOS transistor and the low potential side power supply, and the reference potential and the input signal A differential amplifier circuit that compares and amplifies the reference potential and the potential of the input signal, and
An input buffer circuit comprising: A reference voltage generator that is provided between a high-potential side power supply and a low-potential side power supply, has a plurality of cascade-connected transistors, and inputs a mode designation signal to generate a reference potential obtained by dividing the high-potential side power supply potential And
A Pch MOS transistor whose source is connected to the high potential side power supply and whose mode designation signal is inputted to the gate, and provided between the drain of the Pch MOS transistor and the low potential side power supply, and the reference potential and the input signal A differential amplifier circuit that compares and amplifies the reference potential and the potential of the input signal, and
A logical operation circuit that inputs the mode designation signal and the signal output from the differential amplifier circuit, performs a logical operation, and outputs an output signal;
An input buffer circuit comprising:   3. The input buffer circuit according to claim 2, wherein the logical operation circuit is a NOR circuit or a NAND circuit. A NAND circuit that inputs an input signal, a signal obtained by inverting the logic level of the mode designation signal, and an output signal as feedback, outputs a signal by performing a logical operation, a source is connected to the high-potential side power supply, and the NAND is connected to the gate A first Pch MOS transistor to which a signal output from the circuit is input, and a plurality of transistors connected in cascade between the drain of the first Pch MOS transistor and the low potential side power supply, A reference potential output from a reference voltage generator that generates a reference potential obtained by dividing a high-potential-side power supply potential by inputting a specified signal is input to the input signal, and the reference potential is compared with the potential of the input signal. A first differential amplifier for outputting an amplified signal; and the input signal is input as a set signal, and the signal output from the first differential amplifier is a reset signal. And a first inverter that resets the set signal and a first inverter that inverts the logic level of the signal output from the first latch circuit, and is output from the first inverter. A first input circuit unit that is input to the NAND circuit as an output signal as feedback.
A first NOR circuit that inputs the input signal, the mode designation signal, and an output signal as feedback, outputs a signal by performing a logical operation, and inverts the logic level of the signal output from the first NOR circuit And a second Pch MOS transistor having a source connected to the high-potential side power source and a gate receiving a signal output from the second inverter, and a second Pch MOS transistor. Provided between the drain and the low-potential side power supply, inputs the reference potential output from the reference voltage generator and the input signal, and outputs a signal obtained by comparing and amplifying the reference potential and the potential of the input signal A second differential amplifier that inputs the input signal as a set signal, and a signal that is output from the second differential amplifier as a reset signal. A second latch circuit for resetting the signal and a third inverter for inverting the logic level of the signal output from the second latch circuit, and the signal output from the third inverter is used as feedback. A second input circuit unit input to the first NOR circuit as an output signal;
The mode designation signal, a signal output from the first inverter of the first input circuit unit, and a signal output from the third inverter of the second input circuit unit are input, and logic A logical operation circuit that calculates and outputs an output signal;
An input buffer circuit comprising:   The input buffer circuit according to claim 4, wherein the logical operation circuit is a NOR circuit or a NAND circuit.

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