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JP2006093324A - Wiring board - Google Patents

Wiring board Download PDF

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Publication number
JP2006093324A
JP2006093324A JP2004275519A JP2004275519A JP2006093324A JP 2006093324 A JP2006093324 A JP 2006093324A JP 2004275519 A JP2004275519 A JP 2004275519A JP 2004275519 A JP2004275519 A JP 2004275519A JP 2006093324 A JP2006093324 A JP 2006093324A
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Prior art keywords
wiring board
signal
wiring
line
differential line
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JP4511294B2 (en
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Koki Kawabata
幸喜 川畑
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board where operability of a semiconductor element can be made sufficient by suppressing reflection loss of a high frequency signal which occurs from impedance discontinuity of a signal line in a developing part of a differential line, to be very small. <P>SOLUTION: In the wiring board, the differential line 8 formed of a pair of mutually parallel signal lines 8a and 8b is formed on an upper face of an insulating substrate 2. In the differential line 8, one end is set to be the developing part 8d where an interval between a pair of signal lines 8a and 8b gradually spreads, and thickness of the developing part 8d becomes thicker than that of a part except for the developing part 8d. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、高速で作動する半導体素子や光半導体素子等の電子部品を搭載するのに好適な、差動線路を有する配線基板に関する。   The present invention relates to a wiring board having a differential line suitable for mounting electronic components such as a semiconductor element and an optical semiconductor element that operate at high speed.

従来、高速で作動する半導体素子や光半導体素子等の電子部品を搭載するための配線基板において、従来例の断面図である図4に示すように、高速信号を正確かつ効率よく伝播させるために、差動線路48が用いられる。差動線路48は、従来例の部分断面図である図5に示すように、信号線路48a,48bの幅、間隔、厚み、および信号線路48a,48bと内層接地導体層44aとの間に介在する絶縁層42aの厚みを調整し設定することにより、差動線路48における差動インピーダンス値を任意の値に設定することができるため、良好な伝送特性を有する差動線路48を形成することができる。差動線路48の差動インピーダンスは、一般的には100Ωに設定される場合が多い。   Conventionally, in a wiring board for mounting electronic components such as semiconductor elements and optical semiconductor elements that operate at high speed, as shown in FIG. 4 which is a sectional view of a conventional example, in order to propagate high-speed signals accurately and efficiently A differential line 48 is used. As shown in FIG. 5, which is a partial sectional view of a conventional example, the differential line 48 is interposed between the signal lines 48a and 48b and the inner ground conductor layer 44a. Since the differential impedance value in the differential line 48 can be set to an arbitrary value by adjusting and setting the thickness of the insulating layer 42a to be formed, the differential line 48 having good transmission characteristics can be formed. it can. In general, the differential impedance of the differential line 48 is often set to 100Ω.

また、差動線路48は、半導体素子45と導体バンプ46および半導体素子接続用電極47を介して電気的に接続され、また信号貫通導体49を介して外部入出力用電極410と電気的に接続されている。
特開2002−9511号公報
The differential line 48 is electrically connected to the semiconductor element 45 via the conductor bump 46 and the semiconductor element connection electrode 47, and electrically connected to the external input / output electrode 410 via the signal through conductor 49. Has been.
JP 2002-9511 A

しかしながら、従来の配線基板41上に形成された差動線路48においては、図6に示すように、差動インピーダンスが例えば約100Ωになるように設計された一対の信号線路48a,48b間の間隔が一定である一定部48cに対し、2次実装部である外部入出力用電極410の配列間隔に合わせて一対の信号線路48a,48b間の間隔が漸次広がる展開部48dが形成されている。この展開部48dにおいては、差動線路48の線路間隔が変化することから差動インピーダンスが100Ωからずれて高くなり、一定部48cと展開部48dとにおいてインピーダンスの不整合が起こり、反射損失が大きくなり高周波信号の伝送が阻害され、半導体素子45の作動性が損なわれるという問題点があった。   However, in the differential line 48 formed on the conventional wiring substrate 41, as shown in FIG. 6, the distance between the pair of signal lines 48a and 48b designed so that the differential impedance is about 100Ω, for example. In contrast to the constant portion 48c having a constant width, a development portion 48d is formed in which the interval between the pair of signal lines 48a and 48b gradually increases in accordance with the arrangement interval of the external input / output electrodes 410 as the secondary mounting portion. In the expanded portion 48d, the differential impedance increases from 100Ω because the line spacing of the differential line 48 changes, and impedance mismatch occurs between the constant portion 48c and the expanded portion 48d, resulting in a large reflection loss. As a result, the transmission of high-frequency signals is hindered, and the operability of the semiconductor element 45 is impaired.

本発明は、上記問題点に鑑み完成されたものであり、その目的は、差動線路の線路間隔が広がる展開部分において生じる高周波信号の反射損失を非常に小さなものに抑制することができ、それにより半導体素子の作動性を良好なものとできる配線基板を提供することにある。   The present invention has been completed in view of the above problems, and its purpose is to suppress the reflection loss of the high-frequency signal generated in the expanded portion where the line spacing of the differential line is widened to a very small value. Accordingly, an object of the present invention is to provide a wiring board capable of improving the operability of the semiconductor element.

本発明の配線基板は、絶縁基体の上面に互いに平行な一対の信号線路から成る差動線路が形成された配線基板において、前記差動線路は、一端部が前記一対の信号線路同士の間の間隔が漸次広がっている展開部とされているとともに、前記信号線路の前記展開部の厚みが前記展開部以外の部位の厚みよりも厚いことを特徴とする。   The wiring board of the present invention is a wiring board in which a differential line composed of a pair of signal lines parallel to each other is formed on an upper surface of an insulating base, and the differential line has one end portion between the pair of signal lines. The width of the developed portion of the signal line is larger than the thickness of the portion other than the developed portion.

本発明の配線基板は好ましくは、前記信号線路は、前記展開部の下側が前記絶縁基板に埋め込まれていることを特徴とする。   The wiring board according to the present invention is preferably characterized in that the signal line is embedded in the insulating substrate under the development portion.

また、本発明の配線基板は好ましくは、前記信号線路は、前記展開部の前記絶縁基板に埋め込まれている下側の厚みが前記絶縁基板から露出している上側の厚みよりも厚いことを特徴とする。   In the wiring board of the present invention, it is preferable that the signal line has a lower thickness embedded in the insulating substrate of the development portion than an upper thickness exposed from the insulating substrate. And

また、本発明の配線基板は好ましくは、前記絶縁基板は、下面または内部に前記差動線路と対向するように接地導体が形成されていることを特徴とする。   The wiring board of the present invention is preferably characterized in that a ground conductor is formed on the lower surface or inside of the insulating substrate so as to face the differential line.

本発明の配線基板は、配線基板上に形成された差動線路について、差動線路の信号線路同士の間の間隔が漸次広がっている展開部においてそれぞれの信号線路の厚みが展開部以外の部位の厚みよりも厚いことから、展開部においては、一対の信号線路の誘導成分の減少及び容量成分の増加により差動インピーダンスが減少する。その結果、展開部における差動インピーダンスの不整合による高周波信号の反射損失を抑えることが可能となる。   In the wiring board of the present invention, with respect to the differential lines formed on the wiring board, the thickness of each signal line is a part other than the developed part in the developed part where the distance between the signal lines of the differential line gradually increases. Therefore, in the expanded portion, the differential impedance decreases due to a decrease in the inductive component and an increase in the capacitance component of the pair of signal lines. As a result, it is possible to suppress the reflection loss of the high frequency signal due to the mismatch of the differential impedance in the development part.

本発明の配線基板は好ましくは、展開部の下側が絶縁基板に埋め込まれていることから、埋め込まれた部分同士が配線基板を成す絶縁体を通して容量結合し易くなるとともに、展開部においては一対の信号線路の容量成分増加により差動インピーダンスが減少することとなる。その結果、展開部において差動線路の線路間隔の変化による差動インピーダンスの不整合による高周波信号の反射損失を抑制することが可能となる。   In the wiring board of the present invention, preferably, since the lower side of the development part is embedded in the insulating substrate, the embedded parts can be easily capacitively coupled through an insulator constituting the wiring board, and a pair of parts are provided in the development part. The differential impedance decreases due to an increase in the capacitance component of the signal line. As a result, it is possible to suppress the reflection loss of the high-frequency signal due to the mismatch of the differential impedance due to the change in the line spacing of the differential lines in the development part.

また、本発明の配線基板は好ましくは、展開部の信号線路は絶縁基板に埋め込まれている下側の厚みが絶縁基板から露出している上側の厚みより厚いことから、埋め込まれた部分同士が配線基板を成す絶縁体を通して容量結合し易くなるとともに、信号線路の下面側に形成されている接地導体との距離が短くなり、一対の信号線路の容量成分増加により差動インピーダンスが減少することとなる。その結果、展開部において差動線路の線路間隔の変化による差動インピーダンスの不整合による高周波信号の反射損失を抑制することが可能となる。   Further, in the wiring board of the present invention, preferably, the signal line of the development portion is thicker on the lower side embedded in the insulating substrate than on the upper side exposed from the insulating substrate. Capacitive coupling is facilitated through an insulator forming the wiring board, the distance from the ground conductor formed on the lower surface side of the signal line is shortened, and the differential impedance is reduced by increasing the capacitance component of the pair of signal lines. Become. As a result, it is possible to suppress the reflection loss of the high-frequency signal due to the mismatch of the differential impedance due to the change in the line spacing of the differential lines in the development part.

また、本発明の配線基板は好ましくは、絶縁基板は、下面または内部に差動線路と対向するように接地導体が形成されていることから、接地導体によって高周波信号(電磁波)の漏洩を遮蔽し透過損失を抑制することが可能となる。   In the wiring board of the present invention, preferably, since the grounding conductor is formed on the lower surface or inside of the insulating board so as to face the differential line, the grounding conductor shields leakage of high-frequency signals (electromagnetic waves). Transmission loss can be suppressed.

これらのことにより、本発明の配線基板によれば、差動線路の線路間隔が広がる展開部における高周波信号の反射損失および透過損失を極めて小さくすることができるので、配線基板に搭載される半導体素子の高周波領域における作動性を良好にすることができる。   As a result, according to the wiring board of the present invention, the reflection loss and transmission loss of the high-frequency signal in the expanded portion where the line spacing of the differential lines is widened can be extremely reduced, so that the semiconductor element mounted on the wiring board The operability in the high frequency region can be improved.

本発明の配線基板について以下に図面を参照しつつ詳細に説明する。図1は本発明の配線基板の実施の形態の一例を示す断面図であり、図2は図1に示す配線基板における差動線路の周辺部の要部拡大平面図、図3は図1に示す配線基板における要部拡大断面図である。   The wiring board of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board according to the present invention, FIG. 2 is an enlarged plan view of a main part of the periphery of a differential line in the wiring board shown in FIG. 1, and FIG. It is a principal part expanded sectional view in the wiring board shown.

この配線基板1においては、絶縁基板2を構成する絶縁層2a〜2dは基本的には同じ比誘電率を有する絶縁材料で形成されている。絶縁層2c上には信号配線群3が形成され、絶縁層2b,2d上には信号配線群3に対向させて広面積の電源配線層4a、接地配線層4bが形成されており、信号配線群3の各信号配線はストリップ線路構造を有している。なお、電源配線層4aおよび接地配線層4bは、配線基板1の仕様に応じて入れ換えて配置されることもある。   In this wiring substrate 1, the insulating layers 2a to 2d constituting the insulating substrate 2 are basically formed of an insulating material having the same relative dielectric constant. A signal wiring group 3 is formed on the insulating layer 2c, and a large-area power wiring layer 4a and a ground wiring layer 4b are formed on the insulating layers 2b and 2d so as to face the signal wiring group 3, and the signal wiring Each signal wiring of group 3 has a stripline structure. The power supply wiring layer 4a and the ground wiring layer 4b may be interchanged and arranged depending on the specifications of the wiring board 1.

また、信号配線群3の各信号配線の配線幅および信号配線群3と電源配線層4aもしくは、接地配線層4bとの間に介在する絶縁層2b,2cの厚みを適宜設定することで、信号配線群3の特性インピーダンスを任意の値に設定することができるため、良好な伝送特性を有する信号配線群3を形成することが可能となる。信号配線群3の特性インピーダンスは、一般的には50Ωに設定される場合が多い。   Further, by appropriately setting the wiring width of each signal wiring of the signal wiring group 3 and the thickness of the insulating layers 2b and 2c interposed between the signal wiring group 3 and the power wiring layer 4a or the ground wiring layer 4b, Since the characteristic impedance of the wiring group 3 can be set to an arbitrary value, the signal wiring group 3 having good transmission characteristics can be formed. In many cases, the characteristic impedance of the signal wiring group 3 is generally set to 50Ω.

なお、信号配線群3に含まれる複数の信号配線は、それぞれ異なる電気信号を伝送するものとしてもよい。   The plurality of signal wirings included in the signal wiring group 3 may transmit different electrical signals.

この例では、配線基板1上面には高速で動作するIC,LSI等の半導体集積回路素子や光半導体素子等の半導体素子5が搭載され、錫−鉛(Sn−Pb)合金半田等の半田や金(Au)等から成る導体バンプ6および半導体素子5を接続するための半導体素子接続用電極7を介して、差動線路8と電気的に接続されている。また、配線基板1の半導体素子5を搭載する上面と反対側の下面には、半導体素子5に信号の入出力および電源供給を行なうための外部入出力用電極10が形成されている。   In this example, a semiconductor integrated circuit element such as an IC or LSI that operates at high speed or a semiconductor element 5 such as an optical semiconductor element is mounted on the upper surface of the wiring substrate 1, and solder such as tin-lead (Sn—Pb) alloy solder, It is electrically connected to the differential line 8 via a conductor bump 6 made of gold (Au) or the like and a semiconductor element connection electrode 7 for connecting the semiconductor element 5. An external input / output electrode 10 for inputting / outputting signals and supplying power to the semiconductor element 5 is formed on the lower surface of the wiring board 1 opposite to the upper surface on which the semiconductor element 5 is mounted.

また、差動線路8は、絶縁層2aの上面に電源配線層4aもしくは接地配線層4bとの間で形成されたマイクロストリップ構造の一対の信号線路で形成され、半導体素子接続用電極7および錫−鉛合金半田等の半田や金等から成る導体バンプ6を介して半導体素子5の電極と電気的に接続されており、外部と信号の入出力を行なうために貫通導体9を介して外部入出力用電極10と電気的に接続されている。なお、信号貫通導体9の周りには、信号貫通導体9を中心として同心円状に接地貫通導体11が形成されている。   The differential line 8 is formed of a pair of microstrip signal lines formed between the power wiring layer 4a or the ground wiring layer 4b on the upper surface of the insulating layer 2a. -It is electrically connected to the electrodes of the semiconductor element 5 through conductor bumps 6 made of solder such as lead alloy solder, gold, etc., and externally input through the through conductors 9 in order to input / output signals to / from the outside. The output electrode 10 is electrically connected. A grounding through conductor 11 is formed around the signal through conductor 9 concentrically around the signal through conductor 9.

図2は本発明の配線基板の実施の形態の一例における差動線路8の周辺部を示す要部拡大平面図である。図2において、絶縁層2は図1の絶縁層2aに相当する。   FIG. 2 is an enlarged plan view of a main part showing a peripheral portion of the differential line 8 in an example of the embodiment of the wiring board of the present invention. In FIG. 2, the insulating layer 2 corresponds to the insulating layer 2a of FIG.

また、差動線路8を成す一対の信号線路8a,8bは、導体バンプ6および半導体素子接続用電極7を介して半導体素子5に電気的に接続され、また信号貫通導体9を介して外部入出力用電極10に電気的に接続されている。差動線路8は、一対の信号線路8a,8b間の間隔が一定である一定部8cと、一対の信号線路8a,8b間の間隔が漸次広がる展開部8dとによって形成されている。展開部8dの信号線路8a,8bの厚みは、一定部8cにおける厚みより大きい。そして、展開部8dの端部において、信号線路8a,8bはそれぞれ信号貫通導体9aおよび9bを介して外部入出力用電極10に電気的に接続されている。   The pair of signal lines 8 a and 8 b constituting the differential line 8 are electrically connected to the semiconductor element 5 via the conductor bump 6 and the semiconductor element connection electrode 7, and externally input via the signal through conductor 9. It is electrically connected to the output electrode 10. The differential line 8 is formed by a constant part 8c in which the distance between the pair of signal lines 8a and 8b is constant, and a development part 8d in which the distance between the pair of signal lines 8a and 8b gradually increases. The thickness of the signal lines 8a and 8b of the expanded portion 8d is larger than the thickness of the fixed portion 8c. The signal lines 8a and 8b are electrically connected to the external input / output electrode 10 through the signal through conductors 9a and 9b, respectively, at the end of the expanded portion 8d.

また、図3においては、差動線路8の信号線路8a,8bは下側が絶縁層2aに埋め込まれており、埋め込まれている部分の厚みが露出している上側よりも厚く形成されている。展開部8dにおいて、信号線路8a,8bの間隔が漸次広がるのに応じて信号線路8a,8bの厚みおよび絶縁層2aに埋め込まれる厚みを調整し設定することによって、展開部8dにおける差動インピーダンスを制御することができる。そのため、高周波信号の良好な伝送特性を有する差動線路8を形成することが可能となる。   Further, in FIG. 3, the signal lines 8a and 8b of the differential line 8 are embedded in the insulating layer 2a on the lower side, and are formed thicker than the upper side where the thickness of the embedded part is exposed. By adjusting and setting the thickness of the signal lines 8a and 8b and the thickness embedded in the insulating layer 2a in the expanding portion 8d as the distance between the signal lines 8a and 8b gradually increases, the differential impedance in the expanding portion 8d is set. Can be controlled. Therefore, it is possible to form the differential line 8 having good transmission characteristics for high-frequency signals.

また、信号配線群3および差動線路8の構造は、信号配線群3に対向して形成された電源配線層4a、接地配線層4bを有するマイクロストリップ線路構造の他にも、信号配線群3の上下に電源配線層4a、接地配線層4bを有するストリップ線路構造、また、信号配線群3の各信号配線に隣接して電源配線層4a、接地配線層4bを形成したコプレーナ線路構造であってもよく、配線基板1に要求される仕様等に応じて適宜選択して用いることができる。   The signal wiring group 3 and the differential line 8 are structured in addition to the microstrip line structure having the power wiring layer 4a and the ground wiring layer 4b formed to face the signal wiring group 3, as well as the signal wiring group 3 A strip line structure having a power wiring layer 4a and a ground wiring layer 4b above and below, and a coplanar line structure in which a power wiring layer 4a and a ground wiring layer 4b are formed adjacent to each signal wiring of the signal wiring group 3. In other words, the wiring board 1 can be appropriately selected and used according to the specifications required for the wiring board 1.

また、配線基板1にチップ抵抗,薄膜抵抗,コイルインダクタ,クロスインダクタ,チップコンデンサまたは電解コンデンサ等といったものを搭載して、電子回路モジュール等を構成してもよい。   Further, an electronic circuit module or the like may be configured by mounting a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor, an electrolytic capacitor, or the like on the wiring board 1.

また、各絶縁層2a〜2dの平面視における形状は、正方形状や長方形状の他に、菱形状,六角形状または八角形状等の形状であってもよい。   Further, the shape of each of the insulating layers 2a to 2d in a plan view may be a rhombus shape, a hexagon shape, an octagon shape, or the like in addition to a square shape or a rectangular shape.

そして、本発明の配線基板1は、半導体素子収納用パッケージ等の電子部品収納用パッケージ、電子部品搭載用基板、多数の半導体素子が搭載される所謂マルチチップモジュールやマルチチップパッケージ、あるいはマザーボード等として使用される。   The wiring board 1 of the present invention is an electronic component storage package such as a semiconductor element storage package, an electronic component mounting substrate, a so-called multichip module or multichip package on which a large number of semiconductor elements are mounted, or a motherboard. used.

本発明の配線基板1において、各絶縁層2a〜2dは、例えばセラミックグリーンシート積層法によって、酸化アルミニウム質焼結体,窒化アルミニウム質焼結体,炭化珪素質焼結体,窒化珪素質焼結体,ムライト質焼結体またはガラスセラミックス焼結体等の無機絶縁材料から成る。また、絶縁層2a〜2dは、ポリイミド,エポキシ樹脂,フッ素樹脂,ポリノルボルネンまたはベンゾシクロブテン等の有機絶縁材料を使用して、あるいはセラミックス粉末等の無機絶縁物粉末をエポキシ樹脂等の熱硬化性樹脂で結合して成る複合絶縁材料等の電気絶縁材料から成っていてもよい。   In the wiring board 1 of the present invention, each of the insulating layers 2a to 2d is formed of, for example, a ceramic green sheet lamination method, an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, or a silicon nitride sintered body. Body, mullite sintered body or glass ceramic sintered body and other inorganic insulating materials. The insulating layers 2a to 2d are made of an organic insulating material such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or inorganic insulating powder such as ceramic powder is thermosetting such as epoxy resin. You may consist of electrical insulation materials, such as a composite insulation material couple | bonded with resin.

絶縁層2a〜2dは以下のようにして作製される。例えば酸化アルミニウム質焼結体から成る場合、まず、酸化アルミニウム,酸化珪素,酸化カルシウムまたは酸化マグネシウム等の原料粉末に適当な有機バインダや溶剤等を添加混合して泥漿状となし、これをドクターブレード法等を採用してシート状となすことによって、セラミックグリーンシートを得る。そして、各信号配線群3および各導体層4となる金属ペーストを所定のパターンに印刷塗布して上下に積層し、最後にこの積層体を還元雰囲気中にて約1600℃の温度で焼成することによって製作される。   The insulating layers 2a to 2d are produced as follows. For example, in the case of an aluminum oxide sintered body, first, a suitable organic binder or solvent is added to and mixed with raw material powders such as aluminum oxide, silicon oxide, calcium oxide or magnesium oxide to form a slurry, which is then doctor blade. A ceramic green sheet is obtained by using a method or the like to form a sheet. Then, a metal paste to be used for each signal wiring group 3 and each conductor layer 4 is printed and applied in a predetermined pattern and laminated vertically, and finally the laminated body is fired at a temperature of about 1600 ° C. in a reducing atmosphere. Produced by.

また、絶縁層2a〜2dが例えばエポキシ樹脂から成る場合、一般に酸化アルミニウム質焼結体から成るセラミックスやガラス繊維を織り込んだ布にエポキシ樹脂を含浸させて形成されるガラスエポキシ樹脂等から成る絶縁層の上面に、樹脂前駆体をスピンコート法もしくはカーテンコート法等により被着させ、これを熱硬化処理することによって形成されるエポキシ樹脂等の樹脂から成る絶縁層と、銅を無電解めっき法や蒸着法等の薄膜形成技術およびフォトリソグラフィ技術によって形成される薄膜配線導体層とを交互に積層し、約170℃の温度で加熱硬化することによって製作される。   When the insulating layers 2a to 2d are made of, for example, an epoxy resin, an insulating layer made of glass epoxy resin or the like generally formed by impregnating an epoxy resin into a cloth woven with ceramics or glass fibers made of an aluminum oxide sintered body. An insulating layer made of a resin such as an epoxy resin formed by applying a resin precursor to the upper surface of the substrate by spin coating or curtain coating and thermosetting the copper, and electroless plating or copper It is manufactured by alternately laminating thin film wiring conductor layers formed by thin film formation technology such as vapor deposition and photolithography technology, and heat-curing at a temperature of about 170 ° C.

これらの絶縁層2a〜2dの厚みは、使用する材料の特性に応じて、要求される仕様に対応する機械的強度や電気的特性等の条件を満たすように適宜設定される。   The thicknesses of these insulating layers 2a to 2d are appropriately set so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications, according to the characteristics of the materials used.

また、互いに異なる誘電率を有する絶縁層2a〜2dを得るための方法としては、例えば酸化アルミニウム,窒化アルミニウム,炭化珪素,窒化珪素,ムライトまたはガラスセラミックス等の無機絶縁材料、あるいはポリイミド,エポキシ樹脂,フッ素樹脂,ポリノルボルネンまたはベンゾシクロブテン等の絶縁材料に、チタン酸バリウム,チタン酸ストロンチウム,チタン酸カルシウムまたはチタン酸マグネシウム等の高誘電体材料の粉末を添加混合し、しかるべき温度で加熱硬化することによって、所望の比誘電率のものを得るようにすればよい。   In addition, as a method for obtaining the insulating layers 2a to 2d having different dielectric constants, for example, inorganic insulating materials such as aluminum oxide, aluminum nitride, silicon carbide, silicon nitride, mullite, or glass ceramics, polyimide, epoxy resin, Add and mix powder of high dielectric material such as barium titanate, strontium titanate, calcium titanate or magnesium titanate into insulating material such as fluororesin, polynorbornene or benzocyclobutene, and heat cure at appropriate temperature Thus, a desired dielectric constant can be obtained.

このとき、無機絶縁材料や有機絶縁材料に添加混合する高誘電体材料の粒径は、無機絶縁材料あるいは有機絶縁材料に高誘電体材料を添加混合したことによって起こる絶縁層2a〜2d内の誘電率のバラツキの発生の低下や、絶縁層の粘度変化による加工性の低下を低減するため、0.5〜50μmの範囲とすることが好ましい。   At this time, the particle size of the high dielectric material added to and mixed with the inorganic insulating material or the organic insulating material is the dielectric in the insulating layers 2a to 2d caused by adding and mixing the high dielectric material to the inorganic insulating material or the organic insulating material. In order to reduce a decrease in the rate variation and a decrease in workability due to a change in the viscosity of the insulating layer, the range of 0.5 to 50 μm is preferable.

また、無機絶縁材料や有機絶縁材料に添加混合する高誘電体材料の含有量は、絶縁層2a〜2dの誘電率を大きな値とするためと、無機絶縁材料や有機絶縁材料と高誘電体材料の接着強度の低下を防止するために、5〜75重量%とすることが好ましい。   The content of the high dielectric material added to and mixed with the inorganic insulating material or the organic insulating material is to increase the dielectric constant of the insulating layers 2a to 2d, and the inorganic insulating material, the organic insulating material, and the high dielectric material. In order to prevent a decrease in the adhesive strength, it is preferably 5 to 75% by weight.

また、信号配線群3、差動線路8、電源配線層4aおよび接地配線層4bは、例えばタングステン(W),モリブデン(Mo),モリブデンマンガン(Mo−Mn),銅(Cu),銀(Ag)または銀パラジウム(Ag−Pd)等の金属粉末メタライズ、あるいは銅(Cu),銀(Ag),ニッケル(Ni),クロム(Cr),チタン(Ti),金(Au)またはニオブ(Nb)やそれらの合金等の金属材料の薄膜等により形成すればよい。   The signal wiring group 3, the differential line 8, the power supply wiring layer 4a and the ground wiring layer 4b are made of, for example, tungsten (W), molybdenum (Mo), molybdenum manganese (Mo—Mn), copper (Cu), silver (Ag). ) Or metal powder metallization such as silver palladium (Ag-Pd), or copper (Cu), silver (Ag), nickel (Ni), chromium (Cr), titanium (Ti), gold (Au) or niobium (Nb) Or a thin film of a metal material such as an alloy thereof.

具体的には、信号配線群3等をCu,Wの金属粉末メタライズで形成する場合、W粉末に適当な有機バインダや溶剤等を添加混合して得た金属ペーストを、絶縁層2a〜2dとなるセラミックグリーンシートに所定パターンに印刷塗布し、これをセラミックグリーンシートの積層体とともに焼成することによって形成することができる。   Specifically, when the signal wiring group 3 or the like is formed of a metal powder metallization of Cu and W, a metal paste obtained by adding and mixing an appropriate organic binder or solvent to the W powder is combined with the insulating layers 2a to 2d. It can be formed by printing and applying to a ceramic green sheet to be formed in a predetermined pattern and firing it together with a laminate of ceramic green sheets.

また、信号配線群3等を金属薄膜で形成する場合、例えばスパッタリング法,真空蒸着法またはメッキ法により金属薄膜を形成した後、フォトリソグラフィ法により所定の配線パターンに形成することによって形成できる。   Further, when the signal wiring group 3 or the like is formed of a metal thin film, it can be formed by forming a metal thin film by, for example, a sputtering method, a vacuum evaporation method or a plating method and then forming a predetermined wiring pattern by a photolithography method.

このような配線基板1は、信号配線群3が配設されている絶縁層2a〜2dの誘電率に応じて、信号配線群3及び差動線路8の信号線路8a,8bのそれぞれの配線幅,配線厚み,配線間隔を設定することで、信号配線群3の各信号配線の特性インピーダンス値および差動線路8の差動インピーダンス値を所望の値とすることができる。   Such a wiring board 1 has a wiring width of each of the signal wiring group 3 and the signal lines 8a and 8b of the differential line 8 according to the dielectric constant of the insulating layers 2a to 2d on which the signal wiring group 3 is disposed. By setting the wiring thickness and the wiring interval, the characteristic impedance value of each signal wiring of the signal wiring group 3 and the differential impedance value of the differential line 8 can be set to desired values.

なお、本発明は上記の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の変更を行なうことは何ら差し支えない。例えば、差動線路8は、配線基板1の内層に形成されていてもよく、さらに差動線路8が電気的に接続される二次実装部は、コネクタやワイヤボンディングパッド等でもよい。また、作動線路8の展開部8dにおいて、信号線路8a,8bの厚みが端に向かって漸次厚くなるようにしてもよい。   Note that the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the present invention. For example, the differential line 8 may be formed in the inner layer of the wiring board 1, and the secondary mounting portion to which the differential line 8 is electrically connected may be a connector, a wire bonding pad, or the like. In addition, the thickness of the signal lines 8a and 8b may be gradually increased toward the end in the expanded portion 8d of the working line 8.

本発明の図1の配線基板1を以下のようにして作製した。酸化アルミニウム質焼結体から成る各厚みが0.1mmの絶縁層2a〜2dを、上述したセラミックグリーンシート積層法によって積層し形成することにより、絶縁基板2を作製した。このとき、信号配線群3、差動線路8、電源配線層4a、接地配線層4b、信号貫通導体9および接地貫通導体11を、上述したようにCuの金属粉末を用いたメタライズ層で形成した。   The wiring board 1 of FIG. 1 of the present invention was produced as follows. The insulating substrate 2 was produced by laminating and forming the insulating layers 2a to 2d each having a thickness of 0.1 mm made of the aluminum oxide sintered body by the ceramic green sheet laminating method described above. At this time, the signal wiring group 3, the differential line 8, the power supply wiring layer 4a, the ground wiring layer 4b, the signal through conductor 9, and the ground through conductor 11 were formed of the metallized layer using Cu metal powder as described above. .

そして、図2に示すように、比誘電率が5.2の絶縁基板2に、信号線路8a,8bの線路幅75μm、一定部8cにおける各信号線路8a,8bの厚み12μm、展開部8dにおける各信号線路8a,8bの厚み30μm、一定部8cにおける信号線路8a,8b間の間隔75μmであるマイクロストリップ構造の差動線路8を形成した。   As shown in FIG. 2, the insulating substrate 2 having a relative dielectric constant of 5.2 has a signal line width of 75 .mu.m for the signal lines 8a and 8b, a thickness of 12 .mu.m for each of the signal lines 8a and 8b in the fixed portion 8c, and a developed portion 8d. A differential line 8 having a microstrip structure in which the thickness of each signal line 8a, 8b is 30 μm and the interval between the signal lines 8a, 8b in the fixed portion 8c is 75 μm is formed.

展開部8dの信号線路8a,8bは、外部入出力用電極11の配列間隔1.0mmに合わせて、一定部8cの信号線路8a,8bとの成す角度を30度として形成した。   The signal lines 8a and 8b of the development part 8d were formed with an angle of 30 degrees with the signal lines 8a and 8b of the fixed part 8c in accordance with the arrangement interval of the external input / output electrodes 11 of 1.0 mm.

上記構成の差動線路8について、40GHzの高周波信号を信号線路8a,8bに位相差180度で入力したところ、差動線路8の一定部8cと展開部8dとの接続部における信号線路8a,8bの差動インピーダンスの不連続性を小さくできるため、高周波信号の反射損失を抑えることが可能となった。即ち、差動線路8における高周波信号の反射レベルは、展開部8dの厚みが一定部8cと同じ12μmである比較例の場合は−18dBであったのに対し、本実施例では−23dB程度となり、きわめて小さい値であった。   When the high-frequency signal of 40 GHz is input to the signal lines 8a and 8b with a phase difference of 180 degrees with respect to the differential line 8 having the above-described configuration, the signal lines 8a and 8a at the connection part between the constant part 8c and the development part 8d of the differential line 8 Since the discontinuity of the differential impedance of 8b can be reduced, the reflection loss of the high frequency signal can be suppressed. That is, the reflection level of the high-frequency signal in the differential line 8 is -18 dB in the comparative example in which the thickness of the developed portion 8d is 12 μm, which is the same as the constant portion 8c, whereas it is about -23 dB in this embodiment. It was a very small value.

本発明の配線基板の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the wiring board of this invention. 図1の配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the wiring board of FIG. 図1の配線基板の要部分拡大断面図である。It is a principal part expanded sectional view of the wiring board of FIG. 従来の配線基板の一例を示す断面図である。It is sectional drawing which shows an example of the conventional wiring board. 図4の配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the wiring board of FIG. 図4の配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the wiring board of FIG.

符号の説明Explanation of symbols

1・・・配線基板
2・・・絶縁基板
2a〜2d・・・絶縁層
3・・・信号配線群
4・・・内層接地導体層
5・・・半導体素子
8・・・差動線路
8a,8b・・・一対の信号線路
8d・・・展開部
DESCRIPTION OF SYMBOLS 1 ... Wiring board 2 ... Insulating board 2a-2d ... Insulating layer 3 ... Signal wiring group 4 ... Inner layer grounding conductor layer 5 ... Semiconductor element 8 ... Differential line 8a, 8b ... Pair of signal lines 8d ... Expanding part

Claims (4)

絶縁基板の上面に互いに平行な一対の信号線路から成る差動線路が形成された配線基板において、前記差動線路は、一端部が前記一対の信号線路同士の間の間隔が漸次広がっている展開部とされているとともに、前記信号線路の前記展開部の厚みが前記展開部以外の部位の厚みよりも厚いことを特徴とする配線基板。 In the wiring substrate in which a differential line composed of a pair of signal lines parallel to each other is formed on the upper surface of the insulating substrate, the differential line is developed such that one end portion of the differential line is gradually widened. And a thickness of the developed portion of the signal line is thicker than a thickness of a portion other than the developed portion. 前記信号線路は、前記展開部の下側が前記絶縁基板に埋め込まれていることを特徴とする請求項1記載の配線基板。 The wiring board according to claim 1, wherein a lower side of the development portion of the signal line is embedded in the insulating substrate. 前記信号線路は、前記展開部の前記絶縁基板に埋め込まれている下側の厚みが前記絶縁基板から露出している上側の厚みよりも厚いことを特徴とする請求項2記載の配線基板。 The wiring board according to claim 2, wherein the signal line has a lower thickness embedded in the insulating substrate of the development portion than an upper thickness exposed from the insulating substrate. 前記絶縁基板は、下面または内部に前記差動線路と対向するように接地導体が形成されていることを特徴とする請求項1乃至請求項3のいずれかに記載の配線基板。 The wiring board according to claim 1, wherein a ground conductor is formed on the lower surface or inside of the insulating substrate so as to face the differential line.
JP2004275519A 2004-09-22 2004-09-22 Wiring board Expired - Fee Related JP4511294B2 (en)

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JP2007202005A (en) * 2006-01-30 2007-08-09 Kanji Otsuka Impedance converting apparatus
WO2013017846A1 (en) * 2011-07-29 2013-02-07 Bae Systems Plc Radio frequency communication
JP2013098888A (en) * 2011-11-04 2013-05-20 Sony Corp Electronic circuit, manufacturing method of electronic circuit, and packaging member
JP2016100600A (en) * 2014-11-26 2016-05-30 インテル コーポレイション Electrical interconnect for electronic package

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JP2003152290A (en) * 2001-11-13 2003-05-23 Canon Inc Printed wiring board
JP2004253746A (en) * 2002-12-26 2004-09-09 Kyocera Corp Wiring board

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JPS58136107A (en) * 1982-02-08 1983-08-13 Nec Corp Spiral type transmission line
JP2001203300A (en) * 2000-01-18 2001-07-27 Matsushita Electric Ind Co Ltd Board for wiring, semiconductor device and producing method for board for wiring
JP2003152290A (en) * 2001-11-13 2003-05-23 Canon Inc Printed wiring board
JP2004253746A (en) * 2002-12-26 2004-09-09 Kyocera Corp Wiring board

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Publication number Priority date Publication date Assignee Title
JP2007202005A (en) * 2006-01-30 2007-08-09 Kanji Otsuka Impedance converting apparatus
WO2013017846A1 (en) * 2011-07-29 2013-02-07 Bae Systems Plc Radio frequency communication
US9203132B2 (en) 2011-07-29 2015-12-01 Bae Systems Plc Transition interface having first and second coupling elements comprised of conductive tracks oriented at different angles with respect to each other
JP2013098888A (en) * 2011-11-04 2013-05-20 Sony Corp Electronic circuit, manufacturing method of electronic circuit, and packaging member
JP2016100600A (en) * 2014-11-26 2016-05-30 インテル コーポレイション Electrical interconnect for electronic package

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