JP2006093313A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, which has a leak mode where a current smaller than an on-state but larger than an off-state in addition to the on/off-states flows between source/drain regions, and a manufacturing method thereof. <P>SOLUTION: A transistor 1 has first and second gate electrodes G1, G2. The first and second gate electrodes share the same source/drain region to form first and second transistors. Voltages are applied to the first and second gate electrodes G1, G2 respectively independently. The transistor 1 creates a first state (on-state) that at least the first transistor is in an on-state, a second state (off state) that the first and second transistors are in off-states; and a third state (leak mode) that the first transistor is in the off-state and the second transistor is in the on-state. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a MIS (Metal-Insulator-Semiconductor) structure and a manufacturing method thereof.

  The MIS transistor is a field effect transistor using a MIS structure suitable for an integrated circuit as a gate, and is widely used in a semiconductor memory, a microprocessor, and the like.

  The MIS transistor usually includes a gate electrode on a semiconductor substrate via a gate insulating film, and source / drain regions on both sides of the gate electrode in the semiconductor substrate. A state in which a channel is formed between the source / drain regions and a current flows by a voltage applied to the gate electrode (ON state), and a state in which no channel is formed between the source / drain regions and no current flows (OFF state). Is switched.

  In Japanese Patent Laid-Open No. 2003-51184 (conventional example 1), one memory cell node and a word line in a DRAM-structured memory cell, and one memory cell node and a reference voltage line, respectively. A memory device is disclosed in which each negative resistance device is connected to bistable the amount of charge accumulated in the memory capacity and statically hold information.

In JP-A-8-97305 (conventional example 2), the thickness of the first gate electrode provided on the semiconductor substrate via the first insulating film (gate insulating film) is extremely thin. The two insulating films and the punched two gate electrodes thinner than the first gate electrode are alternately stacked a plurality of times, and the third insulating film is interposed on the side walls of the first and second gate electrodes and the second insulating film. A semiconductor memory device in which a third gate electrode is formed is disclosed. Here, a semiconductor memory device that does not require refreshing is realized by utilizing the Coulomb shielding phenomenon.
JP 2003-511184 A JP-A-8-97305

  However, the semiconductor device as described above has the following problems.

  In the conventional MIS transistor, the current flowing between the source and the drain is switched between two states of ON state / OFF state. On the other hand, from the viewpoint of improving the degree of freedom in designing the semiconductor device, it is possible to form a MIS transistor that realizes the third state in which the current flowing between the source / drain is larger than the OFF state and smaller than the ON state. It is valid. Note that the semiconductor devices according to the conventional examples 1 and 2 do not include the MIS transistor that generates an intermediate state between the ON / OFF states, and the semiconductor device according to the present invention and the semiconductor devices according to the conventional examples 1 and 2 Are completely different in premise and configuration.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a current between the source and the drain that is larger than the OFF state and smaller than the ON state in addition to the ON state / OFF state. It is an object of the present invention to provide a semiconductor device that causes a third state to flow and a manufacturing method thereof.

  A semiconductor device according to the present invention includes a semiconductor substrate, a first transistor including a first gate electrode formed on the main surface of the semiconductor substrate, and source / drain regions formed on the semiconductor substrate, and a main surface of the semiconductor substrate. A second transistor including a second gate electrode and a source / drain region formed thereon, wherein at least the first transistor is in an ON state, and the first and second transistors are in an OFF state. The second state and the third state in which the first transistor is in the OFF state and the second transistor is in the ON state are realized.

  In one aspect, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first gate electrode on a main surface of a semiconductor substrate via a first gate insulating film, and both sides of the first gate electrode in the semiconductor substrate. Forming a source / drain region on the semiconductor substrate, forming an insulating film on the first gate electrode from the main surface of the semiconductor substrate, forming a contact hole reaching the source / drain region in the insulating film, and contact Forming a conductive film connecting the source / drain regions on the insulating film from within the hole, and forming a second gate electrode on the conductive film via the second gate insulating film.

  In another aspect, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a first gate electrode on a main surface of a semiconductor substrate via a gate insulating film, and a gate insulating film on the main surface of the semiconductor substrate. A step of forming a second gate electrode so as to be aligned with the first gate electrode, and a source / drain region in the semiconductor substrate so as to sandwich the first and second gate electrodes in a direction in which the first and second gate electrodes are aligned Forming a step.

  In still another aspect of the method for manufacturing a semiconductor device according to the present invention, a step of forming a first gate electrode on a main surface of a semiconductor substrate via a gate insulating film, and a gate insulating film on the main surface of the semiconductor substrate Forming a second gate electrode so as to be aligned with the first gate electrode through the semiconductor substrate, and sandwiching the first and second gate electrodes in a direction perpendicular to the direction in which the first and second gate electrodes are aligned Forming a source / drain region.

  According to the present invention, in addition to the ON state / OFF state, it is possible to obtain a transistor (semiconductor device) that causes a third state in which a current that is larger than the OFF state and smaller than the ON state flows between the source and drain. .

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to FIGS.

  FIG. 1 is a circuit diagram schematically showing a transistor 1 (semiconductor device) according to first to sixth embodiments described later. 1A shows a “bulk + TFT transistor” described later, FIG. 1B shows a “bulk series transistor” described later, and FIG. 1C shows a “bulk” described later. "Parallel transistor". Referring to FIGS. 1A, 1B, and 1C, a transistor 1 according to the first to sixth embodiments includes first and second gate electrodes G1 and G2. The first and second gate electrodes G1 and G2 share the same source (S) / drain (D) region, and a first transistor is formed by the first gate electrode G1 and the source / drain region. A second transistor is formed by the electrode G2 and the source / drain regions. A voltage is applied independently to the first and second gate electrodes G1, G2. In the transistor 1, at least the first transistor is in an ON state (first state: hereinafter referred to as “the ON state of the transistor 1”), and the first transistor and the second transistor are in an OFF state. There is a certain state (second state: hereinafter referred to as “transistor 1 OFF state”), and a state where the first transistor is OFF and the second transistor is ON (third state: hereinafter , Sometimes referred to as “leak mode” or “slightly ON state”).

  The ON state / OFF state / leakage mode of the transistor 1 is classified according to the magnitude of the current flowing between the source and the drain. For example, when the transistor 1 is in the ON state, a current of about 600 μA or more flows between the source and drain, and when the transistor 1 is in the OFF state, only a current of about 1 fA or less flows between the source and drain. In the leak mode, for example, a current of about 1 pA or more and 10 nA or less flows between the source / drain. That is, in the leak mode, a current that is larger than the OFF state of the transistor 1 and smaller than the ON state of the transistor 1 flows between the source / drain. Table 1 shows an example of voltages applied to the source (S), the first and second gate electrodes (G1, G2), and the drain (D) in the ON state / OFF state / leakage state. The transistor 1 is turned on when the transistor including the first and second gate electrodes G1 and G2 is ON (case-1) and when only the transistor including the first gate electrode G1 is ON ( case-2).

  In the conventional MIS transistor, switching between two states of the ON state (first state) / OFF state (second state) is generally realized. On the other hand, in the transistor 1 according to the first to sixth embodiments described later, in addition to the ON state / OFF state, a leak mode (third state) that is an intermediate state between the ON state / OFF state is realized. Therefore, the degree of freedom in designing the device including the transistor 1 is improved.

  A semiconductor memory device as an application example of the transistor 1 (semiconductor device) described above will be described below. FIG. 30 is an equivalent circuit diagram showing the semiconductor memory device 100. The semiconductor memory device 100 is one of typical semiconductor memory devices together with a DRAM (Dynamic Random-Access Memory), and is an SRAM (Static Random-Access Memory) known as a memory that does not require a refresh operation. A conventional SRAM memory cell generally includes six bulk transistors, and even when the load element is formed of a thin film transistor (TFT (Thin Film Transistor): hereinafter, the thin film transistor may be referred to as a TFT). Includes bulk transistors. Therefore, SRAM memory cells tend to be larger than DRAM memory cells with one bulk transistor. On the other hand, in the semiconductor memory device 100, by using the transistor 1 that realizes the leak mode, the number of bulk transistors per memory cell is reduced, and the memory cell area can be reduced.

  Note that “bulk” is used to mean that a TFT is formed on a substrate while a transistor is formed in a silicon substrate. Hereinafter, a transistor formed in a silicon substrate with respect to a thin film element formed on the substrate like a TFT is referred to as a “bulk transistor”.

  Referring to FIG. 30, memory cell 50 stores two data holding units 50A adjacent to each other in the row direction, each storing 1-bit data and inverted data obtained by inverting the data. Includes 50B. The data holding unit 50A includes an access transistor 52A, a capacitor 54A, and a p-channel TFT 56A, and the data holding unit 50B includes an access transistor 52B, a capacitor 54B, and a p-channel TFT 56B. Here, the transistor 1 having the leak mode is used as the access transistors 52A and 52B.

  The access transistors 52A and 52B are n-channel MOS (Metal-Oxide-Semiconductor) transistors, and include first gate electrodes G1A and G1B and second gate electrodes G2A and G2B, respectively. The first gate electrodes G1A and G1B function as normal gate electrodes connected to the word line, and the second gate electrodes G2A and G2B function as another gate electrode in each of the access transistors 52A and 52B. When a voltage is applied to the second gate electrodes G2A and G2B while the first gate electrodes G1A and G1B are at the L (logic low) level, an incomplete channel is formed between the drain and the source, and the transistor is turned on. Although it is much smaller than the state, a large leak current flows between the drain and the source (leak mode) compared to the normal OFF state.

  Access transistor 52A is connected between bit line 68A and node 60, and first gate electrode G1A is connected to word line 64. The second gate electrode G2A of the access transistor 52A is connected to the node 62. The access transistor 52A is turned on when the word line 64 is activated, and turned off when the word line 64 is deactivated. Here, if the node 62 is at the H level when the word line 64 is inactivated, the access transistor 52A enters the leak mode, and charges are discharged from the node 60 to the bit line 68A fixed at the ground potential. The

  The capacitor 54A stores binary information “1” or “0” depending on whether or not charges are accumulated. Capacitor 54 </ b> A is connected between node 60 and cell plate 70. The voltage corresponding to the binary information “1”, “0” is applied to the capacitor 54A from the bit line 68A via the access transistor 52A and the node 60, whereby the capacitor 54A is charged and discharged, and the data Writing is performed. The p-channel TFT 56A is connected between the power supply node 72 and the node 60, and the gate which is an ON / OFF control electrode is connected to the node 62.

A p-channel TFT 56A and a p-channel TFT 56B, which will be described later, are resistance elements each having a switching function made of polycrystalline polysilicon, and have an OFF resistance of T (Tera, “T” represents 10 ¹² ) Ω and G ( Giga, “G” represents 10 ^9. ) A high-resistance element having an ON resistance on the order of Ω. In the present invention, when the term “resistive element” is used, both the one having a switching function and the one having a constant resistance are shown.

  Access transistor 52B is connected between bit line 68B paired with bit line 68A and node 62, and first gate electrode G1B is connected to word line 66. The second gate electrode G2B of the access transistor 52B is connected to the node 60. Access transistor 52B is turned on when word line 66 is activated and turned off when word line 66 is deactivated. Here, if the node 60 is at the H level when the word line 66 is inactivated, the access transistor 52B enters the leak mode, and charges are discharged from the node 62 to the bit line 68B fixed at the ground potential. The

  The capacitor 54B stores inverted data obtained by inverting the data stored in the capacitor 54A depending on whether or not charges are accumulated. Capacitor 54B is connected between node 62 and cell plate 70. The voltage corresponding to the binary information “1” and “0” is applied to the capacitor 54B from the bit line 68B via the access transistor 52B and the node 62, whereby the capacitor 54B is charged and discharged, and the data Writing is performed. The p-channel TFT 56B is connected between the power supply node 72 and the node 62, and the gate which is an ON / OFF control electrode is connected to the node 60.

  The p-channel TFTs 56A and 56B made of polysilicon and the capacitors 54A and 54B can be formed by being stacked on top of the access transistors 52A and 52B which are bulk transistors. Therefore, the size of the memory cell per bit in semiconductor memory device 100 is substantially determined by the area occupied by two access transistors 52A and 52B and nodes 60 and 62. It is also possible to adopt a memory cell structure in which capacitors 54A and 54B and cell plate 70 are not provided.

  Next, the “write”, “hold”, and “read” operations of this memory cell will be described.

(1) Data Write It is assumed that a state in which charge is stored in the capacitor 54A and no charge is stored in the capacitor 54B corresponds to data “1”. When data "1" is written, bit lines 68A and 68B are precharged to power supply potential Vcc and ground potential GND, respectively, and word lines 64 and 66 are activated. As a result, access transistors 52A and 52B are turned ON, and voltage of power supply potential Vcc is applied from bit line 68A to capacitor 54A via access transistor 52A and node 60, and charge is stored in capacitor 54A. On the other hand, voltage of ground potential GND is applied to capacitor 54B from access line 52B and node 62 from bit line 68B, and electric charge is discharged from capacitor 54B to bit line 68B.

  Since the data holding units 50A and 50B have the same circuit configuration, when data “0” is written, the operations of the data holding units 50A and 50B described above are simply replaced with each other. Therefore, the description thereof will not be repeated.

(2) Data retention In this memory cell 50, the ON current and OFF current of the p-channel TFTs 56A and 56B are about 1 × 10 ⁻¹¹ A and 1 × 10 ⁻¹³ A, respectively. On the other hand, the leakage current from the nodes 60 and 62 due to the OFF current (not in the leakage mode) of the access transistor which is a bulk transistor is about 1 × 10 ⁻¹⁵ A. Therefore, since the ON currents of the p-channel TFTs 56A and 56B exceed the leakage currents from the nodes 60 and 62 by 4 digits, respectively, the nodes 60 and 62 and the capacitors 54A and 54B connected thereto are charged from the power supply node 72, respectively. Can do.

  The current values shown here are not limited to these numerical values, but indicate orders of these degrees.

  Here, the OFF currents of the p-channel TFTs 56A and 56B also exceed the leakage currents from the nodes 60 and 62, respectively. In this memory cell 50, since the driver transistor for discharging the charge of the node and capacitor at the L level is not provided unlike the conventional SRAM, the potential of the node at the L level rises as it is, Data will be destroyed.

  However, in this memory cell 50, the charge of the node at the L level is discharged to the corresponding bit line via the access transistor due to the leak mode, so that the stored data can be held. Hereinafter, the case where the data “1” is held will be described in detail.

At the time of data retention, the bit lines 68A and 68B are fixed to the ground potential, and the word lines 64 and 66 are inactivated. After data “1” is written, capacitor 54A and node 60 are in the charged state (H level), and capacitor 54B and node 62 are in the discharged state (L level). Here, although the access transistor 52A is OFF, as described above, a current of about 1 × 10 ⁻¹⁵ A flows even in the OFF state, and the charge charged in the capacitor 54A and the node 60 is Leakage occurs through the access transistor 52A.

However, the charge decrease due to this leakage is compensated by the p-channel TFT 56A in the ON state. As described above, the ON current, that is, the charging current of the p-channel TFT 56A is about 1 × 10 ⁻¹¹ A, and exceeds the OFF current of the access transistor 52A, that is, the discharge current by 4 digits. The state of charge is maintained.

  It is desirable that the charging current by p channel TFT 56A exceeds the discharging current by access transistor 52A by at least one digit. If the charging current is n times the discharge current (n is smaller than 10), the potential of the node at the H level is reduced by 1 / (1 + n) Vcc, and the reduction cannot be ignored. It is.

On the other hand, since the node 60 is at the H level, the access transistor 52B is in the leak mode, and the charge leaked from the power supply node 72 to the node 62 via the p-channel TFT 56B which is in the OFF state passes through the access transistor 52B. Leaks to the bit line 68B. Here, in order for the potentials of capacitor 54B and node 62 not to rise, the condition is that the leak current of access transistor 52B in the leak mode is larger than the OFF current of p-channel TFT 56B. In this memory cell 50, the leak current of access transistor 52B in the leak mode is about 1 × 10 ⁻¹¹ A and exceeds the OFF current 1 × 10 ⁻¹³ A of p-channel TFT 56B, so that capacitor 54B and node 62 Does not rise, and the discharge state of capacitor 54B and node 62 is maintained. As described above, the memory cell 50 can hold the data “1”.

  It is desirable that the leak current of access transistor 52B in the leak mode exceeds the OFF current of p-channel TFT 56B by at least one digit. This is because if it falls below one digit, the potential rise of the capacitor 54B and the node 62 that cannot be ignored appears.

  In addition, the data “0” is retained by the same operation as the above-described operation because the operations of the data holding units 50A and 50B described above are interchanged with each other, and the description thereof will not be repeated.

  In the above description, the potentials of the bit lines 68A and 68B are fixed to the ground potential at the time of data retention. However, this potential is not limited to the ground potential, and may be a negative potential, for example.

(3) Reading Data Assume that data “1” is stored in the memory cell 50. Bit lines 68A and 68B are precharged to the ground potential in advance, and word lines 64 and 66 are activated when data is read. As a result, the access transistors 52A and 52B are turned on, and the charge is discharged from the charged capacitor 54A to the bit line 68A via the access transistor 52A, and the potential of the bit line 68A rises.

  On the other hand, since the capacitor 54B is in a discharged state, the potential of the bit line 68B remains at the ground potential. Therefore, a potential difference is generated between the bit lines 68A and 68B, the potential difference is compared by a sense amplifier (not shown), and the potential of the bit line pair 68A is amplified to the power supply potential Vcc. Then, data “1” is read by associating the state where the potentials of bit lines 68A and 68B are at power supply potential Vcc and ground potential GND with data “1”.

  When data is read, word lines 64 and 66 are activated again with the potentials of bit line pair 68A and 68B at power supply potential Vcc and ground potential GND, respectively. Then, the access transistors 52A and 52B are turned ON, and the charges are recharged from the bit line pair 68A and 68B to the capacitors 54A and 54B via the access transistors 52A and 52B, respectively. Is done.

  Note that the reading of the data “0” is not repeated because the operation similar to the above-described operation is performed only by the operation of the data holding units 50A and 50B described above being replaced with each other.

(Embodiment 1)
FIG. 2 is a cross-sectional view showing the transistor 1 according to the first embodiment. Referring to FIG. 2, in transistor 1 according to the present embodiment, first gate electrode G1 is formed on the main surface of semiconductor substrate 2 via gate insulating film 5, and second gate electrode G2 is a first gate. It is formed in an upper layer than the electrode G1. An insulating film 6, a conductive film 7, and a gate insulating film 8 are formed between the first and second gate electrodes G1 and G2, and a second gate electrode G2 is formed on the gate insulating film 8. The first and second gate electrodes G1, G2 share the source / drain regions 3, 4. The gate length (L in FIG. 2) of the second gate electrode G2 is smaller than the gate length of the first gate electrode G1, and is, for example, about 0.05 μm or more and 0.1 μm or less. With the above configuration, the bulk transistor (first transistor) including the first gate electrode G1 and the source / drain regions 3 and 4 and the TFT transistor including the second gate electrode G2 and the source / drain regions 3 and 4 (second transistor). ) And are formed. In the present specification, such a transistor 1 may be referred to as a “bulk + TFT transistor”.

  In the transistor 1, when a voltage higher than the threshold voltage of the first transistor is applied to the first gate electrode G 1, an inversion region in which the conductivity type is inverted is formed below the first gate electrode G 1. As a result, a “transistor 1 ON state” in which a current (ON current) of a certain value (for example, about 600 μA) or more flows between the source / drain regions 3 and 4 is realized. Here, a predetermined voltage may or may not be applied to the second gate electrode G2.

  In the transistor 1, when only a voltage lower than the threshold voltage of the first transistor is applied to the first gate electrode G1, a sufficient inversion region is not formed under the first gate electrode G1, and the source / drain region 3 is not formed. , 4 does not flow the ON current. Here, when a voltage higher than the threshold voltage of the second transistor is applied to the second gate electrode G2, the conductive layer 7 below the second gate electrode G2 is affected by this, and although it is smaller than the ON current, it is OFF, which will be described later. A “leak mode” in which a leak current larger than the current (for example, about 1 pA to 10 nA) flows between the source / drain regions 3 and 4 is realized.

  In the transistor 1, when only a voltage lower than the threshold voltage of the first and second transistors is applied to the first and second gate electrodes G1 and G2, respectively, the above-described ON current and leakage current do not occur. "OFF state" is realized. However, also in this case, a minute current (OFF current) of a certain value (for example, about 1 fA) or less flows between the source / drain regions 3 and 4.

  3 to 5 are cross-sectional views showing the states of the respective steps in the manufacturing process of the transistor 1 shown in FIG. A method for manufacturing the transistor 1 will be described with reference to FIGS. In the method for manufacturing the transistor 1 according to the present embodiment, as shown in FIGS. 3 to 5, the first gate electrode G <b> 1 is formed on the main surface of the semiconductor substrate 2 via the gate insulating film 5 (first gate insulating film). Forming the source / drain regions 3 and 4 on both sides of the first gate electrode G1 in the semiconductor substrate 2, and the first gate electrode G1 from above the main surface of the semiconductor substrate 2. A step of forming an insulating film 6 thereon, a step of forming a contact hole 7A reaching the source / drain regions 3 and 4 in the insulating film 6, and a source / drain region 3 and 4 on the insulating film 6 from within the contact hole 7A. The step of forming the conductive film 7 connecting the two (hereinafter, FIG. 4) and the step of forming the second gate electrode G2 on the conductive film 7 via the gate insulating film 8 (second gate insulating film) (FIG. 5). With.

  Referring to FIG. 3, gate insulating film 5 is formed on p type semiconductor substrate 2. Gate insulating film 5 is formed, for example, by thermal oxidation. After a p-type impurity (for example, boron) for adjusting the threshold voltage is implanted into the semiconductor substrate 2, a first gate electrode G1 made of, for example, polysilicon is formed on the gate insulating film 5. The first gate electrode G1 may be doped with n-type / p-type impurities. Thereafter, using the first gate electrode G1 as a mask, n-type impurities (for example, arsenic, phosphorus, etc.) to be the source / drain regions 3 and 4 are implanted into the semiconductor substrate 2 (arrows in FIG. 3).

  Referring to FIG. 4, insulating film 6 is formed to cover first gate electrode G1 and source / drain regions 3 and 4. The insulating film 6 is formed by using, for example, a CVD (Chemical Vapor Deposition) method. Next, contact holes 7 A reaching the source / drain regions 3 and 4 are formed in the insulating film 6. Then, a conductive film 7 made of p-type polysilicon is formed so as to reach the insulating film 6 from the contact hole 7A reaching the source / drain regions 3 and 4. Thereby, the channel region of the TFT transistor is formed.

  Referring to FIG. 5, gate insulating film 8 is formed on conductive film 7. The gate insulating film 8 is formed by, for example, thermal oxidation treatment. On the gate insulating film 8, a second gate electrode G2 made of, for example, polysilicon is formed. The second gate electrode G2 may be doped with n-type / p-type impurities. Through the above steps, a “bulk + TFT transistor” shown in FIG. 2 is obtained.

  FIG. 6 is a top view of the transistor 1. Note that a II-II cross section in FIG. 6 corresponds to FIG. Referring to FIG. 6, in transistor 1 according to the present embodiment, source / drain regions 3 and 4 formed between STIs (Shallow Trench Isolation) 9 are shared by first and second gate electrodes G1 and G2. In addition, since the second gate electrode G2 is formed so as to overlap the first gate electrode G1, a transistor having a leak mode can be obtained without increasing the bulk area.

(Embodiment 2)
FIG. 7 is a cross-sectional view showing the transistor 1 according to the second embodiment. The transistor 1 according to the present embodiment is a modification of the transistor according to the first embodiment. Referring to FIG. 7, in transistor 1 according to the present embodiment, first and second gate electrodes G1, G2 are arranged on the main surface of semiconductor substrate 2 so as to be aligned in a direction from source region 3 to drain region 4. The gate insulating film 5 is interposed therebetween. The first and second gate electrodes G1, G2 share the source / drain regions 3, 4. Further, the gate length of the first gate electrode G1 (L1 in FIG. 7) is larger than the gate length of the second gate electrode G2 (L2 in FIG. 7). Here, the gate length of the second gate electrode G2 is about 0.05 μm or more and 0.1 μm or less. With the above configuration, a bulk transistor (first transistor) including the first gate electrode G1 and the source / drain regions 3 and 4 and a bulk transistor including the second gate electrode G2 and the source / drain regions 3 and 4 (second transistor). ) And are formed. Here, since the first and second gate electrodes G1, G2 are arranged in series between the source / drains 3, 4, such a transistor 1 is referred to as a “bulk series transistor” in the present specification. There is a case.

  In the transistor 1, when a voltage higher than the threshold voltage of the first transistor is applied to the first gate electrode G 1, an inversion region in which the conductivity type is inverted is formed below the first gate electrode G 1. As a result, a “transistor 1 ON state” in which a current (ON current) of a certain value or more flows between the source / drain regions 3 and 4 is realized. Here, a predetermined voltage may or may not be applied to the second gate electrode G2.

  In the transistor 1, when only a voltage lower than the threshold voltage of the first transistor is applied to the first gate electrode G1, a sufficient inversion region is not formed under the first gate electrode G1, and the source / drain region 3 is not formed. , 4 does not flow the ON current. Here, when a voltage higher than the threshold voltage of the second transistor is applied to the second gate electrode G2, the semiconductor substrate 2 below the second gate electrode G2 is affected, and is smaller than the ON current, but will be described later. A “leak mode” in which a leak current larger than the current flows between the source / drain regions 3 and 4 is realized.

  In the transistor 1, when only a voltage lower than the threshold voltage of the first and second transistors is applied to the first and second gate electrodes G1 and G2, respectively, the above-described ON current and leakage current do not occur. "OFF state" is realized. However, also in this case, a minute current (OFF current) of a certain value or less flows between the source / drain regions 3 and 4.

  8 to 10 are cross-sectional views showing the states of the respective steps in the manufacturing process of the transistor 1 shown in FIG. A method for manufacturing the transistor 1 will be described with reference to FIGS. In the method for manufacturing the transistor 1 according to the present embodiment, as shown in FIGS. 8 to 10, a step of forming the first gate electrode G <b> 1 on the main surface of the semiconductor substrate 2 via the gate insulating film 5 (FIG. 8). ), Forming a second gate electrode G2 on the main surface of the semiconductor substrate 2 via the gate insulating film 5 so as to be aligned with the first gate electrode G1 (FIG. 9), and the first and second gate electrodes G1 , G2 in a direction in which the first and second gate electrodes G1 and G2 are sandwiched in the direction in which the second and second gate electrodes G2 are arranged. The first and second gate electrodes G1, G2 may be formed in the same process.

  As shown in FIG. 8, the gate insulating film 5 is formed on the p-type semiconductor substrate 2. After the p-type impurity for adjusting the threshold voltage is implanted into the semiconductor substrate 2, the first gate electrode G <b> 1 is formed on the gate insulating film 5. Next, as shown in FIG. 9, the second gate electrode G2 is formed on the gate insulating film 5 so as to be aligned with the first gate electrode G1. Then, as shown in FIG. 10, n-type impurities to be the source / drain regions 3 and 4 are implanted into both sides of the first and second gate electrodes G1 and G2 (left and right sides in FIG. 10) (in FIG. 10). Arrow). Through the above steps, a “bulk series transistor” shown in FIG. 7 is obtained.

  FIG. 11 is a top view of the transistor 1. In addition, the VII-VII cross section in FIG. 11 corresponds to FIG. Referring to FIG. 11, in the transistor 1 according to the present embodiment, the source / drain regions 3 and 4 formed between the STIs 9 are shared by the first and second gate electrodes G1 and G2. A transistor having a leak mode can be obtained without excessively increasing the transistor.

  FIG. 12 is a top view showing a modification of the transistor 1 according to the present embodiment. 13 corresponds to the XIII-XIII cross section in FIG. Referring to FIGS. 12 and 13, in this modification, a part of second gate electrode G2 is formed so as to overlap first gate electrode G1 with insulating film 6A interposed therebetween. The first and second gate electrodes G1, G2 are electrically insulated by the insulating film 6A. Employing the structure shown in FIGS. 12 and 13 facilitates photolithography in patterning of the first and second gate electrodes G1 and G2.

  By the way, in order to adjust the threshold voltages of the first and second gate electrodes G1 and G2, for example, it may be considered that the conductivity types of the first and second gate electrodes G1 and G2 are different. For example, in an n-channel MOS transistor, the threshold value is greater when n-type (first conductivity type) polysilicon is used as the gate electrode than when p-type (second conductivity type) polysilicon is used. The voltage increases.

  In the present embodiment, detailed description of the same matters as in the above-described first embodiment will not be repeated.

(Embodiment 3)
FIG. 14 is a cross-sectional view showing the transistor 1 according to the third embodiment. The transistor 1 according to the present embodiment is a modification of the transistor according to the first and second embodiments. Referring to FIG. 14, in transistor 1 according to the present embodiment, first and second gate electrodes G1, G2 are directed in a direction from source region 3 to drain region 4 (a direction perpendicular to the paper surface in FIG. 14). It is formed on the main surface of the semiconductor substrate 2 via the gate insulating film 5 so as to be aligned in the orthogonal direction (left-right direction in FIG. 14). The first and second gate electrodes G1, G2 share the source / drain regions 3, 4 (see FIG. 18 described later). Further, the gate width of the first gate electrode G1 (L3 in FIG. 14) is larger than the gate width of the second gate electrode G2 (L4 in FIG. 14). Here, the distance between the first and second gate electrodes G1, G2 (L in FIG. 14) is about 0.05 μm or more and 0.1 μm or less. An insulating film (not shown) is preferably provided between the first and second gate electrodes G1, G2. The first and second gate electrodes G1, G2 are reliably insulated by the insulating film. In FIG. 14, the first and second gate electrodes G1 and G2 are formed so as to reach the STI 9, but the first and second gate electrodes G1 and G2 are located in a region sandwiched between the STI9. It may be formed only on the gate insulating film 5. With the above configuration, a bulk transistor (first transistor) including the first gate electrode G1 and the source / drain regions 3 and 4 and a bulk transistor including the second gate electrode G2 and the source / drain regions 3 and 4 (second transistor). ) And are formed. Here, since the first and second gate electrodes G1, G2 are arranged in parallel between the source / drains 3, 4, such a transistor 1 is referred to as a “bulk parallel transistor” in the present specification. There is a case.

  In the transistor 1, when a voltage higher than the threshold voltage of the first transistor is applied to the first gate electrode G 1, an inversion region in which the conductivity type is inverted is formed below the first gate electrode G 1. As a result, a “transistor 1 ON state” in which a current (ON current) of a certain value or more flows between the source / drain regions 3 and 4 is realized. Here, a predetermined voltage may or may not be applied to the second gate electrode G2.

  In the transistor 1, when only a voltage lower than the threshold voltage of the first transistor is applied to the first gate electrode G1, a sufficient inversion region is not formed under the first gate electrode G1, and the source / drain region 3 is not formed. , 4 does not flow the ON current. Here, when a voltage higher than the threshold voltage of the second transistor is applied to the second gate electrode G2, the semiconductor substrate 2 below the second gate electrode G2 is affected, and is smaller than the ON current, but will be described later. A “leak mode” in which a leak current larger than the current flows between the source / drain regions 3 and 4 is realized.

  In the transistor 1, when only a voltage lower than the threshold voltage of the first and second transistors is applied to the first and second gate electrodes G1 and G2, respectively, the above-described ON current and leakage current do not occur. "OFF state" is realized. However, also in this case, a minute current (OFF current) of a certain value or less flows between the source / drain regions 3 and 4.

  15 to 17 are cross-sectional views showing the states of the respective steps in the manufacturing process of the transistor 1 shown in FIG. A method for manufacturing the transistor 1 will be described with reference to FIGS. In the method for manufacturing the transistor 1 according to the present embodiment, as shown in FIGS. 15 to 17, the first gate electrode G <b> 1 is formed on the main surface of the semiconductor substrate 2 via the gate insulating film 5 (FIG. 15). ), Forming a second gate electrode G2 on the main surface of the semiconductor substrate 2 via the gate insulating film 5 so as to be aligned with the first gate electrode G1 (FIG. 16), and the first and second gate electrodes G1 , G2 forming source / drain regions 3 and 4 (see FIG. 18) in the semiconductor substrate 2 so as to sandwich the first and second gate electrodes G1 and G2 in a direction orthogonal to the direction in which the two are arranged (FIG. 17); Is provided.

  As shown in FIG. 15, the gate insulating film 5 is formed on the p-type semiconductor substrate 2. After the p-type impurity for adjusting the threshold voltage is implanted into the semiconductor substrate 2, the first gate electrode G <b> 1 is formed on the gate insulating film 5. Next, as shown in FIG. 16, the second gate electrode G2 is formed on the gate insulating film 5 so as to be aligned with the first gate electrode G1. Then, as shown in FIG. 17, n-type impurities that become source / drain regions 3 and 4 are formed on both sides of the first and second gate electrodes G1 and G2 (the front side and the back side in FIG. 17). Injected (arrow in FIG. 17). Through the above steps, the “bulk parallel transistor” shown in FIG. 14 is obtained.

  FIG. 18 is a top view of the transistor 1. The XIV-XIV cross section in FIG. 18 corresponds to FIG. Referring to FIG. 18, in transistor 1 according to the present embodiment, since source / drain regions 3 and 4 are shared by first and second gate electrodes G1 and G2, the bulk area is excessively increased. Thus, a transistor having a leak mode can be obtained.

  FIG. 19 is a top view showing a modification of the transistor 1 according to the present embodiment. 20 corresponds to the XX-XX cross section in FIG. Referring to FIGS. 19 and 20, in this modification, a part of second gate electrode G2 is formed so as to overlap first gate electrode G1 with insulating film 6A interposed therebetween. The first and second gate electrodes G1, G2 are electrically insulated by the insulating film 6A. Employing the structure shown in FIGS. 19 and 20 facilitates photolithography in patterning of the first and second gate electrodes G1 and G2.

  In the present embodiment also, the conductivity types of the first and second gate electrodes G1 and G2 can be made different in order to adjust the threshold voltages of the first and second gate electrodes G1 and G2. In the present embodiment, detailed description of the same matters as in the first and second embodiments is not repeated.

(Embodiment 4)
FIG. 21 is a cross-sectional view showing the transistor 1 according to the fourth embodiment. The transistor 1 according to the present embodiment is a modification of the transistor according to the third embodiment. Referring to FIG. 21, in the transistor 1 according to the present embodiment, the gate insulating film 5 located under the first gate electrode G1 is used to adjust the threshold voltages of the first and second gate electrodes G1, G2. And the thickness of the gate insulating film (5, 5A) located under the second gate electrode G2. In the example shown in FIG. 21, the thickness of the gate insulating film (5, 5A) located under the second gate electrode G2 is larger than the thickness of the gate insulating film 5 located under the first gate electrode G1. Thereby, the threshold voltage of the second transistor including the second gate electrode G2 can be set higher. Note that the thickness of the gate insulating film located under the first gate electrode G1 may be larger than the thickness of the gate insulating film located under the second gate electrode G2. In this case, the threshold voltage of the first transistor including the first gate electrode G1 can be set higher.

  22 to 24 are cross-sectional views showing the states of the respective steps in the manufacturing process of the transistor 1 shown in FIG. A method for manufacturing the transistor 1 will be described with reference to FIGS. As shown in FIGS. 22 to 24, the method of manufacturing the transistor 1 according to the present embodiment is performed before the first and second gate electrodes G1 and G2 are formed on the main surface of the semiconductor substrate 2. A gate insulating film 5A (another gate insulating film) is formed on the main surface of the semiconductor substrate 2 located below only one of the second gate electrodes G1 and G2 (only the second gate electrode G2 in the examples of FIGS. 21 to 24). The method further includes the step of forming.

  As shown in FIG. 22, after the gate insulating film 5A is formed on the p-type semiconductor substrate 2, a resist mask 10A is provided on the region where the second gate electrode G2 is provided. Next, as shown in FIG. 23, the portion of the gate insulating film 5A not covered with the resist mask 10A is removed with hydrofluoric acid or the like, and the resist mask 10A is also removed. Then, as shown in FIG. 24, gate insulating film 5 is formed so as to cover semiconductor substrate 2 and gate insulating film 5A. Thereafter, a p-type impurity for adjusting a threshold voltage is implanted into the semiconductor substrate 2, and then first and second gate electrodes G1 and G2 are formed on the gate insulating films 5 and 5A, and the first and second gate electrodes G1 are formed. , G2 are implanted with n-type impurities to be the source / drain regions 3 and 4 on both sides (the front side and the back side in FIG. 24).

  In the present embodiment, as a modification of the “bulk parallel transistor” according to the third embodiment, a case where the thicknesses of the gate insulating films located under the first and second gate electrodes G1 and G2 are made different will be described. However, it is naturally planned to apply the same idea to the “bulk series transistor” according to the second embodiment. In the present embodiment, detailed description of the same matters as in the first to third embodiments described above will not be repeated.

(Embodiment 5)
25 and 26 are cross-sectional views showing the state of each step in the manufacturing process of the transistor 1 according to the fifth embodiment. The transistor 1 according to the present embodiment is a modification of the transistor according to the third embodiment. In the transistor 1 according to the present embodiment, in order to adjust the threshold voltage of the first and second gate electrodes G1 and G2, the impurity concentration and the second gate in the semiconductor substrate 2 located under the first gate electrode G1. The impurity concentration in the semiconductor substrate 2 located under the electrode G2 is made different.

  As shown in FIGS. 25 and 26, the manufacturing method of the transistor 1 according to the present embodiment includes the first and second gate electrodes G1, G1 on the semiconductor substrate 2 positioned below the first and second gate electrodes G1, G2. A step of implanting an impurity for adjusting a threshold voltage of a transistor including G2 (first and second transistors) (FIG. 25), and only one of the first and second gate electrodes G1 and G2 (examples of FIGS. 25 and 26) Then, a step of implanting an impurity for adjusting the threshold voltage of the first or second transistor (second transistor in the examples of FIGS. 25 and 26) into the semiconductor substrate 2 located below the second gate electrode G2 (FIG. 26). ). The process shown in FIG. 25 is also provided in the above-described first to fourth embodiments.

  As shown in FIG. 25, after the gate insulating film 5 is formed on the p-type semiconductor substrate 2, p-type impurities for adjusting the threshold voltage of the first and second transistors are implanted (broken line in FIG. 25). Arrow). Next, as shown in FIG. 26, after the first gate electrode G1 is formed on the gate insulating film 5, using the first gate electrode G1 as a mask, the threshold voltage of the second transistor including the second gate electrode G2 A p-type impurity for adjustment is implanted (broken arrow in FIG. 26). Thereafter, a second gate electrode G2 is formed on the gate insulating film 5, and the source / drain regions 3 are formed on both sides of the first and second gate electrodes G1 and G2 (the front side of the paper and the back side of the paper in FIG. 26). , 4 are implanted. Through the above steps, the threshold voltage of the second transistor including the second gate electrode G2 can be set higher.

  FIG. 27 is a view showing a modification of the manufacturing method. Referring to FIG. 27, after the process shown in FIG. 25 is performed, second gate electrode G2 is formed on gate insulating film 5 and includes first gate electrode G1 using second gate electrode G2 as a mask. A p-type impurity for adjusting the threshold voltage of the first transistor may be implanted (broken arrow in FIG. 27). Thereby, the threshold voltage of the first transistor including the first gate electrode G1 can be set higher.

  In the present embodiment, as a modification of the “bulk parallel transistor” according to the third embodiment, the impurity concentrations in the semiconductor substrate 2 located under the first and second gate electrodes G1, G2 are different. However, it is natural that the same idea is applied to the “bulk series transistor” according to the second embodiment. In the present embodiment, detailed description of the same matters as in the first to fourth embodiments described above will not be repeated.

(Embodiment 6)
FIG. 28 is a cross-sectional view showing a state of an intermediate process in the manufacturing process of transistor 1 according to the sixth embodiment. The transistor 1 according to the present embodiment is a modification of the method for manufacturing the transistor according to the fifth embodiment. In the method for manufacturing the transistor 1 according to the present embodiment, the impurity concentration in the semiconductor substrate 2 located under the first gate electrode G1 is different from the impurity concentration in the semiconductor substrate 2 located under the second gate electrode G2. Therefore, a resist mask 10B is used.

  After performing the process shown in FIG. 25, as shown in FIG. 28, a resist mask 10B is provided in the region where the first gate electrode G1 is formed on the gate insulating film 5. Next, using the resist mask 10B as a mask, a p-type impurity for adjusting the threshold voltage of the second transistor including the second gate electrode G2 is implanted (broken line arrow in FIG. 28). After the resist mask 10B is removed, first and second gate electrodes G1, G2 are formed on the gate insulating film 5, and both sides of the first and second gate electrodes G1, G2 (on the front side of the paper surface in FIG. 28). An n-type impurity to be the source / drain regions 3 and 4 is implanted into the back side of the drawing. Through the above steps, the threshold voltage of the second transistor including the second gate electrode G2 can be set higher.

  FIG. 29 is a view showing a modified example of the manufacturing method. Referring to FIG. 29, after the step shown in FIG. 25 is performed, a resist mask 10A is provided in the region where second gate electrode G2 is formed on gate insulating film 5, and resist mask 10A is used as a mask. A p-type impurity for adjusting the threshold voltage of the first transistor including one gate electrode G1 may be implanted (broken line arrow in FIG. 29). Thereby, the threshold voltage of the first transistor including the first gate electrode G1 can be set higher.

  In the present embodiment, as a modification of the “bulk parallel transistor” according to the third embodiment, the impurity concentrations in the semiconductor substrate 2 located under the first and second gate electrodes G1, G2 are different. However, it is natural that the same idea is applied to the “bulk series transistor” according to the second embodiment. Moreover, in this Embodiment, detailed description is not repeated about the matter similar to Embodiment 1-5 mentioned above.

  As mentioned above, although embodiment of this invention was described, combining the characteristic part of each embodiment mentioned above suitably is planned from the beginning. Moreover, it should be thought that embodiment disclosed this time is an illustration and restrictive at no points. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is the circuit diagram which showed typically the semiconductor device which concerns on Embodiment 1-6 of this invention, (a) shows a "bulk + TFT type transistor", (b) shows a "bulk series type transistor", (C) shows a “bulk parallel transistor”. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. It is the figure which showed the 1st process in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is the figure which showed the 2nd process in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is the figure which showed the 3rd process in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. 1 is a top view showing a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which showed the semiconductor device which concerns on Embodiment 2 of this invention. It is the figure which showed the 1st process in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is the figure which showed the 2nd process in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is the figure which showed the 3rd process in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is the top view which showed the semiconductor device which concerns on Embodiment 2 of this invention. It is the top view which showed the modification of the semiconductor device which concerns on Embodiment 2 of this invention. It is XIII-XIII sectional drawing in FIG. It is sectional drawing which showed the semiconductor device which concerns on Embodiment 3,5,6 of this invention. It is the figure which showed the 1st process in the manufacturing process of the semiconductor device which concerns on Embodiment 3 of this invention. It is the figure which showed the 2nd process in the manufacturing process of the semiconductor device which concerns on Embodiment 3 of this invention. It is the figure which showed the 3rd process in the manufacturing process of the semiconductor device which concerns on Embodiment 3 of this invention. It is the top view which showed the semiconductor device which concerns on Embodiment 3, 5, and 6 of this invention. It is the top view which showed the modification of the semiconductor device which concerns on Embodiment 3,5,6 of this invention. It is XX-XX sectional drawing in FIG. It is sectional drawing which showed the semiconductor device which concerns on Embodiment 4 of this invention. It is the figure which showed the 1st process in the manufacturing process of the semiconductor device which concerns on Embodiment 4 of this invention. It is the figure which showed the 2nd process in the manufacturing process of the semiconductor device which concerns on Embodiment 4 of this invention. It is the figure which showed the 3rd process in the manufacturing process of the semiconductor device which concerns on Embodiment 4 of this invention. It is the figure which showed the 1st process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention. It is the figure which showed the 2nd process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention. It is the figure which showed the intermediate process in the modification of the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention. It is the figure which showed the intermediate process in the manufacturing process of the semiconductor device which concerns on Embodiment 6 of this invention. It is the figure which showed the intermediate process in the modification of the manufacturing process of the semiconductor device which concerns on Embodiment 6 of this invention. 1 is an equivalent circuit diagram of a semiconductor memory device including a semiconductor device according to first to sixth embodiments of the present invention.

Explanation of symbols

  1 transistor (semiconductor device), 2 semiconductor substrate, 3, 4 source / drain region, 5, 5A, 8 gate insulating film, 6, 6A insulating film, 7 conductive film, 9 STI, 10A, 10B resist mask, 50 memory cell 50A, 50B data holding unit, 52A, 52B access transistor, 54A, 54B capacitor, 56A, 56B p-channel TFT, 60, 62 node, 64, 66 word line, 68A, 68B bit line, 70 cell plate, 72 power supply node , G1, G1A, G1B first gate electrode, G2, G2A, G2B second gate electrode, 100 semiconductor memory device.

Claims (19)

A semiconductor substrate;
A first transistor including a first gate electrode formed on a main surface of the semiconductor substrate and source / drain regions formed on the semiconductor substrate;
A second transistor including a second gate electrode formed on the main surface of the semiconductor substrate and the source / drain region;
A first state in which at least the first transistor is in an ON state;
A second state in which the first and second transistors are in an OFF state;
A semiconductor device that realizes a third state in which the first transistor is in an OFF state and the second transistor is in an ON state. The first gate electrode is formed on the main surface of the semiconductor substrate via a gate insulating film,
The semiconductor device according to claim 1, wherein the second gate electrode is formed in an upper layer than the first gate electrode.   2. The semiconductor device according to claim 1, wherein the first and second gate electrodes are formed on a main surface of the semiconductor substrate via a gate insulating film so as to be aligned in a direction from the source region toward the drain region. .   The semiconductor device according to claim 3, wherein a gate length of the first gate electrode is larger than a gate length of the second gate electrode.   The semiconductor device according to claim 4, wherein a gate length of the second gate electrode is 0.05 μm or more and 0.1 μm or less.   The first and second gate electrodes are formed on a main surface of the semiconductor substrate via a gate insulating film so as to be aligned in a direction orthogonal to a direction from the source region to the drain region. The semiconductor device described.   The semiconductor device according to claim 6, wherein a gate width of the first gate electrode is larger than a gate width of the second gate electrode.   The semiconductor device according to claim 7, wherein an interval between the first and second gate electrodes is 0.05 μm or more and 0.1 μm or less.   The semiconductor device according to claim 3, wherein a part of the second gate electrode is formed so as to overlap the first gate electrode with an insulating film interposed therebetween.   The semiconductor device according to claim 3, wherein a conductivity type of the first gate electrode is different from a conductivity type of the second gate electrode.   11. The semiconductor device according to claim 3, wherein a thickness of the gate insulating film located under the first gate electrode is different from a thickness of the gate insulating film located under the second gate electrode. .   The impurity concentration in the semiconductor substrate located under the first gate electrode and the impurity concentration in the semiconductor substrate located under the second gate electrode are different from each other. Semiconductor device. Forming a first gate electrode on a main surface of a semiconductor substrate via a first gate insulating film;
Forming source / drain regions on both sides of the first gate electrode in the semiconductor substrate;
Forming an insulating film on the first gate electrode from the main surface of the semiconductor substrate;
Forming a contact hole reaching the source / drain region in the insulating film;
Forming a conductive film for connecting the source / drain region on the insulating film from within the contact hole;
Forming a second gate electrode on the conductive film with a second gate insulating film interposed therebetween. Forming a first gate electrode on a main surface of a semiconductor substrate via a gate insulating film;
Forming a second gate electrode on the main surface of the semiconductor substrate so as to be aligned with the first gate electrode via the gate insulating film;
Forming a source / drain region in the semiconductor substrate so as to sandwich the first and second gate electrodes in a direction in which the first and second gate electrodes are arranged. Forming a first gate electrode on a main surface of a semiconductor substrate via a gate insulating film;
Forming a second gate electrode on the main surface of the semiconductor substrate so as to be aligned with the first gate electrode via the gate insulating film;
Forming a source / drain region in the semiconductor substrate so as to sandwich the first and second gate electrodes in a direction perpendicular to the direction in which the first and second gate electrodes are arranged. A step of forming an insulating film on the first gate electrode;
16. The method for manufacturing a semiconductor device according to claim 14, wherein a part of the second gate electrode is formed so as to overlap the first gate electrode with the insulating film interposed therebetween. The first gate electrode is formed of a first conductivity type;
The method of manufacturing a semiconductor device according to claim 14, wherein the second gate electrode is formed with a second conductivity type different from the first conductivity type.   18. The method according to claim 14, further comprising a step of forming another gate insulating film on a main surface of the semiconductor substrate located under only one of the first and second gate electrodes. Manufacturing method of the semiconductor device. Injecting an impurity for adjusting a threshold voltage of a transistor including the first and second gate electrodes into the semiconductor substrate located under the first and second gate electrodes;
And a step of implanting an impurity for adjusting a threshold voltage of a transistor including the first and second gate electrodes into the semiconductor substrate located under only one of the first and second gate electrodes. The method for manufacturing a semiconductor device according to claim 14.

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