JP2006086548A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor with high breakdown voltage and low on-resistance. <P>SOLUTION: A semiconductor substrate constituted by laminating an epitaxial region 221 of a SiC semiconductor 211 and a groove 360 formed on a prescribed part on one surface of the semiconductor substrate 211 are installed on the SiC semiconductor substrate 211. The transistor includes a gate semiconductor region 253 formed on an inner face of the groove 360, an N-type embedded channel region 262 formed in an epitaxial region 221 becoming an outer side of the P-type gate semiconductor region 253, and a channel region 382 formed of a P-type body semiconductor region 254 formed on an outer side of the embedded channel region 262. The transistor also includes a source region 242 formed on an upper side of the embedded channel region 262, a gate electrode 282 formed on an inner side of the gate semiconductor region 253 through a gate insulating film 272, and a gate electrode 292 formed on the other surface of the semiconductor substrate 211. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor that can keep on-resistance low.

  As a conventional field effect transistor, for example, the one described in JP-A-9-74193 (Patent Document 1) is known. FIG. 7 is a cross-sectional view showing the configuration of the field effect transistor described in Patent Document 1.

  As shown in the figure, in this field effect transistor, an epitaxial region 202 made of N− type SiC is formed on a wide band gap semiconductor substrate 201 made of high concentration N + type SiC (silicon carbide). An epitaxial region 203 made of P − type SiC is formed on 202.

  An N + type source region 205 and a P + type body contact region 204 are formed in a predetermined region in the surface layer portion of the epitaxial region 203. Further, a groove 208 is formed in the epitaxial region 203 so as to penetrate the epitaxial region 203 and reach the epitaxial region 202.

  Further, a channel region 206 made of N − type SiC is formed on the side wall of the groove 208. Further, the source electrode 211 is formed which is insulated from the gate electrode 209 by the interlayer insulating film 212 and connected to the source region 205 and the body contact region 204, and the drain electrode 210 is formed on the back surface of the wide band gap semiconductor substrate 201. ing.

In this field effect transistor, when a voltage is applied between the drain electrode 210 and the source electrode 211 and a voltage is applied to the gate electrode 209, the surface layer of the channel region 206 facing the gate electrode 209 is An N-type accumulation layer type channel is formed, and a current flows from the drain electrode 210 to the source electrode 211.
Japanese Patent Laid-Open No. 9-74193

  In the SiC storage field effect transistor described in Patent Document 1 described above, an incomplete crystal structure exists at the interface between the gate insulating film 207 and the N − -type storage channel formation region 206. Therefore, a large amount of interface states exist in the accumulation channel in the surface layer of the channel region 206 formed by applying a voltage to the gate electrode 209, and these act as electron traps, so that the channel mobility cannot be increased and the on-resistance is increased. There is a problem that is high.

  Regarding the breakdown voltage, when a high voltage is applied to the drain electrode 210, a high voltage is applied to the gate insulating film 207 at the bottom of the trench 208. When this insulating film 207 is broken, a large amount of leakage current is generated, and therefore, there is a problem that it is impossible to realize a high breakdown voltage utilizing the high dielectric breakdown electric field inherent to SiC, which is a wide cap semiconductor. It was.

  The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a field effect transistor having a high breakdown voltage and a low on-resistance. In particular, an object is to provide a field-effect transistor having a low on-resistance having a high channel mobility, which is a normally-off voltage-driven type, targeting a wide gap semiconductor device.

  In order to achieve the above object, the invention described in claim 1 is a semiconductor substrate configured by stacking an epitaxial region of a wide band gap semiconductor on a substrate of a wide band gap semiconductor having a wider band gap than silicon. And a groove formed in a predetermined part of one surface of the semiconductor substrate, a first conductivity type gate semiconductor region formed in the inner surface of the groove, and formed in the epitaxial region outside the gate semiconductor region A channel region formed of a second conductivity type buried channel region and a first conductivity type body semiconductor region formed outside the buried channel region; and formed above the buried channel region. A source electrode formed in the source region, and a gate electrode formed inside the gate semiconductor region through a gate insulating film. When, and having a drain electrode formed on the other surface of the semiconductor substrate.

  According to a second aspect of the present invention, there is provided a semiconductor substrate configured by laminating an epitaxial region of a wide band gap semiconductor on a wide band gap semiconductor substrate having a wider band gap than silicon, and one of the semiconductor substrates. A groove formed in a predetermined portion of the surface; a first conductivity type gate semiconductor region formed on the inner surface of the groove; and a second conductivity type buried in the epitaxial region outside the gate semiconductor region. A buried channel region, a source region formed above the buried channel region, a source electrode formed in the source region, and a gate insulating film inside the gate semiconductor region. And a drain electrode formed on the other surface of the semiconductor substrate.

  The invention according to claim 3 is characterized in that the first conductive type gate semiconductor region is formed by CVD epitaxial growth.

  The invention according to claim 4 is characterized in that the wide band gap semiconductor is a silicon carbide semiconductor.

  The invention according to claim 5 is characterized in that the first conductivity type is one of P-type and N-type, and the second conductivity type is the other of P-type and N-type. To do.

  According to the first aspect of the present invention, when no gate voltage is applied, the first depletion layer generated at the junction of the gate semiconductor region and the buried channel region is the second depletion layer generated at the junction of the body semiconductor region and the buried channel region. Thus, the buried channel region can be completely depleted, and a storage channel can be formed in the buried channel region by applying a voltage to the gate. Accordingly, the on-resistance between the drain and the source can be reduced.

  According to the invention of claim 2, when the gate voltage is not applied, the buried channel region is completely depleted by the depletion layer generated at the junction between the gate semiconductor region and the buried channel region, while the gate voltage is applied. Thus, a storage channel can be formed in the buried channel region. As a result, the on-resistance between the drain and the source can be reduced.

  In addition, when a high voltage is applied between the drain electrode and the source electrode, an electric field applied to the gate insulating film is shielded by a depletion layer extending from the first conductivity type gate semiconductor region formed along the trench. Therefore, it is possible to realize a high withstand voltage corresponding to the high breakdown electric field of the wide band gap semiconductor, which is not determined by the withstand voltage of the gate insulating film.

  According to the invention of claim 3, since the first conductive type gate semiconductor region along the groove can be formed by CVD epitaxial growth, the gate semiconductor region can be a high quality region with few crystal defects. As a result, there is an advantage that the quality of the gate insulating film formed on the surface of the gate semiconductor region can be improved or the leakage current at the time of ON is reduced.

  In the invention of claim 4, by using silicon carbide semiconductor (SiC) as the wide band gap semiconductor, the built-in voltage of the PN junction is large, and the current becomes non-conductive when no voltage is applied to the gate electrode. Such a design can be easily performed.

  In the fifth aspect of the invention, the first conductivity type and the second conductivity type are P-type and N-type, so that flexibility is high.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the field effect transistor of the present invention, the first conductivity type is P-type and the second conductivity type is N-type, but the first conductivity type is N-type and the second conductivity type is P-type. Also good. In this embodiment, an MIS field effect transistor in which a polysilicon electrode is formed on a gate insulating film will be described as an example. However, a MESFET type using a Schottky metal for the gate electrode may be used.

  Although not taken up in this embodiment, the present invention can also be applied to voltage-driven field effect transistor elements such as IGBTs and MIS thyristors. Furthermore, it goes without saying that modifications within the scope of the present invention are included.

[First embodiment]
FIG. 1 is a cross-sectional view of a unit cell of a SiC field effect transistor according to a first embodiment of the present invention. As shown in the drawing, in a wafer in which an N− type SiC epitaxial region 221 is stacked on an N + type SiC substrate 211 serving as a drain region, an N + type source region 242 is formed in a predetermined region in the surface layer portion of the epitaxial region 221. A P + type body contact region 350 is formed. Further, a groove 360 is formed in a predetermined region of one main surface of the N − type epitaxial region 221, and a P − type gate semiconductor region 253 is formed along the groove 360.

  A P − type body semiconductor region 254 having a predetermined depth including the body contact region 350 is formed in a predetermined region in the surface layer portion of the epitaxial region 221. Here, an N − type buried channel region 262 is formed in the portion of the epitaxial region 221 between the gate semiconductor region 253 and the body semiconductor region 254. A region including the gate semiconductor region 253, the buried channel region 262, and the body semiconductor region 254 is referred to as a channel region 382.

  Note that the thicknesses and carrier concentrations of the gate semiconductor region 253, the buried channel region 262, and the body semiconductor region 254 are such that the conduction carriers existing in the N − type buried channel region 262 are different from the gate semiconductor region 253 and the body semiconductor region 254. Designed to be depleted by electrostatic potential.

  More specifically, the first depletion layer generated at the junction between the gate semiconductor region 253 and the buried channel region 262 contacts the second depletion layer generated at the coupling between the body semiconductor region 254 and the buried channel region 262, thereby The buried channel region 262 is designed to be completely depleted.

  A gate electrode 282 is formed on the surface of the P − -type gate semiconductor region 253 with a gate insulating film 272 interposed therebetween. A source electrode 302 is formed on the upper surface of the source region 242. Further, a body contact electrode 311 is formed on the upper surface of the body contact region 350. A drain electrode 292 is formed on the back surface of the N + -type SiC substrate 211.

  Next, an example of a method for manufacturing the field effect transistor of this example will be described with reference to the cross-sectional views shown in FIGS. 2 (a) to 2 (c) and FIGS. 3 (d) to 3 (f).

First, in the step of FIG. 2 (a), the impurity concentration of, for example, on the N + -type SiC substrate 211 is 1E14~1E18 / cm ^3, thickness to form a 1~100μm N- type SiC epitaxial region 221.

  In the step of FIG. 2B, a groove 360 having a depth of, for example, 0.1 to 5 μm is formed in a predetermined region of one main surface of the N − type epitaxial region 221.

  In the step of FIG. 2C, SiC is homoepitaxially grown along the trench 360 by a CVD method to form a P− type gate semiconductor region 253.

  The P − type gate semiconductor region may be formed by ion implantation of boron or the like, for example.

  3D, for example, phosphorus ions are implanted into a predetermined region of the surface layer portion of the N − type epitaxial region 221 to form an N + type source region 242. Nitrogen, arsenic, or the like may be used in addition to phosphorus as an impurity that becomes an N-type impurity.

  In the step of FIG. 3E, for example, boron ions are implanted into a predetermined region of the surface layer portion of the N − type epitaxial region 221 to form a P + type body contact region 350 and a P − type body semiconductor region 254. . The portion of the epitaxial region 221 between the gate semiconductor region 253 and the body semiconductor region 254 is referred to as an N − type buried channel region 262.

  Here, the thickness and carrier concentration of the gate semiconductor region 253, the buried channel region 262, and the body semiconductor region 254 are such that the first depletion layer generated at the junction between the gate semiconductor region 253 and the buried channel region 262 is the body semiconductor region. It is designed to contact the second depletion layer generated at the junction of 254 and the buried channel region 262, thereby completely depleting the buried channel region 262.

  In addition, after performing ion implantation, the heat processing at 1000-1700 degreeC is performed, for example, and the implanted impurity is activated. Thus, a channel region 382 including the gate semiconductor region 253, the buried channel region 262, and the body semiconductor region 254 is completed.

  In the step of FIG. 3F, a gate insulating film 272 is formed on the surface of the P − type gate semiconductor region 253 by thermal oxidation at 900 to 1300 ° C., for example. Thereafter, the gate electrode 282 is formed from polysilicon, for example.

  Thereafter, although not particularly illustrated, the source electrode 302 is formed on the upper surface of the source region 242, and the body contact electrode 311 is formed on the upper surface of the body contact region 350. A drain electrode 292 is formed on the back surface of the N + substrate 211. Thus, the field effect transistor shown in FIG. 1 is completed.

  In this embodiment, the source electrode 302 and the body contact electrode 311 may be formed at least on part of the surfaces of the N + -type source region 242 and the body semiconductor region 350. Further, although the bottom surface of the groove 360 is formed with a curved surface, it may not be a curved surface. The cross-sectional shape of the groove may be a shape having no bottom surface like a V-shaped groove.

  Next, the operation of the field effect transistor according to this embodiment will be described. In a state where no voltage is applied to the gate electrode 282, the first depletion layer that spreads corresponding to the built-in voltage formed by the junction between the gate semiconductor region 253 and the buried channel region 262 is formed in the body semiconductor region 254 and the buried channel. The buried channel region 262 can be pinched off by contacting the second depletion layer extending from the junction of the region 262 corresponding to the built-in voltage.

  As a result, the current between the source S and the drain D can be cut off, and normally off. In addition, when a wide bandgap semiconductor substrate made of SiC is used, the design is such that the built-in voltage of the PN junction is large and the current is non-conductive when no voltage is applied to the gate electrode. It can be done easily.

  Next, when a negative bias is supplied to the gate electrode 282, an accumulation type channel region extending from the N + type source region 242 toward the N − type drift region (epitaxial region) 221 is formed in the buried channel region 262. Formed and switched to the on state. At this time, electrons flow from the N + type source region 242 to the N − type epitaxial region 221 via the storage channel formed in the buried channel region 262. When reaching the N − type epitaxial region 221, electrons flow perpendicularly to the N + type SiC substrate 211.

  In this manner, by applying a negative voltage to the gate electrode 282, an accumulation channel is induced in the buried channel region 262, and carriers flow between the source electrode 302 and the drain electrode 292.

  As a result, a normally-off voltage-driven field effect transistor having high channel mobility can be obtained. In particular, the accumulation channel formed in the buried channel region 262 is not affected by an incomplete crystal structure existing at the interface between the gate insulating film 272 and the gate semiconductor region 253, and thus channel mobility can be increased. it can. As a result, the channel resistance can be drastically reduced, and the on-resistance between the drain and the source can be reduced.

  When a high voltage is applied between the drain electrode 292 and the source electrode 302, the electric field applied to the gate insulating film 272 is shielded by the depletion layer extending from the P − -type gate semiconductor region 253 formed along the trench 360. Therefore, it is possible to realize a high breakdown voltage that is not determined by the breakdown voltage of the gate insulating film 272 and corresponds to the high breakdown electric field of the wide band gap semiconductor.

[Second Embodiment]
FIG. 4 is a cross-sectional view of a unit cell of an SiC field effect transistor according to the second embodiment of the present invention. As shown in the figure, in a wafer in which an N− type SiC epitaxial region 222 is stacked on an N + type SiC substrate 212 serving as a drain region, an N + type source is provided in a predetermined region in the surface layer portion of the epitaxial region 222. Region 243 is formed. Further, a groove 361 is formed in a predetermined region of one main surface of the N − type epitaxial region 222, and a P − type gate semiconductor region 255 is formed along the groove 361.

  A groove 362 is formed in a predetermined region on one main surface of the epitaxial region 222, and an insulating film 370 is embedded in the groove 362. Here, an N − type buried channel region 263 is formed in a portion of the epitaxial region 222 between the gate semiconductor region 255 and the insulating film 370. A region including the gate semiconductor region 255 and the buried channel region 263 is referred to as a channel region 383.

  Note that the thickness and carrier concentration of the gate semiconductor region 255 and the buried channel region 263 depend on the buried channel region 263 due to a depletion layer extending from the junction between the gate semiconductor region 255 and the buried channel region 263 corresponding to the built-in voltage. Is designed to be fully depleted.

  A gate electrode 283 is formed on the surface of the P − -type gate semiconductor region 255 with a gate insulating film 273 interposed therebetween. A source electrode 303 is formed on the source region 243. A drain electrode 293 is formed on the back surface of the N + substrate 212.

  Next, an example of a method for manufacturing the field effect transistor of this embodiment will be described with reference to the cross-sectional views shown in FIGS. 5 (a) to 5 (c) and FIGS. 6 (d) to 6 (f).

First, in the process of FIG. 5A, an N − SiC epitaxial region 222 having an impurity concentration of 1E14 to 1E18 / cm ³ and a thickness of 1 to 100 μm is formed on an N + SiC substrate 212, for example.

  In the step of FIG. 5B, a groove 361 having a depth of, for example, 0.1 to 5 μm is formed in a predetermined region of one main surface of the N − type epitaxial region 222.

  In the step of FIG. 5C, SiC is homoepitaxially grown along the trench 361 by a CVD method to form a P − type gate semiconductor region 255.

  The P − type gate semiconductor region may be formed by ion implantation of boron or the like, for example.

  In the step shown in FIG. 6D, for example, phosphorus ions are implanted into a predetermined region of the surface layer portion of the N − type epitaxial region 222 to form an N + type source region 243. Nitrogen, arsenic, or the like may be used in addition to phosphorus as an impurity that becomes an N-type impurity.

  In addition, after performing ion implantation, the heat processing at 1000-1700 degreeC is performed, for example, and the implanted impurity is activated.

  In the step of FIG. 6E, a groove 362 having a depth of, for example, 0.1 to 5 μm is formed in a predetermined region of one main surface of the N − type epitaxial region 222.

  In the step shown in FIG. 6F, silicon dioxide having a thickness of 0.1 to 5 μm is deposited by using, for example, the LPCVD method, and the groove 362 is buried. Thereafter, the silicon dioxide film is mechanically and chemically polished using, for example, a CMP method, and the silicon dioxide film 370 is left inside the trench. Here, an N − type buried channel region 263 is formed in a portion of the epitaxial region 222 between the gate semiconductor region 255 and the silicon dioxide film 370.

  Thus, a channel region 383 including the gate semiconductor region 255 and the buried channel region 263 is completed. Note that the thickness and carrier concentration of the gate semiconductor region 255 and the buried channel region 263 are designed so that the gate semiconductor region 255 and the buried channel region 263 are completely depleted.

  Thereafter, a gate insulating film 273 is formed on the surface of the P − type gate semiconductor region 255 by thermal oxidation at 900 to 1300 ° C., for example. Then, the gate electrode 283 is formed from polysilicon, for example.

  Thereafter, although not particularly illustrated, the source electrode 303 is formed on the upper surface of the source region 243. A drain electrode 293 is formed on the back surface of the N + -type SiC substrate 212. Thus, the field effect transistor shown in FIG. 4 is completed.

  In this embodiment, the source electrode 303 only needs to be formed on at least part of the surface of the N + -type source region 243. Further, although the bottom surface of the groove 361 is formed with a curved surface, it may not be a curved surface. The cross-sectional shape of the groove may be a shape having no bottom surface like a V-shaped groove.

  Next, the operation of this field effect transistor will be described. In a state where no voltage is applied to the gate electrode 283, the buried channel region 263 can be pinched off by a depletion layer extending from the junction between the gate semiconductor region 255 and the buried channel region 263 corresponding to the built-in voltage. As a result, the current between the source S and the drain D can be cut off and normally off.

  In addition, when a wide bandgap semiconductor substrate made of SiC is used, the design is such that the built-in voltage of the PN junction is large and the current becomes non-conductive when no voltage is applied to the gate electrode. It can be done easily.

  Next, when a negative bias is supplied to the gate electrode 283, an accumulation type channel region extending from the N + type source region 243 toward the N − type drift region (epitaxial region) 222 is formed in the buried channel region 263. Formed and switched to the on state. At this time, electrons flow from the N + type source region 243 to the N − type epitaxial region 222 via the storage channel formed in the buried channel region 263. When reaching the N − type epitaxial region 222, electrons flow perpendicularly to the N + type SiC substrate 212.

  In this way, by applying a negative voltage to the gate electrode 283, an accumulation channel is induced in the buried channel region 263, and carriers flow between the source electrode 303 and the drain electrode 293.

  As a result, a normally-off voltage-driven field effect transistor having high channel mobility can be obtained. In particular, the accumulation channel formed in the buried channel region 263 is not affected by an incomplete crystal structure existing at the interface between the gate insulating film 273 and the gate semiconductor region 255, and thus channel mobility can be increased. it can. As a result, the channel resistance can be drastically reduced, and the on-resistance between the drain and the source can be reduced.

  When a high voltage is applied between the drain electrode and the source electrode, the electric field applied to the gate insulating film 273 is shielded by the depletion layer extending from the P − -type gate semiconductor region 255 formed along the trench 361. Thus, a high breakdown voltage that is not determined by the breakdown voltage of the gate insulating film 273 and corresponds to the high breakdown electric field of the wide band gap semiconductor can be realized.

  This is extremely useful in providing a field effect transistor having a high breakdown voltage and a low on-resistance.

It is sectional drawing of the unit cell of the field effect transistor which concerns on 1st Example of this invention. (A)-(c) is explanatory drawing which shows the manufacturing process of the field effect transistor which concerns on 1st Example of this invention. (D)-(f) is explanatory drawing which shows the manufacturing process of the field effect transistor which concerns on 1st Example of this invention. It is sectional drawing of the unit cell of the field effect transistor which concerns on 2nd Example of this invention. (A)-(c) is explanatory drawing which shows the manufacturing process of the field effect transistor which concerns on 2nd Example of this invention. (D)-(f) is explanatory drawing which shows the manufacturing process of the field effect transistor which concerns on 2nd Example of this invention. It is sectional drawing of the conventional SiC field effect transistor.

Explanation of symbols

211, 212 N + type SiC substrate 221, 222 N- type SiC epitaxial region 242, 243 N + type source region 253, 255 P- type gate semiconductor region 254 P- type body semiconductor region 262, 263 N- type buried channel Region 272, 273 Gate insulating film 282, 283 Gate electrode 292, 293 Drain electrode 302, 303 Source electrode 311 Body contact electrode 350 Body contact region 360, 361, 362 Groove 370 SiO2 insulating layer 382, 383 Channel region

Claims (5)

A semiconductor substrate configured by stacking an epitaxial region of the wide band gap semiconductor on a wide band gap semiconductor substrate having a wider band gap than silicon; and
A groove formed in a predetermined portion of one surface of the semiconductor substrate;
A first conductivity type gate semiconductor region formed on the inner surface of the groove, a second conductivity type buried channel region formed in the epitaxial region outside the gate semiconductor region, and the buried channel region; A channel region composed of a body semiconductor region of a first conductivity type formed on the outside;
A source region formed above the buried channel region;
A source electrode formed in the source region;
A gate electrode formed inside the gate semiconductor region via a gate insulating film;
A drain electrode formed on the other surface of the semiconductor substrate;
A field effect transistor comprising: A semiconductor substrate configured by stacking an epitaxial region of the wide band gap semiconductor on a wide band gap semiconductor substrate having a wider band gap than silicon; and
A groove formed in a predetermined portion of one surface of the semiconductor substrate;
A channel region composed of a first conductivity type gate semiconductor region formed on the inner surface of the groove, and a second conductivity type buried channel region formed in the epitaxial region outside the gate semiconductor region;
A source region formed above the buried channel region;
A source electrode formed in the source region;
A gate electrode formed inside the gate semiconductor region via a gate insulating film;
A drain electrode formed on the other surface of the semiconductor substrate;
A field effect transistor comprising:   3. The field effect transistor according to claim 1, wherein the first conductive type gate semiconductor region is formed by CVD epitaxial growth.   The field effect transistor according to claim 1, wherein the wide band gap semiconductor is a silicon carbide semiconductor.   The first conductivity type is one of a P type and an N type, and the second conductivity type is the other of a P type and an N type. The field effect transistor according to any one of claims.

Images